LY62L2568GL-55LLI [LYONTEK]
256K X 8 BIT LOW POWER CMOS SRAM;
| 型号： | LY62L2568GL-55LLI |
| 厂家： | 
Lyontek Inc. |
| 描述： | 256K X 8 BIT LOW POWER CMOS SRAM 静态存储器 |
| 文件： | 总16页 (文件大小：342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
LY62L2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.5
REVISION HISTORY
Revision Description
Issue Date
Jul.25.2004
Mar.3.2006
May.14.2007
Rev. 1.0
Rev. 1.1
Rev. 1.2
Initial Issue
Adding PKG type : 32 SOP
Adding PKG type : 32 P-DIP
Revised Test Condition of ISB1/IDR
Deleted L grade
Rev. 1.3
Mar.30.2009
Added SL grade
℃
℃
Added ISB1/IDR values when TA = 25 and TA = 40
FEATURES ORDERING INFORMATION
Revised
&
Lead free
and green package available to Green package available
ORDERING INFORMATION
Added packing type in
Revised VTERM to VT1 and VT2
ABSOLUTE MAXIMUN RATINGS
Deleted TSOLDER in
Rev. 1.4
Rev. 1.5
May.7.2010
Aug.25.2010
PACKAGE OUTLINE DIMENSION
Revised
Revised
Revised
in page 10/11/12/13
ORDERING INFORMATION
in page 14
PACKAGE OUTLINE DIMENSION
in page 9
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
0
®
LY62L2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.5
FEATURES
GENERAL DESCRIPTION
The LY62L2568 is a 2,097,152-bit low power CMOS
static random access memory organized as 262,144
words by 8 bits. It is fabricated using very high
performance, high reliability CMOS technology. Its
standby current is stable within the range of
operating temperature.
Fast access time : 45/55/70ns
Low power consumption:
Operating current : 23/20/18mA (TYP.)
Standby current : 1μA (TYP.) LL/SL -version
Single 2.7V ~ 3.6V power supply
All inputs and outputs TTL compatible
Fully static operation
The LY62L2568 is well designed for very low power
system applications, and particularly well suited for
battery back-up nonvolatile memory application.
Tri-state output
Data retention voltage : 1.5V (MIN.)
Green package available
Package : 32-pin 450 mil SOP
32-pin 8mm x 20mm TSOP-I
32-pin 8mm x 13.4mm STSOP
36-ball 6mm x 8mm TFBGA
The LY62L2568 operates from a single power
supply of 2.7V ~ 3.6V and all inputs and outputs are
fully TTL compatible
32-pin 600 mil P-DIP
PRODUCT FAMILY
Power Dissipation
Speed
Product
Family
LY62L2568
Operating
Temperature
0 ~ 70℃
Vcc Range
Standby(ISB1,TYP.) Operating(Icc,TYP.)
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
45/55/70ns
45/55/70ns
45/55/70ns
1µA
1µA
1µA
23/20/18mA
23/20/18mA
23/20/18mA
-20 ~ 80℃
-40 ~ 85℃
LY62L2568(E)
LY62L2568(I)
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
SYMBOL
DESCRIPTION
Address Inputs
A0 - A17
Vcc
Vss
DQ0 – DQ7 Data Inputs/Outputs
CE#, CE2
WE#
OE#
Chip Enable Inputs
Write Enable Input
Output Enable Input
Power Supply
256Kx8
MEMORY ARRAY
A0-A17
DECODER
VCC
VSS
Ground
NC
No Connection
I/O DATA
CIRCUIT
DQ0-DQ7
COLUMN I/O
CE#
CE2
WE#
OE#
CONTROL
CIRCUIT
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
1
®
LY62L2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.5
PIN CONFIGURATION
A17
A16
A14
A12
A7
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CE2
WE#
A13
A8
3
4
5
A11
A9
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A6
6
A8
3
A13
WE#
CE2
A15
Vcc
A17
A16
A14
A12
A7
4
A5
7
A9
5
6
8
A4
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
7
8
A3
9
LY62L2568
9
A2
10
11
12
13
14
15
16
10
11
12
13
14
15
16
A1
A0
A6
A1
A5
A2
A3
DQ0
DQ1
DQ2
Vss
A4
TSOP-I/STSOP
SOP/P-DIP
A0
A1 CE2 A3
A6
A8
A
B
C
D
E
F
DQ4 A2 WE# A4
A7 DQ0
DQ1
DQ5
Vss
NC
A5
Vcc
Vcc
Vss
DQ6
NC A17
DQ2
DQ7 OE# CE# A16 A15 DQ3
A9 A10 A11 A12 A13 A14
G
H
1
2
3
4
5
6
TFBGA
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
2
®
LY62L2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.5
ABSOLUTE MAXIMUN RATINGS*
PARAMETER
SYMBOL
VT1
RATING
-0.5 to 4.6
UNIT
V
Voltage on VCC relative to VSS
Voltage on any other pin relative to VSS
VT2
-0.5 to VCC+0.5
0 to 70(C grade)
-20 to 80(E grade)
-40 to 85(I grade)
-65 to 150
V
℃
Operating Temperature
TA
℃
W
Storage Temperature
Power Dissipation
DC Output Current
TSTG
PD
1
IOUT
50
mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
CE#
H
CE2
X
OE#
X
WE#
X
SUPPLY CURRENT
ISB,ISB1
MODE
I/O OPERATION
High-Z
Standby
High-Z
ISB,ISB1
X
L
X
X
Output Disable
Read
High-Z
ICC,ICC1
L
H
H
H
DOUT
ICC,ICC1
L
H
L
H
Write
DIN
ICC,ICC1
L
H
X
L
Note: H = VIH, L = VIL, X = Don't care.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
3
®
LY62L2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.5
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
MIN.
2.7
2.2
- 0.2
- 1
TYP. *4
3.0
MAX.
3.6
VCC+0.3
0.6
UNIT
PARAMETER
Supply Voltage
VCC
V
V
V
*1
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage
Current
VIH
VIL
-
-
-
*2
ILI
V
V
CC ≧ VIN ≧ VSS
CC ≧ VOUT ≧ VSS,
Output Disabled
1
A
µ
ILO
- 1
-
1
A
µ
Output High Voltage
Output Low Voltage
VOH IOH = -1mA
2.2
-
2.7
-
-
V
V
VOL
IOL = 2mA
0.4
Cycle time = Min.
CE# = VIL and CE2 = VIH
23
20
18
40
35
30
- 45
- 55
- 70
-
-
-
mA
,
ICC
mA
mA
I
I/O = 0mA
Other pins at VIL or VIH
Cycle time = 1 s
Average Operating
Power supply Current
µ
≧
CE# = 0.2V and CE2 VCC-0.2V,
II/O = 0mA
ICC1
-
4
5
mA
Other pins at 0.2V or VCC - 0.2V
CE# = VIH or CE2 = VIL,
other pins at VIL or VIH
LL
ISB
-
0.3
0.5
mA
-
-
1
1
10
20
A
µ
A
µ
LLE/LLI
Standby Power
Supply Current
CE# ≧VCC-0.2V
SL*5
℃
-
-
1
1
3
3
A
25
µ
µ
≦
or CE2 0.2V
ISB1
SLE*5
SLI*5
Others at 0.2V or
℃
A
40
VCC - 0.2V
SL
-
-
1
1
10
15
A
µ
A
µ
SLE/SLI
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
℃
Typical values are measured at VCC = VCC(TYP.) and TA = 25
5. This parameter is measured at VCC = 3.0V
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
4
®
LY62L2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.5
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
MIN.
-
-
MAX
6
8
UNIT
pF
pF
CIN
CI/O
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0.2V to VCC - 0.2V
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
3ns
1.5V
CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
SYM.
tRC
UNIT
LY62L2568-45 LY62L2568-55 LY62L2568-70
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
45
-
-
-
10
5
-
55
-
-
-
10
5
-
70
-
-
-
10
5
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
45
45
25
-
55
55
30
-
70
70
35
-
tACE
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
*
*
*
*
-
-
-
-
-
10
15
15
-
-
-
10
20
20
-
-
-
10
25
25
-
(2) WRITE CYCLE
PARAMETER
SYM.
tWC
tAW
tCW
tAS
UNIT
LY62L2568-45 LY62L2568-55 LY62L2568-70
MIN.
45
40
40
0
MAX.
MIN.
55
50
50
0
MAX.
MIN.
70
60
60
0
MAX.
Write Cycle Time
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
-
-
-
tWP
tWR
tDW
tDH
tOW
35
0
-
-
45
0
-
-
55
0
-
-
20
0
-
-
25
0
-
-
30
0
-
-
*
5
-
5
-
5
-
tWHZ
*
-
15
-
20
-
25
*These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
5
®
LY62L2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.5
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
Dout
tAA
tOH
Previous Data Valid
Data Valid
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
CE2
OE#
tOE
tOLZ
tOH
tOHZ
tCHZ
tCLZ
High-Z
High-Z
Dout
Data Valid
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low., CE2 = high.
3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
6
®
LY62L2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.5
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC
Address
tAW
CE#
tCW
CE2
WE#
Dout
Din
tAS
tWP
tWR
tWHZ
TOW
High-Z
(4)
(4)
tDW
tDH
Data Valid
WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)
tWC
Address
tAW
CE#
CE2
tAS
tWR
tCW
tWP
WE#
Dout
Din
tWHZ
High-Z
(4)
tDW
tDH
Data Valid
Notes :
1.WE#, CE# must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE#, high CE2, low WE#.
3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high
impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
7
®
LY62L2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.5
DATA RETENTION CHARACTERISTICS
PARAMETER
VCC for Data Retention
SYMBOL
TEST CONDITION
CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V
LL
MIN.
1.5
-
-
TYP. MAX. UNIT
VDR
-
3.6
5
10
V
0.5
0.5
A
µ
µ
LLE/LLI
SL
SLE
SLI
SL
A
VCC = 1.5V
CE# ≧ VCC - 0.2V
or CE2 ≦ 0.2V
℃
-
-
0.5
0.5
3
3
25
A
µ
µ
Data Retention Current
IDR
℃
A
40
Other pins at 0.2V or VCC-0.2V
-
-
0.5
0.5
5
10
A
µ
A
µ
SLE/SLI
Chip Disable to Data
Retention Time
Recovery Time
See Data Retention
Waveforms (below)
tCDR
tR
0
-
-
-
-
ns
ns
tRC
*
tRC = Read Cycle Time
*
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE# controlled)
VDR ≧ 1.5V
Vcc(min.)
Vcc
Vcc(min.)
tCDR
tR
VIH
CE# ≧ Vcc-0.2V
VIH
CE#
Low Vcc Data Retention Waveform (2) (CE2 controlled)
VDR ≧ 1.5V
Vcc(min.)
Vcc
Vcc(min.)
tCDR
tR
CE2 ≦ 0.2V
CE2
VIL
VIL
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
8
®
LY62L2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.5
PACKAGE OUTLINE DIMENSION
32 pin 450 mil SOP Package Outline Dimension
UNIT
SYM.
INCH.(BASE)
MM(REF)
A
A1
A2
b
c
D
0.120(MAX)
0.004(MIN)
0.116(MAX)
0.016(TYP)
0.008(TYP)
0.817(MAX)
3.048(MAX)
0.102(MIN)
2.946(MAX)
0.406(TYP)
0.203(TYP)
20.75(MAX)
E
±
±
11.303 0.152
0.445 0.006
E1
e
±
±
0.555 0.025
14.097 0.635
0.050(TYP)
1.270(TYP)
L
±
±
0.838 0.432
0.033 0.017
L1
S
y
±
±
0.055 0.008
1.397 0.203
0.026(MAX)
0.004(MAX)
0o -10o
0.660(MAX)
0.101(MAX)
0o -10o
Θ
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
9
®
LY62L2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.5
32 pin 8mm x 20mm TSOP-I Package Outline Dimension
UNIT
INCH(BASE)
MM(REF)
SYM.
A
A1
A2
b
0.047 (MAX)
1.20 (MAX)
±
±
0.004 0.002 0.10 0.05
±
±
0.039 0.002 1.00 0.05
±
±
0.009 0.002 0.22 0.05
c
±
±
0.006 0.002 0.155 0.055
D
±
±
0.724 0.008 18.40 0.20
E
±
±
0.315 0.008 8.00 0.20
e
0.020 (TYP) 0.50 (TYP)
HD
L
±
±
0.787 0.008 20.00 0.20
±
±
0.024 0.004 0.60 0.10
L1
y
Θ
±
±
0.0315 0.004 0.08 0.10
0.003 (MAX) 0.08 (MAX)
o
o
o
o
～
～
5
0
5
0
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
10
®
LY62L2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.5
32 pin 8mm x 13.4mm STSOP Package Outline Dimension
HD
c
L
12° (2x)
12° (2x)
32
1
17
16
"A"
y
Seating Plane
D
12° (2X)
16
17
GAUGE PLANE
0
SEATING PLANE
L
12° (2X)
L1
"A" DATAIL VIEW
1
32
UNIT
INCH(BASE)
0.049 (MAX)
MM(REF)
1.25 (MAX)
SYM.
A
A1
A2
b
±
±
0.004 0.002 0.10 0.05
±
±
0.039 0.002 1.00 0.05
±
±
0.009 0.002 0.22 0.05
c
±
±
0.006 0.002 0.155 0.055
D
±
±
0.465 0.008 11.80 0.20
E
±
±
0.315 0.008 8.00 0.20
e
0.020 (TYP) 0.50 (TYP)
HD
L
±
±
13.40 0.20.
±
0.50 0.20
0.528 0.008
±
0.02 0.008
L1
y
Θ
±
±
0.031 0.005 0.8 0.125
0.003 (MAX) 0.076 (MAX)
o
o
o
o
～
～
5
0
5
0
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
11
®
LY62L2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.5
36 ball 6mm × 8mm TFBGA Package Outline Dimension
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
12
®
LY62L2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.5
32 pin 600 mil P-DIP Package Outline Dimension
UNIT
SYM.
INCH(BASE)
0.015(MIN)
MM(REF)
A1
A2
B
0.381(MIN)
±
3.937 0.127
±
0.457 0.127
±
0.155 0.005
±
0.018 0.005
D
±
±
41.910 0.254
1.650 0.01
E
±
±
15.240 0.254
0.600 0.010
E1
e
±
±
0.545 0.005
13.843 0.127
0.100(TYP)
2.540(TYP)
eB
L
±
±
16.510 0.508.
±
4.013 1.092
0.650 0.020
±
0.158 0.043
S
±
±
1.905 0.254
0.075 0.010
Q1
±
±
1.778 0.127
0.070 0.005
Note : D/E1/S dimension do not include mold flash.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
13
®
LY62L2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.5
ORDERING INFORMATION
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
14
®
LY62L2568
256K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.5
THIS PAGE IS LEFT BLANK INTENTIONALLY.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
15
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