LXP600A [LevelOne]
Low-Jitter Clock Adapters(CLADs); 低抖动时钟适配器（包层）
| 型号： | LXP600A |
| 厂家： | 
LEVEL ONE |
| 描述： | Low-Jitter Clock Adapters(CLADs) |
| 文件： | 总10页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Frame Sync Output. Frame synchronization output at 8 kHz. FSO is synced to CLKO
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Select (SEL) input, as listed in Table 2.
Clock Inputï Input clock (1.544, 2.048 or 4.096 MHz) to be converted.
Clock Outputï Output clock (1.544, 2.048 or 4.096 MHz) derived from CLKI.
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Mode Select. controls frequency conversion as listed in Table 2.
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When SEL = Low, 1.544 MHz CLKI is converted to higher frequency CLKO (2.048 for
LXP600A and LXP602, or 4.096 MHz for LXP604).
FSI
Frame Sync Inputï 8 kHz frame synchronization pulse. Tie High or Low if not used.
Power Supplyï +5 V power supply input.
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Standard CMOS device precautions apply to the CLAD.
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1. Transient currents of up to 100 mA will not cause SCR latch-up.
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1. Specifications from AT&T Publication 62411 and ITU Recommendations G.823 (for 1.544 MHz and 2.048 MHz, respectively).
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