LXT305ANI [LevelOne]
PCM Transceiver, 1-Func, CMOS, PDIP28, DIP-28;
| 型号： | LXT305ANI |
| 厂家： | 
LEVEL ONE |
| 描述： | PCM Transceiver, 1-Func, CMOS, PDIP28, DIP-28 |
| 文件： | 总18页 (文件大小：348K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Peak
Detector
RRING
Data
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RPOS
RNEG
Transmit
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MTIP
Receive
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The LXT305A receives the signal input from one twisted-
pair line on each side of a center-grounded transformer.
Positive pulses are received at RTIP and negative pulses
are received at RRING. Recovered data is output at RPOS
and RNEG, and the recovered clock is output at RCLK.
Refer to Test Specifications for LXT305A receiver timing.
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The signal received at RPOS and RNEG is processed
through the peak detector and data slicers. The peak detec-
tor samples the inputs and determines the maximum value
of the received signal. A percentage of the peak value is
provided to the data slicers as a threshold level to ensure
optimum signal-to-noise ratio. For T1 applications (deter-
mined by Equalizer Control inputs EC1 - EC3 ≠ 000 or
001) the threshold is set to 70% of the peak value. This
threshold is maintained above 65% for up to 15 successive
zeros over the range of specified operating conditions. For
E1 applications (EC inputs = 000 or 001) the threshold is
50%.
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The receiver is capable of accurately recovering signals
with up to -13.6 dB of attenuation (from 2.4 V), corre-
sponding to a received signal level of approximately 500
mV. Maximum line length is 1500 feet of ABAM cable
(approximately 6 dB of attenuation). Regardless of re-
ceived signal level, the peak detectors are held above a
minimum level of .3 V to provide immunity from impul-
sive noise.
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After processing through the data slicers, the received sig-
nal is routed to the data and clock recovery sections, and to
the receive monitor. The data and clock recovery circuits
are highly tolerant with an input jitter tolerance significant-
ly better than required by Pub 62411. Refer to Test Speci-
fications for additional information.
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The receiver monitor loads a digital counter at the RCLK
frequency. The count is incremented each time a zero is
received, and reset to zero each time a one (mark) is
received. Upon receipt of 175 consecutive zeros the LOS
pin goes High, and a smooth transition replaces the RCLK
output with the MCLK. Received marks are output regard-
less of the LOS status, but the LOS pin will not reset until
the ones density reaches 12.5%. This level is based on
receipt of at least 4 ones in any 32-bit period with no more
than 15 consecutive zeros.
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Data received for transmission onto the line is clocked seri-
ally into the device at TPOS and TNEG. Input synchroni-
zation is supplied by the transmit clock (TCLK). The
transmitted pulse shape is determined by Equalizer Control
signals EC1 through EC3 as shown in Table 4. Refer to
Test Specifications for master and transmit clock timing
characteristics. Shaped pulses are applied to the AMI line
driver for transmission onto the line at TTIP and TRING.
Equalizer Control signals may be hardwired in the Hard-
ware Mode, or input as part of the serial data stream (SDI)
in the Host Mode
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Pulses can be shaped for either 1.544 or 2.048 Mbps appli-
cations. 1.544 Mbps pulses for DSX-1 applications can be
programmed to match line lengths from 0 to 655 feet of
ABAM cable. The LXT305A also matches FCC and
ECSA specifications for CSU applications. 2.048 Mbps
pulses can drive coaxial or shielded twisted-pair lines.
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Jitter attenuation of the LXT305A transmit outputs is pro-
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Store (ES). An external crystal oscillating at 4 times the bit
rate provides clock stabilization. Refer to Application
Information for crystal specifications. The ES is a 32 x 2-
bit register. Transmit data is clocked into the ES with the
transmit clock (TCLK) signal, and clocked out of the ES
with the dejittered clock from the JAL. When the bit count
in the ES is within two bits of overflowing or underflowing,
the ES adjusts the output clock by 1/8 of a bit period. The
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The LXT305A can be controlled through hard-wired pins
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interface (Host Mode). The mode of operation is set by the
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The LXT305A transmits data as a 50% AMI line code as
shown in Figure 2. The output driver maintains a constant
low output impedance regardless of whether it is driving
marks or spaces. This well controlled output impedance
provides excellent return loss (> 18 dB) when used with
external 9.1 ″ precision (± 1 % accuracy) in series with a
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the serial data and receive data output timing. The Clock
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The serial interface (SDI/SDO) uses a 16-bit word consist-
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byte. Figure 3 shows the serial interface data structure and
relative timing.
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The Host Mode provides a latched Interrupt output (INT)
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ìï Power dissipation while driving 75 Ω load over operating temperature range. Includes device and load. Digital input levels are within 10% of the
supply rails and digital outputs are driving a 50 pF capacitive load.
2. Functionality of pins 23 and 25 depends on mode. See Host/Hardware Mode descriptions.
3. Output drivers will output CMOS logic levels into CMOS loads.
4. Except MTIP and MRING Ill = ± 50 µA.
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3. Circuit attenuates jitter at 20 dB/decade above the corner frequency.
4. In accordance with ITU G.703/ETS 300166 return loss specifications when wired per Figure 5 (E1).
5. Guaranteed by design.
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相关型号：
LXT30X
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