LXT332 [LevelOne]
Dual T1/E1 Line Interface Unit with Crystal-less Attenuation; 双T1 / E1线路接口单元与无晶体衰减
| 型号： | LXT332 |
| 厂家： | 
LEVEL ONE |
| 描述： | Dual T1/E1 Line Interface Unit with Crystal-less Attenuation |
| 文件： | 总32页 (文件大小：734K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TCLK
TTIP
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Timing &
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Line Drivers
Equalizer
B8ZS/HDB3
Unipolar
TPOS
TNEG
TRING
Encoder
Monitor
DFM
DFM
TAOS
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Enable
LEN Select
INT0/1
PS0/1
CLKE
SCLK
SDI
Serial Word
Serial
Port
LLOOP
Enable
RLOOP
Enable
Local
Loopback
SDO
MCLK
Jitter
Attenuator
JASEL
Internal
Clock
HFC
Generator
Decoder
Enable
Remote
Loopback
Data Slicers
B8ZS/HDB3
Unipolar
Decoder
RNEG
RPOS
RTIP
Peak
Detector
Timing and
Data
Recovery
RRING
RCLK
QRSS Detector
LOS/Clear
LOS
LOS
Processor
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TRSTE
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Tristate Output Enable Input Pin. Forces all output pins to high-Z tri-state
when held High. Enables Bipolar I/O mode when held Low. In this mode
the framer interface is bipolar (TPOS/TNEG and RPOS/RNEG), and the
B8ZS/HDB3 encoders are disabled. Enables Unipolar I/O mode when
clocked by MCLK. In this mode the framer interface is unipolar (TDATA
and RDATA), and the TNEG and RNEG pins are re-mapped. The TNEG
pins are re-mapped as Encoder Enable (ECE) to individually enable the
B8ZS/HDB3 encoder/decoder for each port. The RNEG pins are re-mapped
as Bipolar Violation (BPV) indicators to report BPVs received at the respec-
tive ports.
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TCLK0
DI
Transmit Clock - Port 0. 1.544 MHz for T1, 2.048 MHz for E1. The trans-
mit data inputs are sampled on the falling edge of TCLK.
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TPOS0
(Bipolar)
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Transmit Positive and Negative Data - Port 0. In the Bipolar I/O mode,
these pins are the positive and negative sides of a bipolar input pair for port
0. Data to be transmitted onto the twisted-pair line is input at these pins.
However, when the TRSTE pin is clocked by MCLK, the LXT332 switches
to a unipolar mode. Table 2 describes Unipolar mode pin functions.
TNEG0
(Bipolar)
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RNEG0
(Bipolar)
DO Receive Positive and Negative Data - Port 0. In the Bipolar I/O mode,
these pins are the data outputs from port 0. A signal on RNEG corresponds
to receipt of a negative pulse on RTIP/RRING. A signal on RPOS corre-
DO sponds to receipt of a positive pulse on RTIP/RRING. RNEG/RPOS outputs
are Non-Return-to-Zero (NRZ). In Host mode, CLKE determines the clock
edge at which these outputs are stable and valid.
RPOS0
(Bipolar)
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RCLK0
SCLK
VCQ0
DO Receive Clock - Port 0. This clock is recovered from the input signal.
Under Loss of Signal (LOS) conditions, this output is derived from MCLK.
DI
Serial Clock. The Serial Clock shifts data into or out from the serial inter-
face register of the selected port.
DI/O Provides Violation insert, High Frequency Clock, or QRSS generation/detec-
tion functions for Port 0. Pin operation is determined by the VCQE pin.
Violation Insertion Function. When the Violation insertion function is
enabled, this pin is sampled on the falling edge of TCLK to control bipolar
violation (BPV) insertion. If High, a BPV is inserted at the next available
mark transmitted from port 0. A Low-to-High transition is required for each
subsequent violation insertion. (B8ZS and HDB3 zero suppression codes are
not violated.)
Clock Function. When the Clock function is enabled, this pin outputs a
High Frequency Clock (12.352 MHz for T1, 16.384 MHz for E1) tied to the
jitter attenuated clock of port 0. If no JA clock is available, HFC is locked to
the 8x receive timing recovery clock.
Quasi Random Signal Source (QRSS) Function. When the QRSS function
is enabled, a High on this pin enables the QRSS detection circuit and causes
the LXT332 to transmit the QRSS pattern onto the twisted-pair line from
port 0. For error-free QRSS transmission, TPOS0 must be held Low. To
insert errors into the pattern, TPOS must transition from Low to High (TPOS
is sampled on the falling edge of MCLK). A Low-to-High transition is
required for each subsequent violation insertion. (B8ZS and HDB3 zero
suppression codes are not violated.)
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INT1
INT0
DO Interrupt Outputs. The interrupt outputs go Low to flag the host processor
DO that the respective port has changed state. INT0 and INT1 are open drain
outputs. Each must be tied to VCC through a resistor.
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MCLK
DI
Master Clock. The master clock (1.544 MHz for T1, 2.048 MHz for E1)
input must be independent, free-running, continuously active and jitter free
for receiver operation. Since the transceivers derive their RCLK timing from
the MCLK input on Loss of Signal (LOS), MCLK cannot be derived from
RCLK.
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GND
–
Ground. Ground return for power supply VCC.
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TTIP0
TRING0
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Transmit Tip and Ring - Port 0. The tip and ring pins for each port are dif-
ferential driver outputs designed to drive a 35 - 200 Ω load. Line matching
resistors and transformers can be selected to give the desired pulse height.
See Figures 19 through 21.
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TGND0
TVCC0
–
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Ground. Ground return for power supply TVCC0.
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+ 5 volt power supply input for the port 0 transmit driver. TVCC0 must
not vary from TVCC1 or VCC by more than ± 0.3 V.
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DFM
PS0
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Driver Fail Monitor. This signal goes High to indicate a driver output short
in one or both ports.
Port Select - Port 0. This input accesses the serial interface registers for
port 0. For each read or write operation, PS must transition from High to
Low, and remain Low.
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PD0
DO Pattern Detect - Port 0. Unless the QRSS function is selected by the VCQE
pin, PD0 functions as an AIS alarm indicator. The AIS pattern is detected by
the receiver, independent of any loopback mode. AIS goes High when less
than three zeros have been detected in any string of 2048 bits. AIS returns
Low when the received signal contains more than three zeros in 2048 bits.
(LOS is available via the SIO register and interrupt.)
If the QRSS function is enabled by the VCQE pin, PD0 remains High until
pattern sync is reached with the received signal. Once pattern lock is
obtained, PD0 goes Low. (The sync/out-of-sync criteria is less than 3/4
errors in 128 bits.) After sync acquisition, bit errors cause PD0 to go High
for half a clock cycle. This output can be used to trigger an external error
counter.
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RTIP0
RRING0
DI
DI
Receive Tip and Ring - Port 0. RTIP and RRING comprise the receive line
interface. This input pair should be connected to the line through a center-
tapped 1:2 transformer.
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CLKE
DI
Clock Edge Select. When CLKE is High, RPOS/RNEG or RDATA out-
puts are valid on the falling edge of RCLK, and SDO is valid on the rising
edge of SCLK. When CLKE is Low, RPOS/RNEG or RDATA outputs are
valid on the rising edge of RCLK, and SDO is valid on the falling edge of
SCLK.
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RRING1
RTIP1
AI
AI
Receive Tip and Ring - Port 1. RTIP and RRING comprise the receive line
interface. This input pair should be connected to the line through a center-
tapped 1:2 transformer.
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PD1
DO Pattern Detect - Port 1. Reports AIS and QRSS pattern reception. See
PD0 signal description for details.
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SDI
PS1
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Port Select - Port 1. This input accesses the serial interface registers for
port 1. For each read or write operation, PS must transition from High to
Low, and remain Low.
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TRING1
TTIP1
AO
AO
Transmit Tip and Ring - Port 1. The tip and ring pins for each port are dif-
ferential driver outputs designed to drive a 35 - 200 Ω load. Line matching
resistors and transformers can be selected to give the desired pulse height.
See Figures 13 through 15.
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TVCC1
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+ 5 volt power supply input for the port 1 transmit driver. TVCC1 must
not vary from TVCC0 or VCC by more than ± 0.3 V.
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TGND1
VCC
–
Ground. Ground return for power supply TVCC1.
AI
DI
+5 VDC power supply input for all circuits, except the transmit drivers.
JASEL
Jitter Attenuation Select. Selects jitter attenuation for both ports. When
JASEL = 1, JA circuits are placed in the receive paths. When JASEL = 0, JA
circuits are placed in the transmit paths. When JASEL is clocked with
MCLK, the JA circuit is disabled.
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VCQ1
DI/O Violation insert, Clock, or QRSS. Function (Violation insert, Clock, or
QRSS) is determined by the VCQE pin. Provides Violation Insertion, High
Frequency Clock or QRSS Generation functions for Port 1. Refer to VCQ0
signal description for details.
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SPE
DI
Serial Port Enable. SPE must be clocked with MCLK to enable Host Mode
control through the serial port.
VCQE
DI
Violation - Clock - QRSS Enable. When set High, enables the Bipolar
Violation Insert functions of VCQ0 and VCQ1 pins. When set Low, enables
the High Frequency Clock functions of VCQ0 and VCQ1. When clocked
with MCLK, enables the QRSS functions of VCQ0 and VCQ1, and enables
the QRSS Generate and Detect function of PD0 and PD1 pins.
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SDO
DO Serial Data Output. If CLKE is High, SDO is valid on the rising edge of
SCLK. If CLKE is Low, SDO is valid on the falling edge of SCLK.
RCLK1
DO Receive Clock - Port 1. This clock is recovered from the input signal.
Under Loss of Signal (LOS) conditions, this output is derived from MCLK.
RPOS1
(Bipolar)
DO Receive Positive and Negative Data - Port 1. In the Bipolar I/O mode,
these pins are the data outputs from port 1. A signal on RPOS corresponds to
receipt of a positive pulse on RTIP/RRING. A signal on RNEG corresponds
DO to receipt of a negative pulse on RTIP/RRING. RNEG/RPOS outputs are
Non-Return-to-Zero (NRZ). CLKE determines the clock edge at which
these outputs are stable and valid.
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RNEG1
(Bipolar)
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TNEG1
(Bipolar)
DI
Transmit Positive and Negative Data - Port 1. In the Bipolar I/O mode,
these pins are TPOS and TNEG, the positive and negative sides of a bipolar
input pair for port 1. Data to be transmitted onto the twisted-pair line is input
at these pins. However, when TRSTE is clocked by MCLK, the LXT332
switches to a unipolar mode. Unipolar mode pin functions are described sep-
arately.
TPOS1
(Bipolar)
DI
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TCLK1
DI
Transmit Clock - Port 1. 1.544 MHz for T1, 2.048 MHz for E1. The trans-
mit data inputs are sampled on the falling edge of TCLK.
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DI Transmit Data - Port 0. In the Unipolar mode, the data to be transmitted
onto the twisted-pair line from port 0 is input at this pin.
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ECE0
BPV0
DI Encoder Enable - Port 0. In the Unipolar mode, a High on this pin enables
the B8ZS or HDB3 encoder and decoder for port 0.
DO Bipolar Violation - Port 0. In the Unipolar mode this indicator output goes
High when a bipolar violation is received at port 0.
RDATA0
DO Receive Data - Port 0. In the Unipolar mode, RDATA is a Non-Return-to-
Zero (NRZ) output. CLKE determines the RCLK edge which RDATA is
stable and valid.
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RDATA1
DO Receive Data - Port 1. In the Unipolar mode, RDATA is a Non-Return-to-
Zero (NRZ) output. CLKE determines the RCLK edge which RDATA is
stable and valid.
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BPV1
ECE1
DO Bipolar Violation - Port 1. In the Unipolar mode this indicator output goes
High when a bipolar violation is received at port 1.
DI Encoder Enable - Port 1. In the Unipolar mode, a High on this pin enables
the B8ZS or HDB3 encoder and decoder for port 1.
TDATA1
DI Transmit Data - Port 1. In the Unipolar mode, the data to be transmitted
onto the twisted-pair line from port 1 is input at this pin.
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TRSTE
DI Tristate Output Enable Input Pin. Forces all output pins to high-Z Tri-state
when held High. Enables Bipolar I/O mode when held Low. In this mode the
framer interface is bipolar (TPOS/TNEG and RPOS/RNEG), and the B8ZS/
HDB3 encoders are disabled. Enables Unipolar I/O mode when clocked by
MCLK. In this mode the framer interface is unipolar (TDATA and RDATA),
and the TNEG and RNEG pins are re-mapped. The TNEG pins are re-mapped
as Encoder Enable (ECE) to individually enable the B8ZS/HDB3 encoder/
decoder for each port. The RNEG pins are re-mapped as Bipolar Violation
(BPV) indicators to report BPVs received at the respective ports.
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TCLK0
DI Transmit Clock - Port 0. 1.544 MHz for T1, 2.048 MHz for E1. The trans-
mit data inputs are sampled on the falling edge of TCLK.
TPOS0
(Bipolar)
DI Transmit Data Positive and Negative - Port 0. In the Bipolar I/O mode,
these pins are the positive and negative sides of a bipolar input pair for port 0.
Data to be transmitted onto the twp line is input at these pins. However, when
TRSTE is clocked by MCLK, the LXT332 switches to a unipolar mode. Uni-
polar mode pin functions are described separately.
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TNEG0
(Bipolar)
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RNEG0
(Bipolar)
DO Receive Data Positive and Negative - Port 0. In the Bipolar I/O mode, a sig-
nal on RNEG corresponds to receipt of a negative pulse on RTIP/RRING. A
signal on RPOS corresponds to receipt of a positive pulse on RTIP/RRING.
RNEG/RPOS outputs are Non-Return-to-Zero (NRZ). RPOS and RNEG are
stable and valid on the rising edge of RCLK.
RPOS0
(Bipolar)
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RCLK0
TAOS0
DO Receive Clock - Port 0. This clock is recovered from the input signal. Under
Loss of Signal (LOS) conditions, this output is derived from MCLK.
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DI Transmit All Ones Enable - Port 0. When TAOS is High and RLOOP is
Low, the TPOS/TNEG or TDATA input is ignored and port 0 transmits a
stream of ones at the TCLK frequency. If TCLK is not provided, the MCLK
input is used as the transmit reference.
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LEN20
LEN10
LEN00
DI Line Length Equalizer Inputs - Port 0. This pins determine the shape and
DI amplitude of the transmit pulse.
DI
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MCLK
DI Master Clock. The master clock (1.544 MHz for T1, 2.048 MHz for E1) input
must be independent, free-running, continuously active and jitter free for
receiver operation. Since the transceivers derive their RCLK timing from the
MCLK input on Loss of Signal (LOS), MCLK cannot be derived from RCLK.
æ
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GND
–
Ground. Ground return for power supply VCC.
å
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TTIP0
TRING0
AO Transmit Tip and Ring - Port 0. The tip and ring pins for each port are dif-
AO ferential driver outputs designed to drive a 35 - 200 Ω load. Line matching
resistors and transformers can be selected to give the desired pulse height. See
Figures 13 through 15.
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TGND0
TVCC0
–
Ground. Ground return for power supply TVCC0.
ìí
AI + 5 volt power supply input for the port 0 transmit driver. TVCC0 must not
vary from TVCC1 or VCC by more than ± 0.3 V.
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DFM
DO Driver Fail Monitor. This signal goes High to indicate a driver output short
in one or both ports.
RLOOP0
DI Remote Loopback Enable - Port 0. When RLOOP = 1, the port 0 clock and
data inputs from the framer are ignored and the data received from the twisted-
pair line is transmitted back onto the line at the RCLK frequency. (LLOOP0
must be Low for RLOOP0 to occur.)
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LOS0
DO Loss of Signal - Port 0. LOS goes High when 175 consecutive spaces have
been detected. LOS returns Low when the received signal reaches a mark den-
sity of 12.5% (determined by receipt of four marks with a sliding 32-bit period
with no more than 15 consecutive zeros). Received marks are output on
RPOS/RNEG or RDATA even when LOS is High.
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RTIP0
RRING0
AI Receive Tip and Ring - Port 0. RTIP and RRING comprise the receive line
AI interface. This input pair should be connected to the line through a center-
tapped 1:2 transformer.
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LLOOP0
DI Local Loopback Enable - Port 0. When LLOOP is High, the RTIP/RRING
inputs from the port 0 line are disconnected and the transmit data inputs are
routed back into the receive inputs (through JA if enabled). (RLOOP0 must
be Low for LLOOP0 to occur.)
ìå
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RRING1
RTIP1
AI Receive Tip and Ring - Port 1. RTIP and RRING comprise the receive line
AI interface. This input pair should be connected to the line through a center-
tapped 1:2 transformer.
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LOS1
DO Loss of Signal - Port 1. LOS goes High when 175 consecutive spaces have
been detected. LOS returns to a logic 0 when the received signal reaches a
mark density of 12.5% (refer to LOS0 signal description for details).
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LLOOP1
TAOS1
DI Local Loopback Enable - Port 1. (RLOOP1 must be Low for LLOOP1 to
occur.)
DI Transmit All Ones Enable - Port 1. (RLOOP1 must be Low for TAOS1 to
occur.)
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TRING1
TTIP1
AO Transmit Ring - Port 1. The tip and ring pins for each port are differential
AO driver outputs designed to drive a 35 - 200 Ω load. Line matching resistors
and transformers can be selected to give the desired pulse height. See Figures
19 through 21.
ëé
êí
TVCC1
AI + 5 volt power supply input for the port 1 transmit driver. TVCC1 must not
vary from TVCC0 or VCC by more than ± 0.3 V.
ëè
ëæ
ëå
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TGND1
VCC
–
Ground. Ground return for power supply TVCC1.
AI +5 VDC power supply input for all circuits, except the transmit drivers.
JASEL
DI Jitter Attenuation Select. Selects jitter attenuation for both ports. When
JASEL = 1, JA circuits are placed in the receive paths. When JASEL = 0, JA
circuits are placed in the transmit paths. When JASEL is clocked with MCLK,
the JA circuit is disabled.
ëä
êí
êì
êè
êç
êæ
LEN01
LEN11
LEN21
DI Line Length Equalizer inputs - Port 1. These pins determine the shape and
DI amplitude of the transmit pulse.
DI
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êå
RLOOP1
DI Remote Loopback Enable - Port 1. (LLOOP1 must = 0 for RLOOP to
occur.)
êê
êä
RCLK1
DO Receive Clock - Port 1. This clock is recovered from the twisted-pair input
signal. Under Loss of Signal (LOS) conditions, this output is derived from
MCLK.
êé
êè
éí
éì
RPOS1
(Bipolar)
DO Receive Data Positive and Negative - Port 1. In the Bipolar I/O mode, these
pins are the data outputs from port 1. A signal on RPOS corresponds to
receipt of a positive pulse on RTIP/RRING. A signal on RNEG corresponds
DO to receipt of a negative pulse on RTIP/RRING. RNEG/RPOS outputs are
Non-Return-to-Zero (NRZ). RPOS and RNEG are stable and valid on the ris-
ing edge of RCLK.
RNEG1
(Bipolar)
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TNEG1
TPOS1
DI Transmit Data Positive and Negative - Port 1. In the Bipolar I/O mode,
these pins are TPOS and TNEG, the positive and negative sides of a bipolar
DI input pair for port 1. Data to be transmitted onto the twisted-pair line is input
at these pins. However, when the TRSTE pin is clocked by MCLK, the
LXT332 switches to a unipolar mode. Unipolar mode pin functions are
described separately.
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TCLK1
DI Transmit Clock - Port 1. 1.544 MHz for T1, 2.048 MHz for E1. The trans-
mit data inputs are sampled on the falling edge of TCLK.
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TDATA0
ECE0
DI Transmit Data - Port 0. In the Unipolar mode, the data to be transmitted
onto the line from port 0 is input at this pin.
DI Encoder Enable - Port 0. In the Unipolar mode, a High on this pin enables
the B8ZS or HDB3 encoder and decoder for port 0.
BPV0
DO Bipolar Violation - Port 0. In the Unipolar mode this indicator output goes
High when a bipolar violation is received at port 0.
RDATA0
DO Receive Data - Port 0. In the Unipolar mode, RDATA is a Non-Return-to-
Zero (NRZ) output. RDATA is stable and valid on the rising edge of
RCLK.
34
40
RDATA1
DO Receive Data - Port 1. In the Unipolar mode, RDATA is a Non-Return-to-
Zero (NRZ) output. RDATA is stable and valid on the rising edge of
RCLK.
35
36
37
41
42
43
BPV1
ECE1
DO Bipolar Violation - Port 1. In the Unipolar mode this indicator output goes
High when a bipolar violation is received at port 1.
DI Encoder Enable - Port 1. In the Unipolar mode, a High on this pin enables
the B8ZS or HDB3 encoder and decoder for port 1.
TDATA1
DI Transmit Data - Port 1. In the Unipolar mode, the data to be transmitted
onto the line from port 1 is input at this pin.
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1200 UI
1000 UI
138 UI
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Mode
Pub 62411
28 UI
18 UI
Dec 1990
10 UI
1.5 UI @ 20 Hz
1 UI
ITU G.823 Mar 1993
30 kHz
0.4 UI
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100 kHz
300
440
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