LXT6251QE [LevelOne]
Support Circuit, 1-Func, CMOS, PQFP208, PLASTIC, QFP-208;
| 型号： | LXT6251QE |
| 厂家： | 
LEVEL ONE |
| 描述： | Support Circuit, 1-Func, CMOS, PQFP208, PLASTIC, QFP-208 ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总72页 (文件大小：870K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
JUNE 1999
Revision2.0
LXT6251
21 E1 SDH Mapper
LXT
General Description
Features
The LXT6251 21E1 Mapper performs asynchronous
mapping and demapping of 21 E1 PDH signals into SDH.
The PDH side interfaces with E1 LIUs and framers via
NRZ Clock & Data, while the SDH side uses a standard
Telecom bus interface. Further processing by the
companion LXT6051 Overhead Terminator chip creates
the final STM-0 or STM-1 signal. One mapper provides
complete processing of 21 E1s in STM-0, while three
mappers can process 63 E1s in STM-1.
• Maps and Demaps 21 E1 signals between PDH and
SDH networks via VC-12 asynchronous mapping.
• Multiplexes the 21 VC-12 signals into seven
interleaved TUG-2 structures for STM-0 or a TUG-3
structure for STM-1 applications.
• Configurable as a flexible Add/Drop Multiplexer for
up to 21 E1 tributaries, with each E1 I/O port
assignable to any TU time slot within an AU-3 or
TUG-3.
The LXT6251 is compliant with the latest releases of ITU-
T G.703 and G.707. It provides all the alarm and control
features to easily implement the multiplexer specified in
ITU-T G.783.
• Performs VC-12 path overhead processing for all 21
VC-12s, including V5, J2 Path Trace, and K4
Enhanced RDI.
• Records TU pointer alarms (TU-AIS, TU-LOP), BIP-
2 and REI error counts, TIM and PLM alarms, and all
other V5 POH alarms for all 21 tributaries.
Applications
• NRZ Data and Clock interface for E1 tributary access.
• Microprocessor/SEMF interface to set Signal Label,
J2 Path Trace, access alarms and counters
• 21 or 63 E1 Terminal or ADM SDH Multiplexer
• Digital Cross Connect System
• Low power CMOS technology with 3.3V core and 5V
I/O, available in PQFP-208 package.
• Digital Loop Carrier Systems (NGDLC)
• Microwave Radio Systems
• IEEE 1149.1 (JTAG) support.
LXT6251
Block Diagram
SETS
LXT6251
21 Channel
Mapper
4
Telecom Bus Tim ing
TX
6.48M /19.44M Clock
VC-12
Path
Term ination
Fixed
Pointer
Generator
Telecom
Bus
Interface
21
21
E1 Clock
Telecom Bus Data
FIFO,
E1 Data
S/P
E1 Line
Interface
units
LXT6051
Overhead
Terminator
M icrocontroller Interface (Intel/M otorola selectable)
21
21
E1 Clock
E1 Data
Telecom Bus Data
6.48M /19.44M Clock
Telecom Bus Tim ing
FIFO, P/S,
Desynchronizer
VC-12
Path
Term ination
Telecom
Bus
Interface
Pointer
Interpreter
4
RX
Refer to www.level1.com for most current information.
)
LXT6251 21 E1 SDH Mapper
Table Of contents
Pin Assignments and Signal Descriptions....................................................................................... 4
Functional Description ..................................................................................................................... 14
Introduction .................................................................................................................................... 14
Receive Section, Terminal Mode................................................................................................... 14
Receive Alarms......................................................................................................................... 15
High Order Path Adaptation........................................................................................................... 15
Alarms and Status .................................................................................................................... 15
Low Order Path Termination .......................................................................................................... 16
V5 Processing........................................................................................................................... 16
J2 Processing ........................................................................................................................... 17
N2 Processing .......................................................................................................................... 18
K4 Processing........................................................................................................................... 18
Summary of Alarms causing E1 AIS......................................................................................... 19
Low Order Path Adaptation ........................................................................................................... 19
Desynchronizer......................................................................................................................... 19
Transmit Section, Terminal Mode ................................................................................................. 19
Low Order Path Adaptation ........................................................................................................... 20
Low Order Path Termination .......................................................................................................... 20
V5 Processing........................................................................................................................... 20
J2 Processing ........................................................................................................................... 21
K4 Processing........................................................................................................................... 21
N2 Processing .......................................................................................................................... 21
High Order Path Adaptation........................................................................................................... 21
Add/Drop Configuration................................................................................................................. 22
ADM Receive................................................................................................................................. 22
ADM Transmit................................................................................................................................ 22
Data Pass-Through.................................................................................................................. 23
MTBDATA Drive Enable ........................................................................................................... 24
Application Information.................................................................................................................... 25
Port Mapping Configuration.......................................................................................................... 25
Telecom Bus Interface ................................................................................................................... 26
Multiplexer Telecom Bus, Terminal Mode ...................................................................................... 26
Multiplexer Telecom Bus, ADM Mode............................................................................................ 26
MTBDATA Output Enable .............................................................................................................. 27
Demultiplexer Telecom Bus ........................................................................................................... 27
Telecom Bus Timing....................................................................................................................... 28
Serial/Remote Alarm Processing Port.......................................................................................... 31
2
ꢀ
LXT6251
Test Specifications ..................................................................................................................... 32
Microprocessor Interface & Register Definitions.................................................................... 42
Microprocessor Interface........................................................................................................ 42
Intel Interface........................................................................................................................... 42
Motorola Interface ................................................................................................................... 42
Interrupt Handling.................................................................................................................... 42
Interrupt Sources..................................................................................................................... 42
Interrupt Identification......................................................................................................... 43
Interrupt Enables..................................................................................................................... 43
Interrupt Clearing..................................................................................................................... 43
UpdateEn Configuration Bit..................................................................................................... 43
Register Address Map............................................................................................................. 44
Counter Access....................................................................................................................... 44
Register Notations and Definitions.......................................................................................... 44
Configuration Registers.......................................................................................................... 46
GLOB_CONF—Global Configuration (000H).......................................................................... 46
TADD_CONF—Transmit Add Configuration (003–001H) ....................................................... 47
TU_TS_CONF—TU Time Slot Configuration (161–175H)...................................................... 48
SIGLA_SET—Signal Label Setting (xEH)............................................................................... 48
J2_MRST—J2 Memory Reset (004H)..................................................................................... 48
J2_ESDATA—J2 Expected String Data (xCH)........................................................................ 49
J2_TSDATA—J2 Transmit String Data (xFH).......................................................................... 49
ERRI_CONF—Error Insert Configuration (xDH) ..................................................................... 50
INT_CONF—Interrupt Configuration Register (00BH) ............................................................ 51
CHIP_ID—Chip Identification Number (00AH)........................................................................ 51
Interrupt Registers................................................................................................................... 52
GLOB_INTS—Global Interrupt Source (00CH)....................................................................... 52
TRIB_ISRC—Tributary Interrupt Source Identification (00F–00DH) ....................................... 53
TRIB_INT—Tributary Interrupt (x1–x0H)................................................................................. 54
TRIB_INTE—Tributary Interrupt Enable (x5–x4H) .................................................................. 55
Status and Control Registers ................................................................................................. 56
TRIB_STA—Tributary Status (x3–x2H)................................................................................... 56
BIP2_ERRCNT—BIP2 Error Counter (x7–x6H)...................................................................... 56
REI_CNT—Remote Error Indication (REI) Counter (x9–x8H)................................................. 57
K4_STA—K4 Status (xAH)...................................................................................................... 57
V5_STA—V5 Status Register (xBH) ....................................................................................... 57
Testability Modes........................................................................................................................ 58
IEEE 1149.1 Boundary Scan Description............................................................................... 58
Instruction Register and Definitions......................................................................................... 59
3
ꢀ
LXT6251 21 E1 SDH Mapper
EXTEST (‘b00)............................................................................................................................ 59
SAMPLE/PRELOAD (‘b01)......................................................................................................... 59
BYPASS (‘b11)............................................................................................................................ 59
IDCODE (‘b10)............................................................................................................................ 59
Boundary Scan Register.................................................................................................................. 59
Package Specification ...................................................................................................................... 66
Glossary............................................................................................................................................. 67
4
ꢀ
LXT6251 Pin Assignments and Signal Descriptions
PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS
Figure 1: LXT6251 Pin Assignments
C
C
C
C
NC
GND_5
NC
1
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
GND_5
VCC_3
OE
2
GND_3
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
VCC_5
GND_5
A8
3
4
JTCK
5
JTMS
6
JTRST
JTDI
7
8
JTDO
9
SCANTEST
MTC21
MTD21
DTD21
DTC21
DTC20
DTD20
MTD20
MTC20
VCC_5
MTC19
MTD19
DTD19
DTC19
DTC18
DTD18
GND_3
VCC_3
MTD18
MTC18
GND_5
MTC17
MTD17
DTD17
DTC17
DTC16
DTD16
MTD16
MTC16
MTC15
VCC_5
MTD15
DTD15
DTC15
DTC14
DTD14
MTD14
MTC14
MTC13
MTD13
DTD13
DTC13
GND_3
GND_5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
A7
A6
A5
A4
A3
A2
A1
ꢀ
A0
GND_5
VCC_3
GND_3
CS
AS
WR/RW
RD/E
XXXX XXXX
(Date Code) (Trace Code)
INT
MCUTYPE
STMMODE
RST
VCC_5
MRAPDATA
MRAPCLK
MRAPFRM
DSAPFRM
DSAPCLK
DSAPDATA
NC
LXT6251Q E
XXXXXX
(Lot #)
DTC1
DTD1
MTD1
MTC1
MTC2
MTD2
DTD2
DTC2
VCC_3
NC
GND_5
5
ꢀ
LXT6251 21 E1 SDH Mapper
Table 1: Signal Description Nomenclature
Type
Description
Standard input signal
I
O
Standard output signal
Input and output signal
Supports TTL input levels
I/O
TTLin1
HiZ1
High Impedance
1. Some signals indicate buffer strength. For example, HiZ-4ma indicates a high-
impedance buffer capable of sourcing 4 ma.
Table 2: Pin Descriptions (Sheet 1 of 8)
Pin #
Name
Type
Function
E1 Transmit and Receive Ports
44
47
58
61
67
70
75
82
87
90
96
99
MTD1
MTD2
MTD3
MTD4
MTD5
MTD6
MTD7
MTD8
MTD9
I
Transmit Tributary NRZ Data Port # 1. Input E1 NRZ data
input at 2.048 Mbit/s
TTL in
I
Transmit Tributary NRZ Data Port # 2
Transmit Tributary NRZ Data Port # 3
Transmit Tributary NRZ Data Port # 4
Transmit Tributary NRZ Data Port # 5
Transmit Tributary NRZ Data Port # 6
Transmit Tributary NRZ Data Port # 7
Transmit Tributary NRZ Data Port # 8
Transmit Tributary NRZ Data Port # 9
Transmit Tributary NRZ Data Port # 10
Transmit Tributary NRZ Data Port # 11
Transmit Tributary NRZ Data Port # 12
Transmit Tributary NRZ Data Port # 13
Transmit Tributary NRZ Data Port # 14
TTL in
I
TTL in
I
TTL in
I
TTL in
I
TTL in
I
TTL in
I
TTL in
I
TTL in
MTD10
MTD11
MTD12
MTD13
MTD14
I
TTL in
I
TTL in
I
TTL in
109
112
I
TTL in
I
TTL in
6
ꢀ
LXT6251 Pin Assignments and Signal Descriptions
Table 2: Pin Descriptions – continued (Sheet 2 of 8)
Pin # Name Type
117 MTD15
Function
I
Transmit Tributary NRZ Data Port # 15
TTL in
121
126
130
137
141
146
45
MTD16
MTD17
MTD18
MTD19
MTD20
MTD21
MTC1
I
Transmit Tributary NRZ Data Port # 16
Transmit Tributary NRZ Data Port # 17
Transmit Tributary NRZ Data Port # 18
Transmit Tributary NRZ Data Port # 19
Transmit Tributary NRZ Data Port # 20
Transmit Tributary NRZ Data Port # 21
TTL in
I
TTL in
I
TTL in
I
TTL in
I
TTL in
I
TTL in
I
Transmit Tributary Clock Port # 1 Input E1 clock at 2.048
TTL in
MHz
46
MTC2
I
Transmit Tributary Clock Port # 2
Transmit Tributary Clock Port # 3
Transmit Tributary Clock Port # 4
Transmit Tributary Clock Port # 5
Transmit Tributary Clock Port # 6
Transmit Tributary Clock Port # 7
Transmit Tributary Clock Port # 8
Transmit Tributary Clock Port # 9
Transmit Tributary Clock Port # 10
Transmit Tributary Clock Port # 11
Transmit Tributary Clock Port # 12
Transmit Tributary Clock Port # 13
Transmit Tributary Clock Port # 14
TTL in
59
MTC3
I
TTL in
60
MTC4
I
TTL in
68
MTC5
I
TTL in
69
MTC6
I
TTL in
76
MTC7
I
TTL in
81
MTC8
I
TTL in
88
MTC9
I
TTL in
89
MTC10
MTC11
MTC12
MTC13
MTC14
I
TTL in
97
I
TTL in
98
I
TTL in
110
111
I
TTL in
I
TTL in
7
ꢀ
LXT6251 21 E1 SDH Mapper
Table 2: Pin Descriptions – continued (Sheet 3 of 8)
Pin #
119
Name
MTC15
Type
Function
I
Transmit Tributary Clock Port # 15
TTL in
120
127
129
138
140
147
43
MTC16
MTC17
MTC18
MTC19
MTC20
MTC21
DTD1
I
Transmit Tributary Clock Port # 16
Transmit Tributary Clock Port # 17
Transmit Tributary Clock Port # 18
Transmit Tributary Clock Port # 19
Transmit Tributary Clock Port # 20
Transmit Tributary Clock Port # 21
TTL in
I
TTL in
I
TTL in
I
TTL in
I
TTL in
I
TTL in
O
Receive Tributary NRZ Data Port # 1 Received E1 NRZ data
HiZ - 2mA
output from the demapped VC-12 at 2.048Mbit/s
48
DTD2
O
Receive Tributary NRZ Data Port # 2
Receive Tributary NRZ Data Port # 3
Receive Tributary NRZ Data Port # 4
Receive Tributary NRZ Data Port # 5
Receive Tributary NRZ Data Port # 6
Receive Tributary NRZ Data Port # 7
Receive Tributary NRZ Data Port # 8
Receive Tributary NRZ Data Port # 9
Receive Tributary NRZ Data Port # 10
Receive Tributary NRZ Data Port # 11
Receive Tributary NRZ Data Port # 12
Receive Tributary NRZ Data Port # 13
Receive Tributary NRZ Data Port # 14
HiZ - 2mA
57
DTD3
O
HiZ - 2mA
62
DTD4
O
HiZ - 2mA
65
DTD5
O
HiZ - 2mA
71
DTD6
O
HiZ - 2mA
74
DTD7
O
HiZ - 2mA
83
DTD8
O
HiZ - 2mA
86
DTD9
O
HiZ - 2mA
92
DTD10
DTD11
DTD12
DTD13
DTD14
O
HiZ - 2mA
95
O
HiZ - 2mA
100
108
113
O
HiZ - 2mA
O
HiZ - 2mA
O
HiZ - 2mA
8
ꢀ
LXT6251 Pin Assignments and Signal Descriptions
Table 2: Pin Descriptions – continued (Sheet 4 of 8)
Pin # Name Type
116 DTD15
Function
O
Receive Tributary NRZ Data Port # 15
HiZ - 2mA
122
125
133
136
142
145
42
DTD16
DTD17
DTD18
DTD19
DTD20
DTD21
DTC1
O
Receive Tributary NRZ Data Port # 16
Receive Tributary NRZ Data Port # 17
Receive Tributary NRZ Data Port # 18
Receive Tributary NRZ Data Port # 19
Receive Tributary NRZ Data Port # 20
Receive Tributary NRZ Data Port # 21
HiZ - 2mA
O
HiZ - 2mA
O
HiZ - 2mA
O
HiZ - 2mA
O
HiZ - 2mA
O
HiZ - 2mA
O
Receive Tributary Clock Port # 1. Received E1 clock at 2.048
MHz recovered from VC-12. This clock is gapped, data is valid
on the falling edge.
HiZ - 2mA
49
56
63
64
72
73
84
85
93
94
101
107
DTC2
DTC3
DTC4
DTC5
DTC6
DTC7
DTC8
DTC9
DTC10
DTC11
DTC12
DTC13
O
Receive Tributary Clock Port # 2
Receive Tributary Clock Port # 3
Receive Tributary Clock Port # 4
Receive Tributary Clock Port # 5
Receive Tributary Clock Port # 6
Receive Tributary Clock Port # 7
Receive Tributary Clock Port # 8
Receive Tributary Clock Port # 9
Receive Tributary Clock Port # 10
Receive Tributary Clock Port # 11
Receive Tributary Clock Port # 12
Receive Tributary Clock Port # 13
HiZ - 2mA
O
HiZ - 2mA
O
HiZ - 2mA
O
HiZ - 2mA
O
HiZ - 2mA
O
HiZ - 2mA
O
HiZ - 2mA
O
HiZ - 2mA
O
HiZ - 2mA
O
HiZ - 2mA
O
HiZ - 2mA
O
HiZ - 2mA
9
ꢀ
LXT6251 21 E1 SDH Mapper
Table 2: Pin Descriptions – continued (Sheet 5 of 8)
Pin #
114
Name
DTC14
Type
Function
Receive Tributary Clock Port # 14
O
HiZ - 2mA
115
123
124
134
135
143
144
DTC15
DTC16
DTC17
DTC18
DTC19
DTC20
DTC21
O
Receive Tributary Clock Port # 15
Receive Tributary Clock Port # 16
Receive Tributary Clock Port # 17
Receive Tributary Clock Port # 18
Receive Tributary Clock Port # 19
Receive Tributary Clock Port # 20
Receive Tributary Clock Port # 21
HiZ - 2mA
O
HiZ - 2mA
O
HiZ - 2mA
O
HiZ - 2mA
O
HiZ - 2mA
O
HiZ - 2mA
O
HiZ - 2mA
Telecom Bus Interface
204-197
196
MTBDATA <7:0>
MTBPAR
O
Multiplex Telecom Bus Data 7 to 0. This is a byte wide data
output at 19.44 Mbit/s for STM-1 or 6.48 Mbit/s for STM-0. The
output in STM-1 may be tri-stated for certain bytes depending on
the configuration of the device.
HiZ - 4mA
O
Multiplex Telecom Bus Parity. This is the parity check signal
calculated on the MTBDATA byte only. It is an odd parity and is
always a calculated value (i.e. the value is not passed through in
ADM).
HiZ - 4mA
193
191
MTBYCK
I
Multiplexer Telecom Bus Clock. This clock drives the multi-
plexer section at 6.48 MHz for STM-0 or 19.44MHz for STM-1.
TTLin
MTBJ0J1EN
I/O
Multiplex Telecom Bus Frame indicator. This indicates the
presence of the J0 and J1 bytes on the MTBDATA bus. Option-
ally configurable to also indicate H4 multiframe position, instead
of using MTBH4EN.
TTLin - 4mA
188
189
190
MTBH4EN
I/O
Multiplex Telecom Bus H4 multiframe Indicator. An output in
ADM mode, this is a 2 KHz signal that indicates the location of
the 00 value of H4. As input in terminal mode, the signal is sam-
pled during the J1 byte position given by MTBJ0J1EN.
TTLin - 4mA
MTBPAYEN
MTBTUGEN
I/O
Multiplex Telecom Bus Payload Enable. Indicates the position
of VC-4 in the STM-1 mode or VC-3 in the STM-0 mode. In an
ADM configuration the pin is an output while in the terminal
mode it is an input.
TTLin - 4mA
I
Multiplexer Telecom Bus TUG Enable. This pin is used in
STM-1 terminal applications and controls the TUG-3 in which
the LXT6251 will generate data. This pin should be tied to Vcc
for STM-0 terminal applications.
TTLin
10
ꢀ
LXT6251 Pin Assignments and Signal Descriptions
Table 2: Pin Descriptions – continued (Sheet 6 of 8)
Pin # Name Type
205 MTBDOE
Function
O
Multiplexer Telecom Bus Output Enable. Active Low output
enable signal that mirrors the internal MTBDATA data bus con-
trol. Its function is to enable an external tri-state bus driver that
should be used when the device is installed in a multi-card/back-
plane environment. Usually reserved for STM-1 use, the signal is
always active in STM-0
HiZ - 4mA
161 - 168
DTBDATA <7:0>
I
Demultiplexer Telecom Bus Data 7. This is a byte wide data
input at 19.44 Mbit/s for STM-1 or 6.48 Mbit/s for STM-0. In
STM-1 mode, the data is ignored if DTBTUGEN is Low.
TTLin
169
172
DTBPAR
DTBYCK
I
Telecom Bus Parity. This is parity check calculated on the DTB-
DATA byte only. It is an odd parity.
TTLin
I
Demultiplexer Telecom Bus Clock. This clock drives the
demultiplexer section at 6.48 MHz for STM-0 or 19.44MHz for
STM-1
TTLin
174
DTBJ0J1EN
I
Demultiplexer Telecom Bus Frame Indicator. This indicates
the position of J0 and J1 bytes on the DTBDATA bus. Optionally
configurable to also detect H4 multiframe position, instead of
using DTBH4EN.
TTLin
180
179
175
DTBH4EN
I
Demultiplexer Telecom Bus H4 multiframe Indicator. This is
a 2 KHz signal that indicates the location of the 00 value of H4.
This signal is sampled during the J1 pulse from DTBJ0J1EN.
TTLin
DTBPAYEN
DTBTUGEN
I
Demultiplexer Telecom Bus Payload Enable. Indicates the
position of VC-4 in the STM-1 mode or VC-3 in the STM-0
mode. This pin is always an input.
TTL-in
I
Demultiplexer Telecom Bus TUG Enable. This pin is used in
STM-1 applications and indicates the proper TUG-3 payload the
demultiplexer section should process. This pin is tied to VCC for
STM-0 applications.
TTLin
176
177
178
PTTUGA
PTTUGB
PTSOH
I
Pass-Trough TUG Enable-A. A High on this pin indicates the
TUG data received coincident with the pulse is to be passed
through to the MTBDATA output. Refer to “Add/Drop Configu-
ration” on page 22 for use of this pin. This pin should be tied
Low in STM-0 configuration or if unused.
TTLin
I
Pass-Trough TUG Enable-B. A High on this pin indicates the
TUG data received coincident with the pulse is to be passed
through to the MTBDATA output. Refer to “Add/Drop Configu-
ration” on page 22 for use of this pin. This pin should be tied
Low in STM-0 configuration or if unused.
TTLin
I
Pass-Trough SOH Enable. A High on this pin indicates the
SOH data, HPOH data, and VC-4 fixed stuff (STM-1) received
on the telecom bus is to be passed through to the MTBDATA out-
put. Refer to “Add/Drop Configuration” on page 22 for use of
this pin. This pin should be tied to ground in STM-0 or STM-1
terminal configurations or if unused.
TTLin
11
ꢀ
LXT6251 21 E1 SDH Mapper
Table 2: Pin Descriptions – continued (Sheet 7 of 8)
Pin #
Name
Type
Function
Serial Alarm Indication Ports
40
DSAPDATA
O
Serial Alarm Data. Output which provides a rapid indication of
the V5 byte parity error, TU-AIS, TU-Loss of pointer,
HiZ - 2mA
Unequipped detect, Trace ID mismatch, Signal Label mismatch
and VC-AIS alarm status for all 21 VC-12 channels. Refer to
“Serial/Remote Alarm Processing Port” on page 32 for details.
39
38
35
DSAPCLK
DSAPFRM
MRAPDATA
O
Serial Alarm Clock. Clock frequency is nominally 1.62MHz.
HiZ - 2mA
O
Serial Alarm Frame. Frame indicator active during the first bit
of the DSAPDATA data frame.
HiZ - 2mA
I
Serial Alarm Data. Input that contains indication of alarm status
resulting from the V5 byte parity error, TU-AIS, TU-Loss of
pointer, Unequipped detect, Trace ID mismatch, and Signal Label
mismatch, and VC-AIS for all 21 VC-12 channels. Refer to
“Serial/Remote Alarm Processing Port” on page 32 for details.
TTLin
36
37
MRAPCLK
MRAPFRM
I
Serial Alarm Clock input. The clock frequency is nominally
1.62MHz
TTLin
I
Serial Alarm Frame. Frame indicator that must be active during
TTLin
the first bit of the data frame on MRAPDATA.
Microprocessor Bus
14-22
4-11
A<8:0>
I
Address Bus. A nine bit address port for microprocessor access.
TTLin
DATA<7:0>
I/O
TTLin-6mA
Data Bus. Eight bit I/O data port for the microprocessor to read
and write data, commands, and status information to and from the
device.
28
WR/RW
I
Write signal (Intel); Read/Write signal (Motorola)
TTLin
29
26
RD/E
CS
TTLin
I
Read signal (Intel); Enable signal (Motorola)
Chip Select. Active Low signal to enable microprocessor RD or
WR action.
31
30
27
MCUTYPE
INT
I
Motorola/Intel Interface Mode Select. Low = Intel,
High = Motorola
TTLin
O
Interrupt. Active Low interrupt indication.
HiZ - 4mA
AS
TTLin
Address Latch Enable. Used by chip for systems where address
and data busses are multiplexed. Latches A<8:0> on the falling
edge. If address and data are not multiplexed, this pin should be
tied High.
JTAG Boundary Scan Test Functions
148
SCANTEST
TTLin-48PU Active Low Scan Test mode select with ~48 KOhm Pull-up resis-
tor. Should be left unconnected for normal operation.
12
ꢀ
Pin Assignments and Signal Descriptions
Table 2: Pin Descriptions – continued (Sheet 8 of 8)
Pin #
160
Name
SCANEN
Type
Function
ITTLin-48PU
Active Low Scan Enable with ~48 KOhm Pull-up resistor. Con-
trols all Scan FF muxes. Should be left unconnected for normal
operation.
153
JTCK
I
JTAG Clock. This signal has a ~48 KΩ Pull-up resistor. Clock
for the boundary scan circuitry. See “IEEE 1149.1 Boundary
Scan Description” on page 59 for details.
TTLin-48PU
152
151
150
JTMS
JTRS
JTDI
I
Test Mode Select. This signal has a ~48KΩ Pull-up resistor. This
pin determine state of TAP controller.
TTLin-48PU
I
Active low Reset. This signal has a ~35KΩ Pull-down resistor.
Should be left unconnected for normal device usage.
TTLin-35PD
ITTLin-48PU
Data Input. This signal has a ~48KΩ Pull-up resistor. Input sig-
nal used to shift in instructions and data. Should be left uncon-
nected for normal device usage.
149
154
JTDO
OEN
O
Data Output. Output signal used to shift out instruction and
data.
HiZ-2mA
Control Functions
I
Output Enable. This signal has a ~48KOhm Pull-up resistor.
Used to disable all output pins for bed of nails type testing or
other applications. When Low, all outputs are in high impedance
and all bi-directional pins are inputs. Should be left unconnected
for normal operation.
TTLin-48PU
33
32
RST
I
Chip Master Reset. This signal has a ~108KOhm Pull-up resis-
TTLin-108PUS tor. A low will reset all registers to default conditions. Input logic
is a schmidt trigger type.
STMMODE
I
STM Mode Select. Low = STM-0, High = STM-1
TTLin
Table 3: Power, Ground, and No Connects
Pin #
Name
Type
Power Supply
5V Supply for I/O ring
12, 34, 66, 91, 118, 139, 170, 195
VCC_5
GND_5
1, 13, 23, 52, 53, 77, 80, 104, 105, 128,
156, 157, 181, 187, 208
GND 5 Volts. Ground pins for 5 Volt supply.
24, 50, 78, 102, 103, 131, 155, 183, 184,
206, 207
VCC_3
3 V supply for core
3, 25, 54, 55, 79, 106, 132, 158, 159, 185, GND_3
186
GND 3 Volts. Ground pins for 3 Volt supply.
Not Connected. Unused
2, 41, 51, 171, 173, 182, 192, 194
NC
13
ꢀ
LXT6251 21 E1 SDH Mapper
FUNCTIONAL DESCRIPTION
Introduction
Receive Section, Terminal
Mode
The LXT6251 performs mapping and demapping of 21
channels of E1 PDH tributaries into and out of the SDH
hierarchy. It supports two system configurations, terminal
or Add/Drop multiplexing, and two operating frequencies,
STM-0 or STM-1. In the terminal configuration, the
transmit section maps 21 tributaries of E1 data into 21 VC-
12 virtual containers, formatted as a C-3 in STM-0 or as a
TUG-3 in STM-1. The terminal receiver processes either a
C3 or a TUG-3 payload and outputs 21 E1 tributaries after
processing the VC-12 path overhead. In the Add/Drop
configuration, the receiver processes any number of TU-12
containers up to its capacity of 21, and passes the non-
dropped portion of the payload to the transmitter where the
added E1/TU-12 tributaries are multiplexed and output.
At the Telecom Bus input point (DTBDATA), the Mapper
expects to receive byte wide data that has been processed
by the LXT6051 OHT or an other overhead terminator up
to the higher order path terminator (HPT) point. The
Mapper thus receives data that minimally contains C-3 or
C-4 payload data along with the Telecom Bus timing
signals DTBJ0J1EN, DTBPAYEN, DTBH4EN, and
DTBTUGEN (STM-1 only) which synchronize the internal
timing generator to the data. The timing generator in turn
drives 21 identical demapper blocks to process the
appropriate TU-12 signals.
Refer to “Telecom Bus Interface” on page 26 for a detailed
discussion of the Telecom bus signals. Refer to the block
diagram below for the following discussion of a single TU-
12 demultiplexer block. The remaining 20 blocks operate
in an identical manner but with different timing signals.
The discussion will focus first on the terminal functions,
which describe the E1 to SDH process used in the terminal
mode as well as those E1 channels in the add/drop mode.
Following the terminal functions, the configuration details
of the add/drop mode are presented. Further details about
the configuration of the LXT6251 with the LXT6051 in
different system configurations can be found in a
companion document, Application Note AN9801:
LXT6051/LXT6251 SDH Chipset.”
Figure 2: LXT6251 Block Diagram
Low order
Connection
Supervision
Lower order Path
Term ination
Higher order
Path Adaption
Lower order Path
Adaption
M TBDO E
M TBPAR
M TD<1:21>
M TC<1:21>
VC-12
Unequipped
Generator
LUG
TU Pointer
Generation
HPA
ADM
Control
M TBDATA<7:0>
FIFO
S/P
LPA
POH
LPT
M TBYCK
M RAPDATA
M RAPCLK
M RAPFRM
M TBJ0J1EN
M TBPAYEN
M TBH4EN
M TBTUG EN
Rem ote
Alarm
Processing
A<8:0>
STM M O DE
M CUTYPE
Tim ing Control
DATA<7:0>
CS
W R/RW
AS
Synchronous Equipm ent Managem ent Function (SEMF) Interface
Alarm & Control Mem ory
INT
RD/E
DTBYCK
DSAPDATA
DSAPCLK
DSPAFRM
DTBJ0J1EN
DTBPAYEN
DTBTUGEN
DTBH4EN
DTBPAR
Serial
Alarm
Processing
DTD<1:21>
DTC<1:21>
VC-12
POH
TU Pointer
Processing
HPA
Desynchronizer
& FIFO
DTBDATA<7:0>
P/S
LPT/LPOM
LPA
PTSO H
Lower order Path Term ination
and Overhead Monitor
Higher order Path
Adaption
Lower order Path Adaption
O EN
RST
PTTUG A
PTTUG B
14
ꢀ
Functional Description
Figure 3: V1/V2 Pointer Diagram
Receive Alarms
There are two alarms associated with the Telecom bus
interface.
1
2
3
4
5
6
7
I
8
1
I
2
3
I
4
5
I
6
7
I
8
NDF NDF NDF NDF
S
S
D
D
D
D
D
V1
V2
Parity Alarm
The receive telecom bus data integrity is monitored
with a single odd parity bit. The parity is calculated
over the DTBDATA bus only. The mapper checks the
parity for errors every 500mS multiframe and
indicates an alarm in GLOB_INTS—Global Interrupt
Source (00CH) (page 53) if there are more than 16
errors within the 500mS time window. The interrupt is
maskable in INT_CONF—Interrupt Configuration
Register (00BH) (page 51).
After achieving a normal pointer state, the processor will
continually monitor V1 and V2 for the following events:
• Positive Justification from the inversion of the I bits
(3 of 5 majority decision)
• Negative Justification from the inversion of the D bits
(3 of 5 majority decision)
• New pointer value from 3 new valid values in a row
Loss of Multiframe
• New pointer value from single NDF indication (if in
Normal or AIS state only)
A loss of multiframe alarm is detected if the
DTBH4EN signal is always low. The alarm status and
interrupt is indicated in GLOB_INTS—Global
Interrupt Source (00CH) (page 53).
• All 1’s condition on the V1/V2 bytes
• Invalid pointer values occurring 8 times in a row to
trigger a LOP alarm
Consequent Actions:
• Reception of NDF indication 8 times in a row to
trigger a LOP alarm
• An LOM alarm will cause the SF alarm bit on the
SAP bus to be high for all 21 tributaries. The SF
alarm is used to indicate errors that should cause
a VC path protection event. The SAP bus is
described in detail in “Serial/Remote Alarm
Processing Port” on page 32.
Alarms and Status
TU-AIS
If 3 consecutive TU pointers in the all 1’s (AIS) state
are detected, the TU-AIS status bit in TRIB_STA—
Tributary Status (x3–x2H) (page 57) is set. It is
cleared when either the LOP or Normal states are
entered. Whenever the TU-AIS status changes the
TU-AIS interrupt bit in TRIB_INT—Tributary
Interrupt (x1–x0H) (page 55) is set.
High Order Path Adaptation
Within each of the 21 TU-12 demapper blocks, the telecom
bus data bytes first enter the higher order path adaptation
(HPA) block for TU-12 pointer interpretation. The TU-12
pointer is contained in the V1 and V2 bytes shown below.
The 8 bits of V2 and the 2 LSB bits of V1, shown as I and
D bits, represent a binary number that represents the
number of TU-12 bytes between the V5 POH byte and V2.
The SS bits identify Tributary type, and the remaining 4
bits represent a New Data Flag (NDF). Based on the
incoming J0J1, Payload, and H4 timing signals, the V1 and
V2 bytes are located and interpreted. The pointer
interpreter state machine follows the state diagram
provided in the Appendix of ITU-T G.783. The variable N
in that specification, which specifies the number of invalid
pointers required to enter the Loss of Pointer state, is set to
eight (8) in the LXT6251. When a valid pointer is found
(a valid pointer defined as being between the values 0 and
139), the pointer processing block will synchronize the TU
timing block and remove the Loss of Pointer (LOP) alarm.
Consequent Actions:
• An RDI Indication will be sent to the transmitter
via the SAP interface. The RDI indication will
be set on the transmitted V5 byte unless the
XmtLptRdiEn bit in ERRI_CONF—Error Insert
Configuration (xDH) (page 51) is set to 0
• Outgoing E1 data on DTDx will be forced to AIS
with derived 2.048MHz clock on DTCx
TU Loss of Pointer (LOP)
If an invalid pointer state is detected in the TU
pointer, the TU-LOP status bit in TRIB_STA—
Tributary Status (x3–x2H) (page 57) is set. An invalid
15
ꢀ
LXT6251 21 E1 SDH Mapper
pointer state is entered from either the normal or AIS
pointer state after 8 consecutive invalid pointer values
or 8 consecutive NDF pointers are detected. It is
exited when either the LOP or Normal states are
entered at which time the TU-LOP status bit in
TRIB_STA—Tributary Status (x3–x2H) (page 57) is
cleared. Whenever the TU-LOP status changes the
TU-LOP interrupt bit in TRIB_INT—Tributary
Interrupt (x1–x0H) (page 55) is set.
V5 Processing
BIP-2 Errors (V5, bits 1,2)
The LPT block continually calculates the BIP-2 value
by generating a two-bit parity, starting with V5. After
receiving the 140 bytes in a multiframe, the calculated
value is compared with the first two bits of the next
V5 and if a mismatch between the calculated and
received BIP-2 is detected a BIP-2 error interrupt is
generated in TRIB_INT—Tributary Interrupt (x1–
x0H) (page 55). BIP-2 mismatches are also counted
with results available in BIP2_ERRCNT—BIP2 Error
Counter (x7–x6H) (page 57). The BIP2 counters can
Consequent Actions:
• An RDI alarm will be sent to the transmitter via
the SAP interface. The RDI alarm will be set in
the transmitted V5 byte unless the XmtLptRdiEn
bit in ERRI_CONF—Error Insert Configuration
(xDH) (page 51) is set to 0
be
configured
from
GLOB_CONF—Global
Configuration (000H) (page 47) to count either two
possible counts per multiframe (bit count) or one
possible count per multiframe (block count). The
counter will count to a maximum of 4095, which
exceeds the maximum number of bit alarms in one
second and the maximum number of block errors in
two seconds. If the counter overflows, an Overflow
interrupt is generated in TRIB_INT—Tributary
Interrupt (x1–x0H) (page 55) and the count recycles
to zero.
• Outgoing E1 data on DTDx will be forced to AIS
with derived 2.048 MHz clock on DTCx.
Low Order Path Termination
After the TU Timing control has been updated by the
pointer interpreter, the received data is processed by the
lower order path termination (LPT) block which terminates
the POH bytes of each VC-12, and records all information
extractable from the POH for processing by the
microprocessor. For the V5 byte this includes counting
BIP-2 and REI errors and monitoring the RDI, RFI and
signal label bits. For the J2 Path Trace byte this includes
monitoring the Path trace identification and CRC-7 alarms,
and for the K4 byte this includes monitoring enhanced RDI
information. All alarm indications and counts are available
via the microprocessor interface, with the RDI, REI, VC-
AIS, and BIP errors additionally fed to the Serial alarm port
(SAP) for real-time tributary alarm indication and remote
alarm processing.
To read the BIP counter registers, the microprocessor
must first perform a write (any value) to either
(x6H,x7H), then wait at least three cycles of
DTBYCK (0.5uS in STM-0) before reading the two
registers. The write action latches the counter value
into the two registers, and clears the counter to zero.
Consequent Actions:
• REI indication will be sent to the transmitter via
the SAP interface. The REI indication will be set
on the transmitted V5 byte unless the
XmtLptReiEn bit in ERRI_CONF—Error Insert
Configuration (xDH) (page 51) is set to 0.
Figure 4: V5 Byte
REI Detection (V5, bit 3)
5
6
7
1
2
3
4
8
The LPT block continually monitors the value of the
REI bit and sets the REI interrupt bit in TRIB_INT—
Tributary Interrupt (x1–x0H) (page 55) whenever it is
found to be ‘1’ (an event).
Signal Label
BIP 2
REI RFI
RDI
These events are also counted with results available in
REI_CNT—Remote Error Indication (REI) Counter
(x9–x8H) (page 58). The counter will count to a
maximum of 2047, which is more than the maximum
number of REI alarms within one second. If the
counter overflows, an Overflow interrupt is generated
in TRIB_INT—Tributary Interrupt (x1–x0H) (page
55) and the count recycles to zero.
16
ꢀ
Functional Description
To read the REI counter registers, the microprocessor
must first perform a write (any value) to either
register (x8H, x9H), then wait at least three cycles of
DTBYCK (0.5uS in STM-0) before reading the two
registers. The write action latches the counter values
into the two registers, and clears the counter to zero.
unless the XmtLptRdiEn bit in ERRI_CONF—
Error Insert Configuration (xDH) (page 51) is set
to 0. No indication is sent in Supervisory mode.
• Outgoing E1 data on DTDx will be forced to AIS
with derived 2.048MHz clock on DTCx
VC-AIS Detection (V5, bits 5-7)
Consequent Actions: none
If the signal label is detected as ‘111’ in any one
multiframe, a VC-AIS alarm will be indicated on the
SAP bus. There is no internal alarm or interrupt
associated with this alarm, and no hysteresis filtering.
If the SAP bus is used to control protection switching
at the TU-12 level, it is recommended that hysteresis
filtering be added to this alarm in the external circuit.
RFI Detection (V5, bit 4)
The LPT block continually monitors the value of the
RFI bit and updates the RFI status bit in
TRIB_STA—Tributary Status (x3–x2H) (page 57)
with its detected value (there is no filtering or
hysteresis on this bit). Whenever the RFI status bit
changes the RFI interrupt bit in TRIB_INT—
Tributary Interrupt (x1–x0H) (page 55) is set.
VC-AIS is treated like a signal label mismatch. Thus,
consequent actions follow SLM actions.
Consequent Actions: none
Consequent Actions:
• A VC-AIS/SF Indication will be output on the
SAP interface.
Signal Label Mismatch (V5, bits 5-7)
A signal label mismatch (SLM) status bit will be set
in TRIB_STA—Tributary Status (x3–x2H) (page 57)
if the signal label does not match a valid pattern that
can be processed by this chip for five multiframes.
Valid label values are 000 (Unequipped), 001
(Equipped, non-specific), and 010 (Equipped,
asynchronous). It is cleared when the signal label
equals a valid pattern for five multiframes.
RDI Detection (V5, bit 8)
The LPT block continually monitors the value of the
RDI bit and updates the RDI status bit in
TRIB_STA—Tributary Status (x3–x2H) (page 57)
with its detected value (after five consecutive frames).
Whenever the RDI status bit changes the RDI
interrupt bit in TRIB_INT—Tributary Interrupt (x1–
x0H) (page 55) is set.
Whenever the SLM status bit changes the SLM
interrupt bit in TRIB_INT—Tributary Interrupt (x1–
x0H) (page 55) is set.
Consequent Actions: none
Consequent Actions:
J2 Processing
• Outgoing E1 data on DTDx will be forced to AIS
with derived 2.048MHz clock on DTCx
J2 Trace Identifier processing is supported on a per
tributary basis for both transmit and receive paths.
Within the receive section of each tributary, the
RxJ2Access bit in TRIB_INTE—Tributary Interrupt
Enable (x5–x4H) (page 56) controls the support for J2
processing. When RxJ2Access is a ‘1’, both the J2
Path Label Mismatch and the CRC-7 error detection
alarms are completely masked. In this state the
microprocessor is also able to access the J2 RAM cell
of the tributary. This is the default state after a power-
up condition. When RxJ2Access is ‘0’, the two alarms
are enabled, and the microprocessor cannot access the
J2 RAM.
Unequipped Detection (V5, bits 5-7)
The Unequipped (UNEQP) status bit will be set in
TRIB_STA—Tributary Status (x3–x2H) (page 57) if
a ‘000’ is detected in the signal label for five
consecutive multiframes. It is cleared when the signal
label equals a pattern other than ‘000’ for five
consecutive multiframes.
Whenever the UNEQP status bit changes the UNEQP
interrupt bit in TRIB_INT—Tributary Interrupt (x1–
x0H) (page 55) is set.
Consequent Actions:
J2 Memory Access
• If the global Unequipped configuration is not set
to Supervisory, an RDI Indication will be sent to
the transmitter via the SAP interface. The RDI
indication will be set on the transmitted V5 byte
The J2 RAM for each tributary is indirectly accessible
by the microprocessor. That is, there is a single data
port to access the data, while the address is internally
17
ꢀ
LXT6251 21 E1 SDH Mapper
generated and automatically incremented as the J2
RAM byte is read or written. The following procedure
should be followed to correctly program the J2 RAM.
Whenever the CRC7Err status bit changes the
CRC7Err interrupt bit in TRIB_INT—Tributary
Interrupt (x1–x0H) (page 55) is set.
• Ensure that RxJ2Access is set to ‘1’ in
TRIB_INTE—Tributary Interrupt Enable (x5–
x4H) (page 56).
Consequent Actions: none
Trace Identifier Mismatch
The chip compares the received J2 string with the one
stored in memory. If the calculated CRC-7 matches
that of the received value, but there are errors in the
comparison of the remaining 15 bytes, the TIM status
bit is set in TRIB_STA—Tributary Status (x3–x2H)
(page 57). There is no filtering of this alarm, since the
CRC-7 match will indicate the J2 word has been
received without error. The TIM status bit is cleared
when the J2 string is received without errors.
• Write (any value) to J2_MRST-- J2 Memory
reset (008H) page 50. This resets the global
counter used to generate the RAM address. This
step is only required once if multiple tributaries
are being programmed.
• Write the 16 bytes of the J2 word consecutively
to J2_ESDATA—J2 Expected String Data (xCH)
(page 50). Each toggle of the write (or read) will
increment the internal counter in DMA fashion.
Whenever the TIM status bit changes the TIM
interrupt bit in TRIB_INT—Tributary Interrupt (x1–
x0H) (page 55) is set.
If write verification is desired, the microprocessor can
now read 16 bytes in DMA fashion. The internal
address counter resets to 0 after the 16 writes.
Consequent Actions:
Once the RAM is filled and verified, the RxJ2Access
bit can be set to ‘0’ to enable the alarms.
• An RDI Indication will be sent to the transmitter
via the SAP interface
Note that all 16 bytes should be written to the RAM
by the microprocessor. The CRC-7 byte is not needed
in the receiver RAM (the received CRC-7 byte is
compared with a calculated value only), however the
microprocessor must write some value on the first
write to align the remaining 15 words in the RAM.
• Outgoing E1 data toward the PDH network will
be forced to AIS with derived 2.048MHz clock
N2 Processing
N2 processing is not implemented at this time.
During normal operation with J2 support, the
RxJ2Access bit should be set to ‘0’, allowing the
alarms associated with J2 to be generated. As data is
received, each J2 byte is analyzed until the CRC-7
byte is found, which is distinguished from the other
15 bytes by having a 1 in the most significant bit. The
CRC-7 byte is stored, then the following 15 bytes are
used to calculate a CRC-7 value and compared with
successive locations in the RAM. The CRC-7 byte is
never compared with the contents of the J2 RAM.
K4 Processing
The K4 byte contains a protection function and an
Enhanced RDI (ERDI) function. The LXT6251
supports the ERDI function. No alarms or interrupts
will be generated based only on the K4 ERDI
information The V5 RDI bit generates the alarms.
Enhanced RDI
Upon detection of a V5 RDI alarm, K4_STA—K4
Status (xAH) (page 58) can be accessed to determine
the nature of the RDI alarm, assuming the trail
termination source supports the K4 ERDI processing.
The following defects are supported in the ERDI
Two alarms can be generated: the Trace Identifier
Mismatch (TIM) and the CRC-7 mismatch (CRC7).
CRC-7 Error
The chip calculates the CRC-7 value over the 15 bytes
of the received J2 string. This value will be compared
with the received CRC-7 byte. If the calculated and
received CRC-7 bytes do not match, the J2 CRC-7
error (CRC7Err) status bit is set in TRIB_STA—
Tributary Status (x3–x2H) (page 57). If the calculated
and received CRC-7 bytes do match, the CRC7Err
status bit is cleared.
Table 4: Enhanced RDI Interpretation
K4,
bit 5
K4,
bit 6
K4,
bit 7
Alarm
No Alarm
0
X
X
1. Note: The bit numbers above reference a byte whose least sig-
nificant bit is bit 8.
18
ꢀ
Functional Description
The data at this point is still parallel and therefore needs to
be converted to serial and a relatively smooth 2.048MHz
clock generated. The degapper circuit performs these
functions.
Table 4: Enhanced RDI Interpretation
K4,
K4,
K4,
Alarm
bit 5
bit 6
bit 7
1
1
1
1
0
1
0
1
0
1
1
0
Non-specific RDI alarm
Non-specific RDI alarm
TU-AIS, TU-LOP
TIM, UNEQ
Desynchronizer
The LXT-6251 implements a bit leaking function to
reduce the multiplexing jitter that is created during
both the E1 to VC-12 stuffing process and SDH
pointer movements at both the AU and TU level. The
input to the degapper is the byte parallel clock, byte
data, TU timing information, and indications of
pointer movement from the TU level. The degapper
block first interprets the stuffing indicators and
extracts the proper data, then attempts to smooth the
clock, anticipating gaps created by the frame, TU
pointer movements, and stuffing. The output of the
degapper directly feeds to output pins (DTCx/DTDx)
and consists of a relatively smooth E1 clock (and
NRZ data) in which the large gaps from pointer
movements have been distributed over a period of
time. In order for the E1 output to conform to G.783
residual jitter requirements, an external jitter
attenuation circuit is required, such as that available in
San Francisco Telecom’s octal digital interface, the
LXT6282 or Level One’s LXT318 Line Interface
with Jitter Attenuator.
1. Note: The bit numbers above reference a byte whose least sig-
nificant bit is bit 8.
Summary of Alarms causing E1 AIS
A number of alarms cause the LXT6251 to generate
an all 1’s AIS signal at the E1 output port. The
following list summarizes those alarm and the
conditions.
TU-AIS Alarm. V1/V2 = FFh for 8 consecutive
multiframes
TU-LOP Alarm. V1/V2 invalid for 8 consecutive
multiframes
Signal Label Mismatch. Signal Label invalid for 5
consecutive multiframes.
considered as an SLM.
A
VC-AIS is also
The external jitter attenuator must meet the following
specifications or the final output jitter cannot be
guaranteed to meet ITU G.783:
Unequipped Alarm. Signal Label set to ‘000’ for 5
consecutive multiframes (either supervisory or non-
supervisory mode)
• Loop Bandwidth of 3 Hz or lower
• An elastic buffer of at least 32 bits
J2 Path Label Mismatch. 16 byte J2 string has
correct CRC-7 but does not match expected value.
• First or second order loop. Second order is
recommended for best performance
The AIS consequent action from these alarms cannot
be disabled with the exception of the J2 mismatch,
which can be disabled via the use of the RxJ2Access
bit. A Loss of multiframe should also cause an E1 AIS
condition, however there is no direct action taken by
the device to generate the AIS, the incoming Telecom
bus data should already be in AIS.
Transmit Section, Terminal
Mode
At the MTDx/MTCx input pins, the Mapper expects to
receive asynchronous E1 signals in the form of NRZ data
and clock. The mapper also requires the Telecom Bus
timing signals MTBJ0J1EN, MTBPAYEN, MTBH4EN,
and MTBTUGEN (STM-1 only) to drive the internal
timing machine. Refer to “Telecom Bus Interface” on
page 26 for details on these timing signals.
Low Order Path Adaptation
After processing by the Path Overhead Terminator, the data
is passed to the lower order path adaptation (LPA) block.
First, the three C1C2 bits are processed and a majority
decision made as to the value of the two stuffing indicator
bits. A majority of 1’s for Cx indicates the associated Sx bit
is data, while majority Ø’s indicates the Sx bit is stuff and
should be ignored. This is then used along with other
timing inputs to extract the E1 payload data.
The E1 signal must be valid and within frequency
tolerance. Should there be a Loss of Signal alarm on an E1
input to the line interface circuits prior to the LXT6251, it
is the responsibility of the LIU or other external element to
19
ꢀ
LXT6251 21 E1 SDH Mapper
generate a valid E1 clock and AIS signal. The LXT6251
does not support a method to generate a mapped E1 AIS
signal.
should be set to ‘1’. Two bits in ERRI_CONF—Error
Insert Configuration (xDH) (page 51) can modify the
setting of the REI bit. First, the XmtLptReiEn bit can
be set to ‘0’ to disable the automatic response to the
RAP data. By default this bit is set to ‘1’. Second, the
XmtLptRdiFrc can be set to ‘1’ to force the REI bit to
be set to ‘1’ as long as this register bit is set. By
default this bit is set to ‘0’.
Low Order Path Adaptation
The E1 data and clock pairs immediately enter the first-in
first-out memory within the lower order path adaptation
(LPA) block. The LPA block receives timing information
from the master timing control block to identify the frame
positions of the Information (I) bytes, the stuffing
indicators C1C2, and the stuffing bits S1 and S2. This
timing, along with the depth of the FIFO is used to
determine the stuffing decisions for each multiframe. The
data out of the FIFO is converted to parallel bytes at each I
byte position, and the appropriate stuffing indicators and
stuffing bits added during the appropriate time slots. The
output of the LPA block thus consists of a C12 container,
which includes I bytes, R bytes, and stuffing indicator bytes
also containing four O bits. The LXT6251 sets both the R
bytes and the O bits to ‘0’.
RFI Bit
The Remote Failure Indication bit as of yet has no
standard definition that would allow automatic
generation with the LXT6251. Therefore, the RFI bit
can only be set by the microprocessor via the RFISet
bit in SIGLA_SET—Signal Label Setting (xEH)
(page 49).
Signal Label
The transmitted signal label is set to the value
contained in the three SigLabelSet bits in
SIGLA_SET—Signal Label Setting (xEH) (page 49).
By default, the value is set to ‘010’ which indicates
the VC-12 is mapped asynchronously. This value can
be set to ‘001’ for equipped non-specific, or to ‘000’
to indicate the channel is unequipped.
Low Order Path Termination
Next the LPT function adds the path overhead bytes V5, J2,
N2, and K4. The following descriptions detail the POH
bytes and the supported bits within each byte.
Setting the SigLabelSet bits to ‘000’ indicates that a
TU tributary is unused. By doing so, the chip will
generate an unequipped VC-12 signal. If the
V5 Processing
UNEQMode
bit
in
GLOB_CONF—Global
Configuration (000H) (page 47) is set to ‘0’, the result
will be a VC-12 with all bytes set to ‘0’ except the V5
BIP-2. If UNEQMode is set to ‘1’, indicating
Supervisory Unequipped mode, the resulting
unequipped signal will additionally contain a valid J2,
valid REI and RDI bits within the V5 byte, and N2 set
to 00h.
BIP-2
As the LPT block is generating the VC-12, a 2 bit Bit
Interleave Parity (BIP-2) value is being calculated on
all the bytes. At the end of the multiframe, the BIP-2
value is inserted into the following V5 byte (see
Figure 4).
To aid the system designer in the testing phase, the
LXT6251 includes a BIP error generator that is
enabled by setting the BipInv bit in ERRI_CONF—
Error Insert Configuration (xDH) (page 51). The
default value is ‘0’, and the BIP value is not affected.
When set to ‘1’, the calculated BIP value will be
inverted on every V5 byte, simulating a degraded VC-
12 for a receiver.
It is important to set the Signal Label to a valid value.
An invalid value will be detected in a receiver as a
Signal Label mismatch alarm with a consequent
action of generating an AIS signal at the output E1
port.
RDI Bit
The RDI bit is updated every multiframe by
monitoring the receive side status data on the Remote
Alarm Port (RAP). The RAP port is further described
in “Serial/Remote Alarm Processing Port” on
page 32. If the corresponding receive side TU-12
tributary detects defects consisting of TU-AIS, TU-
LOP, J2 TIM, or UNEQ, the RAP port will indicate to
the transmit LPT block that the RDI bit should be set
to ‘1’. There are two bits in ERRI_CONF—Error
REI Bit
The Remote Error Indication bit is updated every
multiframe by monitoring the receive side status data
on the Remote Alarm Port (RAP). The RAP port is
further described in “Serial/Remote Alarm Processing
Port” on page 32. If the corresponding receive side
TU-12 tributary detects BIP-2 errors, the RAP port
will indicate to the transmit LPT block that the REI bit
20
ꢀ
Functional Description
Insert Configuration (xDH) (page 51) that can modify
the setting of the RDI bit. First, the XmtLptRdiEn bit
can be set to ‘0’ to disable the automatic response to
the RAP data. By default this bit is set to ‘1’. Second,
the XmtLptRdiFrc can be set to ‘1’ to force the RDI
bit to be set to ‘1’ as long as this register bit is set. By
default this bit is set to ‘0’.
All 16 bytes are written to the RAM by the
microprocessor. This places a requirement on the
microprocessor that it must calculate the CRC-7 byte
on the 15 byte Path Trace ID and write the calculated
CRC-7 byte in the first position of the J2 RAM.
K4 Processing
The chip supports generation of the enhanced RDI
function if the TxK4En configuration bit is set in
GLOB_CONF—Global Configuration (000H) (page
47). All other bits in the K4 byte will be set to ‘0’. The
alarm status received on the RAP port will drive the
K4 byte as follows:
J2 Processing
J2 Trace Identifier processing support can be enabled
on a tributary per tributary basis for the transmit path.
Within the transmit section of each tributary, the
XmtJ2Access bit in ERRI_CONF—Error Insert
Configuration (xDH) (page 51) controls the support
for J2 processing. When XmtJ2Access is a ‘1’, the
power up default state, J2 transmission is disabled,
and the value ‘00h’ (Unequipped mode) or ‘01’h
(Supervisory Unequipped mode) is sent on every J2
byte. Additionally, in this state the microprocessor is
able to read and write to the J2 RAM cell of the
tributary. When XmtJ2Access is ‘0’, the value
contained in the J2 RAM is transmitted, and the
microprocessor is not able to access the J2 RAM.
Table 5: Enhanced RDI Generation
K4,
bit 5
K4,
bit 6
K4,
bit 7
Alarm
0
0
0
No Alarm or
TxK4En not set
1
1
1
0
1
1
1
0
1
TU-AIS, TU-LOP
TIM, UNEQ
Forced RDI Alarm
J2 Memory Access
The J2 RAM for each tributary is indirectly accessible
by the microprocessor. That is, there is a single data
port to access the data, while the address is internally
generated and automatically incremented as the J2
RAM byte is read or written. The following procedure
should be followed to correctly program the J2 RAM.
1. Note: The bit numbers above reference a byte whose least sig-
nificant bit is bit 8
The forced RDI condition is set by setting the
XmtLptRdiFrc bit in ERRI_CONF—Error Insert
Configuration (xDH) (page 51) to ‘1’.
• Ensure that XmtJ2Access is set to ‘1’ in
ERRI_CONF—Error Insert Configuration (xDH)
(page 51).
N2 Processing
N2 processing is not implemented at this time. The
transmitted value for the N2 byte is ‘00000000’.
• Write (any value) to J2_MRST-- J2 Memory
reset (008H) page 50. This resets the global
counter used to generate the RAM address. This
step is only required once if multiple tributaries
are being programmed.
High Order Path Adaptation
After low order path termination, the completed 35 byte by
4 multiframe VC-12 data enters the HPA block. At this
stage, the four pointer bytes V1-V4 are added to complete
the 36 byte by 4 multiframe TU-12. Since there is no
mechanism that would require pointer processing, the V1
and V2 bytes are statically set with a pointer value of 16,
the New Data Flag set to the normal value of ‘0110’ and the
SS bits set to 01, identifying the payload as E1 traffic. The
values of V3 and V4 are set to ‘00’h.
• Write the 16 bytes of the J2 word consecutively
to J2_TSDATA—J2 Transmit String Data (xFH)
(page 50). Each toggle of the write (or read) will
increment the internal counter in DMA fashion
• If write
verification
is desired, the
microprocessor can now read 16 bytes in DMA
fashion. The internal address counter resets to 0
after the 16 writes.
With all 21 tributaries generated up to the TU-12 level, the
final stage of the HPA block formats the data into the
appropriate higher order path container. In STM-0, the
output is a 86 byte by 9 column C3 container, consisting of
• Once the RAM is filled and verified, the
XmtJ2Access bit can be set to ‘0’ to enable the
transmit J2 word.
21
ꢀ
LXT6251 21 E1 SDH Mapper
seven interleaved TUG-2 structures and the two columns of
fixed stuff at columns 30 and 59. In STM-1, the output is
an 86 byte by 9 column TUG-3 structure consisting of
seven interleaved TUG-2 structures and the two columns of
fixed stuff at columns 1 and 2. The TUG-3 data is output
onto the MTBDATA bus when MTBTUGEN is a ‘1’.
When the MTBTUGEN is ‘0’, the output is in tri-state,
allowing other LXT6251 devices to share the MTBDATA
bus. For configurations where each LXT6251 is installed
on separate cards interconnected via a backplane, the
MTBDOE pin can be used to drive the enable pin of an
external tri-state driver. The signal is high whenever the
MTBDATA bus contains valid data.
ADM Receive
The receive section of the LXT6251 operates essentially
the same in ADM mode as it does in terminal mode. The
key difference is the Port Mapping function mentioned
above. Details of the Port Mapping function can be found
in Port Mapping Configuration (page 25). As in terminal
mode, the LXT6251 expects at the Telecom Bus input to
receive C-3 or C-4 payload data along with the Telecom
Bus signals DTBJ0J1EN, DTBPAYEN, DTBTUGEN and
DTBH4EN timing signals to synchronize the receive
timing generator to the data. From the Telecom bus input
out to the E1 port output, the tributaries behave as in
terminal mode; all tributaries are processed and all alarms
are enabled, unless masked by the appropriate IRQ Mask
Registers. To minimize unnecessary alarm information, it
is recommended that the alarms from those channels that
are passed through be completely masked unless required
for monitoring purposes. The final output of the receiver
will be E1 data.
The final output also includes an odd parity bit on the
MTBPAR pin calculated over the output MTBDATA byte.
Add/Drop Configuration
The LXT6251 can be configured to operate as an Add/Drop
multiplexer by setting the OpMode bit in GLOB_CONF—
Global Configuration (000H) (page 47) to ‘1’. This causes
a number of internal configurations to change from the
terminal mode:
ADM Transmit
Most functions of the transmit section operate the same in
ADM mode as in Terminal mode. There are a few
important differences however. First, in ADM mode, the
timing of the transmitter is controlled by the receive
telecom bus signals DTBJ0J1EN, DTBPAYEN,
DTBTUGEN and DTBH4EN. The transmit telecom bus
timing signals MTBJ0J1EN, MTBPAYEN, and
MTBH4EN timing signals become outputs which drive the
OHT device (i.e. the receive timing information is passed
through to the transmit side). Second, an Add Enable
function is provided in TADD_CONF—Transmit Add
Configuration (003–001H) (page 48). These registers
control the source of each TU time slot data output on the
MTBDATA bus. The bits in these three registers control
the Add Enable status of each TU time slot. If set to ‘0’, the
time slot data is taken from the received DTBDATA input,
if set to ‘1’, the TU time slot data is added from an E1 input
port; which port is determined by the Port Mapping
registers. Finally, as with the receive section, the Port
Mapping function is enabled.
• All Telecom bus data received on the DTBDATA bus
is made available to the transmit section (Pass through
mode)
• The PTSOH pin controls the transparent pass-through
of the higher order path and section data received on
the Telecom Bus.
• TADD_CONF—Transmit Add Configuration (003–
001H) (page 48) control the transparent pass through
of each of the 21 TU tributaries accessible by the
device.
• The Port Mapping function is enabled allowing each
tributary mapping/demapping circuit to operate on
any TU time slot within the STM-0 data or the active
TUG-3 within STM-1. The result of this function is
that each E1 data port (DTCx/DTDx and MTCx/
MTDx pairs) can be assigned any TU time slot. More
information on the Port Mapping function can be
found in “Port Mapping Configuration” on page 25.
It is possible to enable all 21 channels in the Add/Drop
mode and use the device in a terminal configuration. One
consequence of this configuration is that both transmit and
receive sections operate with the same clock and timing
references.
The block diagram shown in Figure 5 highlights the data
and timing flow in the Add/Drop configuration. It is a
requirement in the ADM configuration that the DTBYCK
and MTBYCK are the same clock, sourced, for example,
from the LXT6051 DTBYCK pin.
22
ꢀ
Functional Description
VC-4 HPOH and the two VC-4 fixed stuff columns
and the timing signals MTBJ0J1, MTBPAY, and
MTBH4EN to be output on the MTBDATA bus. If
PTSOH is tied low, none of the above mentioned
bytes are output: MTBDATA is tri-stated during the
corresponding time slots and timing signal pins are
held in tri-state. This pin should be tied low in STM-0
mode as well as in the STM-1 terminal configuration.
Data Pass-Through
In the Add/Drop configuration for STM-1, it is
necessary to control the pass though of the higher
order overhead bytes and the non-dropped TUG-3
payloads. The LXT6251 uses three external pins for
this control: PTSOH, PTTUGA and PTTUGB.
PTSOH
The PTSOH pin controls the pass-through of the SOH
and HPOH bytes along with the Telecom bus timing
signals. Connecting this pin high will cause the nine
columns of the STM-1 SOH, the single column of
Figure 5: Add/Drop Configuration Data Flow
ADD Registers
Add
M ux
Control
PT SOH
PT TUGA
PT TUGB
Control
M TBJ0J1
M TBPAYEN
M TBH 4EN
DT BJ0J1
DT BPAYEN
DT BH4EN
Receive
Transm it
FF
Rx
Tim ing
Tx
Tim ing
M TBYCK
DT BYCK
DT BDATA
FF
M TBD ATA
M UX
VC-12 to E1
E1 to VC-12
Dem apping
M apping
DT Dx/D TCx
M TDx/M TCx
PTTUGx
through to the transmit Telecom Bus. For example, if
the ADM site contains two LXT6251 mappers
processing TUG-3 #1 and TUG-3 #3, then one of the
mappers can be configured to pass through the TUG-3
#2 payload by connecting the OHT DTBTUGEN2
signal to the PTTUGA pin and connecting the
DTTUGB pin to ground. The second mapper chip
must have these two pins connected to ground. The
different configurations are shown schematically in
Figure 6. The functional timing diagram in Figure 9
provides examples of PTTUGA and PTTUGB.
The PTTUGA and PTTUGB pins are used only in
STM-1 mode to control the pass through of the other
TUG-3 payloads not being processed by the device.
The need for this function can arise if an ADM site is
configured to access data in only one TUG-3 payload,
thereby requiring only one LXT6251. The LXT6251
will process the TUG-3 that corresponds with the
TUG enable signal connected to its input pin
DTBTUGEN. The other two TUG-3 payloads can be
passed through by connecting the remaining two
DTBTUGEN signals from the OHT to the PTTUGA
and PTTUGB pins. Whenever either of these pins is
high, the data on the receive Telecom bus is passed
23
ꢀ
LXT6251 21 E1 SDH Mapper
bus when MTBTUGEN is active, and will be in tri-
state during the SOH, HPOH (and two bytes of VC-3/
VC-4 fixed stuff), and the other two TUG-3 payloads.
It is recommended that PTTUGA/B signals be active
only on the device with PTSOH set high.
MTBDATA Drive Enable
Table 6 on page 24 shows the drive of the MTBDATA
bus in all configurations. The first column gives the
configuration, while the remaining four columns
represent the four different data types that can be
output on this bus. For example, the STM-1 ADM
multiplexer with PTSOH tied to ground will drive the
.
Table 6: Multiplex Telecom Bus Drive Matrix
Section
Overhead
POH and
VC Fixed Stuff
PTTUGA/B
= ‘1’
MTBTUGEN
= ‘1’
Configuration
STM-1 ADM,
PTSOH = ‘1’
STM-1 ADM,
PTSOH = ‘0’
STM-1 Term
STM-0 ADM
STM-0 Term
Data
Hi-Z
Data
Data
Data
Hi-Z
Hi-Z
Data
Hi-Z
Data
Data
Hi-Z
Data
Data
Hi-Z
N/A
N/A
Data
Data
Data
Figure 6: ADM Multi-chip Configuration
A
VCC
B
VCC
LXT6051
LXT6251
PTSOH
LXT6051
LXT6251
PTSOH
DTBTUGEN1
DTBTUGEN2
DTBTUGEN3
PTTUGA
PTTUGB
DTBTUGEN1
DTBTUGEN2
DTBTUGEN3
PTTUGA
PTTUGB
DTBTUGEN
DTBTUGEN
LXT6251
PTSOH
A
B
: STM -1 ADM with access to TUG 3 #2
Pass-Thru of TUG 3 #1, #3
PTTUGA
PTTUGB
: STM -1 ADM with access to TUG 3 #2, #3
Pass-Thru of TUG 3 #1
DTBTUGEN
GND
DRAWING
1
-
PAGE-1 - 7/8/99
24
ꢀ
Application Information
APPLICATION INFORMATION
associated with the port mapping register. That is, when the
Port Mapping function is used, both the register address
and the physical E1 port (both Tx and Rx) will operate on
the selected TU-12 time slot.
Port Mapping
Configuration
To allow for the design of a cost-reduced ADM mapper
module, the LXT6251 supports a programmable E1 port
mapping feature that allows each E1 I/O port to be assigned
to any tributary time slot. The cost-reduced module may
contain only four or eight E1 line interface circuits, but the
use of the Port Mapping would allow access to any TU-12
tributary within a TUG-3 or STM-0 payload at an ADM
site.
Table 7 contains the default register values and the ITU
specified Time Slot numbering for the 21 tributaries. In the
STM-1 configuration, the input DTBTUGEN control pin
determines the TUG-3 number (K). The default
associations map port 1 to the first TU-12 time slot (1,1)
and linearly progress to port 21 with TU-12 slot 21 (7,3).
When configuring the port mapping registers, care must be
taken to keep the value in each register unique. If port 1 is
assigned TS (2,1), then no other port should be assigned to
this timeslot. Failure to ensure this could result in an
unstable system. It is also suggested that the multiplexer
Telecom bus be placed in tri-state (the TBTristate bit in the
Global Configuration register) whenever the Port Mapping
registers are changed.
There is a 5 bit Port Mapping register per tributary circuit
that is used to configure the time slot on which the circuit
operates. Each of the 21 circuits has associated with it a set
of alarm and control registers (address range x0H through
xFH) and the E1 I/O ports MTD(T)/MTC(T) and DTB(T)/
DTC(T), where T ranges from 1 to 21. By configuring the
port mapping register to a timeslot, all processing of the
assigned TU-12 is performed by the hardware circuit
Table 7: E1 Port Time Slot Assignment
Tributary Circuit
(Port)
Register
Address
Default
Time Slot
TU-12 Address
(L, M)
Default Value
1
2
161h
162h
163h
164h
165h
166h
167h
168h
169h
16Ah
16Bh
16Ch
16Dh
16Eh
16Fh
170h
171h
172h
173h
174h
1
2
1
2
(1, 1)
(2, 1)
(3, 1)
(4, 1)
(5, 1)
(6, 1)
(7, 1)
(1, 2)
(2, 2)
(3, 2)
(4, 2)
(5, 2)
(6, 2)
(7, 2)
(1, 3)
(2, 3)
(3, 3)
(4, 3)
(5, 3)
(6, 3)
3
3
3
4
4
4
5
5
5
6
6
6
7
7
7
8
8
8
9
9
9
10
11
12
13
14
15
16
17
18
19
20
10
11
12
13
14
15
16
17
18
19
20
10
11
12
13
14
15
16
17
18
19
20
25
ꢀ
LXT6251 21 E1 SDH Mapper
Table 7: E1 Port Time Slot Assignment – continued
Tributary Circuit
(Port)
Register
Address
Default
Time Slot
TU-12 Address
(L, M)
Default Value
21
175h
21
21
(7, 3)
cation (byte H4=00 for TU-12 V1 byte
location) by detecting a two-byte wide
J1 pulse every fourth frame. Note the
H4 indication can be active even when
MTBPAYEN is Low.
Telecom Bus Interface
The LXT6251 uses an industry standard Telecom Bus to
interface with other SDH products, including LXT 6051.
The standard is based on the original work of the IEEE
P1396 project that never made it to final approval. SFT has
enhanced the bus to be compatible with other standard
SDH products on the market.
MTBPAYEN
MTBH4EN
Input Payload Enable. A high on this
input enables the driving of the MTB-
DATA bus with the VC-3 or VC-4 pay-
load. A low indicates the location of the
SOH bytes and the AU Pointers bytes.
Multiplexer Telecom Bus, Terminal
Mode
In terminal mode, the multiplexer side Telecom Bus
operates in a contra-directional mode, meaning the Mapper
receives the timing signals and generates the Data
synchronized to the timing signals but delayed by one half
clock cycle. Functional Timing diagrams are shown in
Figure 7 and Figure 8.
Input indicates the multiframe start posi-
tion. This signal must be active high
during the J1 byte following the multi-
frame when the H4 byte equals ‘00’.
This signal need not be present if the
multiframe indication exists in
MTBJ0J1EN.
MTBTUGEN Input used in STM-1 only. A high
enables the MTBDATA bus to be driven
with the TUG-3 being output by the
device. This signal must also be High
during the VC-4 HPOH byte, regardless
of the TUG-3 it is enabling. In STM-0,
this signal should be tied high.
MTBYCK
Input Telecom Bus byte clock at 6.48
MHz for STM0 or 19.44 MHz for
STM1.
MTBDATA
Output Byte parallel Data. In STM-0,
the data consists of the 21 TU-12 signals
in a 7 by TUG-2 format plus the 2 fixed
stuff columns of a C3 container at posi-
tions 30 and 59. The data bus is also
driven during all other SOH and HPOH
bytes, however, the data during these
times is not valid. In STM-1, the data
consists of a single TUG-3 payload con-
trolled by MTBTUGEN. The bus is in
tri-state for all other bytes (SOH,
NOTE
Note on Telecom Bus Timing Reference
All Telecom Bus timing signals (MTBH4EN,
MTBPAYEN, MTBJ0EN and MTBTUGEN) are
sampled on the falling edge of the MTBYCK
clock, and the output data (MTBPAR and
MTBDATA) are clocked out of the device on the
falling edge of this clock. See Telecom bus timings
in Figure 7 and Figure 8.
HPOH, fixed stuff)
MTBPAR
Output parity bit calculated on each out-
put MTBDATA byte. This is an odd par-
ity calculation.
MTBJ0J1EN
Input Frame Position indicator, active
high during both the J0 and J1 bytes.
The J0 byte is identified when the MTB-
PAYEN is low, J1 when MTBPAYEN is
high. Optionally the MultiFrmSel con-
figuration bit in GLOB_CONF—Global
Configuration (000H) (page 47) can be
set to ‘1’, which adds a multiframe indi-
Multiplexer Telecom Bus, ADM
Mode
In the Add/Drop configuration, the Telecom Bus operates
in a co-directional mode, meaning that both the timing
signals and the data are generated by the Mapper. The
26
ꢀ
Application Information
enable signals are coincident with the associated data on
the bus.
the data are inputs to the LXT6251. The enable signals are
coincident with the associated data on the bus.
MTBYCK
Input, identical to the Terminal mode
DTBYCK
Input Telecom Bus byte clock at 6.48
MHz for STM0 or 19.44 MHz for
STM1
MTBDATA
Output, at a minimum this data bus con-
tains the 7 by TUG-2 (STM-0) or TUG-
3 (STM-1) data. Depending on the pass-
though configuration, MTBDATA could
contain SOH, HPOH, and other TUG-3
data (STM-1). Refer to Table 6.
DTBDATA
Input byte wide Data. In STM-0, the
data must consist of the 21 TU-12 sig-
nals in a 7 by TUG-2 format with the 2
fixed stuff columns at positions 30 and
59. The HPOH and SOH data on the bus
is ignored, except as required for ADM
pass-through. In STM-1, the data must
consist of a valid TUG-3 payload active
when DTBTUGEN is high. Other TUG-
3, HPOH, and SOH data is ignored,
except as required for ADM pass-
through.
MTBPAR
Output, active whenever MTBDATA is
active.
MTBJ0J1EN
MTBPAYEN
MTBH4EN
Output, this is directly the DTBJ0J1EN
delayed by 3 MTBYCK clock periods.
Output, this is directly the DTBPAYEN
delayed by 3 MTBYCK clock periods.
Output, this is directly the DTBH4EN
delayed by 3 MTBYCK clock periods
DTBPAR
Input Parity bit calculated on each DTB-
DATA byte. This is an odd parity calcu-
lation.
MTBTUGEN Not used in ADM mode
NOTE
DTBJ0J1EN
Input Frame Position indicator, active
high during both the J0 and J1 bytes.
The J0 byte is identified when the DTB-
PAYEN is low, J1 when DTBPAYEN is
high. Optionally the MultiFrmSel con-
figuration bit in GLOB_CONF—Global
Configuration (000H) (page 47) can be
set to ‘1’, which adds a multiframe indi-
cation (byte H4=00 for TU-12 V1 byte
location) by detecting a two-byte wide
J1 pulse every fourth frame. Note the
H4 indication can be active even when
DTBPAYEN is Low.
Note on Telecom Bus Timing Reference
All Telecom Bus timing signals (MTBH4EN,
MTBPAYEN, MTBJ0EN and MTBTUGEN) and
data (MTBPAR and MTBDATA) are clocked out
of the device on the rising edge of this clock. See
Telecom bus timings in Figure 7 and Figure 8.
MTBDATA Output Enable
The configuration bit TBTristate within GLOB_CONF—
Global Configuration (000H) (page 47) is used to force the
multiplexer telecom bus into tri-state during configuration
of the chip. It exists for those configurations in STM-1
where multiple chips drive the bus. At power up, the bit
defaults to ‘1’ disabling the MTBDATA and MTBPAR
signals while initial configuration is performed. After all
devices that drive the MTBDATA/MTBPAR bus are
configured, each device can then be enabled by setting the
bit to ‘0’. Should a configuration change take place, for
example re-configuring an ADM site, all devices might be
set into tri-state during the configuration operation if no
specific care is to be given to the propagation order.
DTBPAYEN
DTBH4EN
Input Payload Enable. A high on this
input indicates that the DTBDATA bus
is being driven with the VC-3 or VC-4
payload. A low indicates the location of
the SOH bytes and the AU Pointer
bytes.
Input indicates the multiframe start posi-
tion. This signal must be active high
during the J1 byte following the multi-
frame when the H4 byte equals ‘00’.
This signal need not be present if the
multiframe indication exists in
DTBJ0J1EN.
Demultiplexer Telecom Bus
In both terminal and ADM configurations, the
demultiplexer side Telecom Bus operates in a co-
directional mode, meaning that both the timing signals and
DTBTUGEN
Input used in STM-1 only. A high indi-
cates that the DTBDATA bus is being
driven with the TUG-3 that is to be pro-
cessed by the device. This signal must
27
ꢀ
LXT6251 21 E1 SDH Mapper
also be High during the VC-4 HPOH
byte, regardless of the TUG-3 it is
enabling. In STM-0, this signal should
be tied High.
NOTE
Note on Telecom Bus Timing Reference
All Telecom Bus timing signals (DTBH4EN,
DTBPAYEN, DTBJ0EN and DTBTUGEN), and
the output data (DTBPAR and DTBDATA) are
sampled on the falling edge of the DTBYCK
clock. See Telecom bus timings in Figure 7 and
Figure 8.
28
ꢀ
Application Information
be coincident with the J1 indicator. If the timing reference
signals are sourced from a device that expects to receive
data (contra-directional timing), then the data will be
received one half clock cycle later.
Telecom Bus Timing
The following diagrams show the relation of timing
reference and data signals on the Telecom bus. In
summary, if the timing reference signals (DTBJ0J1,
DTBPAYEN) and the data are sourced from the same
device (co-directional timing), the data byte (i.e., J1) will
Figure 7: STM-0 Telecom Bus Timing
STM -0 Receive Telecom Bus Tim ing (Term inal & Add/Drop)
DTBYCK
Input
Every 4th Fram e
J0
J1
M F-IND
if enabled
DTBJ0J1EN
Input
DTBPAYEN
Input
TU 4:3
TU 5:3
TU 6:3
TU 7:3
DTBDATA
A2
J0
J1
V1
V1
V1
V1
V1
V1
V1
Input
TU 1:1
TU 2:1
TU 3:1
TU 4:1
TU 5:1
TU 6:1
TU 7:1
Goes HI one clock cycle after H4 = 00, Low one clock cycle after H4 = 01
Tied to VCC in STM-0
DTBH4EN
Input
DTBTUGEN
Input
STM -0 Transm it Telecom Bus Tim ing (Add/Drop)
MTBYCK
Input
Every 4th Fram e
if enabled
3
tC YC
J0
J1
J1
M F-IND
MTBJ0J1EN
O utput
MTBPAYEN
O utput
MTBDATA
SOH
SOH
SOH
J0
TU 3:3
TU 4:3
TU 5:3
TU 6:3
TU 7:3
V1
V1
V1
V1
O utput
TU 1:1
TU 2:1
TU 3:1
TU 4:1
STM -0 Transm it Telecom Bus Tim ing (Term inal)
MTBYCK
Input
Every 4th Fram e
if enabled
J0
J1
M F-IND
MTBJ0J1EN
Input
MTBPAYEN
Input
SOH (X)
J0 (X)
TU 4:3
TU 5:3
TU 6:3
TU 7:3
J1 (X)
V1
TU 1:1
V1
V1
V1
TU 4:1
V1
TU 5:1
V1
TU 6:1
V1
TU 7:1
V1
MTBDATA
O utput
TU 2:1
TU 3:1
TU 1:2
Goes HI one clock cycle after H4 = 00, Low one clock cycle after H4 = 01
Tied to VCC in STM-0
MTBH4EN
Input
MTBTUGEN
Input
29
ꢀ
LXT6251 21 E1 SDH Mapper
Figure 8: Terminal STM-1 Telecom Bus Timing (
STM-1 Receive Telecom Bus Tim ing
DTBYCK
Input
Every 4th Fram e
if enabled
DTBJ0J1EN
J0
J1
M F-IND
Input
DTBPAYEN
Input
DTBTUGEN
Input DTBTU GEN1 from OHT
Fixed
Stuff
Fixed
Stuff
Fixed
Stuff
Fixed
Stuff
DTBDATA
A2
J0
X
X
TU 2:7:3 TU 3:7:3
J1
V1
V1
V1
V1
Input
VC-4
VC-4
TUG 3
1
TUG 3:3 TU 1:1:1 TU 2:1:1 TU 3:1:1 TU 1:2:1
STM-1 Transm it Telecom Bus Tim ing
MTBYCK
Input
Every 4th Fram e
if Enabled
MTBJ0J1EN
J0
J1
M F-IND
Input
MTBPAYEN
Input
MTBTUGEN
Input MTBTUGEN1 from OHT
Fixed
Stuff
Fixed
Stuff
V1
MTBDATA
Output
TUG 3
1
TUG 3
1
TU 1:1:1
Figure 9: ADM STM-1 Telecom Bus Timing w/ PTSOH=1
STM-1 Receive Telecom Bus Tim ing - ADM M aster
MTBYCK, DTBYCK
Inputs
Every 4th Fram e
if enabled
J0
J1
M F-IND
DTBJ0J1
Input
DTBPAYEN
Input
DTBTUGEN
Input DTBTU GEN1 from OHT
Fixed
Stuff
Fixed
Stuff
Fixed
Stuff
DTBDATA
Input
A2
J0
X
X
TU 2:7:3 TU 3:7:3
J1
TU 3:1:1 TU 1:2:1 TU 2:2:1 TU 3:2:1 TU 1:3:1
VC-4
VC-4
TUG 3 1
PTTUGA
Input DTBTU GEN2 from OHT
PTTUGB
Input DTBTU GEN3 from OHT
STM-1 Transm it Telecom Bus Tim ing
3
tCYC
Every 4th Fram e
if enabled
PassThrough
Delay
MTBJ0J1EN
J0
J1
J1
M F-IND
Output
MTBPAYEN
Output
Fixed
Stuff
Fixed
Stuff
Fixed
Stuff
A1
A2
A2
A2
J0
X
X
TU 2:7:3 TU 3:7:3
TU 3:1:1 TU 1:2:1
MTBDATA
Output
PTSOH
PTTUGx as Above
= 1
VC-4
VC-4
TUG 3 1
30
ꢀ
Application Information
Figure 10:ADM STM-1 Telecom Bus Timing w/ PTSOH = 0
STM-1 Receive Telecom Bus Tim ing - ADM Slave
MTBYCK, DTBYCK
Inputs
Every 4th Fram e
if enabled
DTBJ0J1
J0
J1
M F-IND
Input
DTBPAYEN
Input
DTBTUGEN
Input DTBTU GEN1 from OHT
Fixed
Stuff
Fixed
Stuff
Fixed
Stuff
DInpTutBDATA
PTTUGA
A2
J0
X
X
TU 2:7:3 TU 3:7:3
J1
TU 3:1:1 TU 1:2:1 TU 2:2:1 TU 3:2:1 TU 1:3:1
VC-4
VC-4
TUG 3 1
Input
= G ND
PTTUGB
Input:
= GND
STM-1 Transm it Telecom Bus Tim ing
Every 4th Fram e
if enabled
3
tCYC PassThrough
Delay
J0
J1
M F-IND
MTBJ0J1EN
Output
MTBPAYEN
Output
Fixed
Stuff
TU 1:2:1
MTBDATA
Output
TUG 3
1
PTSOH
= 0
PTTUGx
=
0
31
ꢀ
LXT6251 21 E1 SDH Mapper
REI
REI indication (from BIP-2 error),
Drives TX V5 REI bit on Tx
Serial/Remote Alarm
Processing Port
RDI-1
Connectivity Defect (UNEQ, TIM),
Drives TX V5 RDI bit, K4 ERDI on Tx.
Note the UNEQ alarm is not active in
Supervisory Unequipped configuration
There are six pins on the chip dedicated to remote alarm
processing, three for the receive section to output the alarm
data (SAP), and three to input the data into the transmit
section (RAP). In a Terminal configuration, the output SAP
pins should be connected to the input RAP pins. In the
ADM configuration, an LXT6251 processes data in one
direction only, therefore the SAP port is used to transfer the
REI/RDI and other feedback alarm information between
the East traffic and West traffic mappers. The
configurations for connecting the SAP Bus are shown in
Figure 11.
RDI-2
SF
Server Defect (TU-LOP, TU-AIS),
Drives TX V5 RDI bit, K4 ERDI on Tx
Signal Fail alarm. A one bit alarm that is
active when the receiver detects either
type of RDI alarm, VC-AIS, or H4 Loss
of multiframe.
The SF bit is ignored on the Tx RAP bus input. It is
provided exclusively for a fast tributary alarm indication
and can be used by using a small external circuit to control
VC-12 protection switching. The frame format for the SAP
Bus is shown in Figure 12.
The SAP Bus consists of three signals: clock, frame signal,
and the alarm data. The following Alarm data is provided
in a framed format on the SAPDATA signal (refer to
Figure 4 for V5 bit assignment):
Figure 11: SAP Bus Connections for Terminal & ADM
M TD/M TC E1 Ports
Term inal
M apper
RX
Term inal
M apper
TX
M TB Telecom Bus
DTB Telecom Bus
M TB Telecom Bus
Term inal
M apper
TX
RAP
RAP
SAP
REI, RDI
Alarm
Status
REI, RDI on
Dropped E1
RAP
SAP
Term inal
M apper
RX
Term inal
M apper
TX
Term inal
M apper
RX
SAP
DTB Telecom Bus
M TB Telecom Bus
DTB Telecom Bus
DTD /D TC E1 Ports
Term inal
Add/Drop
Figure 12:SAP Bus Frame Format
DSAPCLK
DSAPFRM
REI #1 RDI-1 #1 RDI-2 #1 SF #1
REI #2 RDI-1 #2 RDI-2 #2 SF #2
REI #3 RDI-1 #3 RDI-2 #3
DSAPDATA
32
ꢀ
Test Specifications
TEST SPECIFICATIONS
NOTE
NOTE
Notes
Minimum and maximum values in tables 9 though 11 represent the performance specifications of the LXT6251
and are guaranteed by test unless otherwise noted. Minimum and maximum values in tables 12 though 27 and
figures 32 through 45 represent the performance specifications of the LXT6251 and are guaranteed by design and
are not subject to production testing.
NOTE
All timing parameters assume that the outputs have a 50 pF load unless otherwise noted.
Table 8: Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Unit
CC
Supply Voltage
V
6.0
V
V
DC Voltage on any pin1
IN
V
-2.0
+7.0
OP
Ambient operating temperature
Storage temperature range
T
-40
-65
+85
C
C
ST
T
+150
2. Minimum voltage is -0.6V dc which may undershoot to -2.0 V for pulses of less than 20 ns
CAUTION
Exceeding these values may cause permanent damage.
Functional operation under these conditions is not implied
Exposure to maximum rating conditions for extended periods may affect device reliability
Table 9: Operating Conditions
Parameter
Typ1
Symbol
Min
Max
Unit
Recommended Operating Temperature
Supply Voltage - I/O Ring
TOP
-40
-
+85
C
V
VCC5
4.75
5
5.25
1. Typical values are at 25C and nominal voltage and are provided for design aid only; not guaranteed nor subject to production testing
2. Voltages with respect to ground unless otherwise specified
3. STM-1 Terminal mode, PRBS data on all tributaries, outputs loaded, not subject to production testing
33
ꢀ
LXT6251 21 E1 SDH Mapper
Table 9: Operating Conditions
Parameter
Typ1
Symbol
Min
Max
Unit
Supply Voltage - Core
VCC3
IDD5
3.15
-
3.3
15
3.45
25
V
Supply Current - I/O Ring 3
Supply Current - Core 3
mA
IDD3
200
250
mA
1. Typical values are at 25C and nominal voltage and are provided for design aid only; not guaranteed nor subject to production testing
2. Voltages with respect to ground unless otherwise specified
3. STM-1 Terminal mode, PRBS data on all tributaries, outputs loaded, not subject to production testing
Table 10: 5 V Digital I/O Characteristics
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
TTL Input Low Voltage
TTL Input High Voltage
TTL Switching Threshold
Input Leakage High
VIL
VIH
VT
0.8
V
V
2.0
1.4
V
VCC-5.0V, 25C
VIN-VCC=5.5V
VCC=4.5V
IIH
10
uA
V
Output Low Voltage
VOL
VOH
IOZ
0.2
4.2
0.4
Output High Voltage
0.7xVCC
-10
VCC=4.5V
Output Leakage (no pull up)
10
uA
VIN=VDD=5.5V
1. All values applicable over recommended Voltage and Temperature operating range unless otherwise noted
34
ꢀ
Test Specifications
Figure 13:Tributary Timing
tME1cyc
tME1pwh
tME1pwl
MTCx
MTDx
tME1su
tME1h
tDE1cyc
tDE1pwl
tDE1pwh
DTCx
DTDx
tDE1pd
Table 11: Tributary Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
TM + 3 1
MTCx Input E1 Clock pulse width
low
ns
tME1PWL
TM + 5 1
MTCx Input E1 Clock pulse width
high
ns
tME1PWH
MTCx Input E1 Clock cycle time
488
ns
ns
tME1CYC
MTDx setup time to MTCx rising
edge
4
2
tME1SU
MTDx hold time from MTCx rising
edge
tME1H
ns
2(1+2S)TD - 5 2,3 2(1+2S)TD 2,3 5(1+2S)TD + 2 2,3
DTCx output clock pulse width low
DTCx output clock pulse width high
DTCx output E1 Clock cycle time
DTDx delay from DTCx rising edge
tDE1pwl
tDE1pwh
tDE1CYC
tDE1pd
ns
ns
ns
ns
(1+2S)TD - 2 2,3
3(1+2S)TD 2,3
(1+2S)TD 2,3
(1+2S)TD + 5 2,3
6(1+2S)T D 2,3
9
1. TM is the clock period of MTBYCK
2. TD is the clock period of DTBYCK
3. S is `0` for STM0 application and `1` for STM1 application.
35
ꢀ
LXT6251 21 E1 SDH Mapper
Figure 14:Receive Telecom Bus Timing
TERMINAL and ADD/DROP MODE
tD TBcyc
DTBCLK
tD TBsu
tD TBh
DTBDATA<7:0>
DTBJ0J1EN
DTBPAYEN
DTBH4EN
DTBTUGEN
ADD/DROP MODE ONLY
tM TBcyc
M TBCLK
tD TBsu_adm
tD TBh_adm
DTBDATA<7:0>
DTBJ0J1EN
DTBPAYEN
DTBH4EN
DTBTUGEN
DPTTUGA
DPTTUGB
Table 12: Receive Telecom Bus Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
DTBCLK Input clock cycle time
tDTBcyc
6.48/
MHz
19.44
MTBCLK Input clock cycle time
tMTBcyc
tDTBsu
6.48/
19.64
MHz
ns
Any telecom bus input setup time to DTBCLK
falling edge
3
5
4
3
-
-
-
-
-
-
-
-
Any telecom bus input hold time after DTBCLK
falling edge
tDTBh
ns
Any telecom bus input setup time to MTBCLK
falling edge
tDTBsu_adm
tDTBh_adm
ns
Any telecom bus input hold time after MTBCLK
falling edge
ns
36
ꢀ
LXT6251 Test Specifications
Figure 15:Transmit Telecom Bus Timing - Terminal,
tM TBcyc
M TBCLK
tM TBsu
tM TBh
M TBJ0J1
M TBPAYEN
M TBH4EN
M TBTUGEN
tM TBdh
tM TBdv
M TBDATA<7:0>
tM TBdd
tM TBdz
MTBDOE
tM TBcd
tM TBcd
Table 13: Transmit Telecom Bus Timing - Terminal Parameters
Parameter
Symbol
Min
Typ
Max
Unit
MTBCLK Input clock cycle time
tMTBcyc
6.48/
MHz
19.44
Any telecom bus timing input setup time to
MTBCLK falling edge
tMTBsu
tMTBh
1
3
9
-
-
-
-
-
-
ns
ns
ns
Any telecom bus timing input hold time after
MTBCLK falling edge
MTBCLK falling edge to MTBDATA bus driven
(STM1 only)
tMTBdd
MTBCLK falling edge to MTBDATA valid
tMTBdv
tMTBdh
tMTBdz
-
-
-
24
7
ns
ns
ns
MTBDATA hold time after MTBCLK falling edge
-
-
MTBCLK falling edge to MTBDATA bus Hi-Z
(STM1 only)
19
MTBDOE output delay from MTBCLK falling
edge
tMTBcd
9
-
28
ns
37
ꢀ
LXT6251 21 E1 SDH Mapper
Figure 16:Transmit Telecom Bus Timing - ADM Parameters
tM TBcyc
M TBYCK
tM TBpd
M TBJ0J1
M TBPAYEN
M TBH4EN
tM TBdh
tM TBdv
M TBDATA<7:0>
tM TBdd
tM TBdz
MTBDOE
tM TBcd
tM TBcd
Table 14: Transmit Telecom Bus Timing - ADM Parameters
Parameter
Symbol
Min
Typ
Max
Unit
MTBCLK Input clock cycle time
tMTBcyc
6.48/
MHz
19.44
Any telecom bus timing output delay from
MTBCLK rising edge
tMTBpd
tMTBdd
8
-
-
24
-
ns
ns
MTBCLK rising edge to MTBDATA bus driven
(STM1 only)
10
MTBCLK rising edge to MTBDATA valid
tMTBdv
tMTBdh
tMTBdz
-
-
-
23
8
ns
ns
ns
MTBDATA hold time after MTBCLK falling edge
-
-
MTBCLK rising edge to MTBDATA bus Hi-Z
(STM1 only)
22
MTBDOE output delay from MTBCLK rising
edge
tMTBcd
8
-
24
ns
38
ꢀ
LXT6251 Test Specifications
Figure 17:Microprocessor Data Read Timing
MicroProcessor Read Timing (Intel Mode)
MicroProcessor Read Timing (Motorola Mode)
tSAR
tSAR
A<8:0>
A<8:0>
tHAR
tHAR
tSALR
tSALR
tHALR
tHALR
tVL
tVL
AS
AS
tSCR
tHCR
tSLR
CS
RW
tSRW B
tHRW B
tSLR
tVRD
RD
CS
tINTH
tSCR
tHCR
INT
E
tDDR
tZD R
tVRD
tINTH
INT
D<7:0>
tDDR
tZD R
tADR
tAAC
tAAC
tHDR
D<7:0>
tADR
tHDR
tAAC
tAAC
39
ꢀ
LXT6251 21 E1 SDH Mapper
Table 15: Microprocessor Data Read Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
A<8:0> setup time to active read
tSAR
10
2
-
-
-
-
ns
ns
1
A<8:0> hold time from inactive read
tHAR
2
A<8:0> setup time to latch
A<8:0> hold time from latch
Valid latch pulse width
1
3
-
-
-
-
-
-
-
-
ns
ns
ns
ns
tSALR
2
tHALR
2
1.5
11
tVL
2
AS rising edge to active read setup
tSLR
RW setup to active read
RW hold from inactive read
CS setup to active read
tSRWB
tHRWB
tSCR
3
2
2
2
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
-
CS hold from inactive read
tHCR
-
D<7:0> access time from valid address
(or AS whichever comes last for muxed AD bus)
D<7:0> bus driven from active read
tAAC
51
tDDR
tADR
tHDR
tZDR
6
-
-
-
-
-
-
17
-
ns
ns
ns
ns
ns
D<7:0> access time from active read
D<7:0> hold from inactive read
D<7:0> HIgh impedance from inactive read
Valid read pulse width
-
5
-
16
-
3
T+2
tVRD
Inactive read to inactive INT (due to reset on read
feature)
tINTH
3*T + 2
-
4*T + 36
ns
1. For non multiplexed Address and Data bus (AS tied high)
2. For multiplexed Address and Data bus (AS used as address latch enable)
3. T is the minimum cycle time of either MTBYCK or DTBYCK (typically 51.44 ns for STM1, 154.32 ns for STM0)
4. Consecutive reads from the on-chip RAM (“expected and “transmitted” J2 strings) must be separated by more than 4*T
40
ꢀ
LXT6251 Test Specifications
Figure 18: Microprocessor Data Write Timing
MicroProcessor Write Timing (Intel Mode)
MicroProcessor Write Timing (Motorola Mode)
tSAW
tSAW
A<8:0>
A<8:0>
tHAW
tHAW
tSALW
tSALW
tHALW
tHALW
tVL
tVL
AS
AS
tSCW
tHCW
tSLW
tHRW B
CS
RW
tSLW
tSRW B
tHCW
tSCW
W R
INT
CS
E
tINTH
tVW R
tVW R
tSDW
tINTH
tHDW
INT
D<7:0>
tSDW
tHDW
D<7:0>
41
ꢀ
LXT6251 21 E1 SDH Mapper
Table 16: Microprocessor Data Write Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
A<8:0> setup time to active write
tSAW
8
3
-
-
-
-
ns
ns
1
A<8:0> hold time from inactive write
tHAW
2
A<8:0> setup time to latch
A<8:0> hold time from latch
Valid latch pulse width
1
3
-
-
-
-
-
-
-
-
ns
ns
ns
ns
tSALW
2
tHALW
2
1.5
10
tVL
2
AS rising edge to active write setup
tSLW
RW setup to active write
tSRWB
tHRWB
tSCW
3
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
RW hold from inactive write
CS setup to active write
2
CS hold from inactive write
D<7:0> setup to inactive write
D<7:0> hold from inactive write
Valid write pulse width
tHCW
tSDW
2
9
tHDW
6
3
T+2
tVWR
Inactive write to inactive INT (due to interrupt
masking)
tINTH
12
-
36
ns
1. For non multiplexed Address and Data bus (AS tied high)
2. For multiplexed Address and Data bus (AS used as address latch enable)
3. T is the minimum cycle time of either MTBYCK or DTBYCK (typically 51.44 ns for STM1, 154.32 ns for STM0)
4. There must be more than 4*T between the rising edge of a write to a BIP or REI error counter and the falling edge of the read to a BIP or REI
error counter
5. Consecutive writes to the on-chip RAM (“expected and “transmitted” J2 strings) must be separated by more than 4*T
42
ꢀ
Microprocessor Interface & Register Definitions
MICROPROCESSOR INTERFACE & REGISTER DEFINITIONS
A read cycle is indicated to the LXT6251 by the
Microprocessor Interface
microprocessor forcing a High on the RW pin.
The
LXT6251
incorporates
an
asynchronous
A write cycle is indicated to the LXT6251 by the
microprocessor forcing a Low on the RW pin.
microprocessor interface. A microprocessor can be
connected to the LXT6251 for reading and writing data via
the microprocessor interface pins.
Both cycles are initiated by a Low on the E input. The E
input is connected to the E output from the Motorola
microprocessor and is typically a 50% duty cycle
The microprocessor interface is a generic asynchronous
interface, including an address bus (A<8:0>), data bus
(DATA<7:0>) and control pins (WR/RW, RD/E, CS, and
AS). The MCUTYPE input pin configures the type of
microprocessor interface is to be used – Intel or Motorola.
There is also an INT output pin that indicates alarm
conditions to the microprocessor.
waveform with
a
frequency derived from the
microprocessor clock.
Both cycles require the CS pin to be Low and the
microprocessor to drive the A<8:0> address pins. In the
case of the write cycle, the microprocessor is also required
to drive the DATA<7:0> data pins. In the case of the read
cycle, the LXT6251 drives the DATA<7:0> data pins.
Intel Interface
The Intel interface is indicated by driving the MCUTYPE
input pin Low. In this mode the WR/RW input pin is used
as a write-bar (WR) and the RD/E input pin as read-bar
(RD).
When a multiplexed data/address bus is used, the falling
edge of the AS input latches the address provided on
A<8:0>. If the address and data are not multiplexed the AS
pin should be tied High.
A read cycle is indicated to the LXT6251 by the
microprocessor forcing a Low on the RD pin with the WR
pin held High.
Timing diagrams for the Intel interface can be found in
Figures 17 and 18 starting on page page 39.
A write cycle is indicated to the LXT6251 by the
microprocessor forcing a Low on the WR pin with the RD
pin held High.
Interrupt Handling
There are 21 tributaries that are each capable of generating
13 alarms. Any one of these alarms (if enabled) can cause
the device interrupt pin to become active.
Both cycles require the CSB pin to be Low and the
microprocessor to drive the A<8:0> address pins. In the
case of the write cycle, the microprocessor is also required
to drive the DATA<7:0> data pins. In the case of the read
cycle, the LXT6251 drives the DATA<7:0> data pins.
Each tributary has three registers associated with it:
• Interrupt source: These registers identify the source of
the interrupt(s).
When a multiplexed data/address bus is used, the falling
edge of the AS input latches the address provided on
A<8:0>. If the address and data are not multiplexed the AS
pin should be tied High.
• Alarm status: These registers provide the current
status of alarm monitoring hardware processes.
• Interrupt Enable: These registers enable interrupt
sources to affect the state of the INT pin.
Timing diagrams for the Intel interface can be found in
Figures 17 and 18 starting on page 39.
Interrupt Sources
There are three types of interrupt sources:
Motorola Interface
• Status alarm changes: Any time a status alarm
changes state, an interrupt bit is set. For example, the
LXT6251 monitors the incoming V5 RDI bit. A
The Motorola interface is indicated by driving the
MCUTYPE input pin High. In this mode the WR/RW input
pin is used as a read/write-bar (RW) and the RD/E input pin
as enable clock (E).
43
ꢀ
LXT6251 21 E1 SDH Mapper
hardware process monitors this bit for changes and
sets bit 3 in TRIB_INT—Tributary Interrupt (x1–
x0H) (page 55) when the change persists for 5 frames.
Interrupt Clearing
• Status Alarm interrupt sources have their interrupt
bits cleared when their status register is read. For
example, the interrupt due to a change in the incoming
V5 RDI (bit 3 of interrupt register x0H) is cleared
when status register x2H is read. All of these alarm
types have associated status bits.
• Event Alarms: Any time a momentary event alarm
occurs, an interrupt bit is set. For example, the
LXT6251 monitors the incoming V5 byte for a
change in its REI bit from a ‘0’ to a ‘1’. Such an event
will SET bit 5 in interrupt register x0H.
• Event alarm interrupt sources have their interrupt bits
cleared when their interrupt register is read. For
example, the interrupt due to a change in the incoming
V5 REI (bit 5 of interrupt register x0H) from a ‘0’ to a
‘1’ is cleared when register x0H is read. None of these
alarm types have associated status bits.
• Counter overflows: The LXT6251 monitors the
incoming V5 to see if it’s REI bit is set. Each
multiframe with the REI bit set causes an REI counter
to be incremented. If the counter overflows, bit 4 of
interrupt register x0H is set.
• Interrupt sources due to counter overflows have their
interrupt bits cleared when their interrupt register is
read. See below for description of counter access.
Interrupt Identification
There are four registers used to identify the source of
an interrupt. The Global Interrupt Source register
provides three bits to identify tributaries 1-8, 9-14, or
15-21. After the group is determined, there are three
associated Tributary ID registers to indicate the
tributary which caused the alarm.
UpdateEn Configuration Bit
The LXT6251 provides an UpDateEn signal within
INT_CONF—Interrupt Configuration Register (00BH)
(page 51) to help avoid the problem with an asynchronous
microprocessor interface with respect to the system data
clock. With an asynchronous interface, it is possible,
though very rare, that a status register change could fail to
set its associated interrupt register because of the finite time
taken to clear the interrupt registers after a status read. The
time is three byte clock cycles which is enough to provide
a small window after each status read when alarms detected
will not cause an interrupt. This situation as described may
be acceptable and will exist when the UpDateEn bit is set
to ‘0’.
Interrupt Enables
In order for an interrupt source to affect the state of the INT
output pin, its associated interrupt enable bit must be set.
The setting (whether it is 0 or 1) of the interrupt enables
does not affect the updating of the interrupt, status,
overhead byte or counter registers.
Assuming the interrupt enable for a particular interrupt
source is SET and the interrupt source is active, the INT
output pin will be activated.
If the UpdateEn signal is set to ‘1’, this problem is avoided
by freezing both the status and interrupt registers whenever
any interrupt bit within a register is set.
For example, when a tributary incurs a Signal Label
Mismatch (SLM), if the interrupt is enabled, the SlmAlm
bit in the interrupt register will be set causing the device
interrupt pin to become active. The microprocessor would
then read the tributary interrupt registers 00DH–00FH to
identify the tributary in alarm. Next the tributary IRQ
registers x0H & x1H would be read to identify the alarm.
Finally, the status register x2H or x3H is read to determine
the current alarm state.
We encourage programmers to set the UpdateEn bit to ‘1’
during the interrupt service routine to avoid missing alarm
information. The UpdateEn bit can be set to ‘0’ after the
routine has completed.
A read of the status register is usually the event that causes
the interrupt bits to be cleared (active bits in registers x0H
& x1H). However, for Non-persistent events and counter
overflow alarms a read of the interrupt register (x0H or
x1H) is all that is required. In fact, the primary difference
between each of interrupt types is the way their respective
interrupt bits are cleared.
44
ꢀ
LXT6251 Microprocessor Interface & Register Definitions
Register Notations and Definitions
Register Address Map
The registers within the LXT6251 provide access for
configuration, alarm monitoring and control of the chip.
Table 17 shows the LXT6251 register address map. The
registers are listed by ascending address in the table.
The following notations and definitions are used in the
register descriptions.
RO
Read Only. Unless otherwise stated in
the register description, writes have no
affect
Nine address bits are used to access the LXT6251 register
(512 byte address space). Global registers occupy memory
space from 000H to 00FH, and from 160H and above.
Registers pertaining to the individual TU tributaries are
accessed from memory locations 010H through 15FH. The
upper 5 address bits identify the tributary (1-21) and the
lower 4 address bits identify the register for a particular
tributary. All tributary configuration, status and interrupt
registers are identified within this 4 bit address space. The
nomenclature used when referring to tributary addresses is
provided in the Register Notations and Definitions section.
WO
Write Only. Reads return undefined
values.
R/W
Read/Write. A register (or bit) with
this attribute can be read and written.
Reserved Bits Some of the registers contain reserved
bits. Software must deal correctly with
reserved fields. For reads, software
must use appropriate masks to extract
the defined bits and not rely on reserved
bits being any particular value. In some
cases, software must program reserved
bit positions to a particular value. This
value is defined in the individual bit
descriptions.
Counter Access
There are two performance counters associated with each
receive tributary. Both counters contain at least 11 bits of
data and therefore are accessed by reading two adjacent 8
bit register addresses. Counters are accessed by first
buffering their contents and then reading the buffer. Each
counter value is buffered by writing to either register of the
counter, then reading both counter addresses after a wait of
at least three clock cycles of the byte clock (6.48 MHz or
19.44 MHz).
Default
When the LXT6251 is reset, it sets its
registers to predetermined default
states. The default state represents the
minimum functionality feature set
required to successfully bring up the
system. Hence, it does not represent
the optimal system configuration. It is
the responsibility of software to prop-
erly determine the operating parame-
ters, and optional system features that
are applicable, and to program the
LXT6251 registers accordingly.
For example, to read tributary 21’s Low Order Path REI
counter in STM-0, a write to register 159H (15 is a hex
value = 21 in decimal) is required. After 0.5uS (3 STM-0
clock cycles), the contents of the buffer can now be read by
reading registers 158H & 159H (in either order).
Default = X
Undefined
Tributary
Register
Addressing
The first nibble of the tributary register
address (address bits <3:0>) represents
a specific register in a given tributary.
The upper 5 bits of the address (bits
<8:4>) identify the tributary and is rep-
resented by the letter ‘x’. For example,
xCH refers to the CH register in tribu-
tary x. The x is the Tributary identifier
with valid values of 1H to 15H (1 to 21
decimal). Thus, 14AH refers to tribu-
tary 20’s K4 Status Register.
45
ꢀ
LXT6251 21 E1 SDH Mapper
Table 17: Register Address Map
Address
Mnemonic
Register Name
Type
Page #
Global Configuration Registers
000H
GLOB_CONF
Global Configuration
Transmit Address Configuration
J2 Memory Reset
R/W
page 47
page 48
page 49
001–003H
008H
TADD_CONF
J2_MRST
—
R/W
WO
—
005–009H
00AH
Reserved
CHIP_ID
Chip Identification
RO
R/W
RO
RO
page 52
page 51
page 53
page 54
00BH
INT_CONF
GLOB_INTS
TRIB_ISRC
Interrupt Configuration
Global Interrupt Source
Tributary Interrupt Source Identification
00CH
00D–00FH
TU Tributary Registers
(x=1–15H and represents each of the 21 tributary register sets)
x0–x1H
x2–x3H
x4–x5H
x6–x7H
x8–x9H
xAH
TRIB_INT
TRIB_STA
TRIB_INTE
BIP2_ERRCNT
REI_CNT
Tributary Interrupt
Tributary Status
RO
page 55
page 57
page 56
page 57
page 58
page 58
page 58
page 50
page 51
page 49
page 50
RO
Tributary Interrupt Enable
BIP2 Error Counter
Remote Error Indication Counter
K4 Status
R/W
RO
RO
K4_STA
RO
xBH
V5_STA
V5 Status
RO
xCH
J2_ESDATA
ERRI_CONF
SIGLA_SET
J2_TSDATA
J2 Expected String Data
Error Insert Configuration
Signal Label Set
R/W
R/W
R/W
R/W
xDH
xEH
xFH
J2 Transmit String Data
Global Configuration Registers
160H
—
Reserved
—
161–175H
TU_TS_CONF
TU Time Slot Configuration (21 registers repre- R/W
senting Port 1 to Port 21)
page 49
176–1FFH
—
Reserved
—
46
ꢀ
LXT6251 Microprocessor Interface & Register Definitions
Configuration Registers
The registers described in this section are related to global configuration. The global address space includes 000H through
00FH, as well as 161H through 175H.
GLOB_CONF—Global Configuration (000H)
This register configures the high level operational characteristics of the chip.
Bit
Name
Label
Type
Default
7
6
Reserved
TxK4En
This signal enables the use of the K4 Enhanced RDI in the trans-
mit direction.
R/W
0
0 = Force K4 ERDI to 0
1 = Drive K4 ERDI with input RAP alarm signals.
Selects the multiframe indicator used.
0 = Use DTBH4EN and MTBH4EN signals
5
4
MultiFrmSel
TBTristate
R/W
R/W
0
1
1 = Use DTBJOJ1EN and MTBJOJ1EN signals (OHT must be
configured likewise).
This signal defaults to ‘1’, forcing the Transmit side Telecom bus
timing signal pins to tri-state. This bit should be set to ‘0’ after
both this chip and other chips sharing the telecom bus are config-
ured to avoid any device from trashing the bus before configura-
tion is complete.
0 = Telecom Bus outputs enabled
1 = Telecom Bus outputs in Tri-state
3
2
1
0
BIPMode
UNEQMode
OpMode
Sets the BIP Error counting mode for all receive tributary LPT
blocks.
R/W
R/W
R/W
R
0
0
0 = Block Error Counting
1 = BIP Error Counting
Sets the form of the unequipped signal generated by all transmit
tributary LUG blocks, as defined in G707, section 6.2.4.2.
0 = Unequipped
1 = Supervisory Unequipped
Master configuration for the entire chip’s operation, either Termi-
nal or ADM.
0
0 = Terminal Configuration
1 = Add/Drop Configuration
StmMode
Selects the speed of operation and the Telecom bus I/O format.
This is a read-only register; the value is set by pin 32.
X
0 = STM-0, 7 by TUG-2 output
1 = STM-1, TUG-3 output
47
ꢀ
LXT6251 21 E1 SDH Mapper
TADD_CONF—Transmit Add Configuration (003–001H)
003H=Bits<23:16>, 002H=Bits<15:8>, 001H=Bits<7:0>
(Byte access only)
that are set to ‘1’ will add tributary data from the E1 input
source, all bits set to ‘0’ will pass through the tributary data
received on the Telecom bus.
This set of registers configures the transmit side added
tributary channels in an Add/Drop mode configuration
(register 000H bit 1, set to ‘1’). All bits in these registers
This register is ignored if the chip is configured as a
terminal.
Bit
Name
Reserved
Description
Type
Default
23:21
20
19
18
17
16
15
14
13
12
11
10
9
Trib21 (7,3)
Trib20 (6,3)
Trib19 (5,3)
Trib18 (4,3)
Trib17 (3,3)
Trib16 (2,3)
Trib15 (1,3)
Trib14 (7,2)
Trib13 (6,2)
Trib12 (5,2)
Trib11 (4,2)
Trib10 (3,2)
Trib9 (2,2)
Trib8 (1,2)
Trib7 (7,1)
Trib6 (6,1)
Trib5 (5,1)
Trib4 (4,1)
Trib3 (3,1)
Trib2 (2,1)
Trib1 (1,1)
1 = Add; 0 = Pass through.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 = Add; 0 = Pass through.
1 = Add; 0 = Pass through.
1 = Add; 0 = Pass through.
1 = Add; 0 = Pass through.
1 = Add; 0 = Pass through.
1 = Add; 0 = Pass through.
1 = Add; 0 = Pass through.
1 = Add; 0 = Pass through.
1 = Add; 0 = Pass through.
1 = Add; 0 = Pass through.
1 = Add; 0 = Pass through.
1 = Add; 0 = Pass through.
1 = Add; 0 = Pass through.
1 = Add; 0 = Pass through.
1 = Add; 0 = Pass through.
1 = Add; 0 = Pass through.
1 = Add; 0 = Pass through.
1 = Add; 0 = Pass through.
1 = Add; 0 = Pass through.
1 = Add; 0 = Pass through.
8
7
6
5
4
3
2
1
0
48
ꢀ
LXT6251 Microprocessor Interface & Register Definitions
TU_TS_CONF—TU Time Slot Configuration (161–175H)
21 Registers; 161H (Port 1) through 175H (Port 21)
These registers set the TU Time slot for each of the 21 Transmit and Receive I/O ports. The register should only be used
in the Add/Drop configuration.
Bit
Name
Description
Type
Default
7:5
4:0
Reserved
TimeSlot
Unused
Selects which TU Timeslot is associated with Port X. Valid
value range is 1 through 21. The default value corresponds to the
port number. For example, register 168h (configuration for port
8) is associated with TU 8 by default and so its default value will
be ‘01000’. Refer to “Port Mapping Configuration” for a discus-
sion about these 21 registers and a table of the default values.
R/W
*
SIGLA_SET—Signal Label Setting (xEH)
x=1–15H
This register sets the signal label value in outgoing V5 byte. The register also sets the RFI bit.
Bit
Name
Reserved
Label
Type
Default
7:5
4
Unused
RFISet
Set the value of V5 RFI bit in V5.
R/W
R/W
0
3:1
SigLabelSet
Set the values of the three Signal Label bits in V5. The only valid
values that indicate modes supported by the chip are 000, 001 and
010. Setting the channel to Unequipped will cause the mapper to
generate an unequipped VC-12 toward the SDH network. The type
of unequipped signal is controlled from the Global Configuration
register.
010
0
Reserved
Unused
J2_MRST—J2 Memory Reset (008H)
This register is provided as a protection measure when
accessing the J2 memories. During configuration of a
tributary’s J2 memory, a global pointer is used to step
through the internal memory locations. This pointer is
incremented with each write to the address of the string
data. Writing to this register location resets this pointer to
ensure the proper alignment of the microprocessor and the
internal memory. It will take four system clock cycles
(6.48MHz/19.44MHz) for the reset to complete. Under
normal use, the 16 reads or writes necessary to access a J2
word will reset this global pointer back to 0 for the next
tributary.
Bit
Name
Description
Type
Default
7:0
J2MemReset
No specific value. A write resets the memory pointer.
WO
00H
49
ꢀ
LXT6251 21 E1 SDH Mapper
J2_ESDATA—J2 Expected String Data (xCH)
x=1–15H
This register is used to access the J2 memory for this receive channel. Successive reads or writes to this register will
increment a global counter that increments the address 0 through 15. A write to global register 004H resets this counter to
0. This is not needed if all 16 bytes are always read or written to J2 memory.
Bit
Name
Description
Type
Default
7:0
ExpcJ2StrgData
Bits <7:0> correspond to data <7:0>, respectively.
R/W
00H
J2_TSDATA—J2 Transmit String Data (xFH)
x=1–15H
This register is used to access the J2 memory for this transmit channel. Successive reads or writes to this register will
increment a global counter that increments the address 0 through 15. A write to global register 004H resets this counter to
0. This is not needed if all 16 bytes are always read or written to J2 memory.
Bit
Name
Description
Type
Default
7:0
XmtJ2StrgData
Bits <7:0> correspond to data <7:0>, respectively.
R/W
00H
50
ꢀ
LXT6251 Microprocessor Interface & Register Definitions
ERRI_CONF—Error Insert Configuration (xDH)
x=1–15H
Configures normal operation diagnostic functionality. These registers should be set to their default configuration unless the
unit is in diagnostic mode and is not transmitting valid traffic.
Bit
Name
Reserved
XmtJ2Access
Description
Type
Default
7
6
1 = Allows the microprocessor to access the transmit J2 RAM via
register xFH. Sixteen consecutive writes to xFH will fill the
RAM. The address is internally incremented after each write.
A write to register 004H resets this global address counter.
Also forces the J2 output byte to 00H when globally config-
ured for standard unequipped, or 01H for supervisory
unequipped.
R/W
1
0 = Disable
5
4
XmtHpaAisFrc Force TU-AIS generation towards SDH network.
R/W
R/W
0
1
1 = Force
0 = Disable
XmtLptRdiEn
Enable/Disable automatic hardware updates of V5 RDI bit. Used
when the microprocessor needs direct control of RDI.
1 = Enable
0 = Disable
3
2
XmtLptRdiFrc Force active status of V5 RDI. Also causes K4 ERDI bits to be set
to ‘111’.
R/W
R/W
0
1
1 = Force
0 = Disable
XmtLptReiEn
Enable/Disable automatic hardware updates of V5 REI bit. Used
when the microprocessor needs direct control of REI.
1 = Enable
0 = Disable
1
0
XmtLptReiFrc
InvBip
Force active status of V5 REI.
1 = Force
R/W
R/W
0
0
0 = Disable
Enable/Disable the insertion of BIP-2 bit errors. Used to test
receiver functions downstream. When set, both BIP values are
inverted from their calculated value.
1 = Enable
0 = Disable
INT_CONF—Interrupt Configuration Register (00BH)
51
ꢀ
LXT6251 21 E1 SDH Mapper
Bit
Name
Reserved
Description
Type
Default
7:4
3
Unused
UpdateEn
Controls the tributary Status register update mechanism. When set
to ‘1’, an interrupt in the IRQ register associated with the status
register will freeze both registers until the status register has been
read. A ‘0’ allows updates to the status registers every multiframe.
R/W
0
0 = Always update status every multiframe
1 = Disable status update if interrupt alarm
2
1
LOMIntEn
TBParIntEn
When set to ‘1’, allows a LOM alarm to activate the INT pin.
R/W
R/W
0
0
0 = Disable INT output pin dependency
1 = Enable INT output pin dependency
When set to ‘1’, allows a parity error detected on the receive
telecom bus to activate the INT pin.
0 =Disable INT output pin dependency
1 = Enable INT output pin dependency
0
MasIntEn
Master Interrupt Enable; disables the INT output from chip.
R/W
0
0 = Disable
1 = Enable
CHIP_ID—Chip Identification Number (00AH)
This register is read-only and is used to identify the version of the Chip.
Bit
Name
Description
Type
Default
7:0
ChipID
Chip Identification < 7:0>
RO
52
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LXT6251 Microprocessor Interface & Register Definitions
Interrupt Registers
GLOB_INTS—Global Interrupt Source (00CH)
The Tributary Alarm Group identifies the tributary group
that is in alarm. The microprocessor will require two reads
(this and the Tributary ID interrupt register) to determine
which tributary is in alarm. Global alarms not associated
with tributaries are also in this register.
Bit
Name
Reserved
Description
Type
Default
7:6
5
Unused
X,X
0
LOMSt
1 = Indicates the H4 multiframe indicator has been lost. The alarm
is set when the DTBH4EN signal is constant ‘0’.
RO
RO
RO
4
3
LOMInt
TBParInt
1 = Indicates the interrupt has been generated by the LOM alarm.
The interrupt bit is reset when the register is read.
0
0
1 = indicates a mismatch between the received DTBPAR parity bit
and the calculated parity on the DTBDATA byte. The mismatch
must occur 15 times in one multiframe for the alarm to be set. The
alarm will be reset when the register is read.
2
1
0
TribGrp3
TribGrp2
TribGrp1
1 = Indicates Tributaries 17-21 are source of interrupt.
1 = Indicates Tributaries 9-16 are source of interrupt
1 = Indicates Tributaries 1-8 are source of interrupt
RO
RO
RO
0
0
0
53
ꢀ
LXT6251 21 E1 SDH Mapper
TRIB_ISRC—Tributary Interrupt Source Identification (00F–00DH)
00FH=Bits<23:16>, 00EH=Bits<15:8>, 00DH=Bits<7:0>
(Byte access only)
This 24-bit register indicate which tributary (or tributaries)
has active interrupts. A ‘1’ indicates tributary has an active
interrupt.
Bit
Name
Description
Type
Default
23:21 Reserved
Unused
20
19
18
17
16
15
14
13
12
11
10
9
Trib21
Trib20
Trib19
Trib18
Trib17
Trib16
Trib15
Trib14
Trib13
Trib12
Trib11
Trib10
Trib9
1 = Tributary has alarm.
1 = Tributary has alarm.
1 = Tributary has alarm.
1 = Tributary has alarm.
1 = Tributary has alarm.
1 = Tributary has alarm.
1 = Tributary has alarm.
1 = Tributary has alarm.
1 = Tributary has alarm.
1 = Tributary has alarm.
1 = Tributary has alarm.
1 = Tributary has alarm.
1 = Tributary has alarm.
1 = Tributary has alarm.
1 = Tributary has alarm.
1 = Tributary has alarm.
1 = Tributary has alarm.
1 = Tributary has alarm.
1 = Tributary has alarm.
1 = Tributary has alarm.
1 = Tributary has alarm.
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
8
7
Trib8
6
Trib7
5
Trib6
4
Trib5
3
Trib4
2
Trib3
1
Trib2
0
Trib1
54
ꢀ
LXT6251 Microprocessor Interface & Register Definitions
TRIB_INT—Tributary Interrupt (x1–x0H)
x=1–15H; x1H=Bits<15:8>, x0H=Bits<7:0> (Byte access
Tributary Status (x3–x2H) (page 57) which follow the
same bit pattern.
only)
Each tributary has a set of these registers that identify the
interrupt source for the tributary. For those alarms that are
persistent (i.e. they can be active longer than a multiframe),
there are associated status registers in TRIB_STA—
These registers are normally updated every multiframe.
However if the UpDateEn bit is set to ‘1’ in INT_CONF—
Interrupt Configuration Register (00BH) (page 51) they
will be frozen until the associated status register is read.
Bit
Name
Description
Type
Default
15:13 Reserved
Unused
12
11
TuNDF
Tim
This alarm indicates the HPA section has received an NDF flag in the
V1 pointer.
R
R
X
X
This alarm indicates a J2 Trace MisMatch alarm. It is asserted IF the
received vs. calculated CRC-7 match (no J2 bit errors), but the
received J2 word does not match that stored in RAM. The CRC-7
byte in RAM is not used in the comparison.
10
Crc7Err
This alarm indicates a bit error has been detected in the J2 word. The
alarm is asserted when the received CRC-7 byte does not match the
one calculated on the received data. Detection of this alarm will mask
the TIM alarm.
R
X
9
8
TuLop
TuAis
Bip2
This alarm indicates the demapper has detected a Loss of Pointer
alarm.
R
R
X
X
This alarm indicates the demapper has detected the pointer value is in
an AIS condition.
7
6
This alarm indicates that a BIP error has been detected.
R
R
X
X
Bip2OvrFlw This alarm indicates the BIP counter has overflowed. The counter
will rollover to 0 and continue counting.
5
4
Rei
This alarm indicates the V5 REI bit was set to ‘1’.
R
R
X
X
ReiOvrFlw
This alarm indicates the REI counter has overflowed. The counter
will rollover to 0 and continue counting.
3
Rdi
This alarm indicates the V5 RDI bit was set to ‘1’ for five consecu-
tive multiframes.
R
X
2
1
Rfi
This alarm indicates the V5 RFI bit was set to ‘1’.
R
R
X
X
Slm
This alarm indicates that a Signal Label Mismatch has occurred. This
alarm is asserted if the Signal Label is detected to be a value other
than ‘000’ (Uneq), ‘001’ (Equip, non specific), or ‘010’ (Equip,
async) for five consecutive frames. Removal of the alarm also
requires five consecutive frames.
0
UnEqp
This alarm indicates that the Signal Label in V5 is detected as ‘000’
for five consecutive frames. Removal of the alarm also requires five
consecutive frames.
R
X
55
ꢀ
LXT6251 21 E1 SDH Mapper
TRIB_INTE—Tributary Interrupt Enable (x5–x4H)
x=1–15H; x5H=Bits<15:8>, x4H=Bits<7:0> (Byte access
Each tributary has a set of these registers that can be used
only)
to enable an interrupt source for a particular tributary. The
Reset default is not enabled (‘0’).
Bit
Name
Description
Type
Default
15:14 Reserved
Unused
13
RxJ2Access
1= Allows the microprocessor to control access to the expected
J2 RAM via register xCH. Sixteen consecutive writes to
xCH will fill the RAM. The address is internally incre-
mented after each write. A write to register 004h will reset
this global counter. Also disables both the TIM and CRC7
alarm associated with J2 so no alarms or RDI feedback is
generated during configuration of the expected J2 string.
R/W
1
12
11
10
9
TuNDFIntEn
TimIntEn
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
Crc7ErrIntEn
TuLopIntEn
TuAisIntEn
Bip2IntEn
8
7
6
Bip2OvrFlwIntEn
ReiIntEn
5
4
ReiOvrFlwIntEn
RdiIntEn
3
2
RfiIntEn
1
SlmIntEn
0
UnEqIntEn
56
ꢀ
LXT6251 Microprocessor Interface & Register Definitions
Status and Control Registers
TRIB_STA—Tributary Status ( 3– 2H)
x x
x=1–15H; x3H=Bits<15:8>, x2H=Bits<7:0> (Byte access
registers mirror the interrupt registers but do not contain
status of non-persistent alarm events such as the BIP-2
error event.
only)
Each tributary has a set of these registers giving the present
status of each alarm source for a particular tributary. The
Rdi, Rfi, Slm & UnEq bits in interrupt register x0H are
cleared when x2H is read. The TIM, TimCrc7, TuLop &
TuAis bits in x1H are cleared when x3H is read. These
These registers are normally updated every multiframe.
However if the UpDateEn bit is set to ‘1’ in INT_CONF—
Interrupt Configuration Register (00BH) (page 51) they
will be frozen until the register is read.
Bit
Name
Reserved
Description
Type
Default
15:12
11
10
9
Unused
Unused
TimSt
RO
RO
RO
RO
X
X
X
X
Crc7ErrSt
TuLopSt
TuAisSt
Reserved
RdiSt
8
7:4
3
RO
RO
RO
RO
X
X
X
X
2
RfiSt
1
SlmSt
0
UnEqSt
BIP2_ERRCNT—BIP2 Error Counter ( 7– 6H)
x x
x=1–15H; x7H=Bits<15:8>, x6H=Bits<7:0> (Byte access
the microprocessor must provide a Write command to the
MSB address bit of register x6H at least 3 byte clock
periods (0.5us in STM-0) before the two Read commands.
The Write command clears the counter after buffering it.
only)
This counter increments each time a BIP error event in the
Low Order Path section is detected. To access the count,
Bit
15:12 Reserved
11:0 BipCnt
Name
Description
Type
Default
Unused
Bits<11:8> are the most significant byte of the BIP error event
counter. Bits<7:0> are the least significant bits.
RO
X
57
ꢀ
LXT6251 21 E1 SDH Mapper
REI_CNT—Remote Error Indication (REI) Counter (x9–x8H)
x=1–15H; x9H=Bits<15:8>, x8H=Bits<7:0> (Byte access
must provide a Write command to the MSB address bit of
only)
register x9H at least three byte clock periods (0.5us in
STM-0) before the two Read commands. The Write
command clears the counter after buffering it.
This counter increments each frame in which the receive
V5 REI bit is set. To access the count, the microprocessor
Bit
15:11 Reserved
10:0 LptReiCnt
Name
Description
Type
Default
Unused
Bits<10:8> are the most significant bits of the Low Order Path
OverHead REI error event counter. Bits<7:0> are the least sig-
nificant bits.
RO
X
K4_STA—K4 Status (xAH)
x=1–15H
The K4 byte provides an Enhanced RDI that can be retrieved via a read of this register. This register is updated only if there
is a change in the V5 RDI bit and the tributary source supports K4 ERDI.
Bit
Name
Reserved
Description
Type
Default
7:4
3:1
0
RO
RO
RO
0
X
0
Enhanced RDI
Reserved
K4 ERDI bits.
V5_STA—V5 Status Register (xBH)
x=1–15H
The V5 status register is provided for raw access to the received V5 byte (see Figure 4). There is no alarm or INT generation
directly associated with this register. The value in this register changes every multiframe (500uS).
Bit
Name
BIP2
Description
Type
Default
7:6
5
V5 BIP-2 bits
V5 REI bit
RO
RO
RO
RO
RO
X
X
X
X
X
REI
4
RFI
V5 RFI bit
3:1
0
SigLabel
RDI
V5 Signal Label bits
V5 RDI bit
58
ꢀ
Testability Modes
TESTABILITY MODES
The LXT6251 21E1 Mapper/Demapper provides a method
.
for enhancing testability: IEEE1149.1 Boundary Scan
(JTAG) is used for testing of the interconnect.
Table 18: JTAG Pin Description
Pin #
Name
I/O
Function
IEEE 1149.1 Boundary Scan
Description
152
JTMS_P
I
Test Mode Select:
Determines state of
TAP Controller. Pull
up 48k
The boundary scan circuitry allows the user to test the
interconnection between the LXT6251 and the circuit
board.
153
151
JTCK_P
JTRS_P
I
I
Test Clock: Clock for
all boundary scan cir-
cuitry
The boundary scan port consists of 5 pins as shown in
Table 18. The heart of the scan circuitry is the Test Access
Port controller (TAP). The TAP controller is a 16 state
machine that controls the function of the boundary scan
circuitry. Inputs of the TAP controller are the Test Mode
Select (JTMS) and the Test Clock (JTCK) signals.
Test Reset: Active
low asynchronous
signal that causes
the TAP controller to
reset. Pull down 35k
150
149
JTDI_P
I
Test Data In: Input
signal used to shift in
instructions and
Data and instructions are shifted into the LXT6251 through
the Test Data In pin (JTDI). Data and instructions are
shifted out through the Test Data Out pin (JTDO). The
asynchronous reset pin (JTRS) resets the boundary scan
circuitry
data. Pull up 48k
JTDO_P
O
Test data Out: Output
signal used to shift
out instructions and
data.
Figure 19:Test Access Port
Boundary Scan
Bypass Register
JTDI
TDO
Device ID register
Instruction Register
JTMS
Test Access
Port Controller
JTCK
JTRS
59
ꢀ
LXT6251 21 E1 SDH Mapper
BYPASS (‘b11)
Instruction Register and
Definitions
The LXT6251 supports the following instructions
IEEE1149.1: EXTEST, SAMPLE/PRELOAD, BYPASS
and IDCODE. Instructions are shifted into the instruction
register during the SHIFT-IR state, and become active
upon exiting the UPDATE-IR state. The instruction
register definition is shown in the following figure.
This instruction allows a device to be effectively removed
from the scan chain, by inserting a one-bit shift register
stage between TDI and TDO during data shifts. When the
instruction is active, the test logic has no impact upon the
system logic performing its system function. When
selected, the shift-register is set to a logic zero on the rising
edge of the JTCK during the CAPTURE-DR state.
IDCODE (‘b10)
Figure 20:Instruction Register
This instruction allows the reading of component types via
the scan chain. During this instruction, the 32-bit Device
Identification Register (ID-Register) is placed between
TDI and TDO. The ID Register captures a fixed value of
(‘h 1186B0FD) on the rising edge of JTCK during the
CAPTURE-DR state. The Device Identification Register
contains the following information: Manufacturer ID:
‘d126; Design Part Number: ‘d 6251; Design Version
Number: ‘d1.
TDI
MSB
LSB
EXTEST (‘b00)
This instruction allows the testing of circuitry external to
the package, typically the board interconnect, to be tested.
While the instruction is active, the boundary scan register
is connected between TDI and TDO, for any data shifts.
Boundary scan cells at the output pins are used to apply test
stimuli, while those at input pins capture test results.
Signals present on input pins are loaded into the BSR
inputs cells on the rising edge of JTCK during CAPTURE-
DR state. BSR contents are shifted one bit location on each
rising edge of JTCK during the SHIFT-DR state. BSR
output cell contents appear at output pins on the falling
edge of JTCK during the UPDATE-IR state.
Boundary Scan Register
The Boundary Scan Register is a 165 bit shift register,
made of four styles of shift-register cells with two sub-
types. According to the Boundary Scan Description
Language (BSDL):
JTAG_BSRINBOTH,
JTAG_BSROUTBOTH and
JTAG_BSRCTL are designated TYPE2,
JTAG_BSRINCLKOBS is designated TYPE1.
Description
• Length: 165 BSR cells
One test cycle is:
• JTCK_P Jtag Test Clock
1. A test stimuli pattern is shifted into the BSR during
SHIFT-DR state.
• JTDI_P Jtag Test Data Input
• JTDO_C Jtag Test Data Output Control enable
• JTDO_P Jtag Test Data Output
• JTMS_P Jtag Test Mode Select
• JTRS_P Jtag Test Reset
2. This pattern is applied to output pins during the
UPDATE-DR state.
3. The response is loaded into the input BSR cells during
the CAPTURE-DR state.
4. The results are shifted out and next test stimuli shifted
into the BSR.
SAMPLE/PRELOAD (‘b01)
This instruction allows a snapshot of the normal operation
of the LXT6251. The boundary scan register is connected
between the TDI and TDO for any data shifts while this
instruction is active. All BSR cells capture data present at
their inputs on the rising edge of JTCK during the
CAPTURE-DR state. No action is taken during the
UPDATE-DR state.
60
ꢀ
LXT6251 Testability Modes
Figure 21:Boundary Scan Cells
Data in
Data out
Scan out
Scan in
Type 1
Shift dr
Clock dr
Scan out
Data out
Data in
Scan in
Shift dr
Type 2
Clock dr
Update dr
M ode
61
ꢀ
LXT6251 21 E1 SDH Mapper
Table 19: JTAG Scan Chain
Numberingin
Scan chain
Associated
Control enable
PIN Name
Type
Type of BSR Cell
OEN
Data
Enable
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Clock
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Enable
Clock
Data
Data
Data
Data
Data
1
JTAG_BSRINBOTH
JTAG_BSRCTL
OEN_c
2
SCANEN
3
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINCLKOBS
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRCTL
DtbDATA<7>
DtbDATA<6>
DtbDATA<5>
DtbDATA<4>
DtbDATA<3>
DtbDATA<2>
DtbDATA<1>
DtbDATA<0>
DtbPAR
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
DtbYck
DtbJ0J1en
DtbTUGen
PTTUGA
PTTUGB
PTSOH
DtbPAYEN
DtbH4en
MtbH4en/I
MtbH4en/O
MtbPAYEN/I
MtbPAYEN/O
MtbTUGen
MtbJ0J1en/I
MtbJ0J1en/O
MtbTime_c
MtbYck
MtbTime_c
MtbTime_c
MtbTime_c
JTAG_BSRINCLKOBS
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
MtbPAR
MtbDATA_c
MtbDATA_c
MtbDATA_c
MtbDATA_c
MtbDATA_c
MtbDATA<0>
MtbDATA<1>
MtbDATA<2>
MtbDATA<3>
62
ꢀ
LXT6251 Testability Modes
Table 19: JTAG Scan Chain – continued
Numberingin
Scan chain
Associated
Control enable
PIN Name
Type
Type of BSR Cell
MtbDATA<4>
Data
Data
Data
Data
Enable
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Enable
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Clock
Data
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRCTL
MtbDATA_c
MtbDATA_c
MtbDATA_c
MtbDATA_c
MtbDATA<5>
MtbDATA<6>
MtbDATA<7>
MtbDATA_c
MtbDOE
DATA/I<7>
DATA/O<7>
DATA/I<6>
DATA/O<6>
DATA/I<5>
DATA/O<5>
DATA/I<4>
DATA/O<4>
DATA/I<3>
DATA/O<3>
DATA/I<2>
DATA/O<2>
DATA/I<1>
DATA/O<1>
DATA/I<0>
DATA/O<0>
D_c
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRCTL
OEN_C
D_c
D_c
D_c
D_c
D_c
D_c
D_c
D_c
A<8>
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINCLKOBS
JTAG_BSRINBOTH
A<7>
A<6>
A<5>
A<4>
A<3>
A<2>
A<1>
A<0>
CSB
AS
WR/RW
RD/E
63
ꢀ
LXT6251 21 E1 SDH Mapper
Table 19: JTAG Scan Chain – continued
Numberingin
Scan chain
Associated
Control enable
PIN Name
Type
Type of BSR Cell
INT
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
71
72
73
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
OEN_c
MCUTYPE
STMMODE
RST
74
MRAPDATA
MRAPCLK
MRAPFRM
DSAPFRM
DSAPCLK
DSAPDATA
DTC0
75
76
77
78
79
80
OEN_c
OEN_c
OEN_c
OEN_c
OEN_c
81
DTD0
82
MTD0
83
MTC0
84
MTC1
85
MTD1
86
DTD1
87
OEN_c
OEN_c
OEN_c
OEN_c
DTC1
88
DTC2
89
DTD2
90
MTD2
91
MTC2
92
MTC3
93
MTD3
94
DTD3
95
OEN_c
OEN_c
OEN_c
OEN_c
DTC3
96
DTC4
97
DTD4
98
MTD4
99
MTC4
100
101
102
103
104
105
106
MTC5
MTD5
DTD5
OEN_c
OEN_c
OEN_c
OEN_c
DTC5
DTC6
DTD6
64
ꢀ
LXT6251 Testability Modes
Table 19: JTAG Scan Chain – continued
Numberingin
Scan chain
Associated
Control enable
PIN Name
Type
Type of BSR Cell
MTD6
MTC6
MTC7
MTD7
DTD7
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
OEN_c
OEN_c
OEN_c
OEN_c
DTC7
DTC8
DTD8
MTD8
MTC8
MTC9
MTD9
DTD9
OEN_c
OEN_c
OEN_c
OEN_c
DTC9
DTC10
DTD10
MTD10
MTC10
MTC11
MTD11
DTD11
DTC11
DTC12
DTD12
MTD12
MTC12
MTC13
MTD13
DTD13
DTC13
DTC14
DTD14
MTD14
MTC14
MTC15
MTD15
OEN_c
OEN_c
OEN_c
OEN_c
OEN_c
OEN_c
OEN_c
OEN_c
65
ꢀ
LXT6251 21 E1 SDH Mapper
Table 19: JTAG Scan Chain – continued
Numberingin
Scan chain
Associated
Control enable
PIN Name
Type
Type of BSR Cell
DTD15
DTC15
DTC16
DTD16
MTD16
MTC16
MTC17
MTD17
DTD17
DTC17
DTC18
DTD18
MTD18
MTC18
MTC19
MTD19
DTD19
DTC19
DTC20
DTD20
MTD20
MTC20
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
OEN_c
OEN_c
OEN_c
OEN_c
OEN_c
OEN_c
OEN_c
OEN_c
OEN_c
OEN_c
OEN_c
OEN_c
SCANTEST
66
ꢀ
LXT6251 Package Specification
PACKAGE SPECIFICATION
• Part Number LXT6251
• 208-pin Plastic Quad Flat Pack
• Extended Temperature Range
(-40, +850C)
D
D1
Millimeters
Dim
Min
Max
A
A1
A2
b
-
4.10
-
e
0.05
3.20
0.17
E1
3.60
0.27
E
e
/
2
D
30.60 BSC.
D1
E
28.00 BSC.
30.60 BSC.
28.00 BSC.
.50 BSC.
E1
e
θ2
L1
L
0.50
0.75
L1
θ
1.30 REF
A2
A
0°
5°
5°
7°
θ
θ2
θ3
16°
16°
A1
θ3
b
L
67
ꢀ
LXT6251 21 E1 SDH Mapper
GLOSSARY
AIS
Alarm Indication Signal
AUG
RDI
Administrative Unit Group
Remote Defect Indication
Remote Error Indication
Remote Fail Indication
REI
RFI
FIFO
MSOH
NRZ
First in/First Out Memory
Multiplexer Section Overhead
Non-Return to Zero
POH
Path Overhead
RSOH
SDH
Regenerator Section Overhead
Synchronous Digital Hierarchy
Synchronous Payload Envelope
Synchronous Optical NETwork
Synchronous Transport Module
SPE
SONET
STM
STM-RR
Synchronous Transport Module for
Radio Relay
STS
TUG
VC
Synchronous Transport Signal
Tributary Unit Group
Virtual Container
68
ꢀ
LXT6251 Glossary
69
ꢀ
LXT6251 21 E1 SDH Mapper
Notes
70
ꢀ
LXT6251 Glossary
71
ꢀ
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Revision
Date
Status
2.0
1.0
0.0
8/99
02/98
00/00
New product name, logo
Product Release
Advance Information, limited distribution
The products listed in this publication are covered by one or more of the following patents. Additional patents pending.
5,008,637; 5,028,888; 5,057,794; 5,059,924; 5,068,628; 5,077,529; 5,084,866; 5,148,427; 5,153,875; 5,157,690; 5,159,291; 5,162,746; 5,166,635; 5,181,228;
5,204,880; 5,249,183; 5,257,286; 5,267,269; 5,267,746; 5,461,661; 5,493,243; 5,534,863; 5,574,726; 5,581,585; 5,608,341; 5,671,249; 5,666,129; 5,701,099
Copyright © 1999 Level One Communications, Inc., an Intel company. Specifications subject to change without notice.
All rights reserved. Printed in the United States of America.
PDS-6251-8/99-2.0
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