1402 [Linear]
Serial 12-Bit, 2.2Msps Sampling ADC with Shutdown; 串行12位， 2.2Msps采样ADC ，带有关断
| 型号： | 1402 |
| 厂家： | 
Linear |
| 描述： | Serial 12-Bit, 2.2Msps Sampling ADC with Shutdown |
| 文件： | 总24页 (文件大小：281K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1402
Serial 12-Bit, 2.2Msps
Sampling ADC with Shutdown
U
FEATURES
DESCRIPTIO
The LTC®1402 is a 12-bit, 2.2Msps sampling A/D con-
verter. This high performance device includes a high dy-
namic range sample-and-hold and a precision reference.
It operates from a single 5V supply or dual ±5V supplies
and draws only 90mW from 5V.
■
Sample Rate: 2.2Msps
■
72dB S/(N + D) and –89dB THD at Nyquist
■
Power Dissipation: 90mW (Typ)
■
80MHz Full Power Bandwidth Sampling
■
No Missing Codes over Temperature
■
Available in 16-Pin Narrow SSOP Package
The versatile differential input offers a unipolar range of
4.096V and a bipolar range of ±2.048V for dual supply
systems where high performance op amps perform best,
eliminating the need for special translation circuitry.
■
Single Supply 5V or ±5V Operation
■
Nap Mode with Instant Wake-Up: 15mW
■
Sleep Mode: 10µW
■
True Differential Inputs Reject Common Mode Noise
The high common mode rejection allows users to elimi-
nategroundloopsandcommonmodenoisebymeasuring
signals differentially from the source.
■
Input Range (1mV/LSB): 0V to 4.096V or ±2.048V
■
Internal Reference Can Be Overdriven Externally
■
3-Wire Interface to DSPs and Processors (SPI and
MICROWIRETM Compatible)
U
Outstanding AC performance includes 72dB S/(N + D) and
–93dB SFDR at the Nyquist input frequency of 1.1MHz
with dual ±5V supplies and –84dB SFDR with a single 5V
supply.
APPLICATIO S
■ Telecommunications
■
The LTC1402 has two power saving modes: Nap and
Sleep. Nap mode consumes only 15mW of power and can
wake up and convert immediately. In Sleep mode, it
typically consumes 10µW of power. Upon power-up from
Sleep mode, a reference ready (REFRDY) signal is avail-
able in the serial data word to indicate that the reference
has settled and the chip is ready to convert.
High Speed Data and Signal Acquisition
■
Digitally Multiplexed Data Acquisition Systems
■
■
■
■
■
Digital Radio Receivers
Spectrum Analysis
Low Power and Battery-Operated Systems
Handheld or Portable Instruments
Imaging Systems
The 3-wire serial port allows compact and efficient data
transfer to a wide range of microprocessors, microcon-
trollers and DSPs. A digital output driver power supply pin
allows direct connection to 3V or lower logic.
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corp.
W
BLOCK DIAGRA
5V
3V OR 5V
5 Harmonic THD, 2nd, 3rd and SFDR
vs Input Frequency (Unipolar)
1
AV
DD
12 DV
11 OV
DD
DD
10µF
0
THD
SFDR
–10
3
+
A
IN
–20
–30
2ND
3RD
SAMPLE-
10
OUTPUT
BUFFER
12-BIT ADC
D
OUT
AND-HOLD
f
= 2.22MHz
4
5
SAMPLE
–
–40
A
IN
–50
4.096V
V
–60
REF
10µF
64k
64k
–70
–
+
–80
8
BIP/UNI
CONV
SCK
–90
16
15
7
2.048
REFERENCE
TIMING
LOGIC
–100
–110
–120
GAIN
LTC1402
1402 TA01
14
10µF
–5V OR 0V
V
SS
2
AGND1
6
AGND2
13 DGND
9 OGND
4
5
6
7
10
10
10
10
INPUT FREQUENCY (Hz)
1401 G05
1
LTC1402
U
W U
W W
U W
PACKAGE/ORDER INFORMATION
ABSOLUTE MAXIMUM RATINGS
AVDD = DVDD = OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD)................................................. 6V
Negative Supply Voltage (VSS) ............................... –6V
Total Supply Voltage (VDD to VSS) .......................... 12V
Analog Input Voltage
(Note 3) .......................... (VSS – 0.3V) to (VDD + 0.3V)
Digital Input Voltage
(Note 4) .......................... (VSS – 0.3V) to (VDD + 0.3V)
Digital Output Voltage......... (VSS – 0.3V) to (VDD + 0.3V)
Power Dissipation.............................................. 250mW
Operation Temperature Range
LTC1402C ............................................... 0°C to 70°C
LTC1402I............................................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
TOP VIEW
NUMBER
AV
1
2
3
4
5
6
7
8
16 CONV
15 SCK
DD
AGND1
+
LTC1402CGN
LTC1402IGN
A
IN
14
13
12
11
10
9
V
SS
–
A
DGND
IN
V
DV
DD
REF
AGND2
GAIN
0V
DD
GN PART MARKING
D
OUT
BIP/UNI
OGND
1402
1402I
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
TJMAX = 125°C, θJA = 150°C/ W
Consult factory for Military grade parts.
U
CONVERTER CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With internal reference (Note 5).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity
Offset Error
●
●
●
●
●
12
(Note 6)
(Note 6)
(Note 6)
(Note 6)
±0.35
±0.25
±2
±1
±1
LSB
LSB
LSB
LSB
±10
±15
Full-Scale Error
±10
Full-Scale Tempco
Internal Reference (Note 6)
External Reference
±15
±1
ppm/°C
ppm/°C
U
U
A ALOG I PUT
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Analog Differential Input Range (Notes 3, 11)
Bipolar Mode with BIP/UNI High
●
●
±2.048
V
IN
4.75V ≤ V ≤ 5.25V
DD
–5.25V ≤ V ≤ –4.75V
SS
Unipolar Mode with BIP/UNI Low
0 to 4.096
V
4.75V ≤ V ≤ 5.25V
DD
–5.25V ≤ V ≤ 0V
SS
V
Analog Common Mode + Differential
Input Range (Note 12)
Dual ±5V Supply
Single 5V Supply
–2.5 to 5
0 to 5
V
V
CM
I
Analog Input Leakage Current
●
●
1
µA
pF
ns
ns
ps
IN
C
Analog Input Capacitance
10
IN
t
t
t
Sample-and-Hold Acquisition Time
Sample-and-Hold Aperture Delay Time
Sample-and-Hold Aperture Delay Time Jitter
Analog Input Common Mode Rejection Ratio
(Note 9)
57
ACQ
AP
2.6
1
JITTER
CMRR
f
f
= 1MHz, V = 2V to –2V
= 100MHz, V = 2V to –2V
–62
–24
dB
dB
IN
IN
IN
IN
2
LTC1402
U W
DYNAMIC ACCURACY
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. Bipolar mode with ± 5V supplies and unipolar mode with 5V supply. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
S/(N + D)
Signal-to-Noise Plus
Distortion Ratio
100kHz Input Signal
1.1MHz Input Signal
72.5
72.0
dB
dB
●
●
69
THD
SFDR
IMD
Total Harmonic
Distortion
100kHz First 5 Harmonics, Bipolar Mode
1.1MHz First 5 Harmonics, Bipolar Mode
100kHz First 5 Harmonics, Unipolar Mode
1.1MHz First 5 Harmonics, Unipolar Mode
–89
–89
–87
–82
dB
dB
dB
dB
–74.5
Spurious Free
Dynamic Range
100kHz Input Signal, Bipolar Mode
1.1MHz Input Signal, Bipolar Mode
100kHz Input Signal, Unipolar Mode
1.1MHz Input Signal, Unipolar Mode
–93
–93
–93
–84
dB
dB
dB
dB
+
–
Intermodulation
Distortion
±1V 1.25MHz into A , 1.2MHz into A Bipolar Mode
–84
–84
dB
dB
IN
IN
+
–
1.5V to 3.5V 1.25MHz into A , 1.2MHz into A Unipolar Mode
IN
IN
Code-to-Code
V
REF
= 4.096V, 1LSB = 1mV
0.18
LSB
RMS
Transition Noise
Full Power Bandwidth
V
IN
= 4V , D
= 2828LSB (Note 18)
82
MHz
P-P OUT
P-P
Full Linear Bandwidth S/(N + D) ≥ 68dB Bipolar Mode
5.0
3.5
MHz
MHz
Unipolar Mode
U U
U
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
INTERNAL REFERENCE CHARACTERISTICS
PARAMETER CONDITIONS
= 0
MIN
TYP
4.096
15
MAX
UNITS
V
V
V
V
V
V
Output Voltage
Output Tempco
Line Regulation
Output Resistance
Settling Time
I
OUT
REF
REF
REF
REF
REF
ppm/°C
LSB/V
Ω
AV = 4.75V to 5.25V, V = 4.096V
DD
1
REF
Load Current = 0.5mA
2
2
ms
U
U
The ● denotes the specifications which apply over the
DIGITAL I PUTS A D DIGITAL OUTPUTS
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
Digital Input Capacitance
High Level Output Voltage
V
V
V
= 5.25V
= 4.75V
= 0V to V
●
●
●
2.4
V
V
IH
IL
DD
DD
IN
0.8
I
±10
µA
pF
IN
DD
C
V
5
IN
OV = 4.75V, I
OV = 4.75V, I
OV = 3V, I
= –10µA
= –200µA
= –200µA
4.7
V
V
V
OH
DD
OUT
OUT
●
●
4
2.5
DD
2.9
DD
OUT
V
Low Level Output Voltage
V
V
= 4.75V, I
= 4.75V, I
= 160µA
= 1.6mA
0.05
0.10
V
V
OL
DD
DD
OUT
OUT
●
●
0.4
I
Hi-Z Output Leakage D
V
= 0V to V
DD
±10
µA
OZ
OUT
OUT
C
Hi-Z Output Capacitance D
15
pF
OZ
OUT
I
Output Short-Circuit Source Current
V
V
= 0V, OV = 5V
–40
–15
mA
mA
SOURCE
OUT
OUT
DD
= 0V, OV = 3V
DD
I
Output Short-Circuit Sink Current
V
= OV = 5V
40
mA
SINK
OUT
DD
3
LTC1402
POWER REQUIRE E TS
W U
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
4.75
TYP
MAX
5.25
0
UNITS
V
DD
V
SS
Positive Supply Voltage
Negative Supply Voltage
Positive Supply Current
V
V
–5.25
I
Active Mode
Nap Mode
Sleep Mode
●
●
18
3
2
30
5
10
mA
mA
µA
DD
I
Negative Supply Current
Power Dissipation
Active, Sleep or Nap Modes with SCK Off
●
2
µA
SS
PD
Active Mode with SCK in Fixed State (Hi or Lo)
90
150
mW
W U
TI I G CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Maximum Sampling Frequency (Conversion Rate)
Minimum Sampling Period (Conversion + Acquisiton Period)
Minimum Clock Period
●
●
●
2.2
MHz
SAMPLE(MAX)
455
ns
THROUGHPUT
28
57
10000
ns
SCK
CONV
0
Conversion Time
(Note 9)
14
SCK cycles
14th SCLK↑ to CONV↑ Interval
(Notes 9, 10, 16)
(Note 9)
●
●
●
●
●
●
●
●
●
●
●
●
●
●
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
Minimum Positive or Negative SCK Pulse Width
CONV to SCK Setup Time
3.8
7.3
6
1
(Notes 9, 13)
(Note 9)
12
2
SCK After CONV
0
48
4
3
Minimum Positive or Negative CONV Pulse Width
SCKto Sample Mode
(Note 9)
3.5
9
5
14
5
4
(Note 9)
5
CONV to Hold Mode
(Notes 9, 14)
(Note 9)
3.4
6
Minimum Delay Between Conversions
Minimum Delay from SCKto Valid Bits 0 Through 11
Minimum Delay from SCK to Valid REFREADY
7
(Notes 9, 15)
(Notes 9, 15)
(Notes 9, 15)
(Notes 9, 15)
(Notes 9, 17)
(Notes 9, 17)
9
15
11.4
7
12
20
16
8
8a
9
SCK to Hi-Z at D
OUT
Previous D
Bit Remains Valid After SCK
OUT
10
11
12
REFREADY Bit Delay After Sleep-to-Wake Transition
Settling Time After Sleep-to-Wake Transition
10
2
V
REF
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 6: Linearity, offset and full-scale specifications apply for a single-
+
–
ended A input with A grounded and using the internal reference in
IN IN
bipolar mode with ±5V supplies.
Note 2: All voltage values are with respect to ground with DGND, AGND1
and AGND2 wired together.
Note 3: When these pins are taken below V or above V , they will be
Note 7: Integral linearity is defined as the deviation of a code from the
straight line passing through the actual endpoints of a transfer curve. The
deviation is measured from the center of quantization band.
SS
DD
clamped by internal diodes. This product can handle input currents greater
than 100mA below V or greater than V without latchup.
Note 8: Bipolar offset is the offset measured from –0.5LSB when the input
SS
DD
flickers between 1000 0000 0000 and 0111 1111 1111.
Note 4: When these pins are taken below V , they will be clamped by
SS
internal diodes. This product can handle input currents greater than
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
100mA below V or greater than V . These pins are not clamped to V .
SS
DD
DD
Note 5: V = 5V, f
specifications and V = –5V for bipolar specifications.
= 2.2MHz, V = 0V for unipolar mode
SS
DD
SAMPLE
Note 11: The analog input range is defined as the voltage difference
+
–
SS
between A and A . The bipolar ±2.048V input range could be used
IN
IN
with a single 5V supply if the absolute voltages of the inputs remain within
the single 5V supply voltage.
4
LTC1402
ELECTRICAL CHARACTERISTICS
+
–
Note 12: The absolute voltage at A and A must be within this range.
Note 16: The time period for acquiring the input signal is started by the
IN
IN
14th rising clock and it is ended by the rising edge of convert.
Note 17: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10µF capacitive load. The
Note 13: If less than 7.3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Sleep mode resets the REFREADY bit in the D
REFREADY bit goes high again 10ms after the V has stopped slewing in
wake up. This ensures valid REFREADY bit operation even with higher load
sequence. The
REF
Note 14: Not the same as aperture delay. Aperture delay is smaller (2.6ns)
because the 0.8ns delay through the sample-and-hold is subtracted from
the CONV to Hold mode delay.
Note 15: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
OUT
capacitances at V
.
REF
Note 18: The full power bandwidth is the frequency where the output code
swing drops to 2828LSBs with a 4V input sine wave.
P-P
U W
(Bipolar Mode Plots Run with Dual ±5V Supplies.
TYPICAL PERFOR A CE CHARACTERISTICS
Unipolar Mode Plots Run with a Single 5V Supply. VDD = 5V, VSS = –5V for Bipolar, VDD = 5V, VSS = 0V for Unipolar), TA = 25°C.
5 Harmonic THD, 2nd, 3rd and
SFDR vs Input Frequency
(Bipolar)
ENOBs and SINAD
vs Input Frequency (Bipolar)
SNR vs Input Frequency (Bipolar)
12
11
10
9
74
68
62
56
50
44
38
32
26
20
14
8
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–2
–8
THD
SFDR
2ND
3RD
f
= 2.22MHz
SAMPLE
–14
–20
–26
–32
–38
–44
–50
–56
–62
–68
–74
f
= 2.22MHz
SAMPLE
8
7
6
5
4
3
2
1
f
= 2.22MHz
SAMPLE
0
10
2
4
5
6
7
4
5
6
7
4
5
6
7
10
10
10
10
10
10
10
10
10
10
10
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
1401 G01
1401 G02
1401 G03
5 Harmonic THD, 2nd, 3rd and
SFDR vs Input Frequency
(Unipolar)
ENOBs and SINAD
vs Input Frequency (Unipolar)
SNR vs Input Frequency (Unipolar)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–2
–8
12
11
10
9
74
68
62
56
50
44
38
32
26
20
14
8
THD
SFDR
2ND
3RD
f
= 2.22MHz
SAMPLE
–14
–20
–26
–32
–38
–44
–50
–56
–62
–68
–74
f
= 2.22MHz
SAMPLE
8
7
6
5
4
3
2
1
f
= 2.22MHz
SAMPLE
0
2
4
5
6
7
4
5
6
7
4
5
6
7
10
10
10
10
10
10
10
10
10
10
10
10
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
1401 G05
1401 G06
1401 G04
5
LTC1402
TYPICAL PERFOR A CE CHARACTERISTICS
U W
(Bipolar Mode Plots Run with Dual ±5V Supplies.
Unipolar Mode Plots Run with a Single 5V Supply. VDD = 5V, VSS = –5V for Bipolar, VDD = 5V, VSS = 0V for Unipolar), TA = 25°C.
Sine Wave Spectrum Plot
(Bipolar) ±5V Supply
Sine Wave Spectrum Plot
(Bipolar) Dual ±5V Supply
IMD Spectrum Plot (Bipolar)
10
0
10
0
10
0
f
f
f
= 2352941.18Hz
SAMPLE
SINEA
SINEB
+
–
= 1250000Hz ±1V INTO A
IN
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
= 1199449Hz ±1V INTO A
IMD = 83.9dB
IN
2048 SAMPLES
2f – f
A
B
B
2f + f
A
0
0.55
1.11
0
0.55
FREQUENCY (MHz)
1.11
0
0.59
FREQUENCY (MHz)
1.18
FREQUENCY (MHz)
1402 G09
1402 G11
1402 G10
Sine Wave Spectrum Plot
(Unipolar) 5V Supply
Sine Wave Spectrum Plot
(Unipolar) 5V Supply
IMD Spectrum Plot (Unipolar)
10
0
10
0
10
0
f
f
= 2222222.22Hz
f
= 2352941.18Hz
SAMPLE
SAMPLE
SINE
+
= 1131727.43Hz
f
= 1250000Hz INTO A
1.5V TO 3.5V
,
,
SINEA
IN
IN
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
2048 SAMPLES
–
f
= 1199449Hz INTO A
1.5V TO 3.5V
SINEB
IMD = –84.1dB
2048 SAMPLES
3f
B
5TH
f
A
– 2f
B
0
0
0.55
1.11
0.55
1.11
0
0.59
FREQUENCY (MHz)
1.18
FREQUENCY (MHz)
FREQUENCY (MHz)
1402 G08
1402 G12
1402 G13
4VP-P Power Bandwidth and
100mVP-P Small-Signal
Bandwidth
PSRR vs Frequency
Load Regulation for VREF
5
0
4.100
4.090
4.080
4070
0
V
V
V
CC
SS
DD
–10
–20
–30
–40
–50
–60
–70
–80
100mV
P-P
DGND
–3
–5
4V
P-P
–10
–15
–20
–25
.4.060
4.050
4.040
0
0.4
0.8
1.2
1.6
2.0
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
1
10
FREQUENCY (MHz)
100
1000
LOAD CURRENT (mA)
1402 F07
1402 G18
1402 G20
6
LTC1402
U W
TYPICAL PERFOR A CE CHARACTERISTICS
(Bipolar Mode Plots Run with Dual ±5V Supplies.
Unipolar Mode Plots Run with a Single 5V Supply. VDD = 5V, VSS = –5V for Bipolar, VDD = 5V, VSS = 0V for Unipolar), TA = 25°C.
Differential Nonlinearity
vs Output Code (Bipolar)
Positive Power Supply Rejection
for VREF
Integral Nonlinearity
vs Output Code (Bipolar)
4.095
4.090
4.085
4.080
4.075
4.070
4.065
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
f
= 2.2MHz
SAMPLE
–0.25
–0.50
–0.75
–1.00
–0.25
–0.50
–0.75
–1.00
4.5
4.75
5.0
5.25
(V)
5.5
5.75
6.0
2048 2560
CODE
2048 2560
CODE
0
512 1024 1536
3072 3584 4096
0
512 1024 1536
3072 3584 4096
V
DD
1402 G21
1402 G15
1402 G14
Differential Nonlinearity
vs Output Code (Unipolar)
Integral Nonlinearity
vs Output Code (Unipolar)
Negative Power Supply Rejection
for VREF
4.095
4.090
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
4.085
4.080
–0.25
–0.50
–0.75
–1.00
–0.25
–0.50
–0.75
–1.00
4.075
4.070
4.065
–5
–4
–3
–2
(V)
–1
0
2048 2560
CODE
2048 2560
CODE
0
512 1024 1536
3072 3584 4096
0
512 1024 1536
3072 3584 4096
V
SS
1402 G19
1402 G17
1402 G16
U
U
U
PIN FUNCTIONS
AVDD (Pin 1): 5V Analog Power Supply. Bypass to AGND1 AIN– (Pin4):NegativeAnalogSignalInput.Canbegrounded
and solid analog ground plane with 10µF ceramic (or 10µF or driven differentially with AIN+. Identical to AIN+, except
tantalum in parallel with 0.1µF ceramic).
that it inverts the input signal. (Note 3)
AGND1(Pin2):AnalogGround. Tietosolidanalogground VREF (Pin 5): 4.096V Reference Voltage Output. Bypass to
plane. The analog ground plane should be solid and have AGND1 and solid analog ground plane with 10µF ceramic
no cuts near the LTC1402.
(or 10µF tantalum in parallel with 0.1µF ceramic).
AIN+ (Pin 3): Positive Analog Signal Input. 0V to 4.096V in AGND2 (Pin 6): Analog Ground Return for the Reference
unipolar mode and ±2.048V in bipolar mode when AIN– is and Internal CDAC. AGND2 could be overdriven externally
grounded. Both of these ranges operate fully differentially above ground. Tie to solid analog ground plane.
with respect to AIN–. (Note 3)
7
LTC1402
U
U
U
PIN FUNCTIONS
GAIN (Pin 7): Tie to AGND2 to set the reference voltage to
4.096VortietoVREF tosetthereferencevoltageto2.048V.
(Note 4)
DGND (Pin 13): Digital Ground for Internal Logic. Tie to
solid analog ground plane.
VSS (Pin 14): Negative Supply Voltage. Bypass to solid
analog ground plane with 10µF ceramic (or 10µF tantalum
in parallel with 0.1µF ceramic) or tie directly to the solid
analog ground plane for single supply use. Must be set
more negative than either AIN+ or AIN – . Set to 0V or –5V.
BIP/UNI (Pin 8): Tie to logic low to set the input range to
unipolar mode or tie to logic high to set the input range to
bipolar mode. (Note 4)
OGND (Pin 9): Output Ground for the Output Driver. This
pincanbetiedtothedigitalgroundofthesystem. Allother
ground pins should be tied to the analog ground plane.
SCK (Pin 15): External Clock. Advances the conversion
process and sequences the output data at DOUT on the
risingedge.Respondsto5Vor3VCMOSandtoTTLlevels.
(Note 4). One or more pulses wake from Nap or Sleep.
DOUT (Pin 10): Three-State Data Output. (Note 3) Each
output data word represents the analog input at the start
of the previous conversion.
CONV (Pin 16): Holds the input analog signal and starts
the conversion on the rising edge. Responds to 5V or 3V
CMOS and to TTL levels. (Note 4). Two pulses with SCK in
fixed high or fixed low state start Nap Mode. Four pulses
with SCK in fixed high or fixed low state start Sleep mode.
OVDD (Pin 11):Output Data Driver Power. Tie to VDD when
driving 5V logic. Tie to 3V when driving 3V logic.
DVDD (Pin 12): Digital Power for Internal Logic. Bypass to
DGNDwith10µFceramic(or10µFtantaluminparallelwith
0.1µF ceramic).
W
BLOCK DIAGRA
C
C
SAMPLE
SAMPLE
3
4
+
A
A
IN
IN
1
AV
DD
12
14
DV
DD
–
V
SS
ZEROING SWITCHES
2.048V REF
+
+
REF AMP
COMP
12-BIT CAPACITIVE DAC
–
–
64k
64k
7
5
GAIN
8
BIP/UNI
V
REF
10
SUCCESSIVE APPROXIMATION
REGISTER
OUTPUT
DRIVER
6
D
OUT
AGND2
AGND1
DGND
2
11
9
OV
DD
13
INTERNAL
CLOCK
CONTROL LOGIC
OGND
1402 BD
16
15
SCK
CONV
8
LTC1402
W U
W
TI I G DIAGRA S
t
2
t
7
t
3
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
1
2
14
SCK
t
t
t
5
4
CONV
t
6
0
INTERNAL
S/H STATUS
SAMPLE
HOLD
SAMPLE
HOLD
t
t
8
8a
D
REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION
OUT
Hi-Z
Hi-Z
D
OUT
REF D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
REF
REFRDY BIT + 12-BIT DATA WORD
t
CONV
t
1402 TD01
THROUGHPUT
Nap Mode and Sleep Mode Waveforms
SCK
t
1
t
1
CONV
NAP
SLEEP
t
12
V
REF
t
11
REFRDY
1402 TD02
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS. REFRDY APPEARS AS A BIT IN THE D
WORD.
OUT
SCK to DOUT Delay
SCK
SCK
V
V
IH
IH
t
10
8
t
t
9
V
V
90%
10%
OH
OL
D
D
OUT
OUT
1402 TD03
9
LTC1402
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APPLICATIONS INFORMATION
DRIVING THE ANALOG INPUT
second requirement is that the closed-loop bandwidth
must be greater than 40MHz to ensure adequate small-
signal settling for full throughput rate. If slower op amps
are used, more time for settling can be provided by
increasing the time between conversions. The best choice
for an op amp to drive the LTC1402 will depend on the
application. Generally, applications fall into two catego-
ries: AC applications where dynamic specifications are
most critical, and time domain applications where DC
accuracy and settling time are most critical. The following
list is a summary of the op amps that are suitable for
driving the LTC1402. More detailed information is avail-
able in the Linear Technology Databooks and on the
LinearViewTM CD-ROM.
LT®1206: 60MHz Current Feedback Amplifier with Shut-
down Pin (Amplifier Draws 200µA While in Shutdown).
±5V to ±15V supplies. Distortion is –80dB to 1MHz
(2VP-P into 30Ω). Good for AC applications. Dual avail-
able with shutdown as LT1207. Output swings to within
2VBE of the supply rails.
The differential analog inputs of the LTC1402 are easy to
drive.Theinputsmaybedrivendifferentiallyorasasingle-
ended input (i.e., the AIN– input is grounded). The AIN+ and
AIN– inputsaresampledatthesameinstant.Anyunwanted
signalthatiscommontobothinputswillbereducedbythe
common mode rejection of the sample-and-hold circuit.
The inputs draw only one small current spike while charg-
ing the sample-and-hold capacitors at the end of conver-
sion. During conversion, the analog inputs draw only a
small leakage current. If the source impedance of the
driving circuit is low, then the LTC1402 inputs can be
driven directly. As source impedance increases, so will
acquisition time (see Figure 1). For minimum acquisition
time with high source impedance, a buffer amplifier must
be used. The only requirement is that the amplifier driving
the analog input(s) must settle after the small current
spikebeforethenextconversionstarts(settlingtimemust
be 50ns for full throughput rate).
1500
1400
1300
LT1223: 100MHz Video Current Feedback Amplifier. 6mA
supply current. ±5V to ±15V supplies. Low distortion at
frequencies above 400kHz. Low noise. Good for AC appli-
cations.
±5V
1200
1100
1000
900
800
700
5V
LT1227:140MHzVideoCurrentFeedbackAmplifier.10mA
supply current; has shutdown pin (draws 120µA while in
shutdown). ±5V to ±15V supplies. Lowest distortion
(–92dB)atfrequenciesabove400kHz. Lownoise. Bestfor
AC applications.
600
500
400
300
200
100
0
10
100
1k
10k
100k
SOURCE RESISTANCE (Ω)
LT1229/LT1230: Dual and Quad 100MHz Current Feed-
back Amplifiers. ±2V to ±15V supplies. Low noise. Good
AC specifications, 6mA supply current each amplifier.
1402 F01
Figure 1. Acquisition Time vs Source Resistance
in Bipolar and Unipolar Modes
LT1360: 50MHz Voltage Feedback Amplifier. 3.8mA sup-
ply current. ±5V to ±15V supplies. Good AC and DC
specifications. 70ns settling to 0.5LSB.
CHOOSING AN INPUT AMPLIFIER
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (<100Ω) at the closed-loop bandwidth
frequency. For example, if an amplifier is used in a gain of
1 and has a unity-gain bandwidth of 50MHz, then the
output impedance at 50MHz must be less than 100Ω. The
LT1363: 70MHz, 1000V/µs Op Amps. 6.3mA supply cur-
rent. Good AC and DC specifications. 60ns settling to
0.5LSB.
LT1364/LT1365: Dual and Quad 70MHz, 1000V/µs Op
Amps. 6.3mA supply current per amplifier. 60ns settling
to 0.5LSB.
LinearView is a trademark of Linear Technology Corporation.
10
LTC1402
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APPLICATIONS INFORMATION
51Ω
LT1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier.
2.7V to ±15V supplies. Very high AVOL, 500µV offset and
520ns settling to 0.5LSB for a 4V swing. THD and noise
are –93dB to 40kHz and below 1LSB to 320kHz (AV = 1,
2VP-P into1kΩ,VS =5V),makingthepartexcellentforAC
applications (to 1/3 Nyquist) where rail-to-rail perfor-
mance is desired. Quad version is available as LT1631.
3
ANALOG
INPUT
+
–
A
A
IN
68pF
4
2
5
IN
AGND1
LTC1402
V
REF
10µF
6
7
AGND2
GAIN
LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier.
2.7V to ±15V supplies. Very high AVOL, 1.5mV offset and
400ns settling to 0.5LSB for a 4V swing. It is suitable for
applications with a single 5V supply. THD and noise are
–93dB to 40kHz and below 1LSB to 800kHz (AV = 1,
2VP-P into1kΩ,VS =5V),makingthepartexcellentforAC
applications where rail-to-rail performance is desired.
Quad version is available as LT1633.
1402 F02
Figure 2. RC Input Filter
less susceptible to both problems. When high amplitude
unwantedsignalsarecloseinfrequencytothedesiredsignal
frequency,amultiplepolefilterisrequired.Figure3shows
asimpleimplementationusinganLTC1560-1,afifth order
elliptic continuous-time 1MHz filter.
LT1813: Dual 100MHz 750V/µs 3mA Voltage Feedback
Amplifier. 5V to ±5V supplies. Distortion is –86dB to
100kHzand–77dBto1MHzwith±5Vsupplies(2VP-P into
500Ω). Excellent part for fast AC applications with
±5V supplies.
3
1
2
3
8
7
6
+
–
A
A
IN
4
2
5
V
IN
IN
LTC1560-1
INPUT FILTERING AND SOURCE IMPEDANCE
AGND1
LTC1402
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1402 noise and distortion. The small-signal band-
width of the sample-and-hold circuit is 80MHz. Any noise
ordistortionproductsthatarepresentattheanaloginputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For example, Figure 2 shows a 68pF
capacitor from AIN+ to ground and a 51Ω source resistor
to limit the input bandwidth to 47MHz. The 68pF capacitor
also acts as a charge reservoir for the input sample-and-
hold and isolates the ADC input from sampling glitch-
sensitive circuitry.
4
5
V
REF
–5V
5V
10µF
6
7
0.1µF
0.1µF
AGND2
GAIN
1402 F03
Figure 3. 1MHz Fifth Order Elliptic Lowpass Filter
BIPOLAR AND UNIPOLAR INPUT RANGES
The ±2V bipolar input range of the LTC1402 is optimized
for low noise and low distortion. Most op amps also
perform best over this same range, allowing direct cou-
pling to the analog inputs and eliminating the need for
special translation circuitry. The inputs of the LTC1402
may also be driven fully differential in bipolar mode with
a single supply. Each input should not swing more than
2VP-P individuallytogetthebestperformancefromsingle
supply amplifiers.
Highqualitycapacitorsandresistorsshouldbeusedsince
thesecomponentscanadddistortion.NPOandsilvermica
type dielectric capacitors have excellent linearity.
Carbon surface mount resistors can generate distortion
from self heating and from damage that may occur during
soldering. Metal film surface mount resistors are much
The 0V to 4V range is ideal for single ended input use with
single supply applications.
11
LTC1402
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APPLICATIONS INFORMATION
INTERNAL REFERENCE
ADC can then be adjusted to match the peak input signal,
maximizing the signal-to-noise ratio. The filtering of the
internal LTC1402 reference amplifier will limit the band-
width and settling time of this circuit. A settling time of
5ms should be allowed after a reference adjustment.
The LTC1402 has an on-chip, temperature compensated,
curvature corrected, bandgap reference that is factory
trimmedto2.048V.Itisconnectedinternallytoareference
amplifier, see Figure 4. The reference amplifier amplifies
the voltage at the VREF pin by 2 to create the required
internal reference voltage of 4.096V. This provides buffer-
ing for the high speed capacitive DAC. The reference
amplifier output VREF, (Pin 5) must be bypassed with a
capacitor to ground. The reference amplifier is stable with
capacitors of 1µF or greater. For the best noise perfor-
mance, a 10µF ceramic or a 10µF tantalum in parallel with
a 0.1µF ceramic is recommended.
DIFFERENTIAL INPUTS
The LTC1402 has a unique differential sample-and-hold
circuit that allows inputs from –2.5V to 5V. The ADC will
–
always convert the difference of AIN+ – AIN independent
of the common mode voltage. The common mode rejec-
tion holds up at extremely high frequencies, see Figure 7.
The only requirement is that both inputs not exceed
–2.5V or 5V. Integral nonlinearity errors (INL) and differ-
ential nonlinearity errors (DNL) are independent of the
common mode voltage. However, the bipolar zero error
(BZE) will vary. The change in BZE is typically less than
0.1% of the common mode voltage. Figure 5b shows the
use of bipolar mode with single 5V supply.
The VREF pin can be driven with an external reference as
shown in Figure 5a. The GAIN pin (Pin 7) is tied to the
positive supply to disable the internal reference buffer.
A DAC may also be used to drive VREF as shown in
Figure 6. This is useful in applications where the peak
input signal amplitude may vary. The input span of the
5V
3
4
5
6
7
V
IN
2.5V ±2.048V
+
–
LTC1402
A
A
V
IN
2.048V
BANGAP
+
REFERENCE
V
IN
5
V
REF
4.096V
2.5V
REFERENCE
IN
AMP
LT1019-2.5
–
10µF
LTC1402
8
5V
BIP
REF
10µF
64k
10µF
64k
14
GAIN
7
6
AGND2
GAIN
V
SS
AGND2
1402 F04
1402 F04a
Figure 4. LTC1402 Reference Circuit
Figure 5b. Bipolar Mode with Single Supply
5V
3
+
3
+
A
A
IN
IN
ANALOG INPUT
ANALOG INPUT
V
IN
4
–
4
–
A
A
IN
IN
LT1019-2.5
V
LTC1402
LTC1402
5
5
6
7
V
LTC1451
V
OUT
REF
REF
10µF
10µF
6
7
AGND2
GAIN
AGND2
GAIN
5V
5V
1402 F04a
1402 F06
Figure 6. Driving VREF with a 12 Bit, VOUT DAC
Figure 5a. Using the LT1019-2.5 as an External Reference
12
LTC1402
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APPLICATIONS INFORMATION
0
all the internal references. When AGND2 (Pin 6) is tied to
the external ground plane, it sources 2.7mA ±30% typi-
cally; approximately 2mA are sourced through an internal
equivalent 2k resistance tied to the VREF (Pin 5) at 4.096V
and the remaining 0.7mA supply the internal reference
ground. The VREF (Pin 5) equivalent input resistance is the
same 2k tied to AGND2 (Pin 6). When you bus a common
reference voltage to several LTC1402 ADCs, you need to
keep PC board track resistance low to avoid reference
voltage attenuation at each ADC. For example, 0.5Ω of
track resistance to Pins 5 or 6 causes 0.025% of reference
voltage and input range reduction. Figure 8 shows op-
tional buffer amplifiers at each ADC to eliminate resistive
voltagedropsfromthecommonexternalreferencetoeach
ADC. Figure 8 shows 10µF bypass capacitors tied to the
common analog ground plane, at VREF (Pin 5) and AGND2
(Pin 6), wired closely to each ADC to eliminate crosstalk of
internalADC glitchcurrentsfromoneADCtoanother. The
10µF bypass capacitors are recommended whether you
drive Pins 5 and 6 with amplifiers, or with copper traces
–10
–20
–30
–40
–50
–60
–70
0.1
1
10
100
1000
FREQUENCY (MHz)
1402 F07
Figure 7. CMRR vs Input Frequency
INPUT SPAN VERSUS REFERENCE VOLTAGE
The differential input range has a voltage span that equals
the difference between the voltage at the reference buffer
output VREF at Pin 5, and the voltage at the reference
ground AGND2 at Pin 6. The external reference voltage
may have any value between 2V and 5V. The internal ADC
is referenced to these two points. If you use an external
reference, tie the GAIN (Pin 7) to AVDD (Pin 1) to disable
the internal reference, and connect the external reference
between VREF (Pin 5) and AGND2 (Pin 6).
3
2
5
6
7
+
A
A
V
IN
ANALOG
INPUTS
1/2 LT1368CS8
5V
–
IN
6
8
If you cut the reference voltage in half by halving the gain
of the reference buffer with the GAIN (Pin 7) tied to VREF
(Pin 5), the input span also cuts in half. In bipolar mode,
the differential input range changes from ±2.048V to
±1.024V, when the reference is cut in half. In unipolar
mode, the differential input range changes from 0V-
4.096V to 0V-2.048V, for the same reference cut in half.
Note that in both unipolar and bipolar modes, the input
range pivots around 0V with changing reference voltage.
AGND2 (Pin 6) has no direct effect on the ADC offset
voltage, it only affects input voltage span. Any external
offsetting voltages must be applied through the AIN+ and
AIN– inputs, as shown in Figure 10b.
–
+
7
LTC1402
5
REF
10µF
1/2 LT1368CS8
2
AGND2
GAIN
–
+
1
3
4
10µF
–5V
5V
•
•
•
4.096V
3
2
5
6
7
+
A
A
V
IN
5V
ANALOG
INPUTS
1/2 LT1368CS8
5V
–
10k
1k
IN
6
8
–
+
7
LTC1402
5
0.1µF
10µF
REF
1/2 LT1368CS8
SEVERAL LTC1402 ADCs MAY SHARE ONE
EXTERNAL REFERENCE
2
AGND2
GAIN
–
+
1
3
LT1634AI-4.096
10µF
4
Figure 8 shows how several ADCs can share a single
common external reference. The VREF (Pin 5) and AGND2
(Pin 6) of several LTC1402 ADCs can be tied together to
share the same external reference in a data acquisition
system. Tie GAIN (Pin 7) to AVDD at each ADC to disable
–5V
1402 F08
5V
Figure 8. Several LTC1402 ADCs Can Share a Single
External Reference
13
LTC1402
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APPLICATIONS INFORMATION
more than 0.25 inch long to the common reference. You
may also choose to tie AGND2 (Pin 6) directly to a solid
analog ground plane and eliminate all the 10µF capacitors
at this pin. The external reference source needs to have
enough output drive current for the 2kΩ load at each ADC.
Adjustment in Unipolar Mode with Pin 8 Held Low
The code transitions occur midway between successive
integer LSB values (i.e., –FS + 0.5LSB, –FS + 1.5LSB,
–FS + 2.5LSB,...FS – 2.5LSB, FS – 1.5LSB). The output at
DOUT is binary with 1LSB = FS/4096 = 4.096V/4096 =
1.0mV. In applications where absolute accuracy is impor-
tant, offset and full-scale errors can be adjusted to zero.
Offset error must be adjusted before full-scale error. In
Figure 10b, zero offset is achieved by adjusting the offset
FULL-SCALE AND OFFSET ADJUSTMENT
Figure 9 shows the ideal input/output characteristics for
the LTC1402 in bipolar mode and unipolar mode. Figure
10a shows the components required for full-scale error
adjustment. Figure 10b includes the components for off-
set and full-scale adjustment.
–
applied to the AIN input. For zero offset error apply
–0.5mV (i.e., –0.5LSB) to AIN+ and adjust the offset at the
AIN– input using R8 until the output code flickers between
R1
LTC1402
+
51Ω
3
4
A
A
011...111
011...110
011...101
111...111
111...110
111...101
IN
IN
ANALOG INPUT
0V TO 4.096V
OR ±2.048V
R2
39k
R3
51Ω
S/H
–
2.048V
BANGAP
REFERENCE
5
V
REF
REFERENCE
AMP
R4
470k
10µF
64k
64k
100...010
100...001
100...000
000...010
000...001
000...000
7
6
GAIN
R5
500Ω
AGND2
–(FS – 1LSB)
FS – 1LSB
INPUT VOLTAGE (V)
1402 F010a
1402 F09
Figure 9. LTC1402 Transfer Characteristic
Figure 10a. Full-Scale Adjustment Circuit with
±10LSB Range
Adjustment in Bipolar Mode with Pin 8 Held High
5V
The code transitions occur midway between successive
integerLSBvalues(i.e., –FS+0.5LSB, –FS+1.5LSB, –FS
+2.5LSB,...FS–2.5LSB, FS–1.5LSB). TheoutputatDOUT
is two’s complement binary with 1LSB = FS – (–FS)/4096
= 4.096V/4096 = 1.0mV. In applications where absolute
accuracy is important, offset and full-scale errors can be
adjusted to zero. Offset error must be adjusted before full-
scale error. In Figure 10b, zero offset is achieved by
R6
R1
LTC1402
+
–
24k
51Ω
3
4
A
A
IN
IN
ANALOG INPUT
0V TO 4.096V
OR ±2.048V
R2
24k
R3
51Ω
S/H
5V
R7
7.5k
2.048V
BANGAP
REFERENCE
OFFSET
ADJ
R8
10k
5
V
REF
REFERENCE
AMP
R4
470k
–
adjusting the offset applied to the AIN input. For zero
10µF
64k
64k
+
offset error, apply –0.5mV (i.e., –0.5LSB) to AIN and
adjust the offset at the AIN– input using R8 until the output
code flickers between 0000 0000 0000 and 1111 1111
1111. For full-scale adjustment in Figures 10a and 10b,
7
6
GAIN
FULL-SCALE
R5
ADJ 500Ω
AGND2
1402 F010b
+
apply an input voltage of 2.0465V (FS – 1.5LSB) to AIN
Figure 10b. Offset and Full-Scale Adjustment
Circuits with ±10LSB Range
and adjust R5 until the output code flickers between 0111
1111 1110 and 0111 1111 1111.
14
LTC1402
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APPLICATIONS INFORMATION
0000 0000 0000 and 0000 0000 0001. For full-scale ad-
justment in Figures 10a and 10b, apply an input voltage of
The LTC1402 has differential inputs to minimize noise
coupling. Common mode noise on the AIN+ and AIN– leads
will be rejected by the input CMRR. The AIN– input can be
usedasagroundsensefortheAIN+ input;theLTC1402will
hold and convert the difference voltage between AIN+ and
AIN– . The leads to AIN+ (Pin 3) and AIN– (Pin 4) should be
kept as short as possible. In applications where this is not
possible, the AIN+ and AIN– traces should be run side-by-
side to cancel noise coupling.
+
2.0465V (FS – 1.5LSBs) to AIN and adjust R5 until the
output code flickers between 1111 1111 1110 and 1111
1111 1111.
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC1402, a printed circuit board
with ground plane is required. Layout for the printed
circuit board should ensure that digital and analog signal
linesareseparatedasmuchaspossible. Inparticular, care
should be taken not to run any digital track alongside an
analog signal track.
SUPPLY BYPASSING
High quality, low series resistance 10µF ceramic bypass
capacitors should be used at the VDD and VREF pins.
Surface mount ceramic capacitors such as Murata
GRM235Y5V106Z016 provide excellent bypassing in a
small board space. Alternatively, 10µF tantalum capaci-
tors in parallel with 0.1µF ceramic capacitors can be used.
Bypass capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypass
capacitorsmustbekeptshortandshouldbemadeaswide
as possible.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 2 (AGND1), Pin 6 (AGND2), Pin 13 (DGND) and all
other analog grounds should be connected directly to an
analog ground plane. Pin 9 (OGND) should be connected
near Pin13 (DGND), where the analog ground plane ties to
the logic system ground. The VREF bypass capacitor and
the DVDD bypass capacitor should also be connected to
this analog ground plane, see Figure 11. No other digital
groundsshouldbeconnectedtothisanaloggroundplane.
Low impedance analog and digital power supply common
returnsareessentialtolownoiseoperationoftheADCand
the foil width for these tracks should be as wide as
possible. The traces connecting the pins and bypass
capacitorsmustbekeptshortandshouldbemadeaswide
as possible.
POWER-DOWN MODES
Upon power-up, the LTC1402 is initialized to the active
stateandisreadyforconversion. TheNapandSleepMode
waveforms showthepower-downmodesfortheLTC1402.
TheSCKandCONVinputscontrolthepower-downmodes
(see Timing Diagrams). Two rising edges at CONV, with-
out any intervening rising edges at SCK, put the LTC1402
in Nap mode and the power drain drops from 90mW to
12
3V TO 5V
OV
D
DD
10
3
+
DIGITAL
SYSTEM
LTC1402
AGND1
A
OUT
OGND
9
IN
–
A
V
AGND2
6
V
AV
DV DGND
DD
IN
REF
DD
1
SS
SYSTEM
GROUND
ANALOG
INPUT
CIRCUITRY
4
+
5
14
10µF
2
12
10µF
13
–
1402 F11
10µF
ANALOG GROUND PLANE
Figure 11. Power Supply Grounding Practice
15
LTC1402
U
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APPLICATIONS INFORMATION
15mW. The internal reference remains powered in Nap
mode. One or more rising edges at SCK wake up the
LTC1402 for service very quickly, and CONV can start an
accurateconversionwithinaclockcycle.Fourrisingedges
at CONV, without any intervening rising edges at SCK, put
the LTC1402 in Sleep mode and the power drain drops
from 90mW to 10µW. One or more rising edges at SCK
wake up theLTC1402foroperation. The internalreference
(VREF) takes 2ms to slew and settle with a 10µF load, and
the REFREADY bit in the DOUT stream takes an additional
10mstogohighafterthereferenceoutputPin5(VREF)has
finished slewing. Note that, using sleep mode more fre-
quently than every 2ms, compromises the settled accu-
racy of the internal reference. Figure 12 shows the power
consumption versus the conversion rate. Note that, for
slower conversion rates, the Nap and Sleep modes can be
used for substantial reductions in power consumption.
CONV at Pin 16
The rising edge of CONV starts a conversion but subse-
quent rising edges at CONV, during the following 14 SCK
cycles of conversion, are ignored by the LTC1402. The
duty cycle of CONV can be arbitrarily chosen to be used as
a frame sync signal for the processor serial port. A simple
approach to generate CONV is to create a pulse that is one
SCK wide to drive the LTC1402 and then buffer this signal
withtheappropriatenumberofinverterstodrivetheframe
sync input of the processor serial port. It is good practice
todrivetheLTC1402CONVinputfirsttoavoiddigitalnoise
interferenceduringthesample-to-holdtransitiontriggered
by CONV at the start of conversion. Another point to con-
sider is the level of jitter in the CONV signal if the input
signals have fast transients or sinewaves. Some proces-
sors can be programmed to generate a convenient frame
sync pulse at their serial port, but often this signal is de-
rived from a jittery processor phase locked loop clock
multiplier. Thisistrueevenifalowjittercrystalclockisthe
reference for the processor clock multiplier.
100
V
CURRENT
DD
DUAL ±5V
V
CURRENT
DD
SINGLE 5V
10
1
SCK at Pin 15
V
CURRENT
DD
The rising edge of SCK advances the conversion process
and also udpates each bit in the DOUT data stream. After
CONV rises, the second rising edge of SCK sends out the
REFREADY bit. Subsequent edges send out the 12 data
bits, with the MSB sent first. A simple approach is to
generate SCK to drive the LTC1402 and then buffer this
signalwiththeappropriatenumberofinverterstodrivethe
serial clock input of the processor serial port. The rising
edge of SCK is guaranteed to coincide with stable data at
DOUT. It is good practice to drive the LTC1402 SCK input
first to avoid digital noise interference during the internal
bit comparison decision by the internal high speed com-
parator. Unlike the CONV input, the SCK input is not
sensitive to jitter because the input signal is already
sampled and held constant.
NAP MODE
V
CURRENT
DD
SLEEP MODE
0.1
V
CURRENT
SINGLE 5V
SS
V
CURRENT
0.01
SS
DUAL ±5V
0.001
0.01
0.1
1
10
SAMPLE RATE (MHz)
1402 F12
Figure 12. Power Consumption vs Sample Rate
in Normal Mode, Nap Mode and Sleep Mode
DIGITAL INTERFACE
The LTC1402 has a 3-wire SPI (Serial Protocol Interface)
interface. The SCK and CONV inputs and DOUT output
implementthisinterface.TheSCKandCONVinputsareTTL
compatibleandalsoacceptswingsfrom3Vor5Vlogic.The
amplitude of DOUT can easily produce 5V logic or 3V logic
swings by tying the independent output supply OVDD
(Pin11) tothesamesupplyassystemlogic. Adetailedde-
scription of the three serial port signals follows.
DOUT at Pin 10
Upon power-up, the DOUT output is automatically reset to
thehighimpedancestate.TheDOUT outputremainsinhigh
impedance until a new conversion is started. DOUT sends
out13bitsintheoutputdatastreamafterthesecondrising
edge of SCK after the start of conversion with the rising
16
LTC1402
U
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APPLICATIONS INFORMATION
edge of CONV. Please note the delay specification from speed crystal (i.e., 10MHz) to generated a fast, but jittery,
SCK to a valid DOUT. DOUT is always guaranteed to be valid phaselockedloopsystemclock(i.e., 40MHz). Thejitter, in
by the next rising edge of SCK.
these PLL-generated high speed clocks, can be several
nanoseconds. Note that if you choose to use the frame
syncsignalgeneratedbytheDSPport,thissignalwillhave
the same jitter of the DSP’s master clock.
DIGITAL JITTER AT CONV (PIN 16)
Inhighspeedapplications,wherehighamplitudesinewaves
above 100kHz are sampled, the CONV signal must have as
little jitter as possible (10ps or less). The square wave
SERIAL TO PARALLEL CONVERSION
output of a common crystal clock module usually meets YoucantakeadvantageoftheserialinterfaceoftheLTC1402
thisrequirementeasily.ThechallengeistogenerateaCONV in a parallel data system to minimize bus wiring conges-
signalfromthiscrystalclockwithoutjittercorruptionfrom tion in the PC board layout. Figure 13 shows an example
other digital circuits in the system. A clock divider and any of this interface. It is best to send the SCK and CONV
gates in the signal path from the crystal clock to the CONV signalstotheLTC1402,andthenbusthemtogetheracross
input should not share the same integrated circuit with the board to avoid excessive time skew among the three
other parts of the system. As shown in the interface circuit signals. It is usually not necessary to buffer DOUT, if the PC
examples, theLTC1402’sSCKandCONVinputsshouldbe track is not too long. Buffering SCK and CONV prevents
driven first with digital buffers used to drive the serial port jitter from corrupting these signals. The relative phase
interface. Also note that the master clock in the DSP may between SCK and CONV affects the position of the parallel
already be corrupted with jitter, even if it comes directly word at the output of the 74HC595. The position of the
from the DSP crystal. Another problem with high speed outputwordinFigure13assumes16clocksbetweeneach
processor clocks is that they often use a low cost, low CONV rising edge, and the CONV pulse is one clock wide.
5V
11
OV
DD
10
74ACT04
SRCLR
16
15
12
11
14
13
15
1
CONV
LTC1402
SCK
RCK
QA
QB
QC
QD
QE
D0
D1
D2
D3
D4
D5
D6
2
SRCK
3
74HC595
SER
10
9
4
D
OUT
5
QF
OGND
6
G
QG
QH
QH′
7
9
CONV
CLK
10
SRCLR
RCK
12
11
14
13
15
1
QA
QB
QC
QD
QE
D7
D8
2
SRCK
D9
3
74HC595
SER
D10
D11
REFRDY
3-WIRE SERIAL
INTERFACE LINK
4
5
QF
6
G
QG
QH
QH′
7
9
1402 F13
Figure 13. Serial to Parallel Interface
17
LTC1402
U
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APPLICATIONS INFORMATION
HARDWARE INTERFACE TO TMS320C54x
edge clock. Buffers near the LTC1402 may be added to
drive long tracks to the DSP to prevent corruption of the
signal to LTC1402. This configuration is adequate to
traverseatypicalsystemboard,but sourceresistorsatthe
buffer outputs, and termination resistors at the DSP may
be needed to match the characteristic impedance of very
long transmission lines. If you need to terminate the DOUT
transmission line, buffer it first with one or two 74ACxx
gates. The TTL threshold inputs of the DSP port respond
properly to the 2.5V swing of the terminated transmission
lines.TheOVDD supplyoutputdriversupplyvoltagecanbe
driven directly from the DSP.
The LTC1402 is a serial output ADC whose interface has
been designed for high speed buffered serial ports in fast
digital signal processors (DSPs). Figure 14 shows an
example of this interface using a TMS320C54X.
The buffered serial port in the TMS320C54x has direct
accesstoa2kBsegmentofmemory. TheADC’sserialdata
can be collected in two alternating 1kB segments, in real
time, at the full 2.2Msps conversion rate of the LTC1402.
TheDSPassemblycodesetsframesyncmodeattheBFSR
pin to accept an external positive going pulse, and the
serial clock at the BCLKR pin to accept an external positive
5V
11
OV
DD
V
CC
16
15
CONV
LTC1402
SCK
BFSR
TMS320C54x
BCLKR
REF
B11 B10
10
9
D
BDR
OUT
OGND
CONV
CLK
3-WIRE SERIAL
INTERFACELINK
1402 F14
Figure 14. DSP Serial Interface to TMS320C54x
18
LTC1402
U
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APPLICATIONS INFORMATION
; ***************************************************************************
; Files: BSP2KB.ASM ->
; 2kbyte collection into DSKPlus TMS320C542 with Serial Port interface to LTC1402
; first element at 1024, last element at 1023, two middle elements at 2047 and 0000
; bipolar mode
; ***************************************************************************
.width 160
.length 110
.title “sineb0 BSP in auto buffer mode”
.mmregs
.setsect “.text”, 0x500,0
.setsect “vectors”, 0x180,0
.setsect “buffer”, 0x800,0
;Set address of executable
;Set address of incoming 1402 data
;Set address of BSP buffer for clearing
.setsect “result”, 0x1800,0 ;Set address of result for clearing
.text
;.text marks start of code
start:
;Make sure /PWRDWN is low at J1-9 to turn off AC01 adc
tim=#0fh
prd=#0fh
tcr = #10h
tspc = #0h
; stop timer
; stop TDM serial port to AC01
pmst = #01a0h ; set up iptr. Processor Mode STatus register
sp = #0700h
dp = #0
; init stack pointer.
; data page
ar2 = #1800h ; pointer to computed receive buffer.
ar3 = #0800h ; pointer to Buffered Serial Port receive buffer
ar4 = #0h
; reset record counter
call sineinit
sinepeek:
call sineinit
; Double clutch the initialization to insure a proper
; insert debugger break here to view results
; reset. The external frame sync must occur 2.5 clocks
; or more after the port comes out of reset.
wait goto wait
————————Buffered Receive Interrupt Routine —————————
breceive:
ifr = #10h
;
; clear interrupt flags
TC = bitf(@BSPCE,#4000h)
if (NTC) goto bufull
bspce = #(2023h + 08000h)
return_enable
; check which half (bspce(bit14)) of buffer
; if this still the first half get next half
; turn on halt for second half (bspce(bit15))
;
———————mask and shift input data after 2k buffer is full——-
bufull:
b = *ar3+ << -2
; load acc b with BSP buffer and shift right 2
b = #00FFFh & b
b = #00800h ^ b
*ar2+ = data(#0bh)
; mask out the REF bit and the 3 other tristate bits
; invert BIPOLAR MSB. Comment this line in UNIPOLAR mode
; store B to out buffer and advance AR2 pointer
TC = (@ar2 == #02000h) ; output buffer is 2k starting at 1800h
if (TC) goto start
goto bufull
; restart if out buffer is at 1fffh
;
—————————dummy bsend return————————————
bsend return_enable
;this is a dummy return to define bsend
;in vector table below
;
——————————— end ISR ——————————————
;initialize buffered serial port
**********************************************************************
*
*
*
BSP initialization code for the ‘C54x DSKplus
for use with 1402 in standard mode
BSPC and SPC are the same in the ‘C542
*
*
*
**********************************************************************
ON
.set 1
OFF
YES
NO
.set !ON
.set 1
.set !YES
.set 2
BIT_8
BIT_10 .set 1
BIT_12 .set 3
BIT_16 .set 0
GO
.set 0x80
**********************************************************************
19
LTC1402
U
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APPLICATIONS INFORMATION
* This is an example of how to initialize the Buffered Serial Port (BSP).
* The BSP is initialized to require an external CLK and FSX for
* operation. The data format is 16-bits, burst mode, with autobuffering
* enabled.
*
*
*****************************************************************************************************
*Timing at BSP pins in DSKPLUS TMS320c542 board with inverters at BCLKR and BFSR.
*
*BFSR Pin JP1-20 ~\___/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\___/~~~~~~~~~~*
*BCLKR Pin JP1-14 _/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/
*BDR Pin JP1-26 -_—_—<REF-B11-B10-B09-B08-B07-B06-B05-B04-B03-B02-B01-B00>—_—_—<REF-B11-
*CLKIN Pin JP5-09 ~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~
*
*A 2 place right shift is needed to right justify the input data.
*The REF bit is also be masked in this example
*
*
*
*
*
*
*****************************************************************************************************
*
Loopback
Format
IntSync
.set NO
.set BIT_16
.set NO
;(digital looback mode?)
DLB bit
FO bit
TXM bit
MCM bit
;(Data format? 16,12,10,8)
;(internal Frame syncs generated?)
;(internal clks generated?)
IntCLK
.set NO
BurstMode
CLKDIV
PCM_Mode
FS_polarity
CLK_polarity .set YES
Frame_ignore .set !YES
XMTautobuf .set NO
.set YES
;(if BurstMode=NO, then Continuous) FSM bit
;(3=default value, 1/4 CLOCKOUT)
;(Turn on PCM mode?)
;(change polarity)YES=^^^\_/^^^, NO=___/^\___
;(change polarity)for BCLKR YES=_/^, NO=~\_
;(inverted !YES -ignores frame)
;(transmit autobuffering)
.set
3
.set NO
.set NO
RCVautobuf
XMThalt
RCVhalt
XMTbufAddr .set 0x800
XMTbufSize .set 0x000
RCVbufAddr .set 0x800
.set YES
.set NO
.set NO
;(receive autobuffering)
;(transmit buff halt if XMT buff is full)
;(receive buff halt if RCV buff is full)
;(address of transmit buffer)
;(length of transmit buffer)
;(address of receive buffer)
RCVbufSize
.set 0x800
;(length of receive buffer)works up to 800
*
*
*
**********************************************************************
.eval ((Loopback >> 1)|((Format & 2)<<1)|(BurstMode <<3)|(IntCLK <<4)|(IntSync <<5)) ,SPCval
.eval ((CLKDIV)|(FS_polarity <<5)|(CLK_polarity<<6)|((Format & 1)<<7)|(Frame_ignore<<8)|(PCM_Mode<<9)), SPCEval
.eval (SPCEval|(XMTautobuf<<10)|(XMThalt<<12)|(RCVautobuf<<13)|(RCVhalt<<15)), SPCEval
sineinit:
bspc = #SPCval
ifr = #10h
; places buffered serial port in reset
; clear interrupt flags
imr = #210h
intm = 0
; Enable HPINT,enable BRINT0
; all unmasked interrupts are enabled.
; programs BSPCE and ABU
; initializes transmit buffer start address
; initializes transmit buffer size
; initializes receive buffer start address
; initializes receive buffer size
; bring buffered serial port out of reset
;for transmit and receive because GO=0xC0
;clear a chunk at the end to mark the end
bspce = #SPCEval
axr = #XMTbufAddr
bkx = #XMTbufSize
arr = #RCVbufAddr
bkr = #RCVbufSize
bspc = #(SPCval | GO)
return
.space 16*32
;======================================================================
;
; VECTORS
;
;======================================================================
.sect “vectors”
;The vectors start here
;get BSP vectors
; ***************************************************************************
;
;
;
Vector Table for the ‘C54x DSKplus
BSP vectors and Debugger vectors
TDM vectors just return
; ***************************************************************************
20
LTC1402
U
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APPLICATIONS INFORMATION
; The vectors in this table can be configured for processing external and
; internal software interrupts. The DSKplus debugger uses four interrupt
; vectors. These are RESET, TRAP2, INT2, and HPIINT.
;
;
* DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER *
; All other vector locations are free to use. When programming always be sure
; the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and
; host PC interact. INT2 should normally be masked (IMR(bit 2) = 0) so that the
; DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally.
;
;
;
.mmregs
reset goto #80h
;00; RESET * DO NOT MODIFY IF USING DEBUGGER *
;04; non-maskable external interrupt
nop
nop
nmi return_enable
nop
nop
nop
trap2 goto #88h
;08; trap2 * DO NOT MODIFY IF USING DEBUGGER *
nop
nop
.space 52*16
int0 return_enable
;0C-3F: vectors for software interrupts 18-30
;40; external interrupt int0
nop
nop
nop
int1 return_enable
;44; external interrupt int1
;48; external interrupt int2
;4C; internal timer interrupt
;50; BSP receive interrupt
;54; BSP transmit interrupt
;58; TDM receive interrupt
nop
nop
nop
int2 return_enable
nop
nop
nop
tint
return_enable
nop
nop
nop
brint goto breceive
nop
nop
nop
bxint goto bsend
nop
nop
nop
trint return_enable
nop
nop
nop
txint return_enable
nop
;5C; TDM transmit interrupt
;60; external interrupt int3
nop
int3 return_enable
nop
nop
nop
hpiint dgoto #0e4h
nop
;64; HPIint * DO NOT MODIFY IF USING DEBUGGER *
nop
.space 24*16
.sect “buffer”
.space 16*0x800
.sect “result”
.space 16*0x800
.end
;68-7F; reserved area
;Set address of BSP buffer for clearing
;Set address of result for clearing
21
LTC1402
U
TYPICAL APPLICATION
Using Quad Cable Drivers/Receivers in Remote
unshielded cable. Using these devices, the LTC1402’s
serial data can be transmitted up to 100 feet without data
corruption. Because the SCK, CONV and DOUT signals
originate at the LTC1402, they arrive at the serial port with
similar delays and remain synchronized. When the data is
received at the serial port of the DSP or other controller,
the port must be programmed to respond to the appropri-
ate SCK and CONV edges. It is also necessary to check
where the 12-bit output DATA resides in the 16-bit data
frame. The TMS320C54x serial port READ instructions
canshiftthe12-bitdatatothepreferredpositionwithinthe
16-bit data frame.
LTC1402 Applications
In some applications, the host controller or main proces-
sor may be located some distance from the sensor, the
signal conditioning circuitry, and the ADC. In these appli-
cations, maintaining serial data integrity over long cable
distances can be a challenge. The circuit in Figure 15
showsonewaytoconveytheLTC1402’shigh-speedserial
data over a long distance. The circuit uses the LTC1688
quad cable driver and an LTC1520 quad cable receiver to
transmit/receive the LTC1402’s high-speed 35.2Mbps
serial data to the DSPs serial port over category-5
5V
5V
DV
DD
10µF
11
16
15
10
9
16
0V
DD
16
2
1
2
V
DD
3
4
1
3
5
+
–
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
BFSR
A
CONV
SCK
IN
3
TMS320C54x
BCLKR
SIGNAL
6
6
7
9
A
D
OUT
IN
7
5
OGND
LTC1402
10
10
11
BDR
GND
9
8
4
11
8
CATEGORY-5
UNSHIELDED CABLE
UP TO 100 FEET
REMEE PART NO.
5A244UTPM30BU
CONV
2.2Msps
4
15
12
14
14
15
13
CLK
13
35.2MHz
PIN 4 = ENA
PIN12 = ENB
LTC1688
QUAD DRIVER
LTC1520
QUAD RECEIVER
Figure 15. The LTC1402 3-Wire Serial Port Sends Data Over 100 Feet of Category-5
Twisted Pair with the LTC1688/LTC1520 Quad Driver/Receiver Pairs
22
LTC1402
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
0.009
(0.229)
REF
16 15 14 13 12 11 10 9
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
2
3
4
5
6
7
8
0.015 ± 0.004
(0.38 ± 0.10)
× 45°
0.053 – 0.068
(1.351 – 1.727)
0.004 – 0.0098
(0.102 – 0.249)
0.007 – 0.0098
(0.178 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.0250
(0.635)
BSC
0.008 – 0.012
(0.203 – 0.305)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 1098
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC1402
RELATED PARTS
PART NUMBER
RESOLUTION
SPEED
COMMENTS
16-Bit
LTC1604
LTC1605
LTC1606
LTC1608
14-Bit
16
16
16
16
333ksps
100ksps
250ksps
500ksps
±2.5V Input Range, ±5V Supply
±10V Input Range, Single 5V Supply
±10V Input Range, Pin-Compatible with LTC1605
±2.5V Input Range, Pin-Compatible with LTC1604
LTC1414
LTC1419
LTC1416
LTC1418
12-Bit
14
14
14
14
2.2Msps
800ksps
400ksps
200ksps
175mW, 80dB SINAD and 95dB SFDR
150mW, 81.5dB SINAD and 95dB SFDR
75mW, Low Power with Excellent AC Specs
15mW, Single 5V, Serial/Parallel I/O
LTC1412
LTC1410
LTC1415
LTC1409
LTC1404
LTC1400
PART NUMBER
References
LT1019-2.5
LT1460-2.5
LT1461-2.5
DACs
12
3Msps
1.25Msps
1.25Msps
800ksps
600ksps
400ksps
150mW, 72dB SINAD and 82dB SFDR
150mW, 71.5dB SINAD and 84dB THD
55mW, Single 5V Supply
12
12
12
80mW, 71.5dB SINAD and 84dB THD
High Speed Serial I/O in SO-8 Package
High Speed Serial I/O in SO-8 Package
COMMENTS
12
12
DESCRIPTION
Precision Band Gap Voltage Reference
Micropower Series Voltage Reference
Precision Voltage Reference
3ppm/°C Drift, 0.5% Max Initial Accuracy
0.075% Initial Accuracy, 10ppm/°C Max Drift
3ppm/°C Drift, 0.05% Max Initial Accuracy
LTC1451
LTC1452
LTC1456
12-Bit V
12-Bit V
12-Bit V
DAC
SO-8 Package, 12-Bit Monotonic Overtemperature
SO-8 Package, 2.7V to 5.5V Operation
OUT
OUT
OUT
Multiplying DAC
DAC
0.5LSB DNL, SO-8 Package, Internal Reference
1402f LT/TP 0800 4K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
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LINEAR TECHNOLOGY CORPORATION 1999
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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