1408-12_技术文档

LTC1408-12

6 Channel, 12-Bit, 600ksps

Simultaneous Sampling ADC

U

with Shutdown

FEATURES

DESCRIPTIO

The LTC^®1408-12 is a 12-bit, 600ksps ADC with six

simultaneously sampled differential inputs. The device

draws only 5mA from a single 3V supply, and comes in a

tiny 32 pin (5mm× 5mm) QFN package. A SLEEP shut-

down feature further reduces power consumption to

6µW. The combination of low power and tiny package

makes the LTC1408-12 suitable for portable applications.

■

600ksps ADC with 6 Simultaneously Sampled

Differential Inputs

■

100ksps Throughput per Channel

■

72dB SINAD

■

Low Power Dissipation: 15mW

■

3V Single Supply Operation

■

2.5V Internal Bandgap Reference, Can be Overdriven

with External Reference

3-Wire SPI-Compatible Serial Interface

The LTC1408-12 contains six separate differential inputs

that are sampled simultaneously on the rising edge of the

CONV signal. These six sampled inputs are then

converted at a rate of 100ksps per channel.

■

0V to 2.5V Unipolar, or ±1.25V Bipolar Differential

Input Range

■

SLEEP (6µW) Shutdown Mode

The 83dB common mode rejection allows users to

eliminate ground loops and common mode noise by

measuring signals differentially from the source.

■

NAP (3.3mW) Shutdown Mode

■

Internal Conversion Triggered by CONV

■

83dB Common Mode Rejection

■

Tiny 32-Pin (5mm × 5mm) QFN Package

The device converts 0V to 2.5V unipolar inputs differen-

tially, or ±1.25V bipolar inputs also differentially,

depending on the state of the BIP pin. Any analog input

may swing rail-to-rail as long as the differential input

range is maintained.

U

APPLICATIO S

■

Multiphase Power Measurement

■

Multiphase Motor Control

The conversion sequence can be abbreviated to convert

fewer than six channels, depending on the logic state of

the SEL2, SEL1 and SEL0 inputs.

Data Acquisition Systems

Uninterruptable Power Supplies

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Protected by U.S. Patents including 6084440, 6522187.

The serial interface sends out the six conversion results in

96 clocks for compatibility with standard serial interfaces.

W

BLOCK DIAGRA

–

+

–

+

–

+

–

+

–

+

–

+

10µF

3V

25

CH5

CH4

CH3

CH2

CH1

CH0

V

CC

V

DD

21

20 19 18

17 16 15

14 12 11

13

10

9

8

7

6

5

4

24

12-BIT LATCH 0

12-BIT LATCH 1

12-BIT LATCH 2

12-BIT LATCH 3

12-BIT LATCH 4

12-BIT LATCH 5

OV

3V

DD

–

3

1

2

–

THREE-

STATE

SERIAL

OUTPUT

PORT

S AND H

600ksps

12-BIT ADC

SD0

0.1µF

OGND

MUX

TIMING

LOGIC

CONV

30

32

31

2.5V

REFERENCE

SCK

DGND

V

GND

22

REF

23

33

29

26

27

28

10µF

235114 TA01

BIP

SEL2 SEL1 SEL0

140812f

1

LTC1408-12

W U

W W W

U

/O

PACKAGE RDER I FOR ATIO

ABSOLUTE AXI U RATI GS

(Notes 1, 2)

TOP VIEW

ORDER PART

NUMBER

Supply Voltage (V_DD, V_CC, OV_DD) .............................. 4V

Analog and V_REFInput Voltages

(Note 3) ................................... – 0.3V to (V_DD+ 0.3V)

Digital Input Voltages .................. – 0.3V to (V_DD+ 0.3V)

Digital Output Voltage.................. – 0.3V to (V_DD+ 0.3V)

Power Dissipation.............................................. 100mW

Operation Temperature Range

LTC1408C-12 .......................................... 0°C to 70°C

LTC1408I-12 ...................................... –40°C to 85°C

Storage Temperature Range ................. –65°C to 125°C

32 31 30 29 28 27 26 25

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

SDO

V

CC

LTC1408CUH-12

LTC1408IUH-12

OGND

REF

OV

GND

DD

+

CH0

CH5–

CH5+

GND

33

–

GND

+

CH1

CH4–

CH4+

–

CH1

QFN PART MARKING

1408-12

9

10 11 12 13 14 15 16

QFN PACKAGE

32-PIN (5mm × 5mm) PLASTIC QFN

T_JMAX= 125°C, θ_JA= 34°C/ W

EXPOSED PIN IS GND (PAD 33)

MUST BE SOLDERED TO PCB

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

U

CO VERTER CHARACTERISTICS

The

●

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. With internal reference, V = V = 3V.

A

DD

CC

PARAMETER

CONDITIONS

MIN

12

TYP

MAX

UNITS

Bits

LSB

mV

Resolution (No Missing Codes)

Integral Linearity Error

Offset Error

●

(Note 5)

(Note 4)

●

–1

± 0.25

±1

1

4.5

3

–4.5

–3

Offset Match from CH0 to CH5

Range Error

±0.5

±2

mV

(Note 4)

●

–12

–5

12

5

mV

Range Match from CH0 to CH5

Range Tempco

±1

mV

Internal Reference (Note 4)

External Reference

± 15

±1

ppm/°C

U

A ALOG I PUT

The

A

●

denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T = 25°C. With internal reference, V = V = 3V.

DD

CC

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Analog Differential Input Range (Notes 3, 8, 9)

2.7V ≤ V ≤ 3.3V

0 to 2.5

V

IN

DD

Analog Common Mode + Differential

Input Range

0 to V

CM

DD

(Note 8)

(Note 6)

I

Analog Input Leakage Current

●

1

µA

pF

ns

ps

IN

C

Analog Input Capacitance

13

IN

t

Sample-and-Hold Acquisition Time

Sample-and-Hold Aperture Delay Time

Sample-and-Hold Aperture Delay Time Jitter

Channel to Channel Aperture Skew

Analog Input Common Mode Rejection Ratio

39

ACQ

AP

1

0.3

JITTER

SK

200

CMRR

f

= 100kHz, V = 0V to 3V

–83

–67

dB

IN

= 10MHz, V = 0V to 3V

IN

140812f

2

LTC1408-12

U W

DY A IC ACCURACY

The

●

denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T = 25°C. With internal reference, V = V = 3V.

A

DD

CC

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

SINAD

Signal-to-Noise Plus

Distortion Ratio

100kHz Input Signal

300kHz Input Signal

●

70

72

dB

THD

SFDR

IMD

Total Harmonic

Distortion

100kHz First 5 Harmonics

300kHz First 5 Harmonics

–80

–90

–86

dB

Spurious Free

Dynamic Range

100kHz Input Signal

300kHz Input Signal

90

86

dB

Intermodulation

Distortion

0.625V , 833kHz into CH0+, 0.625V , 841kHz into CH0–.

–80

dB

P-P

Bipolar Mode. Also Applicable to Other Channels

Code-to-Code

V

REF

= 2.5V (Note 17)

0.2

LSB

RMS

Transition Noise

Full Power Bandwidth

V

= 2.5V , SDO = 11585LSB (–3dBFS) (Note 15)

50

5

MHz

IN

P-P

Full Linear Bandwidth S/(N + D) ≥ 68dB, Bipolar Differential Input

U U

U

T = 25°C. V = V = 3V.

I TER AL REFERE CE CHARACTERISTICS

A

DD

CC

PARAMETER

CONDITIONS

= 0

MIN

TYP

MAX

UNITS

V

Output Voltage

Output Tempco

Line Regulation

Output Resistance

Settling Time

I

2.5

15

REF

OUT

ppm/°C

µV/V

Ω

V

= 2.7V to 3.6V, V = 2.5V

600

0.2

2

DD

REF

Load Current = 0.5mA

= 10µF

C

ms

REF

External V

Input Range

2.55

V

DD

V

REF

U

The

DD

●

denotes the specifications which apply over the

CC

DIGITAL I PUTS A D DIGITAL OUTPUTS

full operating temperature range, otherwise specifications are at T = 25°C. V = V = 3V.

A

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

V

= 3.3V

= 2.7V

●

2.4

V

IH

IL

DD

IN

0.6

I

= 0V to V

± 10

µA

pF

V

IN

DD

C

V

Digital Input Capacitance

High Level Output Voltage

Low Level Output Voltage

5

IN

V

= 3V, I = –200µA

OUT

●

2.5

2.9

0.05

OH

OL

DD

V

= 2.7V, I

= 160µA

V

DD

OUT

= 1.6mA

●

0.4

I

Hi-Z Output Leakage D

V

= 0V and V

DD

± 10

µA

pF

OZ

OUT

C

Hi-Z Output Capacitance D

1

OZ

OUT

I

Output Short-Circuit Source Current

Output Short-Circuit Sink Current

V

= 0V, V = 3V

20

15

mA

SOURCE

SINK

OUT

DD

= V = 3V

DD

140812f

3

LTC1408-12

POWER REQUIRE E TS

W U

The

●

denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T = 25°C. With internal reference, V = V = 3V.

A

DD

CC

SYMBOL

, V

PARAMETER

Supply Voltage

Supply Current

CONDITIONS

MIN

TYP

MAX

UNITS

V

2.7

3.0

3.6

V

DD CC

I

+ I

CC

Active Mode, f

Nap Mode

Sleep Mode

= 600ksps

SAMPLE

●

5

1.1

2.0

7

1.9

15

mA

µA

DD

PD

Power Dissipation

Active Mode with SCK, f

= 600ksps

15

mW

SAMPLE

W U

TI I G CHARACTERISTICS

The

DD

●

denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T = 25°C. V = 3V.

A

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

f

Maximum Sampling Rate per Channel

(Conversion Rate)

●

100

kHz

SAMPLE(MAX)

t

Minimum Sampling Period (Conversion + Acquisiton Period)

Clock Period

●

10

µs

THROUGHPUT

(Note 16)

100

96

2

10000

ns

SCK

Conversion Time

(Notes 6, 17)

(Note 6)

SCLK cycles

CONV

Minimum High or Low SCLK Pulse Width

CONV to SCKSetup Time

ns

ms

1

(Notes 6, 10)

(Note 6)

3

10000

2

SCK Before CONV

0

3

Minimum High or Low CONV Pulse Width

SCK↑ to Sample Mode

(Note 6)

4

(Note 6)

4

5

CONV↑ to Hold Mode

(Notes 6, 11)

(Notes 6, 7, 13)

(Notes 6, 12)

(Notes 6, 14)

1.2

45

6

96th SCK↑ to CONV↑ Interval (Affects Acquisition Period)

Delay from SCKto Valid Bits 0 Through 11

SCK↑ to Hi-Z at SDO

7

8

6

8

9

Previous SDO Bit Remains Valid After SCK

2

10

11

V

Settling Time After Sleep-to-Wake Transition

2

REF

+

–

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliabilty and lifetime.

Note 9: The absolute voltage at CHx and CHx must be within this range.

Note 10: If less than 3ns is allowed, the output data will appear one clock

cycle later. It is best for CONV to rise half a clock before SCK, when

running the clock at rated speed.

Note 2: All voltage values are with respect to ground GND.

Note 11: Not the same as aperture delay. Aperture delay (1ns) is the

difference between the 2.2ns delay through the sample-and-hold and the

1.2ns CONV to Hold mode delay.

Note 3: When these pins are taken below GND or above V , they will be

DD

clamped by internal diodes. This product can handle input currents greater

than 100mA below GND or greater than V without latchup.

DD

Note 12: The rising edge of SCK is guaranteed to catch the data coming

out into a storage latch.

Note 13: The time period for acquiring the input signal is started by the

96th rising clock and it is ended by the rising edge of CONV.

+

Note 4: Offset and range specifications apply for a single-ended CH0 –

+

–

CH5 input with CH0 – CH5 grounded and using the internal 2.5V

reference.

Note 5: Integral linearity is tested with an external 2.55V reference and is

defined as the deviation of a code from the straight line passing through

the actual endpoints of a transfer curve. The deviation is measured from

the center of quantization band. Linearity is tested for CH0 only.

Note 6: Guaranteed by design, not subject to test.

Note 7: Recommended operating conditions.

Note 14: The internal reference settles in 2ms after it wakes up from Sleep

mode with one or more cycles at SCK and a 10µF capacitive load.

Note 15: The full power bandwidth is the frequency where the output code

swing drops by 3dB with a 2.5V input sine wave.

P-P

Note 16: Maximum clock period guarantees analog performance during

conversion. Output data can be read with an arbitrarily long clock period.

Note 8: The analog input range is defined for the voltage difference

between CHx and CHx , x = 0–5.

Note 17: The conversion process takes 16 clocks for each channel that is

enabled, up to 96 clocks for all 6 channels.

+

–

140812f

4

LTC1408-12

U W

V

DD

= 3V, T = 25°C

A

TYPICAL PERFOR A CE CHARACTERISTICS

THD, 2nd and 3rd

vs Input Frequency

THD, 2nd and 3rd

SINAD vs Input Frequency

vs Input Frequency

–50

–56

–62

–68

–74

–80

–86

–92

–98

–104

–110

74

71

68

65

62

59

56

53

UNIPOLAR SINGLE-ENDED

BIPOLAR SINGLE-ENDED

–56

–62

–68

THD

–74

2nd

–80

–86

–92

3rd

–98

–104

–110

0.1

1

10

0.1

1

10

0.1

10

1

FREQUENCY (MHz)

140812 G02

140812 G03

140814 G01

100kHz Unipolar Sine Wave 8192

Point FFT Plot

SNR vs Input Frequency

SFDR vs Input Frequency

0

–10

–20

77

74

71

68

92

86

80

74

68

62

56

50

–30

–40

–50

–60

–70

–80

–90

–100

65

62

59

56

53

50

–110

–120

0.1

1

10

0.1

10

0

10

20

30

40

50

1

FREQUENCY (MHz)

FREQUENCY (kHz)

140812 G05

140812 G06

140814 G04

Differential Linearity vs Output

Code, CH0, Unipolar Mode

Integral Linearity vs Output Code,

CH0, Unipolar Mode

100kHz Bipolar Sine Wave 8192

Point FFT Plot

0

–10

1

0.8

0.6

0.4

0.2

0

1

0.8

–20

0.6

–30

0.4

–40

0.2

–50

–60

0

–70

–0.2

–0.4

–0.6

–0.8

0

–0.2

–0.4

–0.6

–0.8

–1

–80

–90

–100

–110

–120

0

20

30

40

50

0

512 1024 1536 2048 2560 3072 3584 4096

OUTPUT CODE

10

0

512 1024 1536 2048 2560 3072 3584 4096

OUTPUT CODE

FREQUENCY (KHZ)

140812 G09

140812 G07

140812 G08

140812f

5

LTC1408-12

U W

V

DD

= 3V, T = 25°C

TYPICAL PERFOR A CE CHARACTERISTICS

A

Full Scale Signal Response

CMRR vs Frequency

3

0

–20

–3

–6

–40

–60

–9

–12

–15

–18

–21

–24

–27

–30

–80

–100

–120

10

100

1000

100 1k 10k 100k 1M 10M 100M 1G

FREQUENCY (Hz)

FREQUENCY (MHz)

1408 G11

1408 G10

PSRR vs Frequency

Crosstalk vs Frequency

0

–20

–40

–60

–40

–60

–80

–100

–120

–80

–100

–120

100 1k 10k 100k 1M 10M 100M 1G

FREQUENCY (Hz)

1408 G12

1408 G13

140812f

6

LTC1408-12

U

PI FU CTIO S

CH3⁺(Pin 14): Non-Inverting Channel 3. CH3⁺operates

fully differentially with respect to CH3^–with a 0V to 2.5V,

or ±1.25V differential swing and a 0V to V_DDabsolute

input range.

CH3^–(Pin 15): Inverting Channel 3. CH3^–operates fully

differentially with respect to CH3⁺with a –2.5V to 0V, or

±1.25V differential swing and a 0V to V_DDabsolute

input range.

CH4⁺(Pin 17): Non-Inverting Channel 4. CH4⁺operates

fully differentially with respect to CH4^–with a 0V to 2.5V,

or±1.25Vdifferentialswinganda0VtoV_DDabsoluteinput

range.

SDO (Pin 1): Three-State Serial Data Output. Each set of

six output data words represent the six analog input

channels at the start of the previous conversion. Data for

CH0 comes out first and data for CH5 comes out last. Each

data word comes out MSB first.

OGND (Pin 2): Ground Return for SDO Currents. Connect

to the solid ground plane.

OV_DD(Pin 3): Power Supply for the SDO Pin. OV_DDmust

be no more than 300mV higher than V_DDand can be

brought to a lower voltage to interface to low voltage logic

families. The unloaded high state at SDO is at the potential

of OV_DD.

CH0⁺(Pin 4): Non-Inverting Channel 0. CH0⁺operates

fully differentially with respect to CH0^–with a 0V to 2.5V,

or ±1.25V differential swing and a 0V to V_DDabsolute

input range.

CH4^–(Pin 18): Inverting Channel 4. CH4^–operates fully

differentially with respect to CH4⁺with a –2.5V to 0V, or

±1.25V differential swing and a 0V to V_DDabsolute input

range.

CH0^–(Pin 5): Inverting Channel 0. CH0^–operates fully

differentially with respect to CH0⁺with a –2.5V to 0V,

or ±1.25V differential swing and a 0V to V_DDabsolute

input range.

CH5⁺(Pin 20): Non-Inverting Channel 5. CH5⁺operates

fully differentially with respect to CH5^–with a 0V to 2.5V,

or±1.25Vdifferentialswinganda0VtoV_DDabsoluteinput

range.

CH5^–(Pin 21): Inverting Channel 5. CH5^–operates fully

differentially with respect to CH5⁺with a –2.5V to 0V, or

±1.25V differential swing and a 0V to V_DDabsolute input

range.

GND (Pins 6, 9, 12, 13, 16, 19): Analog Grounds. These

groundpinsmustbetieddirectlytothesolidgroundplane

under the part. Analog signal currents flow through these

connections.

CH1⁺(Pin 7): Non-Inverting Channel 1. CH1⁺operates

fully differentially with respect to CH1^–with a 0V to 2.5V,

or ±1.25V differential swing and a 0V to V_DDabsolute

input range.

CH1^–(Pin 8): Inverting Channel 1. CH1^–operates fully

differentially with respect to CH1⁺with a –2.5V to 0V,

or ±1.25V differential swing and a 0V to V_DDabsolute

input range.

CH2⁺(Pin 10): Non-Inverting Channel 2. CH2⁺operates

fully differentially with respect to CH2^–with a 0V to 2.5V,

or ±1.25V differential swing and a 0V to V_DDabsolute

input range.

CH2^–(Pin 11): Inverting Channel 2. CH2^–operates fully

differentially with respect to CH2⁺with a –2.5V to 0V, or

±1.25V differential swing and a 0V to V_DDabsolute

input range.

GND (PIN 22): Analog Ground for Reference. Analog

ground must be tied directly to the solid ground plane

under the part. Analog signal currents flow through this

connection. The 10µF reference bypass capacitor should

be returned to this pad.

V_REF(Pin 23): 2.5V Internal Reference. Bypass to GND

and a solid analog ground plane with a 10µF ceramic

capacitor (or 10µF tantalum in parallel with 0.1µF ce-

ramic). Can be overdriven by an external reference voltage

between 2.55V and V_DD, V_CC.

V_CC(Pin 24): 3V Positive Analog Supply. This pin supplies

3V to the analog section. Bypass to the solid analog

ground plane with a 10µF ceramic capacitor (or 10µF

tantalum) in parallel with 0.1µF ceramic. Care should be

taken to place the 0.1µF bypass capacitor as close to

Pin 24 as possible. Pin 24 must be tied to Pin 25.

140812f

7

LTC1408-12

U

PI FU CTIO S

BIP (Pin 29): Bipolar/Unipolar Mode. The input differen-

tial range is 0V – 2.5V when BIP is LOW, and it is ±1.25V

when BIP is HIGH. Must be kept in fixed state during

conversion and during subsequent conversion to read

data. When changing BIP between conversions the full

acquisition time must be allowed before starting the next

conversion. The output data is in 2’s complement

format for bipolar mode and straight binary format for

unipolar mode.

V_DD(Pin 25): 3V Positive Digital Supply. This pin supplies

3V to the logic section. Bypass to DGND pin and solid

analog ground plane with a 10µF ceramic capacitor (or

10µF tantalum in parallel with 0.1µF ceramic). Keep in

mind that internal digital output signal currents flow

through this pin. Care should be taken to place the 0.1µF

bypass capacitor as close to Pin 25 as possible. Pin 25

must be tied to Pin 24.

SEL2 (Pin 26): Most significant bit controlling the

number of channels being converted. In combination with

SEL1andSEL0,000selectsjustthefirstchannel(CH0)for

conversion. Incrementing SELx selects additional

channels(CH0–CH5) for conversion. 101, 110 or 111

selectall6channelsforconversion. Mustbekeptinafixed

state during conversion and during the subsequent con-

version to read data.

CONV (Pin 30): Convert Start. Holds the six analog input

signals and starts the conversion on CONV’s rising edge.

Two CONV pulses with SCK in fixed high or fixed low state

starts Nap mode. Four or more CONV pulses with SCK in

fixed high or fixed low state starts Sleep mode.

DGND (Pin 31): Digital Ground. This ground pin must be

tied directly to the solid ground plane. Digital input signal

currents flow through this pin.

SEL1 (Pin 27): Middle significance bit controlling the

number of channels being converted. In combination with

SEL0andSEL2,000selectsjustthefirstchannel(CH0)for

conversion. Incrementing SELx selects additional

channels for conversion. 101, 110 or 111 select all 6

channels (CH0–CH5) for conversion. Must be kept in a

fixed state during conversion and during the subsequent

conversion to read data.

SCK (Pin 32): External Clock Input. Advances the conver-

sion process and sequences the output data at SD0 (Pin1)

on the rising edge. One or more SCK pulses wake from

sleep or nap power saving modes. 16 clock cycles are

needed for each of the channels that are activated by SELx

(Pins 26, 27, 28), up to a total of 96 clock cycles needed

to convert and read out all 6 channels.

SEL0 (Pin 28): Least significant bit controlling the

number of channels being converted. In combination with

SEL1andSEL2,000selectsjustthefirstchannel(CH0)for

conversion. Incrementing SELx selects additional

channels for conversion. 101, 110 or 111 select all 6

channels (CH0–CH5) for conversion. Must be kept in a

fixed state during conversion and during the subsequent

conversion to read data.

EXPOSED PAD (Pin 33): GND. Must be tied directly to the

solid ground plane.

140812f

8

LTC1408-12

W

BLOCK DIAGRA

0.1µF

10µF

3V

V

DD

CC

24

25

+

CH0

4

+

S & H

–

CH0

5

6

7

–

+

–

CH1

+

–

CH1

8

9

+

–

CH2

10

+

–

OV

3V

DD

12-BIT LATCH 0

12-BIT LATCH 1

12-BIT LATCH 2

12-BIT LATCH 3

12-BIT LATCH 4

12-BIT LATCH 5

3

1

2

CH2

THREE-

STATE

SERIAL

OUTPUT

PORT

11

SD0

0.1µF

600ksps

12-BIT ADC

MUX

12 13

14

OGND

+

–

CH3

+

–

CH3

15

16

17

TIMING

LOGIC

CONV

SCK

30

32

+

–

CH4

+

–

CH4

18

19

20

+

–

CH5

+

–

CH5

21

2.5V

REFERENCE

V

REF

EXPOSED PAD

33

22

23 29

26

27

28

31

10µF

DGND

GND

BIP

SEL2 SEL1 SEL0

1408 BD

140812f

9

LTC1408-12

W U

W

TI I G DIAGRA S

S C K

140812f

10

LTC1408-12

W U

W

TI I G DIAGRA S

Nap Mode and Sleep Mode Waveforms

SCK

t

1

t

1

CONV

NAP

SLEEP

t

11

V

REF

1408 TD02

NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS

SCK to SDO Delay

SCK

V

IH

V

IH

t

10

8

t

9

V

OH

SDO

Hi-Z

OL

1408 TD03

140812f

11

LTC1408-12

W U U

U

APPLICATIO S I FOR ATIO

SELECTING THE NUMBER OF CONVERTED CHANNELS

(SEL2, SEL1, SEL0)

BIPOLAR/UNIPOLAR MODE

The input voltage range for each of the CHx input differen-

tial pairs is UNIPOLAR 0V – 2.5V when BIP is LOW, and

BIPOLAR ±1.25V when BIP is HIGH. This pin must be kept

in fixed state during conversion and during subsequent

conversion to read data. When changing BIP between

conversions the full acquisition time must be allowed

beforestartingthenextconversion. Afterchangingmodes

from BIPOLAR to UNIPOLAR, or from UNIPOLAR to

BIPOLAR, you can still read the first set of channels in the

new mode, by inverting the MSB to read these channels in

the mode that they were converted in.

These three control pins select the number of channels

being converted (see Table 1). 000 selects only the first

channel (CH0) for conversion. Incrementing SELx selects

additional channels for conversion, up to 6 channels. 101,

110or111selectall6channelsforconversion. Thesepins

must be kept in a fixed state during conversion and during

the subsequent conversion to read data. When changing

modes between conversions, keep in mind that the output

data of a particular channel will remain unchanged until

afterthatchannelisconvertedagain. Forexample:convert

a sequence of 4 channels (CH0, CH1, CH2, CH3) with

SELx = 011, then, after these channels are converted

change SELx to 001 to convert just CH0 and CH1. During

the conversion of the first set of two channels you will be

able to read the data from the same two channels con-

verted as part of the previous group of 4 channels. Later,

you could convert 4 or more channels to read back the

unread CH2 and CH3 data that was converted in the first

setof4channels. Thesepinsareoftenhardwiredtoenable

the right number of channels for a particular application.

Choosing to convert fewer channels per conversion re-

sults in faster throughput of those channels. For example,

6 channels can be converted at 100ksps/ch, while 3

channels can be converted at 200ksps/ch.

DRIVING THE ANALOG INPUT

The differential analog inputs of the LTC1408-12 may be

driven differentially or as a single-ended input (i.e., the

CHx^–input is grounded). All twelve analog inputs of all six

differential analog input pairs, CH0⁺and CH0^–, CH1⁺and

CH1^–, CH2⁺and CH2^–, CH3⁺and CH3^–, CH4⁺and CH4^–

and CH5⁺and CH5^–, are sampled at the same instant. Any

unwanted signal that is common to both inputs of each

input pair will be reduced by the common mode rejection

of the sample-and-hold circuit. The inputs draw only one

small current spike while charging the sample-and-hold

capacitors at the end of conversion. During conversion,

the analog inputs draw only a small leakage current. If the

source impedance of the driving circuit is low, then the

Table 1. Conversion Sequence Control

(“acquire” represents simultaneous sampling of all channels; CHx represents conversion of channels)

SEL2

SEL1

SEL0

CHANNEL ACQUISITION AND CONVERSION SEQUENCE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

acquire, CH0, acquire, CH0...

acquire, CH0, CH1, acquire, CH0, CH1...

acquire, CH0, CH1, CH2, acquire, CH0, CH1, CH2...

acquire, CH0, CH1, CH2, CH3, acquire, CH0, CH1, CH2, CH3...

acquire, CH0, CH1, CH2, CH3, CH4, acquire, CH0,CH1,CH2, CH3, CH4...

acquire, CH0, CH1, CH2, CH3, CH4, CH5, acquire, CH0, CH1, CH2, CH3, CH4, CH5...

140812f

12

LTC1408-12

W U U

APPLICATIO S I FOR ATIO

U

LTC1566-1: Low Noise 2.3MHz Continuous Time

LTC1408-12 inputs can be driven directly. As source

impedance increases, so will acquisition time. For mini-

mum acquisition time with high source impedance, a

buffer amplifier must be used. The main requirement is

that the amplifier driving the analog input(s) must settle

after the small current spike before the next conversion

starts (the time allowed for settling must be at least 39ns

for full throughput rate). Also keep in mind while choosing

an input amplifier the amount of noise and harmonic

distortion added by the amplifier.

Lowpass Filter.

LT^®1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier.

2.7V to ±15V supplies. Very high A_VOL, 500µV offset and

520ns settling to 0.5LSB for a 4V swing. THD and noise

are –93dB to 40kHz and below 1LSB to 320kHz (A_V= 1,

2V_P-Pinto1kΩ,V_S=5V),makingthepartexcellentforAC

applications (to 1/3 Nyquist) where rail-to-rail perfor-

mance is desired. Quad version is available as LT1631.

LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier.

2.7V to ±15V supplies. Very high A_VOL, 1.5mV offset and

400ns settling to 0.5LSB for a 4V swing. It is suitable for

applications with a single 5V supply. THD and noise are

–93dB to 40kHz and below 1LSB to 800kHz (A_V= 1,

2V_P-Pinto1kΩ,V_S=5V),makingthepartexcellentforAC

applications where rail-to-rail performance is desired.

Quad version is available as LT1633.

CHOOSING AN INPUT AMPLIFIER

Choosing an input amplifier is easy if a few requirements

are taken into consideration. First, to limit the magnitude

of the voltage spike seen by the amplifier from charging

the sampling capacitor, choose an amplifier that has a low

output impedance (< 100Ω) at the closed-loop bandwidth

frequency. For example, if an amplifier is used in a gain of

1 and has a unity-gain bandwidth of 50MHz, then the

output impedance at 50MHz must be less than 100Ω. The

second requirement is that the closed-loop bandwidth

must be greater than 40MHz to ensure adequate small-

signal settling for full throughput rate. If slower op amps

are used, more time for settling can be provided by

increasing the time between conversions. The best choice

for an op amp to drive the LTC1408-12 depends on the

application. Generally, applications fall into two catego-

ries: AC applications where dynamic specifications are

most critical and time domain applications where DC

accuracy and settling time are most critical. The following

list is a summary of the op amps that are suitable for

driving the LTC1408-12. (More detailed information is

available in the Linear Technology Databooks and on the

website at www.linear.com.)

LT1801: 80MHz GBWP, –75dBc at 500kHz, 2mA/ampli-

fier, 8.5nV/√Hz.

LT1806/LT1807: 325MHz GBWP, –80dBc distortion at

5MHz, unity gain stable, rail-to-rail in and out,

10mA/amplifier, 3.5nV/√Hz.

LT1810: 180MHz GBWP, –90dBc distortion at 5MHz,

unity gain stable, rail-to-rail in and out, 15mA/amplifier,

16nV/√Hz.

LT1818/LT1819: 400MHz, 2500V/µs, 9mA, Single/Dual

Voltage Mode Operational Amplifier.

LT6200: 165MHz GBWP, –85dBc distortion at 1MHz,

unity gain stable, rail-to-rail in and out, 15mA/amplifier,

0.95nV/√Hz.

LT6203: 100MHz GBWP, –80dBc distortion at 1MHz,

unity gain stable, rail-to-rail in and out, 3mA/amplifier,

1.9nV/√Hz.

LinearView is a trademark of Linear Technology Corporation.

LT6600: Amplifier/Filter Differential In/Out with 10MHz

Cutoff frequency.

140812f

13

LTC1408-12

W U U

U

APPLICATIO S I FOR ATIO

INPUT RANGE

INPUT FILTERING AND SOURCE IMPEDANCE

The analog inputs of the LTC1408-12 may be driven fully

differentially with a single supply. Either input may swing

uptoV_CC,providedthedifferentialswingisnogreaterthan

2.5V with BIP (Pin 29) Low, or ±1.25V with (BIP Pin 29)

High. The 0V to 2.5V range is also ideally suited for single-

ended input use with single supply applications. The

common mode range of the inputs extend from ground to

the supply voltage V_CC. If the difference between the CH⁺

andCH^–atanyinputpairexceeds2.5V(unipolar)or1.25V

(bipolar), the output code will stay fixed at positive full-

scale, and if this difference goes below 0V (unipolar) or –

1.25V (bipolar), the output code will stay fixed at negative

full-scale.

The noise and the distortion of the input amplifier and

other circuitry must be considered since they will add to

the LTC1408-12 noise and distortion. The small-signal

bandwidth of the sample-and-hold circuit is 50MHz. Any

noise or distortion products that are present at the analog

inputs will be summed over this entire bandwidth. Noisy

input circuitry should be filtered prior to the analog inputs

tominimizenoise. Asimple1-poleRCfilterissufficientfor

many applications. For example, Figure 1 shows a 47pF

capacitor from CHO⁺to ground and a 51Ω source resistor

to limit the net input bandwidth to 30MHz. The 47pF ca-

pacitoralsoactsasachargereservoirfortheinputsample-

and-hold and isolates the ADC input from sampling-glitch

sensitive circuitry. High quality capacitors and resistors

should be used since these components can add distor-

tion. NPO and silvermica type dielectric capacitors have

excellent linearity. Carbon surface mount resistors can

generate distortion from self heating and from damage

thatmayoccurduringsoldering. Metalfilmsurfacemount

resistors are much less susceptible to both problems.

When high amplitude unwanted signals are close in

frequency to the desired signal frequency a multiple pole

filter is required.

INTERNAL REFERENCE

The LTC1408-12 has an on-chip, temperature compen-

sated, bandgap reference that is factory trimmed to 2.5V

to obtain a precise 2.5V input span. The reference ampli-

fieroutputV_REF, (Pin23)mustbebypassedwithacapaci-

tortoground.Thereferenceamplifierisstablewithcapaci-

tors of 1µF or greater. For the best noise performance, a

10µF ceramic or a 10µF tantalum in parallel with a 0.1µF

ceramic is recommended. The V_REFpin can be overdriven

with an external reference as shown in Figure 2. The volt-

age of the external reference must be higher than the 2.5V

of the open-drain P-channel output of the internal refer-

ence. The recommended range for an external reference

is 2.55V to V_DD. An external reference at 2.55V will see a

DC quiescent load of 0.75mA and as much as 3mA

during conversion.

High external source resistance, combined with 13pF of

inputcapacitance,willreducetherated50MHzinputband-

width and increase acquisition time beyond 39ns.

51Ω*

1

ANALOG

INPUT

+

–

CH0

47pF*

2

CH0

LTC1408-12

REF

3

V

3.5V to 18V

10µF

11

GND

51Ω*

ANALOG

INPUT

4

+

3V

23

CH1

LT1790-3

V

REF

LTC2351-12

GND

47pF*

5

–

10µF

22

1408 F01

*TIGHT TOLERANCE REQUIRED TO AVOID

APERTURE SKEW DEGRADATION

1408 F02

Figure 2. Overdriving V Pin with an External Reference

Figure 1. RC Input Filter

REF

140812f

14

LTC1408-12

W U U

APPLICATIO S I FOR ATIO

U

INPUT SPAN VERSUS REFERENCE VOLTAGE

Figure 4 shows the ideal input/output characteristics for

the LTC1408-12 in unipolar mode (BIP = Low). The code

transitionsoccurmidwaybetweensuccessiveintegerLSB

values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, FS – 1.5LSB). The

output code is straight binary with 1LSB = 2.5V/4096 =

610µV for the LTC1408-12. The LTC1408-12 has 0.2 LSB

RMS of Gaussian white noise.

The differential input range has a unipolar voltage span

that equals the difference between the voltage at the

reference buffer output V_REF(Pin 23) and the voltage at

ground. The differential input range of the ADC is 0V to

2.5V when using the internal reference. The internal ADC

is referenced to these two nodes. This relationship also

holds true with an external reference.

111...111

111...110

111...101

DIFFERENTIAL INPUTS

The ADC will always convert the difference of CH⁺minus

CH^–, independentofthecommonmodevoltageatanypair

of inputs. The common mode rejection holds up at high

frequencies (see Figure 3.) The only requirement is that

both inputs not go below ground or exceed V_DD.

000...010

000...001

000...000

0

FS – 1LSB

0

INPUT VOLTAGE (V)

1408 F04

–20

Figure 4. LTC1408-12 Transfer Characteristic

in Unipolar Mode (BIP = Low)

–40

–60

Figure 5 shows the ideal input/output characteristics for

the LTC1408-12 in bipolar mode (BIP = High). The code

transitionsoccurmidwaybetweensuccessiveintegerLSB

values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, FS – 1.5LSB). The

output code is 2’s complement with 1LSB = 2.5V/4096 =

610µV for the LTC1408-12. The LTC1408-12 has 0.2 LSB

RMS of Gaussian white noise.

–80

–100

–120

100 1k 10k 100k 1M 10M 100M 1G

FREQUENCY (Hz)

1408 G11

Figure 3. CMRR vs Frequency

011...111

011...110

011...101

Integral nonlinearity errors (INL) and differential nonlin-

earityerrors(DNL)arelargelyindependentofthecommon

mode voltage. However, the offset error will vary. DC

CMRR is typically better than –90dB.

100...010

100...001

100...000

–FS

FS – 1LSB

INPUT VOLTAGE (V)

1408 F05

Figure 5. LTC1408-12 Transfer Characteristic

in Bipolar Mode (BIP = High)

140812f

15

LTC1408-12

W U U

U

APPLICATIO S I FOR ATIO

Conversion Start Input (CONV)

POWER-DOWN MODES

The rising edge of CONV starts a conversion, but subse-

quent rising edges at CONV are ignored by the LTC1408-12

until the following 96 SCK rising edges have occurred. The

duty cycle of CONV can be arbitrarily chosen to be used as

aframesyncsignalfortheprocessorserialport.Asimple

approachtogenerateCONVistocreateapulsethatisone

SCK wide to drive the LTC1408-12 and then buffer this

signal to drive the frame sync input of the processor

serial port. It is good practice to drive the LTC1408-12

CONVinputfirsttoavoiddigitalnoiseinterferenceduring

the sample-to-hold transition triggered by CONV at the

start of conversion. It is also good practice to keep the

width of the low portion of the CONV signal greater than

15ns to avoid introducing glitches in the front end of the

ADCjustbeforethesample-and-holdgoesintoHoldmode

at the rising edge of CONV.

Upon power-up, the LTC1408-12 is initialized to the

activestateandisreadyforconversion.TheNapandSleep

mode waveforms show the power down modes for the

LTC1408-12. TheSCKandCONVinputscontrolthepower

down modes (see Timing Diagrams). Two rising edges at

CONV, without any intervening rising edges at SCK, put

the LTC1408-12 in Nap mode and the power consumption

drops from 15mW to 3.3mW. The internal reference

remains powered in Nap mode. One or more rising edges

at SCK wake up the LTC1408-12 very quickly and CONV

can start an accurate conversion within a clock cycle. Four

rising edges at CONV, without any intervening rising

edges at SCK, put the LTC1408-12 in Sleep mode and the

power consumption drops from 15mW to 6µW. One or

more rising edges at SCK wake up the LTC1408-12 for

operation. Theinternalreference(V_REF)takes2mstoslew

and settle with a 10µF load. Using sleep mode more

frequently compromises the accuracy of the output data.

Note that for slower conversion rates, the Nap and Sleep

modes can be used for substantial reductions in power

consumption.

Minimizing Jitter on the CONV Input

In high speed applications where high amplitude sine

waves above 100kHz are sampled, the CONV signal must

have as little jitter as possible (10ps or less). The square

wave output of a common crystal clock module usually

meets this requirement. The challenge is to generate a

CONV signal from this crystal clock without jitter corrup-

tion from other digital circuits in the system. A clock

divider and any gates in the signal path from the crystal

clock to the CONV input should not share the same

integrated circuit with other parts of the system. The SCK

andCONVinputsshouldbedrivenfirst,withdigitalbuffers

DIGITAL INTERFACE

The LTC1408-12 has a 3-wire SPI (Serial Peripheral Inter-

face) interface. The SCK and CONV inputs and SDO output

implement this interface. The SCK and CONV inputs

acceptswingsfrom3VlogicandareTTLcompatible, ifthe

logic swing does not exceed V_DD. A detailed description of

the three serial port signals follows:

140812f

16

LTC1408-12

W U U

APPLICATIO S I FOR ATIO

U

after the next convert pulse. It is good practice to drive the

LTC1408-12 SCK input first to avoid digital noise interfer-

ence during the internal bit comparison decision by the

internal high speed comparator. Unlike the CONV input,

the SCK input is not sensitive to jitter because the input

signal is already sampled and held constant.

used to drive the serial port interface. Also note that the

master clock in the DSP may already be corrupted with

jitter, even if it comes directly from the DSP crystal.

Another problem with high speed processor clocks is that

they often use a low cost, low speed crystal (i.e., 10MHz)

to generate a fast, but jittery, phase-locked-loop system

clock (i.e., 40MHz). The jitter in these PLL-generated high

speed clocks can be several nanoseconds. Note that if you

choose to use the frame sync signal generated by the DSP

port, this signal will have the same jitter of the DSP’s

master clock.

Serial Data Output (SDO)

Upon power-up, the SDO output is automatically reset

to the high impedance state. The SDO output remains

in high impedance until a new conversion is started.

SDO sends out up to six sets of 12 bits in the output data

stream after the third rising edge of SCK after the start

of conversion with the rising edge of CONV. The six or

fewer 12-bit words are separated by two don’t care bits

and two clock cycles in high impedance mode. Please

note the delay specification from SCK to a valid SDO.

SDO is always guaranteed to be valid by the next rising

edge of SCK. The 16 – 96-bit output data stream is

compatible with the 16-bit or 32-bit serial port of most

processors.

The Typical Application Figure on page 20 shows a circuit

for level-shifting and squaring the output from an RF

signal generator or other low-jitter source. A single D-type

flip flop is used to generate the CONV signal to the

LTC1408-12.Re-timingthemasterclocksignaleliminates

clock jitter introduced by the controlling device (DSP,

FPGA, etc.) Both the inverter and flip flop must be treated

as analog components and should be powered from a

clean analog supply.

Serial Clock Input (SCK)

BOARD LAYOUT AND BYPASSING

The rising edge of SCK advances the conversion process

and also udpates each bit in the SDO data stream. After

CONV rises, the third rising edge of SCK sends out up to

six sets of 12 data bits, with the MSB sent first. A simple

approach is to generate SCK to drive the LTC1408-12 first

and then buffer this signal with the appropriate number of

inverters to drive the serial clock input of the processor

serial port. Use the falling edge of the clock to latch data

from the Serial Data Output (SDO) into your processor

serial port. The 12-bit Serial Data will be received in six

16-bit words with 96 or more clocks per frame sync. If

fewer than 6 channels are selected by SEL0–SEL2 for

conversion, then 16 clocks are needed per channel to

convert the analog inputs and read out the resulting data

Wire wrap boards are not recommended for high resolu-

tion and/or high speed A/D converters. To obtain the best

performancefromtheLTC1408-12,aprintedcircuitboard

with ground plane is required. Layout for the printed

circuit board should ensure that digital and analog signal

linesareseparatedasmuchaspossible. Inparticular, care

should be taken not to run any digital track alongside an

analog signal track. If optimum phase match between the

inputsisdesired, thelengthofthetwelveinputwiresofthe

six input channels should be kept matched. But each pair

of input wires to the six input channels should be kept

separated by a ground trace to avoid high frequency

crosstalk between channels.

140812f

17

LTC1408-12

APPLICATIO S I FOR ATIO

W U U

U

Highqualitytantalumandceramicbypasscapacitorsshould HARDWARE INTERFACE TO TMS320C54x

be used at the V_CC, V_DDand V_REFpins as shown in the

The LTC1408-12 is a serial output ADC whose interface

Block Diagram on the first page of this data sheet. For

has been designed for high speed buffered serial ports in

optimum performance, a 10µF surface mount tantalum

fast digital signal processors (DSPs). Figure 7 shows an

example of this interface using a TMS320C54X.

capacitor with a 0.1µF ceramic is recommended for the

V_CC, V_DDand V_REFpins. Alternatively, 10µF ceramic chip

The buffered serial port in the TMS320C54x has direct

access to a 2kB segment of memory. The ADC’s serial

data can be collected in two alternating 1kB segments, in

real time, at the full 600ksps conversion rate of the

LTC1408-12. The DSP assembly code sets frame sync

mode at the BFSR pin to accept an external positive going

pulse and the serial clock at the BCLKR pin to accept an

external positive edge clock. Buffers near the LTC1408-12

may be added to drive long tracks to the DSP to prevent

corruption of the signal to LTC1408-12. This configura-

tion is adequate to traverse a typical system board, but

source resistors at the buffer outputs and termination

resistors at the DSP, may be needed to match the charac-

teristic impedance of very long transmission lines. If you

need to terminate the SDO transmission line, buffer it first

withoneortwo74ACxxgates. TheTTLthresholdinputsof

the DSP port respond properly to the 3V swing used with

the LTC1408-12.

capacitors such as X5R or X7R may be used. The capaci-

tors must be located as close to the pins as possible. The

tracesconnectingthepinsandthebypasscapacitorsmust

bekeptshortandshouldbemadeaswideaspossible. The

V_CCand V_DDbypass capacitor returns to the ground plane

and the V_REFbypass capacitor returns to the Pin 22. Care

should be taken to place the 0.1µF V_CCand V_DDbypass

capacitor as close to Pins 24 and 25 as possible.

Figure6showstherecommendedsystemgroundconnec-

tions. All analog circuitry grounds should be terminated at

theLTC1408-12ExposedPad. Thegroundreturnfromthe

LTC1408-12 to the power supply should be low imped-

ance for noise-free operation. The Exposed Pad of the 32-

pin QFN package is also internally tied to the ground pads.

The Exposed Pad should be soldered on the PC board to

reduce ground connection inductance. All ground pins

(GND, DGND, OGND) must be connected directly to the

same ground plane under the LTC1408-12.

OV BYPASS,

DD

0.1µF, 0402

TMS320C54x

LTC1408-12

3V

5V

3

OV

DD

V

CC

30

CONV

SCK

BFSR

32

BCLKR

BDR

B11 B10

1

2

V

BYPASS,

SDO

DD

0.1µF, 0402

OGND

CONV

CLK

3-WIRE SERIAL

INTERFACE LINK

V

BYPASS,

1408 F06

CC

31

0.1µF, 0402 AND

10µF, 0805

DGND

0V TO 3V LOGIC SWING

Figure 7. DSP Serial Interface to TMS320C54x

V BYPASS,

REF

10µF, 0805

Figure 6. Recommended Layout

140812f

18

LTC1408-12

U

PACKAGE DESCRIPTIO

UH Package

32-Lead Plastic QFN (5mm x 5mm)

(Reference LTC DWG # 05-08-1693)

0.70 ±0.05

5.50 ±0.05

4.10 ±0.05

3.45 ± 0.05

3.50 REF

(4 SIDES)

3.45 ± 0.05

PACKAGE OUTLINE

0.25 ± 0.05

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH R = 0.30 TYP

OR 0.35 × 45° CHAMFER

R = 0.05

TYP

0.00 – 0.05

R = 0.115

TYP

0.75 ± 0.05

5.00 ± 0.10

(4 SIDES)

31 32

0.40 ± 0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

3.45 ± 0.10

3.50 REF

(4-SIDES)

3.45 ± 0.10

(UH32) QFN 0406 REV D

0.200 REF

0.25 ± 0.05

0.50 BSC

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE

M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

140812f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

19

LTC1408-12

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

ADCs

LTC1402

12-Bit, 2.2Msps Serial ADC

5V or ±5V Supply, 4.096V or ±2.5V Span

3V, 15mW, Unipolar Inputs, MSOP Package

3V, 15mW, Bipolar Inputs, MSOP Package

5V, Selectable Spans, 115mW

LTC1403/LTC1403A

12-/14-Bit, 2.8Msps Serial ADC

LTC1403-1/LTC1403A-1 12-/14-Bit, 2.8Msps Serial ADC

LTC1405

12-Bit, 5Msps Parallel ADC

LTC1407/LTC1407A

12-/14-Bit, 3Msps Simultaneous Sampling ADC

3V, 14mW, 2-Channel Unipolar Input Range

3V, 14mW, 2-Channel Bipolar Input Range

3V, 15mW, Selectable Bipolar (Unipolar Input, Six Differential Inputs)

5V, Selectable Spans, 80dB SINAD

LTC1407-1/LTC1407A-1 12-/14-Bit, 3Msps Simultaneous Sampling ADC

LTC1408

LTC1411

LTC1412

LTC1420

LTC1608

LTC1609

14-Bit, 600ksps Simultaneous Sampling ADC

14-Bit, 2.5Msps Parallel ADC

12-Bit, 3Msps Parallel ADC

±5V Supply, ±2.5V Span, 72dB SINAD

5V, Selectable Spans, 72dB SINAD

12-Bit, 10Msps Parallel ADC

16-Bit, 500ksps Parallel ADC

±5V Supply, ±2.5V Span, 90dB SINAD

5V Configurable Bipolar/Unipolar Inputs

5V or 3V (L-Version), Micropower, MSOP Package

16-Bit, 250ksps Serial ADC

LTC1864/LTC1865

LTC1864L/LTC1865L

16-Bit, 250ksps 1-/2-Channel Serial ADCs

DACs

LTC1592

16-Bit, Serial SoftSpan^TM

I

DAC

±1LSB INL/DNL, Software Selectable Spans

OUT

LTC1666/LTC1667

LTC1668

12-/14-/16-Bit, 50Msps DAC

87dB SFDR, 20ns Settling Time

References

LT1460-2.5

LT1461-2.5

LT1790-2.5

Micropower Series Voltage Reference

Precision Voltage Reference

0.10% Initial Accuracy, 10ppm Drift

0.04% Initial Accuracy, 3ppm Drift

0.05% Initial Accuracy, 10ppm Drift

Micropower Series Reference in SOT-23

SoftSpan is a trademark of Linear Technology Corporation.

U

TYPICAL APPLICATIO

Low-Jitter Clock Timing with RF Sine Generator Using Clock

Squaring/Level Shifting Circuit and Re-Timing Flip-Flop

V

CC

1k

NC7SVU04P5X

0.1µF

50Ω

MASTER CLOCK

CC

V

1k

CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

PRE

CLR

D

Q

CONV

LTC

1408-12

CONVERT ENABLE

NL17SZ74

1408 TA02

140812f

LT/LWI 1006 • PRINTED IN THE USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	1408-12
厂家：	Linear
描述：	6 Channel, 12-Bit, 600ksps Simultaneous Sampling ADC with Shutdown 6通道， 12位， 600ksps同时采样ADC ，带有关断
文件：	总20页 (文件大小：267K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

1408-12 [Linear]

相关型号：

1408-1A

1408-1B

1408-1C

1408-2

1408-6002

1408028

1408030

1408047

1408048

1408051-2

1408051-4

1408051-5