1654I_技术文档

LTC1654

Dual 14-Bit Rail-to-Rail DAC

in 16-Lead SSOP Package

U

FEATURES

DESCRIPTIO

The LTC^®1654 is a dual, rail-to-rail voltage output, 14-bit

digital-to-analog converter (DAC). It is available in a

16-leadnarrowSSOPpackage,makingitthesmallestdual

14-bit DAC available. It includes output buffer amplifiers

and a flexible serial interface.

■

14-Bit Monotonic Over Temperature

Individually Programmable Speed/Power:

■

3µs Settling Time at 930µA

8.5µs Settling Time at 540µA

■

3V to 5V Single Supply Operation

■

Maximum Update Rate: 0.9MHz

Buffered True Rail-to-Rail Voltage Outputs

The LTC1654 has REFHI pins for each DAC that can be

driven up to V_CC. The output will swing from 0V to V_CCin

a gain of 1 configuration or V_CC/2 in a gain of 1/2 configu-

ration. It operates from a single 2.7V to 5.5V supply.

■

User Selectable Gain

Power-On Reset and Clear Function

■

Schmitt Trigger On Clock Input Allows Direct

The LTC1654 has two programmable speeds: a FAST and

SLOW mode with ±1LSB settling times of 3µs or 8.5µs

respectively and supply currents of 930µA and 540µA in

the two modes. The LTC1654 also has shutdown capabil-

ity, power-on reset and a clear function to 0V.

Optocoupler Interface

■

Smallest Dual 14-Bit DAC: 16-Lead Narrow

SSOP Package

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APPLICATIO S

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 5396245.

■

Digital Calibration

■

Industrial Process Control

■

Automatic Test Equipment

Offset/Gain Adjustment

Multiplying DAC

■

W

BLOCK DIAGRA

CS/LD

REFHI B

CONTROL

LOGIC

SCK

INPUT

LATCH

DAC

REGISTER

DAC B

SDI

+

V

OUT B

–

32-BIT

SHIFT

REGISTER

X /X

B

1

1/2

REFHI A

INPUT

LATCH

DAC

REGISTER

DAC A

+

–

V

OUT A

SDO

POWER-ON

RESET

CLR

X /X

1

A

1/2

1654 BD

REFLO B

REFLO A

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LTC1654

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ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

V_CCto GND .............................................. –0.5V to 7.5V

TTL Input Voltage, REFHI,

REFLO, X₁/X_1/2........................................ –0.5V to 7.5V

V_OUT, SDO .................................. –0.5V to (V_CC+ 0.5V)

Operating Temperature Range

LTC1654C ............................................. 0°C to 70°C

LTC1654I ........................................ –40°C to 85°C

Maximum Junction Temperature .......................... 125°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

TOP VIEW

ORDER PART

NUMBER

X /X

B

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

1

1/2

CC

CLR

SCK

SDI

OUT B

LTC1654CGN

LTC1654IGN

REFHI B

REFLO B

AGND

CS/LD

DGND

SDO

REFLO A

REFHI A

GN PART MARKING

X /X

1

A

V

1/2

OUT A

1654

1654I

GN PACKAGE

16-LEAD PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 110°C/W

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS ^The

●

denotes specifications which apply over the full operating tempera-

ture range, otherwise specifications are at T = 25°C. Unless otherwise noted, V = 2.7V to 5.5V, V

REFHI B = 4.096V (V = 5V), REFHI A, REFHI B = 2.048V (V = 2.7V), REFLO = 0V, X /X = 0V.

, V

unloaded, REFHI A,

A

CC

OUT A OUT B

CC

1

1/2

SYMBOL PARAMETER

DAC

CONDITIONS

MIN

TYP

MAX

UNITS

n

Resolution

●

14

Bits

LSB

Monotonicity

DNL

INL

Differential Nonlinearity

Integral Nonlinearity

Zero Scale Error

Guaranteed Monotonic (Note 2)

Integral Nonlinearity (Note 2)

±0.3

±1.2

±1

±4

6.5

9.0

ZSE

0°C ≤ T ≤ 70°C

●

0

mV

A

–40°C ≤ T ≤ 85°C

A

V

Offset Error

0°C ≤ T ≤ 70°C (Note 3)

●

±6.5

±9.0

mV

OS

A

–40°C ≤ T ≤ 85°C (Note 3)

A

TC

Offset Error Tempco

Gain Error

± 15

µV/°C

LSB

●

±24

Gain Error Drift

5

ppm/°C

Power Supply

V

Positive Supply Voltage

For Specified Performance

●

2.7

5.5

V

CC

I

Supply Current (SLOW/FAST)

2.7V ≤ V ≤ 5.5V (Note 5) SLOW

●

540

930

350

680

3

850

1400

500

1000

10

µA

CC

2.7V ≤ V ≤ 5.5V (Note 5) FAST

CC

2.7V ≤ V ≤ 3.3V (Note 5) SLOW

CC

2.7V ≤ V ≤ 3.3V (Note 5) FAST

CC

In Shutdown (Note 5)

Op Amp DC Performance

Short-Circuit Current Low

V

Shorted to GND

●

70

80

40

120

200

2.5

mA

OUT

Short-Circuit Current High

Output Impedance to GND

Power Supply Rejection

Shorted to V

CC

Input Code = 0

Ω

mV/V

PSR

REFHIA, REFHIB = 4.096V (V = 5V ±10%)

CC

REFHIA, REFHIB = 2.048V (V = 3V ±10%)

Input Code = 16383

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LTC1654

ELECTRICAL CHARACTERISTICS

The

●

denotes specifications which apply over the full operating tempera-

ture range, otherwise specifications are at T = 25°C. Unless otherwise noted, V = 2.7V to 5.5V, V

, V

unloaded, REFHI A,

A

CC

OUT A OUT B

REFHI B = 4.096V (V = 5V), REFHI A, REFHI B = 2.048V (V = 2.7V), REFLO = 0V, X /X = 0V.

CC

SYMBOL PARAMETER

AC Performance

CC

1

1/2

CONDITIONS

MIN

TYP

MAX

UNITS

Voltage Output Slew Rate

(Note 8) SLOW

(Note 8) FAST

●

0.20

1.25

0.9

3.8

V/µs

●

Voltage Output Settling Time

(Note 4) to ±1LSB, SLOW

(Note 4) to ±1LSB, FAST

8.5

3.0

µs

Digital Feedthrough

(Note 7)

1

nV•s

Midscale Glitch Impulse

Output Noise Voltage Density

DAC Switch Between 8000 and 7FFF

20

at 10kHz, SLOW

at 10kHz, FAST

170

150

nV/√Hz

Digital I/O

V

Digital Input High Voltage

Digital Input Low Voltage

Digital Output High Voltage

Digital Output Low Voltage

Digital Input High Voltage

Digital Input Low Voltage

Digital Output High Voltage

Digital Output Low Voltage

Digital Input Leakage

V

= 5V

●

2.4

V

IH

IL

CC

IN

= 5V

0.8

0.4

0.8

= 5V, I

= 3V

= –1mA, D

Only

V

– 0.4

CC

V

OH

OL

IH

OUT

= 1mA, D

Only

V

OUT

2.4

– 0.4

V

= 3V

V

IL

= 3V, I

= –1mA, D

Only

V

OH

OL

LEAK

OUT

CC

= 1mA, D

0.4

± 10

10

V

OUT

I

= GND to V

µA

pF

CC

C

Digital Input Capacitance

(Note 6)

IN

Reference Input

Reference Input Resistance

REFHI to REFLO

(Note 6)

●

30

0

60

kΩ

V

Reference Input Range

Reference Input Current

V

CC

In Shutdown

1

µA

Switching Characteristics (V = 4.5V to 5.5V)

CC

t

SDI Valid to SCK Setup

SDI Valid to SCK Hold

SCK High Time

●

30

0

ns

1

(Note 6)

2

15

10

5

3

SCK Low Time

4

CS/LD Pulse Width

LSB SCK to CS/LD

CS/LD Low to SCK

SD0 Output Delay

SCK Low to CS/LD Low

CLR Pulse Width

5

6

7

C

= 100pF

LOAD

100

8

(Note 6)

10

30

9

10

Switching Characteristics (V = 2.7V to 5.5V)

CC

t

SDI Valid to SCK Setup

SDI Valid to SCK Hold

SCK High Time

●

45

0

ns

1

2

3

4

5

6

7

(Note 6)

20

15

SCK Low Time

CS/LD Pulse Width

LSB SCK to CS/LD

CS/LD Low to SCK

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LTC1654

ELECTRICAL CHARACTERISTICS

The

●

denotes specifications which apply over the full operating

, V unloaded,

temperature range, otherwise specifications are at T = 25°C. Unless otherwise noted, V = 2.7V to 5.5V, V

A

CC

OUT A OUT B

REFHI A, REFHI B = 4.096V (V = 5V), REFHI A, REFHI B = 2.048V (V = 2.7V), REFLO = 0V, X /X = 0V.

CC

1

1/2

SYMBOL PARAMETER

Switching Characteristics (V = 2.7V to 5.5V)

CONDITIONS

MIN

TYP

MAX

UNITS

CC

t

SDO Output Delay

SCK Low to CS/LD Low

CLR Pulse Width

C

= 100pF

●

5

150

ns

8

LOAD

(Note 6)

15

45

9

10

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 4: DAC switched between code 2 k and code 16383. See

L

Applications Information (page 11) for definition of low code k .

L

Note 2: Nonlinearity is defined from low code k to code 16383. See

Note 5: Digital inputs at 0V or V

.

CC

L

Applications Information (page 11).

Note 6: Guaranteed by design.

Note 3: Offset error is measured at low code k . See Applications

Information (page 11).

L

Note 7: CS/LD = 0, V

Note 8: 100pF load capacitor.

= 4.096V and data is being clocked in.

OUT

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TYPICAL PERFOR A CE CHARACTERISTICS

Integral Nonlinearity (INL)

vs Input Code

Differential Nonlinearity (DNL)

vs Input Code

Offset vs Temperature

2.0

1.5

2.0

1.5

2.50

1.25

0

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

–1.25

–2.50

8192

0

16383

0

16383

5

35

–55

–25

65

95

125

INPUT CODE

TEMPERATURE (°C)

1654 G02

1654 G01

1654 G03

Minimum Output Voltage

vs Load Current (Output Sinking)

Minimum Supply Headroom vs

Load Current (Output Sourcing)

Gain Error vs Temperature

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

5.0

2.5

CODE: ALL 1s

REFHI

CODE: ALL ZEROS

V

= 4.096V

T

= 25°C

T

= 125°C

A

0

T

= 25°C

A

T

A

= 125°C

T

= –55°C

A

–2.5

–5.0

T

A

= –55°C

0

5

10

15

5

35

–55

–25

65

95

125

0

10

15

5

LOAD CURRENT (mA)

TEMPERATURE (°C)

OUTPUT SINK CURRENT (mA)

1645 G06

1654 G04

1645 G05

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LTC1654

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TYPICAL PERFOR A CE CHARACTERISTICS

Supply Current

vs Logic Input Voltage

Large-Signal Settling—Fast Mode

Large-Signal Settling—Slow Mode

3.0

1.5

0

V_OUT

1V/DIV

CS/LD

2V/DIV

CS/LD

2V/DIV

0

1

2

3

4

5

TIME (2µs/DIV)

1654 G08

TIME (2µs/DIV)

1654 G09

LOGIC INPUT VOLTAGE (V)

1654 G07

Midscale Glitch—Fast Mode

Midscale Glitch—Slow Mode

V

OUT

Glitch at Power-Up

V_CC

0.5V/DIV

V_OUT

10mV/DIV

V_OUT

10mV/DIV

CS/LD

2V/DIV

CS/LD

2V/DIV

V_OUT

50mV/DIV

TIME (50ms/DIV)

1654 G12

TIME (1µs/DIV)

1654 G11

TIME (1µs/DIV)

1654 G10

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LTC1654

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PI FU CTIO S

CS/LD (Pin 5): The TTL Level Input for the Serial Interface

Enable and Load Control. When CS/LD is low, the SCK

signal is enabled, so the data can be clocked in. When

CS/LD is pulled high, the control/address bits are

decoded.

X₁/X_1/2B, X₁/X_1/2A (Pins 1, 8): The Gain of 1 or Gain of

1/2 Pin. When this pin is tied to V_OUT, the output range will

be REFLO to (REFLO + REFHI)/2 (0V to REFHI/2 when

REFLO = 0V). When this pin is tied to REFLO, the output

range will be REFLO to REFHI (0V to REFHI when REFLO

= 0V). These pins should not be left floating.

DGND/AGND (Pins 6, 12): Digital and Analog Grounds.

CLR (Pin 2): The Asynchronous Clear Input.

SDO (Pin 7): The output of the shift register that becomes

valid on the rising edge of the serial clock.

SCK (Pin 3): The TTL Level Input for the Serial Interface

Clock.

V_{OUT A/B}(Pins 9, 15): The Buffered DAC Outputs.

SDI (Pin 4): The TTL Level Input for the Serial Interface

Data. Data on the SDI pin is latched into the shift register

on the rising edge of the serial clock. The LTC1654 allows

either a 24-bit or 32-bit word. When a 24-bit word is used,

the first 8 bits are control and address followed by 16 data

bits. The last two of the 16 data bits are don’t cares. When

a 32-bit word (required for daisy-chain operation) is used,

thefirst8-bitsaredon’tcaresandthefollowing24-bitsare

as above.

REFHIA/B(Pins10, 14):TheReferenceHighInputsofthe

LTC1654. There is a gain of 1 from this pin to the output

in a gain of 1 configuration. In a gain of 1/2 configuration,

there is a gain of 1/2 from this pin to V_OUT

.

REFLOA/B(Pins11, 13):TheReferenceLowInputsofthe

LTC1654. These inputs can swing up to V_CC– 1.5V.

V_CC(Pin16):ThePositiveSupplyInput.2.7V≤V_CC≤5.5V.

Requires a 0.1µF bypass capacitor to ground.

W U

W

TI I G DIAGRA S

t

6

2

t

7

1

4

3

SCK

SDI

t

9

X

C3 B0

X

t

5

CS/LD

SDO

t

8

X

C3

X

CURRENT WORD

1654 TD01

(PREVIOUS

WORD)

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LTC1654

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TI I G DIAGRA S

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LTC1654

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OPERATIO

Serial Interface

Three examples are given to illustrate the DAC’s opera-

tion:

The data on the SDI input is loaded into the shift register

on the rising edge of SCK. The MSB is loaded first. The 1. Load and update DAC A in FAST mode. Leave DAC B

ClockisdisabledinternallywhenCS/LDishigh. Note:SCK

must be low before CS/LD is pulled low to avoid an extra

internal clock pulse.

unchanged. Perform the following sequence for the

control, address and DATA bits:

Step 1: Set DAC A in FAST mode

If no daisy-chaining is required, the input word can be

24-bitwide, asshowninthetimingdiagrams. The8MSBs,

which are loaded first, are the control and address bits

followed by a 16-bit data word. The last two LSBs in the

data word are don’t cares. The input word can be a stream

of three 8-bit wide segments as shown in the “24-Bit

Update” timing diagram.

CS/LD clock in 0101 0000 XXXXXXXX XXXXXXXX;

CS/LD

Step 2: Load and update DAC A with DATA

CS/LD

clock in 0011 0000 + DATA; CS/LD

2. Load and update DAC A in SLOW mode. Power down

DAC B. Perform the following sequence for the con-

trol, address and DATA bits:

If daisy-chaining is required or if the input needs to be

written in two 16-bit wide segments, then the input word

can be 32 bits wide and the top 8 bits (MSBs) are don’t

cares.Theremaining24bitsarecontrol/addressanddata.

This is also shown in the timing diagrams. The buffered

output of the internal 32-bit shift register is available on

the SDO pin, which swings from GND to V_CC.

Step 1: Set DAC A in SLOW mode

CS/LD

clock in 0110 0000 XXXXXXXX

XXXXXXXX;

CS/LD

Step 2: Load and update DAC A with DATA

Multiple LTC1654s may be daisy-chained together by

connecting the SDO pin to the SDI pin of the next IC. The

SCK and CS/LD signals remain common to all ICs in the

daisy-chain. The serial data is clocked to all of the chips,

then the CS/LD signal is pulled high to update all DACs

simultaneously.

CS/LD

clock in 0011 0000 + DATA; CS/LD

Step 3: Power down DAC B

CS/LD

clock in 0100 0001 XXXXXXXX

XXXXXXXX;

CS/LD

Table 1 shows the truth table for the control/address bits.

When the supplies are first applied, the LTC1654 uses

SLOW mode, the outputs are set at 0V, and zeros are

loaded into the 32-bit input shift register. About 300ns

after power-up, the outputs are released from 0V (AGND)

and will go to the voltage on the REFLO pin.

3. PowerdownbothDACsatthesametime.Performthe

following sequence for the control, address and DATA

bits:

Step 1: Power down both DACs simultaneously

CS/LD

clock in 0100 1111 XXXXXXXX

When CLR goes active, zeros are loaded into the input and

DAC latch and the outputs are forced to AGND. After CLR

is forced high, the ouputs will go to the voltage on the

REFLO pin.

XXXXXXXX;

CS/LD

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LTC1654

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OPERATIO

Voltage Output

The total supply current is 930µA in the FAST mode and

540µA in the SLOW mode. The output noise voltage

density at 10kHz is 170nV/√Hz in SLOW mode and

150nV/√Hz in FAST mode.

The LTC1654 comes complete with rail-to-rail voltage

output buffer amplifiers. These amplifiers will swing to

withinafewmillivoltsofeithersupplyrailwhenunloaded

and to within a 450mV of either supply rail when sinking

or sourcing 5mA.

Power Down

EachDACcanalsobeindependentlypowereddowntoless

than 5µA/DAC of supply current. The reference pin also

goesintoahighimpedancestatewhentheDACispowered

down and the reference current will drop to below 0.1µA.

The amplifiers’ output stage is also three-stated but the

V_OUTpins still have the internal gain-setting resistors

connectedtothemresultinginaneffectiveresistancefrom

V_OUTto REFLO. This resistance is typically 90k when the

X₁/X_1/2pin is tied to V_OUTand 36k when X₁/X_1/2is tied to

REFLO. Because of this resistance, V_OUTwill go to V_REFLO

when the DAC is powered down and V_OUTis unloaded.

TherearetwoGAINconfigurationmodesfortheLTC1654:

a) GAIN of 1: (X₁/X_1/2tied to REFLO)

V_OUT= (V_REFHI– V_REFLO)(CODE/16384) + V_REFLO

b) GAIN of 1/2: (X₁/X_1/2tied to V_OUT

)

V_OUT=(1/2)(V_REFHI–V_REFLO)(CODE/16384)+V_REFLO

The LTC 1654 has two SPEED modes: A FAST mode and

a SLOW mode. When operating in the FAST mode, the

output amplifiers will settle in 3µs (typ) to 14 bits on a 4V

outputswing.IntheSLOWmode,theywillsettlein8.5µs.

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LTC1654

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OPERATIO

Table 1.

ADDRESS (n)

CONTROL

A3 A2 A1 A0

C3 C2 C1 C0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DAC A

0

1

0

1

0

1

0

1

0

1

Load Input Register n

DAC B

Update (Power-Up) DAC Register n

Load Input Register n, Update (Power-Up) All

Load and Update n

Reserved (Do Not Use)

Both DACs

Power Down n

Fast n (Speed States are Maintained Even If DAC is

Put in Power-Down Mode)

0

1

0

Slow n (Default State is Slow When Supplies are

Powered Up)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved (Do Not Use)

No Operation

INPUT WORD

CONTROL

ADDRESS

DATA (14 + 2 DON'T CARE LSBs)

D6

A3 A2

A0

D12

C3

C1

A1

D13

D11 D10 D9 D8

D5 D4 D3 D2 D1

D0

X

1654 TABLE

D7

C2

C0

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LTC1654

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APPLICATIO S I FOR ATIO

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The offset, gain error and linearity of the LTC1654 are

defined and tested in output ranges that avoid limiting.

The low code k_Lused in these measurements is defined as

the code which gives a nominal output of 32mV above

ground; see Table 2.

Rail-to-Rail Output Considerations

Rail-to-rail DACs take full advantage of the supply range

available to them, but cannot produce output voltages

above V_CCor below ground. See Figure 2a.

If REFLO is tied to GND, the output for the lowest codes

may limit at 0V, as shown in Figure 2b. Similarly, limiting

can occur near full scale if the REFHI pin is tied to V_CC, as

shown in Figure 2c.

POSITIVE

V

REF

= V

CC

FSE

OUTPUT

VOLTAGE

INPUT CODE

(c)

V

REF

= V

CC

OUTPUT

VOLTAGE

0

8192

16383

INPUT CODE

(a)

OUTPUT

VOLTAGE

0V

NEGATIVE

OFFSET

INPUT CODE

(b)

1654 F02

Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve: (a) Overall Transfer Function, (b) Effect of Negative

Offset for Codes Near Zero Scale, (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V = V

REF

CC

Table 2. Low Code k

L

V , V

REFHI

4.096 2.048

1

128

256

512

1/2 256

Note: V

= O

REFLO

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LTC1654

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DEFI ITIO S

Resolution (n): Resolution is defined as the number of

digital input bits (n). It is also the number of DAC output

states(2ⁿ)thatdividethefull-scalerange.Resolutiondoes

not imply linearity.

Least Significant Bit (LSB): One LSB is the ideal voltage

difference between two successive codes.

LSB = (V_FS– V_OS)/(2ⁿ– 1) = (V_FS– V_OS)/16383

Nominal LSBs:

Full-Scale Voltage (V_FS): This is the output of the DAC

when all bits are set to 1.

LTC1654 LSB = 4.09575V/16383 = 250µV

Voltage Offset Error (V_OS): Normally, DAC offset is the

voltageattheoutputwhentheDACisloadedwithallzeros.

The DAC can have a true negative offset, but because the

partisoperatedfromasinglesupply, theoutputcannotgo

below 0V. If the offset is negative, the output will remain

near 0V resulting in the transfer curve shown in Figure 3.

Zero-Scale Error (ZSE): The output voltage when the

DAC is loaded with all zeros. Since this is a single supply

part, this value cannot be less than 0V.

Integral Nonlinearity (INL): End-point INL is the maxi-

mum deviation from a straight line passing through the

end points of the DAC transfer curve. Because the part

operates from a single supply and the output cannot go

below zero, the linearity is measured between low code

k_Land full scale. The INL error at a given input code is

calculated as follows:

OUTPUT

VOLTAGE

INL = [V_OUT– V_OS– (V_FS– V_OS)(code/16383)]/LSB

V_OUT= The output voltage of the DAC measured at the

given input code

0V

NEGATIVE

OFFSET

DAC CODE

1654 F01

Figure 3. Effect of Negative Offset

Differential Nonlinearity (DNL): DNL is the difference

between the measured change and the ideal one LSB

change between any two adjacent codes. The DNL error

between any two codes is calculated as follows:

Therefore,theoffsetofthepartismeasuredatlowcodek_L:

(k_L)(V )

FS

V_OUT(k_L)–

DNL = (∆V_OUT– LSB)/LSB

∆V_OUT= The measured voltage difference between

two adjacent codes

2ⁿ– 1

V_OS

=

k_L

n

⎛

⎞

1–

⎜

⎟

⎝

⎠

2 – 1

DigitalFeedthrough: Theglitchthatappearsattheanalog

outputcausedbyACcouplingfromthedigitalinputswhen

they change state. The area of the glitch is specified in

nV • s.

1654fb

12

LTC1654

U

TYPICAL APPLICATIO S

ThiscircuitshowshowtouseanLTC1654andanLT^®1077

to make a wide bipolar output swing 14-bit DAC with an

offset that can be digitally programmed. V_OUTA, which can

be set by loading the appropriate code for DAC A, sets the

offset. As this value changes, the transfer curve for the

output moves up and down as illustrated in the graph

below.

A Wide Swing, Bipolar Output 14-Bit DAC with Digitally Controlled Offset

5V

0.1µF

LTC1654

B

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

X /X

1

V

1/2

CC

CLR

SCK

SDI

V

OUT B

49.9k

1%

15V

LT1077

–15V

REFHI B

REFLO B

AGND

µP

+

–

V

OUT

OUTB

CS/LD

DGND

SDO

100k

1%

2 (V

– V

)

OUTA

REFLO A

REFHI A

X /X

1

A

V

OUT A

1/2

1654 TA02

49.9k

1%

100k

1%

10

5

V

≅ 0V

OUTA

V

≅ 2.5V

OUTA

0

CODE

16383

V

OUTA

≅ 5V

–5

–10

1654 TA03

1654fb

13

LTC1654

U

TYPICAL APPLICATIO S

Dual 14-Bit Voltage Output DAC

2.7V TO 5.5V

0.1µF

LTC1654

B

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

X /X

1

V

1/2

CC

OUTPUT B: 0V TO V

CLR

SCK

SDI

V

OUT B

CC

REFHI B

REFLO B

AGND

µP

CS/LD

DGND

SDO

REFLO A

REFHI A

9

OUTPUT A: 0V TO V

X /X

1

A

V

OUT A

CC

1/2

1654 TA01

1654fb

14

LTC1654

U

PACKAGE DESCRIPTION

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.189 – .196*

(4.801 – 4.978)

.045 ±.005

.009

(0.229)

REF

16 15 14 13 12 11 10 9

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165

±

.0015

.0250 TYP

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

5

6

7

8

.015 ± .004

(0.38 ± 0.10)

×

45°

.053 – .068

(1.351 – 1.727)

.004 – .0098

(0.102 – 0.249)

.007 – .0098

(0.178 – 0.249)

0°

– 8° TYP

.016 – .050

(0.406 – 1.270)

.0250

(0.635)

BSC

.008 – .012

(0.203 – 0.305)

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

GN16 (SSOP) 0502

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

1654fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

15

LTC1654

U

TYPICAL APPLICATIO

A Wide Swing, Bipolar Output 14-Bit DAC with Digitally Controlled Offset

5V

0.1µF

LTC1654

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

X /X

1

B

V

1/2

CC

CLR

SCK

SDI

V

OUT B

49.9k

1%

15V

LT1077

–15V

REFHI B

REFLO B

AGND

µP

+

–

V

OUT

2 (V

CS/LD

DGND

SDO

100k

1%

– V

)

OUTA

OUTB

REFLO A

REFHI A

X /X

1

A

V

OUT A

1/2

1654 TA02

49.9k

1%

100k

1%

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1257

Single 12-Bit V

Reference Can Be Overdriven Up to 12V, i.e., FS

DAC, Full Scale: 2.048V, V : 4.75V to 15.75V,

5V to 15V Single Supply, Complete V

SO-8 Package

DAC in

OUT

CC

= 12V

MAX

LTC1446/LTC1446L Dual 12-Bit V

DACs in SO-8 Package

LTC1446: V = 4.5V to 5.5V, V

= 0V to 4.095V

OUT

CC

OUT

LTC1446L: V = 2.7V to 5.5V, V

= 0V to 2.5V

CC

OUT

LTC1448

Dual 12-Bit V

DAC, V : 2.7V to 5.5V

Output Swings from GND to REF. REF Input

Can Be Tied to V

CC

LTC1450/LTC1450L Single 12-Bit V

DACs with Parallel Interface

LTC1450: V = 4.5V to 5.5V, V

= 0V to 4.095V

OUT

CC

OUT

LTC1450L: V = 2.7V to 5.5V, V

= 0V to 2.5V

CC

OUT

LTC1451

LTC1452

LTC1453

Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, V : 4.5V to 5.5V,

Internal 2.048V Reference Brought Out to Pin

5V, Low Power Complete V

DAC in SO-8 Package

CC

OUT

Single Rail-to-Rail 12-Bit V

Multiplying DAC, V : 2.7V to 5.5V

Low Power, Multiplying V

DAC with Rail-to-Rail

OUT

CC

Buffer Amplifier in SO-8 Package

Single Rail-to-Rail 12-Bit V

DAC, Full Scale: 2.5V, V : 2.7V to 5.5V

3V, Low Power, Complete V DAC in SO-8 Package

OUT

CC

OUT

LTC1454/LTC1454L Dual 12-Bit V

DACs in SO-16 Package with Added Functionality

LTC1454: V = 4.5V to 5.5V, V

= 0V to 4.095V

OUT

CC

OUT

LTC1454L: V = 2.7V to 5.5V, V

= 0V to 2.5V

CC

OUT

LTC1456

Single Rail-to-Rail Output 12-Bit DAC with Clear Pin,

Full Scale: 4.095V, V : 4.5V to 5.5V

Low Power, Complete V

Package with Clear Pin

DAC in SO-8

OUT

CC

LTC1458/LTC1458L Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality

LTC1458: V = 4.5V to 5.5V, V

= 0V to 4.095V

CC

OUT

LTC1458L: V = 2.7V to 5.5V, V

= 0V to 2.5V

CC

OUT

LTC1658

LTC1659

14-Bit Rail-to-Rail Micropower DAC in MSOP, V : 2.7V to 5.5V

Output Swings from GND to REF. REF Input

Can Be Tied to V

CC

Single Rail-to-Rail 12-Bit V

DAC in 8-Pin MSOP, V : 2.7V to 5.5V

Low Power, Multiplying V

DAC in MS8 Package.

OUT

CC

Output Swings from GND to REF. REF Input Can Be

Tied to V

CC

References

LT1460

Micropower Precision Reference

Precision Voltage Reference

Low Cost, 10ppm Drift

LT1461

Ultralow Drift 3ppm/°C, Initial Accuracy: 0.04%

Low Drift 10ppm/°C, Initial Accuracy: 0.05%

LT1634

Micropower Precision Reference

1654fb

LT/LT 0705 REV B • PRINTED IN USA

16 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	1654I
厂家：	Linear
描述：	Dual 14-Bit Rail-to-Rail DAC in 16-Lead SSOP Package 双通道14位轨至轨DAC，采用16引脚SSOP封装
文件：	总16页 (文件大小：181K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

1654I [Linear]

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