1977EFE [Linear]
High Voltage 1.5A, 500kHz Step-Down Switching Regulator with 100uA Quiescent Current; 高电压1.5A ， 500kHz的降压型开关稳压器具有100uA的静态电流
| 型号： | 1977EFE |
| 厂家： | 
Linear |
| 描述： | High Voltage 1.5A, 500kHz Step-Down Switching Regulator with 100uA Quiescent Current |
| 文件： | 总24页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1977
High Voltage 1.5A, 500kHz
Step-Down Switching Regulator
with 100µA Quiescent Current
U
FEATURES
DESCRIPTIO
The LT®1977 is a 500kHz monolithic buck switching
regulator that accepts input voltages up to 60V. A high
efficiency 1.5A, 0.2Ω switch is included on the die along
with all the necessary oscillator, control and logic cir-
cuitry. Current mode topology is used for fast transient
response and good loop stability.
■
Wide Input Range: 3.3V to 60V
■
1.5A Peak Switch Current
Burst Mode® Operation: 100µA Quiescent Current**
Low Shutdown Current: IQ < 1µA
Power Good Flag with Programmable Threshold
Load Dump Protection to 60V
■
■
■
■
■
■
■
500kHz Switching Frequency
Innovative design techniques along with a new high volt-
age process achieve high efficiency over a wide input
range. Efficiency is maintained over a wide output current
rangebyemployingBurstModeoperationatlowcurrents,
utilizing the output to bias the internal circuitry, and by
using a supply boost capacitor to fully saturate the power
switch. Patented circuitry maintains peak switch current
over the full duty cycle range.* Shutdown reduces input
supply current to less than 1µA. External synchronization
canbeimplementedbydrivingtheSYNCpinwithlogic-level
inputs. A single capacitor from the CSS pin to the output
providesacontrolledoutputvoltageramp(soft-start).The
device also has a power good flag with a programmable
threshold and time-out and thermal shutdown protection.
Saturating Switch Design: 0.2Ω On-Resistance
Peak Switch Current Maintained Over
Full Duty Cycle Range*
■
■
■
■
1.25V Feedback Reference Voltage
Easily Synchronizable
Soft-Start Capability
Small 16-Pin Thermally Enhanced TSSOP Package
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APPLICATIO S
■
High Voltage Power Conversion
■
14V and 42V Automotive Systems
■
Industrial Power Systems
■
Distributed Power Systems
The LT1977 is available in a 16-pin TSSOP package with
exposed pad leadframe for low thermal resistance. The
LT1976,a200kHzreducedswitchfrequencyversionofthe
LT1977,isalsoavailable.SeetheApplicationsInformation
section for selection criteria between the LT1976 and
LT1977.
■
Battery-Powered Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
*U.S. Patent 6,498,466 and 6,531,909 **See Burst Mode Operation section for conditions
U
Efficiency and Power Loss
TYPICAL APPLICATIO
vs Load Current
Supply Current vs Input Voltage
100
75
50
25
0
10
150
125
100
75
14V to 3.3V Step-Down Converter with
V
= 12V
V
OUT
T
A
= 3.3V
IN
= 25°C
EFFICIENCY
3.3V
100µA No Load Quiescent Current
5V
1
V
3.3V
1A
OUT
V
V
BOOST
SW
IN
IN
2.2µF
100V
CER
10µH
0.1µF
1N4148
SHDN
0.1
0.01
0.001
LT1977
0.1µF
TYPICAL
POWER LOSS
10MQ100N
V
C
SS
C
50
330pF
1500pF
26k
V
BIAS
FB
165k
1%
10pF
25
100µF
6.3V
TANT
+
C
T
PGFB
PG
1µF
SYNC
GND
0
100k
1%
0.0001 0.001
0.1
0.01
LOAD CURRENT (A)
1
10
0
10
30
40
50
60
20
INPUT VOLTAGE (V)
1977 TA01
1977 TA02
1977 F05
1977f
1
LT1977
W W U W
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W
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ABSOLUTE AXI U RATI GS
(Note 1)
PACKAGE/ORDER I FOR ATIO
TOP VIEW
VIN, SHDN, BIAS..................................................... 60V
BOOST Pin Above SW ............................................ 35V
BOOST Pin Voltage ................................................. 68V
SYNC, CSS, PGFB, FB................................................ 6V
Operating JunctionTemperature Range
LT1977EFE (Note 2) ........................ –40°C to 125°C
LT1977IFE (Note 2) ......................... –40°C to 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
NC
SW
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PG
SHDN
SYNC
PGFB
FB
LT1977EFE
LT1977IFE
V
IN
17
NC
BOOST
V
C
C
T
BIAS
FE PART
MARKING
GND
C
SS
FE PACKAGE
16-LEAD PLASTIC TSSOP
1977EFE
1977IFE
TJMAX = 125°C, θJA = 45°C/W, θJC(PAD) = 10°C/W
EXPOSED PAD IS GND (PIN 17)
MUST BE SOLDERED TO GND (PIN 8)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VIN = 12V, SHDN = 12V, BIAS = 5V, FB/PGFB = 1.25V, CSS/SYNC = 0V
unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
1.3
5
MAX
1.45
20
UNITS
V
V
SHDN Threshold
1.15
SHDN
SHDN
I
I
SHDN Input Current
SHDN = 12V
●
●
µA
Minimum Input Voltage (Note 3)
Supply Shutdown Current
Supply Sleep Current (Note 4)
2.4
0.1
3
V
SHDN = 0V, BOOST = 0V, FB/PGFB = 0V
2
µA
VINS
VIN
BIAS = 0V, FB = 1.35V
FB = 1.35V
●
●
170
45
250
75
µA
µA
I
Supply Quiescent Current
BIAS = 0V, FB = 1.15V
BIAS = 5V, FB = 1.15V
4.10
3.25
mA
mA
Minimum BIAS Voltage (Note 5)
BIAS Sleep Current (Note 4)
BIAS Quiescent Current
●
●
2.7
110
700
1.8
40
3
V
µA
I
I
180
900
BIASS
BIAS
SYNC = 3.3V
µA
Minimum Boost Voltage (Note 6)
Input Boost Current (Note 7)
I
I
= 1.5A
= 1.5A
V
SW
SW
mA
V
V
Reference Voltage (V
)
REF
3.3V < V < 60V
●
1.225
1.25
75
1.275
200
REF
VIN
I
FB Input Bias Current
nA
V/V
µMho
µA
FB
EA Voltage Gain (Note 8)
900
650
40
EA Voltage g
dI(V )= ±10µA
450
20
900
55
C
m
EA Source Current
EA Sink Current
FB = 1.15V
FB = 1.35V
15
30
40
µA
V to SW g
3
A/V
V
C
m
V High Clamp
C
2.1
1.5
2.2
2.4
2.4
3.5
I
SW Current Limit
●
A
PK
1977f
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LT1977
ELECTRICAL CHARACTERISTICS
unless otherwise noted.
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VIN = 12V, SHDN = 12V, BIAS = 5V, FB/PGFB = 1.25V, CSS/SYNC = 0V
SYMBOL PARAMETER
Switch On Resistance (Note 9)
CONDITIONS
MIN
TYP
0.2
500
92
MAX
0.4
UNITS
Ω
●
●
Switching Frequency
425
86
575
kHz
%
Maximum Duty Cycle
Minimum SYNC Amplitude
SYNC Frequency Range
SYNC Input Impedance
1.5
700
85
2.0
V
575
7
kHz
kΩ
µA
nA
%
I
I
C
Current Threshold (Note 10)
SS
13
20
100
92
CSS
PGFB Input Current
25
PGFB
V
PGFB Voltage Threshold (Note 11)
●
88
2
90
PGFB
I
C Source Current (Note 11)
T
3.6
2
5.5
µA
mA
V
CT
C Sink Current (Note 11)
T
1
V
C Voltage Threshold (Note 11)
T
1.16
1.2
0.1
200
1.26
1
CT
PG Leakage (Note 11)
V
PG
= 12V
µA
µA
PG Sink Current (Note 11)
PGFB = 1V, PG = 400mV
100
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 5: Minimum BIAS voltage is the voltage on the BIAS pin when I
sourced into the pin.
is
BIAS
Note 2: The LT1977EFE is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT1977IFE is guaranteed and tested over the full –40°C to 125°C
operating junction temperature range.
Note 3: Minimum input voltage is defined as the voltage where switching
starts. Actual minimum input voltage to maintain a regulated output will
depend upon output voltage and load current. See Applications
Information.
Note 6: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 7: Boost current is the current flowing into the BOOST pin with the pin
held 3.3V above input voltage. It flows only during switch on time.
Note 8: Gain is measured with a V swing from 1.15V to 750mV.
C
Note9:SwitchonresistanceiscalculatedbydividingV toSWvoltagebythe
IN
forced current (1.5A). See Typical Performance Characteristics for the graph
of switch voltage at other currents.
Note 10: The C threshold is defined as the value of current sourced into the
SS
C
pin which results in an increase in sink current from the V pin. See the
SS
C
Note 4: Supply input current is the quiescent current drawn by the input
pin. Its typical value depends on the voltage on the BIAS pin and operating
state of the LT1977. With the BIAS pin at 0V, all of the quiescent current
Soft-Start section in Applications Information.
Note 11: The PGFB threshold is defined as the percentage of V voltage
REF
which causes the current source output of the C pin to change from
T
required to operate the LT1977 will be provided by the V pin. With the
IN
sinking (below threshold) to sourcing current (above threshold). When
BIAS voltage above its minimum input voltage, a portion of the total
quiescent current will be supplied by the BIAS pin. Supply sleep current is
defined as the quiescent current during the “sleep” portion of Burst Mode
operation. See Applications Information for determining application supply
currents.
sourcing current, the voltage on the C pin rises until it is clamped
T
internally. When the clamp is activated, the output of the PG pin will be set
to a high impedance state. When the C clamp is inactive the PG pin will
T
be set active low with a current sink capability of 200µA.
1977f
3
LT1977
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TYPICAL PERFOR A CE CHARACTERISTICS
FB Voltage
Oscillator Frequency
SHDN Threshold
550
540
530
520
510
500
490
480
470
460
450
1.40
1.30
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.20
1.35
1.30
1.25
1.20
0.15
1.10
1.05
1.00
–50
0
25
50
75 100 125
–25
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1977 G02
1977 G03
1977 G01
Shutdown Supply Current
Sleep Mode Supply Current
SHDN Pin Current
25
20
15
10
5
200
180
160
140
120
100
80
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0
T
= 25°C
J
V
= 0V
BIAS
V
= 60V
IN
V
= 5V
BIAS
25
60
40
V
IN
= 42V
V
IN
= 12V
20
0
0
–50
–50 –25
50
75 100 125
50
125
0
10
30
SHDN VOLTAGE (V)
40
50
60
0
25
0
75
100
20
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
1977 G05
1977 G06
1977 G04
PGFB Threshold
Bias Sleep Current
PG Sink Current
200
180
160
140
120
100
80
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.06
1.04
1.02
1.00
250
200
150
100
50
60
40
20
0
0
–50
–25
0
25
50
75 100 125
–50
0
25
50
75 100 125
–25
–50
0
25
50
75 100 125
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1977 G07
1977 G08
1977 G09
1977f
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LT1977
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TYPICAL PERFOR A CE CHARACTERISTICS
Soft-Start Current Threshold
vs FB Voltage
Frequency Foldback Percentage
Switch Peak Current Limit
100
90
80
70
60
50
40
30
20
10
0
3.5
3.0
2.5
2.0
50
45
40
35
30
25
20
15
10
5
T
= 25°C
J
SOFT-START
DEFEATED
1.5
0
0
0.25
0.5
0.75
1
1.25
–50 –25 –0
25
50
75 100 125
0
0.2
0.6
0.8
1.0
1.2
0.4
TEMPERATURE (°C)
FB PIN VOLTAGE (V)
FB VOLTAGE (V)
1977 G12
1977 G10
1977 G11
Switch On Voltage (VCESAT
)
Supply Current vs Input Voltage
Minimum Input Voltage
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
500
450
400
350
300
250
200
150
100
50
150
125
100
75
V
= 3.3V
= 25°C
OUT
A
T
V
= 5V
OUT
START-UP
RUNNING
T
J
= 125°C
V
= 3.3V
OUT
T
J
= 25°C
START-UP
RUNNING
50
25
T
J
= –50°C
0
0
0
0.25
0.5
0.75
1
1.25
–0.1
0.7
1.1 1.3
0
10
30
40
50
60
0.1 0.3 0.5
0.9
1.5
20
LOAD CURRENT (A)
LOAD CURRENT (A)
INPUT VOLTAGE (V)
1977 G19
1977 G13
1977 F05
Burst Mode Threshold
vs Input Voltage
Minimum On Time
Boost Current vs Load Current
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
45
40
35
30
25
20
15
10
5
V
= 3.3V
OUT
L = 10µH
= 100µF
C
OUT
LOAD CURRENT = 0.5A
LOAD CURRENT = 1A
Burst Mode EXIT
(INCREASING LOAD)
Burst Mode ENTER
(DECREASING LOAD)
0
0
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
INPUT VOLTAGE (V)
1977 G20
–50
0
25
50
75
125
–25
100
0
0.25
0.5
0.75
1.5
1
1.25
TEMPERATURE (°C)
LOAD CURRENT (A)
1977 G21
1977 G22
1977f
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LT1977
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TYPICAL PERFOR A CE CHARACTERISTICS
Burst Mode Operation
Burst Mode Operation
V
OUT
20mV/DIV
V
OUT
20mV/DIV
I
I
SW
SW
500mA/DIV
500mA/DIV
1977 G15
1977 G14
V
V
I
= 12V
= 3.3V
= 100µA
2µs/DIV
V
V
I
= 12V
= 3.3V
= 100µA
5ms/DIV
IN
OUT
Q
IN
OUT
Q
No Load 1A Step Response
Step Response
V
V
OUT
50mV/DIV
OUT
50mV/DIV
I
OUT
500mA/DIV
I
OUT
500mA/DIV
1977 G17
1977 G18
V
V
C
= 12V
500µs/DIV
V
V
C
= 12V
500µs/DIV
IN
IN
= 3.3V
= 3.3V
OUT
OUT
OUT
OUT
= 100µF
= 100µF
I
= 0mA
I
= 350mA
DC
DC
U
U
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PI FU CTIO S
NC (Pins 1, 3, 5): No Connection.
BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal
bipolarNPNpowerswitch. Withoutthisaddedvoltage, the
typical switch voltage loss would be about 1.5V. The
additional BOOST voltage allows the switch to saturate
and its voltage loss approximates that of a 0.2Ω FET
structure.
SW(Pin2):TheSWpinistheemitteroftheon-chippower
NPN switch. This pin is driven up to the input pin voltage
during switch on time. Inductor current drives the SW pin
negativeduringswitchofftime.Negativevoltageisclamped
with the external catch diode. Maximum negative switch
voltage allowed is –0.8V.
CT (Pin7):AcapacitorontheCT pindeterminestheamount
of delay time between the PGFB pin exceeding its thresh-
old (VPGFB) and the PG pin set to a high impedance state.
When the PGFB pin rises above VPGFB, current is sourced
from the CT pin into the external capacitor. When the volt-
age on the external capacitor reaches an internal clamp
(VCT), the PG pin becomes a high impedance node. The
resultant PG delay time is given by t = CCT • VCT/ICT. If the
1977f
VIN (Pin 4): This is the collector of the on-chip power NPN
switch. VIN powers the internal control circuitry when a
voltage on the BIAS pin is not present. High di/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the VIN pin through the input bypass
capacitor, through the catch diode back to SW. All trace
inductanceonthispathwillcreateavoltagespikeatswitch
off, adding to the VCE voltage across the internal NPN.
6
LT1977
U
U
U
PI FU CTIO S
voltage on the PGFB pin drops below VPGFB, CCT will be
discharged rapidly to 0V and PG will be active low with a
200µAsinkcapability.IftheCT pinisclamped(PowerGood
condition)duringnormaloperationandSHDNistakenlow,
the CT pin will be discharged and a delay period will occur
when SHDN is returned high. See the Power Good section
in Applications Information for details.
During the sleep portion of Burst Mode operation, the VC
pin is held at a voltage slightly below the burst threshold
for better transient response. Driving the VC pin to ground
will disable switching and place the IC into sleep mode.
FB (Pin 12): The feedback pin is used to determine the
output voltage using an external voltage divider from the
outputthatgenerates1.25VattheFBpin. WhentheFBpin
drops below 0.9V, switching frequency is reduced, the
SYNC function is disabled and output ramp rate control is
enabled via the CSS pin. See the Feedback section in
Applications Information for details.
GND (Pins 8, 17): The GND pin connection acts as the
reference for the regulated output, so load regulation will
suffer if the “ground” end of the load is not at the same
voltage as the GND pin of the IC. This condition will occur
when load current or other currents flow through metal
paths between the GND pin and the load ground. Keep the
path between the GND pin and the load ground short and
use a ground plane when possible. The GND pin also acts
as a heat sink and should be soldered (along with the
exposed leadframe) to the copper ground plane to reduce
thermal resistance (see Applications Information).
PGFB (PIN 13): The PGFB pin is the positive input to a
comparator whose negative input is set at VPGFB. When
PGFB is taken above VPGFB, current (ICSS) is sourced into
the CT pin starting the PG delay period. When the voltage
on the PGFB pin drops below VPGFB, the CT pin is rapidly
discharged resetting the PG delay period. The PGFB volt-
age is typically generated by a resistive divider from the
regulated output or input supply. See Power Good section
in Applications Information for details.
CSS (Pin 9): A capacitor from the CSS pin to the regulated
output voltage determines the output voltage ramp rate
during start-up. When the current through the CSS capaci-
tor exceeds the CSS threshold (ICSS), the voltage ramp of
the output is limited. The CSS threshold is proportional to
the FB voltage (see Typical Performance Characteristics)
and is defeated for FB voltage greater than 0.9V (typical).
See Soft-Start section in Applications Information for
details.
SYNC (Pin 14): The SYNC pin is used to synchronize the
internal oscillator to an external signal. It is directly logic
compatible and can be driven with any signal between
30% and 70% duty cycle. The synchronizing range is
equaltomaximuminitialoperatingfrequencyupto700kHz.
When the voltage on the FB pin is below 0.9V the SYNC
function is disabled. See the Synchronizing section in
Applications Information for details.
BIAS (Pin 10): The BIAS pin is used to improve efficiency
when operating at higher input voltages and light load
current. Connecting this pin to the regulated output volt-
age forces most of the internal circuitry to draw its
operating current from the output voltage rather than the
input supply. This architecture increases efficiency espe-
cially when the input voltage is much higher than the
output. Minimum output voltage setting for this mode of
operation is 3V.
SHDN (Pin 15): The SHDN pin is used to turn off the
regulator and to reduce input current to less than 1µA. The
SHDN pin requires a voltage above 1.2V with a typical
source current of 3µA to take the IC out of the shutdown
state.
PG (Pin 16): The PG pin is functional only when the SHDN
pin is above its threshold, and is active low when the
internal clamp on the CT pin is below its clamp level and
high impedance when the clamp is active. The PG pin has
a typical sink capability of 200µA. See the Power Good
section in Applications Information for details.
VC (Pin 11): The VC pin is the output of the error amplifier
and the input of the peak switch current comparator. It is
normally used for frequency compensation, but can also
serve as a current clamp or control loop override. VC sits
at about 0.45V for light loads and 2.2V at maximum load.
1977f
7
LT1977
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BLOCK DIAGRA
V
IN
INTERNAL REF
SLOPE
COMP
4
2.4V
UNDERVOLTAGE
LOCKOUT
Σ
+
–
BIAS
THERMAL
SHUTDOWN
500kHz
10
CURRENT
COMP
OSCILLATOR
SYNC
SHDN
14
15
BOOST
SW
6
2
ANTISLOPE
COMP
+
–
R
SHDN
COMP
SWITCH
LATCH
DRIVER
CIRCUITRY
Q
S
1.3V
BURST MODE
DETECT
C
SS
SOFT-START
9
V
C
CLAMP
FOLDBACK
DETECT
FB
12
+
ERROR
AMP
–
1.25V
V
C
11
13
PG
16
PGFB
+
PG
COMP
1.2V C
T
CLAMP
1.12V
–
GND 17
PGND
C
8
T
7
1977 BD
Figure 1. LT1977 Block Diagram
The LT1977 is a constant frequency, current mode buck
converter.Thismeansthatthereisaninternalclockandtwo
feedback loops that control the duty cycle of the power
switch. In addition to the normal error amplifier, there is a
current sense amplifier that monitors switch current on a
cycle-by-cycle basis. A switch cycle starts with an oscilla-
torpulsewhichsetstheRSlatchtoturntheswitchon.When
switch current reaches a level set by the current compara-
tor the latch is reset and the switch turns off. Output volt-
age control is obtained by using the output of the error
amplifiertosettheswitchcurrenttrippoint.Thistechnique
means that the error amplifier commands current to be
delivered to the output rather than voltage. A voltage fed
system will have low phase shift up to the resonant fre-
quencyoftheinductorandoutputcapacitor,thenanabrupt
180° shift will occur. The current fed system will have 90°
phaseshiftatamuchlowerfrequency,butwillnothavethe
additional 90° shift until well beyond the LC resonant fre-
quency. This makes it much easier to frequency compen-
sate the feedback loop and also gives much quicker tran-
sient response.
Most of the circuitry of the LT1977 operates from an
internal 2.4V bias line. The bias regulator normally draws
1977f
8
LT1977
W
BLOCK DIAGRA
power from the VIN pin, but if the BIAS pin is connected to
an external voltage higher than 3V bias power will be
drawn from the external source (typically the regulated
output voltage). This improves efficiency.
To further optimize efficiency, the LT1977 automatically
switches to Burst Mode operation in light load situations.
In Burst Mode operation, all circuitry associated with
controlling the output switch is shut down reducing the
input supply current to 45µA.
High switch efficiency is achieved by using the BOOST pin
to provide a voltage to the switch driver which is higher
than the input voltage, allowing switch to be saturated.
This boosted voltage is generated with an external capaci-
tor and diode.
The LT1977 contains a power good flag with a program-
mable threshold and delay time. A logic-level low on the
SHDN pin disables the IC and reduces input suppy current
to less than 1µA.
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APPLICATIO S I FOR ATIO
the LT1977’s input range will be similar to the LT1976.
Loweringtheinputvoltagebelowthemaximumdutycycle
limitation will cause a dropout in regulation.
CHOOSING THE LT1976 OR LT1977
The LT1976 and LT1977 are both high voltage 1.5A step-
down Burst Mode switching regulators with a typical
quiescent current of 100µA. The difference between the
two is that the fixed switching frequency of the LT1976 is
200kHz versus 500kHz for the LT1977. The switching
frequency affects: inductor size, input voltage range in
continuous mode operation, efficiency, thermal loss and
EMI.
Table 1. LT1976/LT1977 Comparison
PARAMETER
Minimum Duty Cycle
Maximum Duty Cycle
Inductor Size
ADVANTAGE
LT1976
LT1976
LT1977
LT1977
LT1976
LT1976
LT1976
LT1977
Output Capacitor Size
Efficiency
EMI
OUTPUT RIPPLE AND INDUCTOR SIZE
Input Range
Output ripple current is determined by the input to output
voltage ratio, inductor value and switch frequency. Since
the switch frequency of the LT1977 is 2.5 times greater
thanthatoftheLT1976,theinductanceusedintheLT1977
application can be 2.5 times lower than the LT1976 while
maintaining the same output ripple current. The lower
value used in the LT1977 application allows the use of a
physically smaller inductor.
Output Ripple
FEEDBACK PIN FUNCTIONS
The feedback (FB) pin on the LT1977 is used to set output
voltage and provide several overload protection features.
The first part of this section deals with selecting resistors
to set output voltage and the remaining part talks about
frequency foldback and soft-start features. Please read
both parts before committing to a final design.
INPUT VOLTAGE RANGE
Referring to Figure 2, the output voltage is determined by
a voltage divider from VOUT to ground which generates
1.25VattheFBpin.Sincetheoutputdividerisaloadonthe
output care must be taken when choosing the resistor
divider values. For light load applications the resistor
values should be as large as possible to achieve peak
efficiencyinBurstModeoperation. Extremelylargevalues
forresistorR1willcauseanoutputvoltageerrorduetothe
The LT1976 and LT1977 minimum on and off times are
equivalent. This results in a narrower range of continuous
mode operation for the LT1977. Typical minimum and
maximum duty cycles are 6% to 95% for the LT1976 and
15% to 90% for the LT1977. Both parts will regulate up to
an input voltage of 60V but the LT1977 will transistion into
pulse skipping/Burst Mode operation when the input
voltageisabove30Vfora5Voutput. Atoutputsabove10V
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LT1977
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APPLICATIO S I FOR ATIO
and Soft-Start Current graphs in Typical Performance
Characteristics).
V
OUT
LT1977
SW
2
9
C1
Frequencyfoldbackisusedtocontrolpowerdissipationin
both the IC and in the external diode and inductor during
short-circuit conditions. A shorted output requires the
switching regulator to operate at very low duty cycles. As
a result the average current through the diode and induc-
tor is equal to the short-circuit current limit of the switch
(typically 2A for the LT1977). Minimum switch on time
limitations would prevent the switcher from operating at a
sufficiently low duty cycle if switching frequency were
maintained at 500kHz, so frequency is reduced by about
4:1 when the FB pin voltage drops below 0.4V (see
Frequency Foldback graph). In addition, if the current in
the switch exceeds 1.5 times the current limitations speci-
fied by the VC pin, due to minimum switch on time, the
LT1977 will skip the next switch cycle. As the feedback
voltagerises,theswitchingfrequencyincreasesto500kHz
with 0.95V on the FB pin. During frequency foldback,
external synchronization is disabled to prevent interfer-
ence with foldback operation. Frequency foldback does
not affect operation during normal load conditions.
C
SS
SOFT-START
500kHz
OSCILLATOR
FOLDBACK
DETECT
R1
FB
+
–
12
11
ERROR
AMP
R2
1.25V
V
C
1977 F02
Figure 2. Feedback Network
R1
Table 2
OUTPUT
VOLTAGE
(V)
OUTPUT
ERROR
(%)
R2
NEAREST (1%)
(kΩ, 1%)
(kΩ)
2.5
3
100
100
100
100
100
100
100
100
100
140
165
300
383
536
698
866
0
0
In addition to lowering switching frequency the soft-start
ramp rate is also affected by the feedback voltage. Large
capacitive loads or high input voltages can cause a high
input current surge during start-up. The soft-start func-
tion reduces input current surge by regulating switch
current via the VC pin to maintain a constant voltage ramp
rate(dV/dt)attheoutput. Acapacitor(C1inFigure2)from
the CSS pin to the output determines the maximum output
dV/dt. Whenthefeedbackvoltageisbelow0.4V, theVC pin
will rise, resulting in an increase in switch current and
outputvoltage.IfthedV/dtoftheoutputcausesthecurrent
through the CSS capacitor to exceed ICSS the VC voltage is
reduced resulting in a constant dV/dt at the output. As the
feedback voltage increases ICSS increases, resulting in an
increased dV/dt until the soft-start function is defeated
with 0.9V present at the FB pin. The soft-start function
does not affect operation during normal load conditions.
However, if a momentary short (brown out condition) is
present at the output which causes the FB voltage to drop
below 0.9V, the soft-start circuitry will become active.
3.3
5
0.38
0
6
0.63
–0.63
–0.25
0.63
8
10
12
50nA FB pin input current. The suggested value for the
output divider resistor (see Figure 2) from FB to ground
(R2) is 100k or less. A formula for R1 is shown below. A
table of standard 1% values is shown in Table 2 for
common output voltages.
VOUT – 1.25
R1= R2 •
1.25 +R2 • 50nA
More Than Just Voltage Feedback
The FB pin is used for more than just output voltage
sensing. It also reduces switching frequency and con-
trolsthesoft-startvoltagerampratewhenoutputvoltage
is below the regulated level (see the Frequency Foldback
1977f
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LT1977
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U
INPUT CAPACITOR
exceeded. The AVX TPS and Kemet T495 series are surge
rated. AVX recommends derating capacitor operating
voltage by 2:1 for high surge applications.
Step-down regulators draw current from the input supply
in pulses. The rise and fall times of these pulses are very
fast. The input capacitor is required to reduce the voltage
ripple this causes at the input of LT1977 and force the
switching current into a tight local loop, thereby minimiz-
ing EMI. The RMS ripple current can be calculated from:
OUTPUT CAPACITOR
The output capacitor is normally chosen by its effective
series resistance (ESR) because this is what determines
output ripple voltage. To get low ESR takes volume, so
physically smaller capacitors have higher ESR. The ESR
range for typical LT1977 applications is 0.05Ω to 0.2Ω. A
typical output capacitor is an AVX type TPS, 100µF at 10V,
with a guaranteed ESR less than 0.1Ω. This is a “D” size
surface mount solid tantalum capacitor. TPS capacitors
are specially constructed and tested for low ESR, so they
give the lowest ESR for a given volume. The value in
microfarads is not particularly critical and values from
22µF to greater than 500µF work well, but you cannot
cheat Mother Nature on ESR. If you find a tiny 22µF solid
tantalum capacitor, it will have high ESR and output ripple
voltage could be unacceptable. Table 3 shows some
typical solid tantalum surface mount capacitors.
IOUT
V
IRIPPLE(RMS)
=
VOUT V – V
IN OUT
(
)
IN
Ceramiccapacitorsareidealforinputbypassing.At500kHz
switching frequency input capacitor values in the range of
4.7µF to 20µF are suitable for most applications. If opera-
tionisrequiredclosetotheminimuminputrequiredbythe
LT1977 a larger value may be required. This is to prevent
excessive ripple causing dips below the minimum operat-
ing voltage resulting in erratic operation.
Input voltage transients caused by input voltage steps or
by hot plugging the LT1977 to a pre-powered source such
as a wall adapter can exceed maximum VIN ratings. The
sudden application of input voltage will cause a large
surge of current in the input leads that will store energy in
the parasitic inductance of the leads. This energy will
causetheinputvoltagetoswingabovetheDClevelofinput
power source and it may exceed the maximum voltage
rating of the input capacitor and LT1977. All input voltage
transient sequences should be observed at the VIN pin of
the LT1977 to ensure that absolute maximum voltage
ratings are not violated.
Table 3. Surface Mount Solid Tantalum Capacitor ESR
and Ripple Current
E CASE SIZE
AVX TPS
ESR MAX (Ω)
RIPPLE CURRENT (A)
0.1 to 0.3
0.7 to 1.1
D CASE SIZE
AVX TPS
0.1 to 0.3
0.2
0.7 to 1.1
0.5
C CASE SIZE
AVX TPS
The easiest way to suppress input voltage transients is to
addasmallaluminumelectrolyticcapacitorinparallelwith
the low ESR input capacitor. The selected capacitor needs
to have the right amount of ESR to critically damp the
resonant circuit formed by the input lead inductance and
theinputcapacitor. ThetypicalvaluesofESRwillfallinthe
range of 0.5Ω to 2Ω and capacitance will fall in the range
of 5µF to 50µF.
Many engineers have heard that solid tantalum capacitors
are prone to failure if they undergo high surge currents.
This is historically true and type TPS capacitors are
specially tested for surge capability but surge ruggedness
is not a critical issue with the output capacitor. Solid
tantalum capacitors fail during very high turn-on surges
which do not occur at the output of regulators. High
discharge surges, such as when the regulator output is
dead shorted, do not harm the capacitors.
If tantalum capacitors are used, values in the 22µF to
470µF range are generally needed to minimize ESR and
meet ripple current and surge ratings. Care should be
taken to ensure the ripple and surge ratings are not
Unlike the input capacitor RMS, ripple current in the
output capacitor is normally low enough that ripple cur-
rent rating is not an issue. The current waveform is
1977f
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LT1977
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triangular with a typical value of 200mARMS. The formula
V
OUT
10mV/DIV
100µF
to calculate this is:
75mΩ
TANTALUM
Output capacitor ripple current (RMS)
0.29 V
OUT)(
V – V
IN OUT
(
)
=
IP-P
12
V
OUT
IRIPPLE(RMS)
=
10mV/DIV
100µF
L f V
( )( )(
)
IN
CERAMIC
CERAMIC CAPACITORS
V
SW
10V/DIV
Higher value, lower cost ceramic capacitors are now
becoming available. They are generally chosen for their
good high frequency operation, small size and very low
ESR(effectiveseriesresistance).LowESRreducesoutput
ripple voltage but also removes a useful zero in the loop
frequency response, common to tantalum capacitors. To
compensate for this a resistor RC can be placed in series
with the VC compensation capacitor CC (Figure 10). Care
must be taken however since this resistor sets the high
frequency gain of the error amplifier including the gain at
the switching frequency. If the gain of the error amplifier
is high enough at the switching frequency output ripple
voltage (although smaller for a ceramic output capacitor)
may still affect the proper operation of the regulator. A
filter capacitor CF in parallel with the RC/CC network, along
with a small feedforward capacitor CFB, is suggested to
control possible ripple at the VC pin. The LT1977 can be
stabilized using a 100µF ceramic output capacitor and VC
component values of CC = 1500pF, RC = 10k, CF = 330pF
and CFB = 10pF.
1977 F03
V
V
L
= 12V
500ns/DIV
IN
OUT
= 3.3V
I = 1A
Figure 3. LT1977 Ripple Voltage Waveform
Peak-to-peak output ripple voltage is the sum of a triwave
created by peak-to-peak ripple current times ESR and a
square wave created by parasitic inductance (ESL) and
ripple current slew rate. Capacitive reactance is assumed
to be small compared to ESR or ESL.
di
dt
VRIPPLE = I
ESR + ESL
) (
(
P-P)(
)
Example: with VIN = 12V, VOUT = 3.3V, L = 15µH, ESR =
0.08Ω, ESL = 10nH:
3.3 12 – 3.3
)(
(
)
IP-P
di
=
= 0.319A
12 15e − 6 500e3
( )(
12
)(
)
=
= 0.8e6
dt 15e – 6
OUTPUT RIPPLE VOLTAGE
VRIPPLE = (0.319A)(0.08) + (10e – 9)(0.8e6)
= 0.026 + 0.008 = 34mVP-P
Figure 3 shows a typical output ripple voltage waveform
for the LT1977. Ripple voltage is determined by the
impedance of the output capacitor and ripple current
through the inductor. Peak-to-peak ripple current through
the inductor into the output capacitor is:
MAXIMUM OUTPUT LOAD CURRENT
Maximum load current for a buck converter is limited by
the maximum switch current rating (IPK). The minimum
specified current rating for the LT1977 is 1.5A. Unlike
most current mode converters, the LT1977 maximum
switch current limit does not fall off at high duty cycles.
Most current mode converters suffer a drop off of peak
switch current for duty cycles above 50%. This is due to
the effects of slope compensation required to prevent
subharmonic oscillations in current mode converters.
VOUT V – V
(
)
IN
OUT
IP-P
=
V
L f
(
IN)( )( )
For high frequency switchers the ripple current slew rate
is also relevant and can be calculated from:
di
dt
V
IN
L
=
(For detailed analysis, see Application Note 19.)
1977f
12
LT1977
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APPLICATIO S I FOR ATIO
U
IPK22 f L V
The LT1977 is able to maintain peak switch current limit
over the full duty cycle range by using patented circuitry to
cancel the effects of slope compensation on peak switch
current without affecting the frequency compensation it
provides.
( )( )(
)
IN
IOUT(MAX)
=
2 V
OUT)(
V – V
IN OUT
(
)
CHOOSING THE INDUCTOR
For most applications the output inductor will fall in the
range of 5µH to 33µH. Lower values are chosen to reduce
physical size of the inductor. Higher values allow more
output current because they reduce peak current seen by
the LT1977 switch, which has a 1.5A limit. Higher values
also reduce output ripple voltage and reduce core loss.
Maximum load current would be equal to maximum
switch current for an infinitely large inductor, but with
finite inductor size, maximum load current is reduced by
one-half peak-to-peak inductor current. The following
formula assumes continuous mode operation, implying
that the term on the right (IP-P/2) is less than IOUT
.
When choosing an inductor you might have to consider
maximum load current, core and copper losses, allow-
able component height, output voltage ripple, EMI, fault
current in the inductor, saturation and of course cost.
The following procedure is suggested as a way of han-
dling these somewhat complicated and conflicting
requirements.
V
V – V
IN OUT
(
OUT)(
)
IP-P
2
I
OUT(MAX) = IPK
–
= IPK –
2 L f V
( )( )(
)
IN
Discontinuous operation occurs when:
VOUT V – V
(
)
IN
OUT
IOUT(DIS)
≤
2(L)(f)(V )
IN
1. Choose a value in microhenries such that the maximum
load current plus half the ripple current is less than the
minimum peak switch current (IPK). Choosing a small
inductor with lighter loads may result in discontinuous
mode of operation, but the LT1977 is designed to work
well in either mode.
For VOUT = 5V, VIN = 8V and L = 15µH:
5 8 – 5
( )(
)
IOUT(MAX) = 1.5 –
2 15e – 6 500e3 8
( )( )( )
= 1.5 – 0.125 = 1.375A
Assume that the average inductor current is equal to
load current and decide whether or not the inductor
must withstand continuous fault conditions. If maxi-
mum load current is 0.5A, for instance, a 0.5A inductor
may not survive a continuous 2A overload condition.
Note that there is less load current available at the higher
inputvoltagebecauseinductorripplecurrentincreases.At
VIN = 15V, duty cycle is 33% and for the same set of
conditions:
For applications with a duty cycle above 50%, the
inductor value should be chosen to obtain an inductor
ripple current of less than 40% of the peak switch
current.
5 15 – 5
( )(
)
I
OUT(MAX) = 1.5 –
2 15e – 6 500e3 15
)( )( )
(
= 1.5 – 0.22 = 1.28A
2. Calculate peak inductor current at full load current to
ensure that the inductor will not saturate. Peak current
canbesignificantlyhigherthanoutputcurrent,especially
with smaller inductors and lighter loads, so don’t omit
thisstep.Powderedironcoresareforgivingbecausethey
saturate softly, whereas ferrite cores saturate abruptly.
Other core materials fall somewhere in between. The
following formula assumes continuous mode of opera-
tion, but it errs only slightly on the high side for discon-
To calculate actual peak switch current in continuous
mode with a given set of conditions, use:
VOUT V – VOUT
(
IN
)
ISW(PK) = IOUT
+
2 L f V
( )( )( IN
)
If a small inductor is chosen which results in discontinous
mode operation over the entire load range, the maximum
load current is equal to:
tinuous mode, so it can be used for all conditions.
1977f
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LT1977
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APPLICATIO S I FOR ATIO
Table 4. Inductor Selection Criteria
VENDOR/
PART NO.
Short-Circuit Considerations
VALUE
H)
I
DCR
(Ohms)
HEIGHT
(mm)
DC(MAX)
The LT1977 is a current mode controller. It uses the VC
node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
this peak current is reached. The internal clamp on the VC
node, nominally 2.2V, then acts as an output switch peak
current limit. This action becomes the switch current limit
specification. The maximum available output power is
thendeterminedbythemaximumspecifiedswitchcurrent
limit.
(µ
(Amps)
Coiltronics
UP1B-100
10
22
22
33
15
1.9
1.2
2.0
1.7
1.5
0.111
0.254
0.062
0.092
0.175
5.0
5.0
6.0
6.0
5.0
UP1B-220
UP2B-220
UP2B-330
UP1B-150
Coilcraft
D01813P-153HC
D01813P-103HC
D53316P-223
D53316P-333
LP025060B-682
Sumida
15
10
22
33
1.5
1.9
1.6
1.4
1.3
0.170
0.111
0.207
0.334
0.165
5.0
5.0
A potential control problem could occur under short-
circuit conditions. If the power supply output is short
circuited, the feedback amplifier responds to the low
output voltage by raising the control voltage, VC, to its
peak current limit value. Ideally, the output switch would
be turned on, and then turned off as its current exceeded
thevalueindicatedbyVC.However,thereisfiniteresponse
time involved in both the current comparator and turn-off
of the output switch. These result in a typical minimum on
time of 300ns (see Typical Performance Characteristics).
When combined with the large ratio of VIN to (VF + I • R),
the diode forward voltage plus inductor I • R voltage drop,
the potential exists for a loss of control. Expressed math-
ematically the requirement to maintain control is:
5.1
5.1
6.8
1.65
CDRH4D28-4R7
CDRH5D28-100
CDRH6D28-150
CDRH6D28-180
CDRH6D28-220
CDRH6D38-220
4.7
10
15
18
22
22
1.32
1.30
1.40
1.32
1.20
1.30
0.072
0.065
0.084
0.095
0.128
0.096
3.0
3.0
3.0
3.0
3.0
4.0
VOUT V – V
(
)
IN
OUT
IPEAK = IOUT
+
2 f L V
( )( )(
V +I•R
)
IN
F
f • tON
≤
V
IN
VIN = maximum input voltage
f = switching frequency, 500kHz
where:
f = switching frequency
tON = switch on time
3. Decide if the design can tolerate an “open” core geom-
etry like a rod or barrel, which have high magnetic field
radiation, or whether it needs a closed core like a toroid
to prevent EMI problems. This is a tough decision
because the rods or barrels are temptingly cheap and
small and there are no helpful guidelines to calculate
when the magnetic field radiation will be a problem.
VF = diode forward voltage
VIN = Input voltage
I • R = inductor I • R voltage drop
If this condition is not observed, the current will not be
limited at IPK but will cycle-by-cycle ratchet up to some
higher value. Using the nominal LT1977 clock frequency
of 500kHz, a VIN of 12V and a (VF + I • R) of say 0.7V, the
maximum tON to maintain control would be approximately
116ns, an unacceptably short time.
4. After making an initial choice, consider the secondary
things like output voltage ripple, second sourcing, etc.
Use the experts in the Linear Technology’s applications
department if you feel uncertain about the final choice.
They have experience with a wide range of inductor
types and can tell you about the latest developments in
low profile, surface mounting, etc.
The solution to this dilemma is to slow down the oscillator
to allow the current in the inductor to drop to a sufficiently
1977f
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APPLICATIO S I FOR ATIO
U
low value such that the current doesn’t continue to ratchet
higher. When the FB pin voltage is abnormally low thereby
indicating some sort of short-circuit condition, the oscil-
lator frequency will be reduced. Oscillator frequency is
reduced by a factor of 4 when the FB pin voltage is below
0.4V and increases linearly to its typical value of 500kHz at
aFBvoltageof0.95V(seeTypicalPerformanceCharacter-
istics). In addition, if the current in the switch exceeds 1.5
• IPK current demanded by the VC pin, the LT1977 will skip
the next on cycle effectively reducing the oscillator fre-
quency by a factor of 2. These oscillator frequency reduc-
tions during short-circuit conditions allow the LT1977 to
maintain current control.
C
= 1000pF
CSS
V
OUT
1V/DIV
C
= 0.01µF
CSS
C
= 0.1µF
CSS
1977 F04
V
V
= 12V
= 3.3V
1ms/DIV
IN
OUT
Figure 4. VOUT dV/dt
capacitor charged to the proper voltage while minimizing
the input quiescent current. During Burst Mode opera-
tion, the LT1977 delivers short bursts of current to the
output capacitor followed by sleep periods where the
output power is delivered to the load by the output
capacitor. In addition, VIN and BIAS quiescent currents
are reduced to typically 45µA and 125µA respectively
during the sleep time. As the load current decreases
towards a no load condition, the percentage of time that
the LT1977 operates in sleep mode increases and the
average input current is greatly reduced resulting in
higher efficiency.
SOFT-START
For applications where [VIN/(VOUT + VF)] ratios > 10 or
large input surge currents can’t be tolerated, the LT1977
soft-start feature should be used to control the output
capacitor charge rate during start-up, or during recovery
from an output short circuit thereby adding additional
control over peak inductor current. The soft-start function
limits the switch current via the VC pin to maintain a
constant voltage ramprate(dV/dt)atthe outputcapacitor.
A capacitor (C1 in Figure 2) from the CSS pin to the
regulated output voltage determines the output voltage
ramp rate. When the current through the CSS capacitor The minimum average input current depends on the VIN to
exceeds the CSS threshold (ICSS), the voltage ramp of the VOUT ratio, VC frequency compensation, feedback divider
output capacitor is limited by reducing the VC pin voltage. network and Schottky diode leakage. It can be approxi-
The CSS threshold is proportional to the FB voltage (see mated by the following equation:
Typical Performance Characteristics) and is defeated for
I
BIASS +IFB +IS
⎛ VOUT
⎞
(
)
FB voltages greater than 0.9V (typical). The output dV/dt
can be approximated by:
IIN(AVG) ≅ IVINS +ISHDN +
⎜
⎟
⎝ V
⎠
η
( )
IN
where:
dV ICSS
=
IVINS = input pin current in sleep mode
VOUT = output voltage
dt CSS
but actual values will vary due to start-up load conditions,
compensation values and output capacitor selection.
VIN = input voltage
IBIASS = BIAS pin current in sleep mode
IFB = feedback network current
IS = catch diode reverse leakage at VOUT
Burst Mode OPERATION
T
oenhanceefficiencyatlightloads,theLT1977automati-
cally switches to Burst Mode operation (see Typical
Performance Characteristics) which keeps the output
η = low current efficiency (non Burst Mode operation)
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Example: For VOUT = 3.3V, VIN = 12V
VOUT
50mV/DIV
125µA + 12.5µA + 0.5µA
3.3
12
(
)
⎛
⎜
⎝
⎞
⎟
⎠
I
= 45µA + 5µA +
IN(AVG)
0.8
(
)
= 45µA + 5µA + 44µA = 99µA
VSHDN
2V/DIV
150
V
= 3.3V
= 25°C
OUT
T
A
125
100
75
50
25
0
ISW
500mA/DIV
VIN = 12V
VOUT = 3.3V
IQ = 15µA
TIME (50ms/DIV)
1977 G16
Figure 6. Burst Mode with Shutdown Pin
To maximize high and low load current efficiency a fast
switching diode with low forward drop and low reverse
leakage should be used. Low reverse leakage is critical to
maximize low current efficiency since its value over tem-
perature can potentially exceed the magnitude of the
LT1977 supply current. Low forward drop is critical for
high current efficiency since the loss is proportional to
forward drop.
0
10
30
40
50
60
20
INPUT VOLTAGE (V)
1977 F05
Figure 5. IQ vs VIN
During the sleep portion of the Burst Mode cycle, the VC
pin voltage is held just below the level needed for normal
operation to improve transient response. See the Typical
Performance Characteristics section for burst and tran-
sient response waveforms.
These requirements result in the use of a Schottky type
diode. DC switching losses are minimized due to its low
forward voltage drop and AC behavior is benign due to its
lackofasignificantreverserecoverytime.Schottkydiodes
are generally available with reverse voltage ratings of 60V
and even 100V and are price competitive with other types.
Ifanoloadconditioncanbeanticipated,thesupplycurrent
can be further reduced by cycling the SHDN pin at a rate
higher than the natural no load burst frequency. Figure 6
shows Burst Mode operation with the SHDN pin. VOUT
burstrippleismaintainedwhiletheaveragesupplycurrent
drops to 15µA. The PG pin will be active low during the
“on” portion of the SHDN waveform due to the CT capaci-
tor discharge when SHDN is taken low. See the Power
Good section for further information.
The effect of reverse leakage and forward drop on effi-
ciency for various Schottky diodes is shown in Table 5. As
can be seen these are conflicting parameters and the user
Table 5. Catch Diode Selection Criteria
I at 125°C EFFICIENCY
Q
V
LEAKAGE
= 3.3V
=12V
= 3.3
V
=12V
IN
IN
V
OUT
V AT 1A
F
V
V = 3.3V
OUT
OUT
CATCH DIODE
DIODE
25°C
125°C
59µA
25°C
0.72V
0.48V
I = 0A
I = 1A
L
L
The catch diode carries load current during the SW off
time. The average diode current is therefore dependent on
theswitchdutycycle. Athighinputtooutputvoltageratios
the diode conducts most of the time. As the ratio ap-
proaches unity the diode conducts only a small fraction of
the time. The most stressful condition for the diode is
whentheoutputisshortcircuited.Underthisconditionthe
diode must safely handle IPEAK at maximum duty cycle.
IR 10BQ100
0.0µA
125µA
215µA
76.1%
80.4%
Diodes Inc.
B260SMA
0.1µA 242µA
0.2µA 440µA
1µA 1.81mA
0.5µA 225µA
Diodes Inc.
B360SMB
0.45V
0.42V
0.59V
270µA
821µA
206µA
80.8%
81.4%
78.8%
IR
MBRS360TR
IR 30BQ100
1977f
16
LT1977
W U U
APPLICATIO S I FOR ATIO
mustweightheimportanceofeachspecificationinchoos-
ing the best diode for the application.
U
OPTIONAL
The use of so-called “ultrafast” recovery diodes is gener-
ally not recommended. When operating in continuous
mode, the reverse recovery time exhibited by “ultrafast”
diodes will result in a slingshot type effect. The power
internalswitchwillrampupVIN currentintothediodeinan
attempt to get it to recover. Then, when the diode has
finallyturnedoff,sometensofnanosecondslater,theVSW
node voltage ramps up at an extremely high dV/dt, per-
haps 5V to even 10V/ns! With real world lead inductances
the VSW node can easily overshoot the VIN rail. This can
result in poor RFI behavior and, if the overshoot is severe
enough, damage the IC itself.
V
V
BOOST
SW
V
OUT
IN
IN
LT1977
GND
V
– V = V
SW OUT
= V + V
IN OUT
BOOST
BOOST(MAX)
V
(7a)
V
V
BOOST
SW
IN
IN
LT1977
V
GND
OUT
V
V
– V = V
SW IN
BOOST
= 2V
BOOST(MAX)
IN
BOOST PIN
(7b)
For most applications the boost components are a 0.1µF
capacitor and a MMSD914 diode. The anode is typically
connected to the regulated output voltage to generate a
voltage approximately VOUT above VIN to drive the output
stage (Figure 7a). However, the output stage discharges
the boost capacitor during the on time of the switch. The
output driver requires at least 2.5V of headroom through-
out this period to keep the switch fully saturated. If the
output voltage is less than 3.3V it is recommended that an
alternate boost supply is used. The boost diode can be
connected to the input (Figure 7b) but care must be taken
to prevent the boost voltage (VBOOST = VIN • 2) from
exceeding the BOOST pin absolute maximum rating. The
additional voltage across the switch driver also increases
power loss and reduces efficiency. If available, an inde-
pendent supply can be used to generate the required
BOOST voltage (Figure 7c). Tying BOOST to VIN or an
independent supply may reduce efficiency but it will re-
duce the minimum VIN required to start-up with light
loads. If the generated BOOST voltage dissipates too
much power at maximum load, the BOOST voltage the
LT1977 sees can be reduced by placing a Zener diode in
series with the BOOST diode (Figure 7a option).
V
V
BOOST
V
V
IN
IN
DC
LT1977
GND SW
OUT
D
SS
1977 F07
V
– V = V
SW DC
= V + V
DC IN
BOOST
BOOST(MAX)
V
(7c)
Figure 7. BOOST Pin Configurations
value is derived from worst-case conditions of 1800ns on
time, 40mA boost current and 0.7V discharge ripple. The
boost capacitor value could be reduced under less de-
mandingconditionsbutthiswillnotimprovecircuitopera-
tion or efficiency. Under low input voltage and low load
conditions a higher value capacitor will reduce discharge
ripple and improve start-up operation.
SHUTDOWN FUNCTION AND UNDERVOLTAGE
LOCKOUT
The SHDN pin on the LT1977 controls the operation of the
IC. When the voltage on the SHDN pin is below the 1.2V
shutdown threshold the LT1977 is placed in a “zero”
supply current state. Driving the SHDN pin above the
shutdown threshold enables normal operation. The SHDN
A 0.1µF boost capacitor is recommended for most appli-
cations. Almost any type of film or ceramic capacitor is
suitablebuttheESRshouldbe<1Ωtoensureitcanbefully
recharged during the off time of the switch. The capacitor
pin has an internal sink current of 3µA.
1977f
17
LT1977
W U U
U
APPLICATIO S I FOR ATIO
In addition to the shutdown feature, the LT1977 has an
undervoltage lockout function. When the input voltage is
below 2.4V, switching will be disabled. The undervoltage
lockout threshold doesn’t have any hysteresis and is
mainly used to insure that all internal voltages are at the
correct level before switching is enabled. If an undervolt-
age lockout function with hysteresis is needed to limit
input current at low VIN to VOUT ratios refer to Figure 8 and
the following:
LT1977
V
IN
4
+
–
V
IN
COMP
2.4V
1.3V
ENABLE
R1
R2
R3
SHDN
V
OUT
15
+
–
SHDN
COMP
3µA
V
V
⎛
⎜
⎞
SHDN
V
UVLO = R1
+
SHDN +ISHDN + V
⎟
SHDN
1977 F08
⎝ R3
R2
⎠
Figure 8. Undervoltage Lockout
VOUT R1
( )
VHYST
=
self-oscillating frequency (575kHz), not the typical oper-
ating frequency of 500kHz. Caution should be used when
R3
R1shouldbechosentominimizequiescentcurrentduring synchronizing above 575kHz because at higher sync
frequencies the amplitude of the internal slope compen-
sation used to prevent subharmonic switching is re-
duced. Thistypeofsubharmonicswitchingonlyoccursat
input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insufficient slope compensa-
tion. Application Note 19 has more details on the theory
of slope compensation.
normal operation by the following equation:
V – 2V
IN
R1=
1.5 I
(
)
(
)
SHDN(MAX)
Example:
12 – 2
R1=
= 1.3MΩ
1.5 5µA
(
)
5 1.3MΩ
(
)
If the FB pin voltage is below 0.9V (power-up or output
short-circuit conditions) the sync function is disabled.
This allows the frequency foldback to operate to avoid any
hazardous conditions for the SW pin.
R3 =
= 6.5MΩ (Nearest 1% 6.49MΩ)
1
1.3
R2 =
7 – 1.3
1.3MΩ
1.3
6.49MΩ
– 1µA –
If no synchronization is required this pin should be con-
nected to ground.
= 408k (Nearest 1% 412k)
See the Typical Performance Characteristics section for
graphs of SHDN and VIN currents versus input voltage.
POWER GOOD
The LT1977 contains a power good block which consists
ofacomparator, delaytimerandactivelowflagthatallows
the user to generate a delayed signal after the power good
threshold is exceeded.
SYNCHRONIZING
Oscillatorsynchronizationtoanexternalinputisachieved
by connecting a TTL logic-compatible square wave with a
duty cycle between 30% and 70% to the LT1977 SYNC
pin. The synchronizing range is equal to initial operating
frequency up to 700kHz. This means that minimum
practical sync frequency is equal to the worst-case high
Referring to Figure 2, the PGFB pin is the positive input to
a comparator whose negative input is set at VPGFB. When
PGFB is taken above VPGFB, current (ICSS) is sourced into
the CT pin starting the delay period. When the voltage on
1977f
18
LT1977
W U U
APPLICATIO S I FOR ATIO
U
the PGFB pin drops below VPGFB the CT pin is rapidly
discharged resetting the delay period. The PGFB voltage is
typically generated by a resistive divider from the regu-
lated output or input supply.
When the PGFB pin rises above VPGFB current is sourced
(ICT) from the CT pin into the external capacitor. When the
voltageontheexternalcapacitorreachesaninternalclamp
(VCT), the PG pin becomes a high impedance node. The
resultant PG delay time is given by t = CCT • (VCT)/(ICT). If
thevoltageonthePGFBpindropsbelowitsVPGFB, CCT will
be discharged rapidly and PG will be active low with a
200µA sink capability. If the SHDN pin is taken below its
threshold during normal operation, the CT pin will be
dischargedandPGinactive,resultinginanonPowerGood
cycle when SHDN is taken above its threshold. Figure 9
shows the power good operation with PGFB connected to
FB and the capacitance on CT = 0.1µF. Figure 10 shows
several different configurations for the LT1977 Power
Good circuitry.
The capacitor on the CT pin determines the amount of
delay time between the PGFB pin exceeding its threshold
(VPGFB) and the PG pin set to a high impedance state.
VOUT
500mV/DIV
PG
100k TO VIN
VCT
500mV/DIV
VSHDN
2V/DIV
LAYOUT CONSIDERATIONS
TIME (10ms/DIV)
1977 F09
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
Figure 9. Power Good
PG at 80% V
with 100ms Delay
PG at V > 4V with 100ms Delay
IN
OUT
V
IN
V
IN
200k
200k
PG
LT1977
PG
LT1977
V
= 3.3V
OUT
511k
200k
C
153k
12k
OUT
PGFB
PGFB
V
= 3.3V
OUT
165k
100k
C
OUT
FB
FB
100k
C
C
T
T
0.27µF
0.27µF
V
Disconnect at 80% V
with 100ms Delay
V Disconnect 3.3V Logic Signal
OUT
OUT
OUT
with 100µs Delay
V
V
IN
PG
LT1977
PGFB
IN
PG
LT1977
200k
200k
V
= 3.3V
V
= 12V
OUT
OUT
153k
12k
C
C
OUT
OUT
PGFB
866k
100k
FB
FB
100k
C
C
T
T
0.27µF
270pF
1977 F10
Figure 10. Power Good Circuits
1977f
19
LT1977
W U U
U
APPLICATIO S I FOR ATIO
electrical, thermal and noise performance. For maximum
efficiency switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted the high speed switching current path, shown
in Figure 11, must be kept as short as possible. This is
implemented in the suggested layout of Figure 12. Short-
ening this path will also reduce the parasitic trace induc-
tance of approximately 25nH/inch. At switch off, this
parasitic inductance produces a flyback spike across the
LT1977 switch. When operating at higher currents and
input voltages, with poor layout, this spike can generate
voltages across the LT1977 that may exceed its absolute
maximum rating. A ground plane should always be used
under the switcher circuitry to prevent interplane coupling
and overall noise.
The VC and FB components should be kept as far away as
possible from the switch and boost nodes. The LT1977
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic like oscillation.
Board layout also has a significant effect on thermal
resistance. Pin 8 and the exposed die pad, Pin 17, are a
continuous copper plate that runs under the LT1977 die.
This is the best thermal path for heat out of the package.
Reducing the thermal resistance from Pin 8 and exposed
pad onto the board will reduce die temperature and in-
creasethepowercapabilityoftheLT1977.Thisisachieved
by providing as much copper area as possible around the
exposed pad. Adding multiple solder filled feedthroughs
under and around this pad to an internal ground plane will
also help. Similar treatment to the catch diode and coil
terminations will reduce any additional heating effects.
LT1977
L1
V
OUT
V
IN
4
2
SW
V
IN
+
HIGH
C2
FREQUENCY
CIRCULATION
PATH
D1
C1 LOAD
THERMAL CALCULATIONS
Power dissipation in the LT1977 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current,andinputquiescentcurrent.Thefollowingformu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
1977 F11
Figure 11. High Speed Switching Path
C2
D2
CONNECT PIN 8 GND TO THE
PIN 17 EXPOSED PAD GND
V
OUT
L1
C1
PLACE VIA's UNDER EXPOSED
PAD TO A BOTTOM PLANE TO
ENHANCE THERMAL
Switch loss:
KELVIN SENSE
FEEDBACK
TRACE AND
KEEP SEPARATE
FROM BIAS TRACE
D1
CONDUCTIVITY
2
RSW OUT
I
V
OUT
(
) (
)
MINIMIZE
D1-C3
LOOP
PSW
=
+ tEFF 1/2 I
V
f
(
)
(
OUT)( IN)( )
GND
1
2
3
4
5
6
7
8
NC
SW
NC
PGOOD 16
SHDN 15
V
IN
R3
LT1977
SYNC 14
PGFB 13
FB 12
Boost current loss:
C3
V
R1
R2
C2
IN
2
V
IN
NC
V
OUT
I
/32
(
=
)
(
)
OUT
P
BOOST
TCAP
GND
V
11
C
BOOST
V
IN
BIAS 10
C4
C5
C
SS
9
Quiescent current loss:
PQ = VIN (0.0015) + VOUT (0.003)
RSW = switch resistance (≈0.3 when hot )
GND
tEFF = effective switch current/voltage overlap time
(tr + tf + tIR + tIF)
1977 F12
Figure 12. Suggested Layout
1977f
20
LT1977
W U U
APPLICATIO S I FOR ATIO
U
tr = (VIN/1.1)ns
For example, while the combination of VIN = 40V, VOUT =
5V at 1A and fOSC = 500kHz may be easily achievable, si-
multaneously raising VIN to 60V and fOSC to 700kHz is not
possible. Nevertheless, input voltage transients up to 60V
can usually be accommodated, assuming the resulting
increase in internal dissipation is of insufficient time dura-
tion to raise die temperature significantly.
tf = (VIN/1.8)ns
tIR = tIF = (IOUT/0.05)ns
f = switch frequency
Example: with VIN = 12V, VOUT = 5V and IOUT = 1A:
0.3 1 2 5
A second consideration is control. A potential limitation
occurs with a high step-down ratio of VIN to VOUT, as this
requires a correspondingly narrow minimum switch on
time. An approximate expression for this (assuming con-
tinuous mode operation) is given as follows:
(
)( ) ( )
PSW
=
+ 57.6e−9 1/2 1 12 500e3
( )( )( )(
)
(
)
12
0.04 + TBD = 0.125 + 0.172 = 0.297W
2
5
( )
1/32
(
)
P
=
= 0.002W
BOOST
12
t
ON(MIN) = VOUT + VF/VIN(fOSC
where:
VIN = input voltage
VOUT = output voltage
)
P = 12 0.0015 + 5 0.003 = 0.033W
(
)
(
)
Q
Total power dissipation is:
PTOT = 0.297 + 0.065 + 0.033 = 0.40W
VF = Schottky diode forward drop
fOSC = switching frequency
Thermal resistance for the LT1977 package is influenced
by the presence of internal or backside planes. With a full
plane under the FE16 package, thermal resistance will be
about 45°C/W. No plane will increase resistance to about
150°C/W. To calculate die temperature, use the proper
thermal resistance number for the desired package and
add in worst-case ambient temperature:
A potential control problem arises if the LT1977 is called
upon to produce an on time shorter than it is able to
produce. Feedback loop action will lower then reduce the
VC control voltage to the point where some sort of cycle-
skipping or Burst Mode behavior is exhibited.
TJ = TA + QJA (PTOT
)
In summary:
With the FE16 package (QJA = 45°C/W) at an ambient
temperature of 70°C:
1. Be aware that the simultaneous requirements of high
VIN, high IOUT and high fOSC may not be achievable in
practice due to internal dissipation. The Thermal Con-
siderations section offers a basis to estimate internal
power.Inquestionablecasesaprototypesupplyshould
be built and exercised to verify acceptable operation.
TJ = 70 + 45(0.40) = 98°C
Input Voltage vs Operating Frequency Considerations
TheabsolutemaximuminputsupplyvoltagefortheLT1977
is specified at 60V. This is based solely on internal semi-
conductor junction breakdown effects. Due to internal
power dissipation the actual maximum VIN achievable in a
particular application may be less than this.
2.ThesimultaneousrequirementsofhighVIN,lowVOUT and
high fOSC can result in an unacceptably short minimum
switch on time. Cycle skipping and/or Burst Mode be-
havior will result causing an increase in output voltage
ripple while maintaining the correct output voltage.
A detailed theoretical basis for estimating internal power
loss is given in the section Thermal Considerations. Note
that AC switching loss is proportional to both operating
frequency and output current. The majority of AC switch-
ing loss is also proportional to the square of input voltage.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
responsethefollowingshouldberemembered—theworse
1977f
21
LT1977
W U U
U
APPLICATIO S I FOR ATIO
the board layout, the more difficult the circuit will be to
stabilize. This is true of almost all high frequency analog
circuits. Read the Layout Considerations section first.
Common layout errors that appear as stability problems
aredistantplacementofinputdecouplingcapacitorand/or
catch diode and connecting the VC compensation to a
ground track carrying significant switch current. In addi-
tionthetheoreticalanalysisconsidersonlyfirstordernon-
idealcomponentbehavior.Forthesereasons,itisimportant
that a final stability check is made with production layout
and components.
transient response is required, a zero can be added to the
loop using a resistor (RC) in series with a compensation
capacitor(s). As the value of RC is increased, transient re-
sponsewillgenerallyimprovebuttwoeffectslimititsvalue.
First, the combination of output capacitor ESR and a large
RC may stop loop gain rolling off altogether. Second, if the
loop gain is not rolled off sufficiently at the switching fre-
quencyoutputripplewillperturbtheVC pinenoughtocause
unstable duty cycle switching similar to subharmonic
oscillation. This may not be apparent at the output. Small-
signal analysis will not show this since a continuous time
system is assumed. If needed, an additional capacitor (CF)
canbeaddedtoformapoleatbelowtheswitchingfrequency
(if RC = 26k, CC = 1500pF, CF = 330pF).
The LT1977 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 12.
The LT1977 can be considered as two gm blocks, the error
amplifier and the power stage.
When checking loop stability the circuit should be oper-
ated over the application’s full voltage, current and tem-
perature range. Any transient loads should be applied and
the output voltage monitored for a well-damped behavior.
Figure13showstheoverallloopresponsewitha330pFVC
capacitor and a typical 100µF tantalum output capacitor.
The response is set by the following terms:
LT1977
Error amplifier: DC gain is set by gm and RO:
CURRENT MODE
SW
OUTPUT
POWER STAGE
2
Ω
Ω
g
= 3
m
EA Gain = 650µ • 1.5M = 975
C
R1
12
R2
FB
Ω
g
= 650µ
m
FB
+
–
The pole set by CF and RL:
V
C
ERROR
AMP
11
ESR
EA Pole = 1/(2π • 1.5M • 330pF) = 322Hz
Unity gain frequency is set by CF and gm:
R
1.5M
C
1.25V
C
C
OUT
F
C
C
Ω
EA Unity Gain Frequency = 650µ /(2π • 330pF)
1977 F13
= 313kHz
Powerstage: DC gain is set by gm and RL (assume 10Ω):
PS DC Gain = 3 • 10 = 30
Figure 13. Model for Loop Response
100
50
0
100
V
C
F
= 3.3V
OUT
OUT
= 100µF, 0.1Ω
C = 330pF
Pole set by COUT and RL:
R /C = NC
C
C
135
90
45
0
I
= 350mA
LOAD
PS Pole = 1/(2π • 100µF • 10) = 159Hz
Unity gain set by COUT and gm:
PS Unity Gain Freq = 3/(2π • 100µF) = 4.7kHz.
Tantalum output capacitor zero is set by COUT and COUT
ESR
–50
10
100
1k
10k
100k
1M
Output Capacitor Zero = 1/(2π • 100µF • 0.1) = 159kHz
FREQUENCY (Hz)
1977 F14
The zero produced by the ESR of the tantalum output ca-
pacitor is very useful in maintaining stability. If better
Figure 14. Overall Loop Response
1977f
22
LT1977
U
PACKAGE DESCRIPTIO
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BC
4.90 – 5.10*
(.193 – .201)
3.58
(.141)
3.58
(.141)
16 1514 13 12 1110
9
6.60 ±0.10
4.50 ±0.10
2.94
(.116)
6.40
(.252)
BSC
SEE NOTE 4
2.94
(.116)
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.0433)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE16 (BC) TSSOP 0204
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
1977f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LT1977
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
V : 7.3V to 45V/64V, V
LT1074/LT1074HV
4.4A (I ), 100kHz, High Efficiency Step-Down DC/DC Converters
= 2.21V, I = 8.5mA,
Q
OUT
IN
OUT(MIN)
< 10µA, DD5/7, TO220-5/7
I
SD
LT1076/LT1076HV
LT1676
1.6A (I ), 100kHz, High Efficiency Step-Down DC/DC Converters
V : 7.3V to 45V/64V, V
= 2.21V, I = 8.5mA,
Q
OUT
IN
OUT(MIN)
I
< 10µA, DD5/7, TO220-5/7
SD
60V, 440mA (I ), 100kHz, High Efficiency Step-Down DC/DC
V : 7.4V to 60V, V
= 1.24V, I = 3.2mA,
OUT
IN
OUT(MIN) Q
Converter
I
< 2.5µA, S8
SD
LT1765
25V, 3A (I ), 1.25MHz, High Efficiency Step-Down DC/DC
Converter
V : 3V to 25V, V
SO-8, TSSOP16/E
= 1.20V, I = 1mA, I < 15µA,
OUT(MIN) Q SD
OUT
IN
LT1766
60V, 1.2A (I ), 200kHz, High Efficiency Step-Down DC/DC
Converter
V : 5.5V to 60V, V
= 1.20V, I = 2.5mA,
OUT(MIN) Q
OUT
IN
I
< 25µA, TSSOP16E
SD
LT1767
25V, 1.5A (I ), 1.25MHz, High Efficiency Step-Down DC/DC
Converter
V : 3V to 25V, V
MS8E
= 1.20V, I = 1mA, I < 6µA,
OUT(MIN) Q SD
OUT
IN
LT1776
40V, 550mA (I ), 200kHz, High Efficiency Step-Down DC/DC
Converter
V : 7.4V to 40V, V
= 1.24V, I = 3.2mA,
OUT(MIN) Q
OUT
IN
I
< 30µA, N8, S8
SD
LTC®1875
LT1940
1.5A (I ), 550kHz, Synchronous Step-Down DC/DC Converter
V : 2.7V to 6V, V
TSSOP16
= 0.8V, I = 15µA, I < 1µA,
Q SD
OUT
IN
OUT(MIN)
OUT(MIN)
Dual 1.2A (I ), 1.1MHz, High Efficiency Step-Down DC/DC
V : 3V to 25V, V
IN
= 1.2V, I = 3.8mA, MS10
Q
OUT
Converter
LT1956
60V, 1.2A (I ), 500kHz, High Efficiency Step-Down DC/DC
Converter
V : 5.5V to 60V, V
= 1.20V, I = 2.5mA,
OUT(MIN) Q
OUT
IN
I
< 25µA, TSSOP16E
SD
LT1976
60V, 1.5A (I ), 200kHz High Efficiency Step-Down DC/DC
Converter
V : 3.3V to 60V, I = 100µA, I < 1µA, TSSOP16E
IN Q SD
OUT
LT3010
80V, 50mA, Low Noise Linear Regulator
V : 1.5V to 80V, V
MS8E
= 1.28V, I = 30µA, I < 1µA,
OUT(MIN) Q SD
IN
LTC3407
LTC3412
LTC3414
LT3430
Dual 600mA (I ), 1.5MHz, High Efficiency Step-Down DC/DC
Converter
V : 2.5V to 5.5V, V
= 0.6V, I = 40µA, MS10
Q
OUT
IN
OUT(MIN)
OUT(MIN)
2.5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
V : 2.5V to 5.5V, V
= 0.8V, I = 60µA, I < 1µA,
Q SD
OUT
IN
TSSOP16E
4A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
V : 2.25V to 5.5V, V
= 0.8V, I = 64µA, I < 1µA,
OUT(MIN) Q SD
OUT
IN
TSSOP20E
60V, 2.5A (I ), 200kHz, High Efficiency Step-Down DC/DC
V : 5.5V to 60V, V
IN
= 1.20V, I = 2.5mA,
Q
OUT
OUT(MIN)
Converter
I
< 30µA, TSSOP16E
SD
LT3431
60V, 2.5A (I ), 500kHz, High Efficiency Step-Down DC/DC
Converter
V : 5.5V to 60V, V
= 1.20V, I = 2.5mA,
Q
OUT
IN
OUT(MIN)
I
< 30µA, TSSOP16E
SD
LT3433
60V, 400mA (I ), 200kHz, Buck-Boost DC/DC Converter
V : 5V to 60V, V : 3.3V to 20V, I = 100µA, TSSOP16E
IN OUT Q
OUT
LTC3727/LTC3727-1 36V, 500kHz, High Efficiency Step-Down DC/DC Controllers
V : 4V to 36V, V
QFN-32, SSOP-28
= 0.8V, I = 670µA, I < 20µA,
OUT(MIN) Q SD
IN
1977f
LT/TP 0604 1K PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
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