3572 [Linear]
Dual Full-Bridge Piezo Driver with 900mA Boost Converter; 双路全桥式压电驱动器具有900mA升压转换器
| 型号： | 3572 |
| 厂家： | 
Linear |
| 描述： | Dual Full-Bridge Piezo Driver with 900mA Boost Converter |
| 文件： | 总12页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3572
Dual Full-Bridge Piezo Driver
with 900mA Boost Converter
FEATURES
DESCRIPTION
The LT®3572 is a highly integrated dual Piezo motor driver
capable of driving two Piezo motors at up to 40V from a
5V supply. Each Piezo driver can be independently turned
on or off along with the boost converter.
■
2.7V to 10V Input Voltage Range
■
900mA Boost Converter
■
Dual Full-Bridge Piezo Drivers
■
Programmable Switching Frequency from
500kHz to 2.25MHz
Theboostregulatorhasasoft-startcapabilitythatlimitsthe
inrush current at start-up. The boost regulator switching
frequencyissetbyanexternalresistororthefrequencycan
besynchronizedbyanexternalclock.APGOODpinindicates
when the output of the boost converter is in regulation and
the Piezo drivers are allowed to start switching.
■
Synchronizable Up to 2.5MHz
■
Soft-Start
■
Separate Enable for Each Piezo Driver and Boost
Converter
■
Available in a 4mm × 4mm 20-Pin QFN Package
The LT3572 is available in a (4mm × 4mm) 20-pin QFN
APPLICATIONS
package.
■
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Piezo Motor Drive
TYPICAL APPLICATION
Dual Piezo Driver
10μH
V
OUT
V
IN
Response Driving Piezo Motor at 70kHz
30V
3V TO 5V
50mA
15pF 576k
24.3k
V
SW
V
OUT
IN
SHDN
10μF
100k
SHDNA
SHDNB
PWMA
PWMB
SYNC
FB
V
OUTA
20V/DIV
OUTA
OUTA
LT3572
V
OUTA
4.7μF
3572 TA01a
20V/DIV
PGOOD
RT
SS
OUTB
OUTB
PWMA
2V/DIV
42.2k
GND
3572 TA01b
10nF
2μs/DIV
3572fa
1
LT3572
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
V
Voltage.............................................................40V
TOP VIEW
OUT
OUTA, OUTA, OUTB, OUTB Voltage...........................40V
SW Voltage ...............................................................42V
RT, SS, SYNC..............................................................2V
FB ...............................................................................3V
All Other Pins............................................................10V
Maximum Junction Temperature........................... 125°C
Operating Temperature Range (Note 2).... –40°C to 85°C
Storage Temperature Range................... –65°C to 125°C
20 19 18 17 16
PGOOD
SS
SW
1
2
3
4
5
15
14
13
12
11
V
IN
FB
SYNC
RT
21
8
SHDNB
SHDNA
GND
6
7
9 10
UF PACKAGE
20-LEAD (4mm s 4mm) PLASTIC QFN
= 125°C, θ = 37°C/W
T
JMAX
JA
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
20-Lead (4mm × 4mm) Plastic DFN
TEMPERATURE RANGE
–40°C to 85°C
LT3572EUF#PBF
LT3572EUF#TRPBF
3572
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDNA= VSHDNB = VSHDN = 5V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
2.5
3.4
0
MAX
2.7
4
UNITS
●
Minimum Operating Voltage
V
mA
μA
V
V
IN
V
IN
Quiescent Current
Shutdown Current
V
V
= 1.3V
FB
= V
= V = 0V
SHDNB
1
SHDN
SHDNA
SHDN Pin Threshold
SHDNA Pin Threshold
SHDNB Pin Threshold
SHDN Pin Bias Current
0.3
0.3
0.3
1.5
1.5
1.5
V
V
V
SHDN
V
SHDN
= 5V, V
= 0V, V
= 0V, V
= 0V, V
= 0V
= 0V
8
0.1
15
1
μA
μA
SHDNA
SHDNA
SHDNB
SHDNB
SHDNA Pin Bias Current
SHDNB Pin Bias Current
V
V
= 0V, V
= 0V, V
= 5V, V
= 0V, V
= 0V
= 0V
8
15
1
μA
μA
SHDN
SHDN
SHDNA
SHDNA
SHDNB
SHDNB
0.1
V
SHDN
V
SHDN
= 0V, V
= 0V, V
= 5V
= 0V
8
0.1
15
1
μA
μA
SHDNA
SHDNA
SHDNB
SHDNB
= 0V, V
= 0V, V
3572fa
2
LT3572
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDNA= VSHDNB = VSHDN = 5V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
0.3
TYP
MAX
1.5
UNITS
PWMA Pin Threshold
PWMB Pin Threshold
PGOOD Rising Threshold
PGOOD Falling Threshold
PGOOD Resistance
Switching Frequency
V
V
0.3
1.5
●
●
●
(Note 3)
(Note 4)
1.12
1.01
1.16
1.04
1
1.19
1.065
3
V
V
kΩ
●
●
RT = 75.0kΩ
RT = 13.0kΩ
425
1.9
500
2.25
575
2.6
kHz
MHz
●
●
Maximum Duty Cycle
RT = 75.0kΩ
RT = 13.0kΩ
95
85
%
%
Synchronization Frequency
SYNC Pin Thresholds
SS Current
575
0.3
2500
1.5
kHz
V
(Note 5)
4.5
1.225
0.01
50
μA
V
●
FB Pin Voltage
1.195
0.9
1.255
0.05
200
1.7
FB Pin Voltage Line Regulation
FB Pin Bias Current
SW Current Limit
V
V
= 2.5V to 10V
%/V
nA
A
IN
= 1.225V (Note 6)
FB
(Note 7)
= 800mA
1.3
SW V
I
310
0.2
450
5
mV
μA
ns
CESAT
SW
SW Leakage Current
OUTx Rise Time
OUTx Fall Time
SW = 40V
C = 2.2nF, V
C = 2.2nF, V
= 30V (Note 8)
= 30V (Note 8)
120
120
OUT
ns
OUT
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3572 is guaranteed to meet specified performance from
0°C to 70°C operating junction temperature. Specifications over the
–40°C to 85°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
Note 3: Rising threshold voltage on FB pin that pulls PGOOD low.
Note 4: Falling threshold voltage on FB pin that causes a high impedance
on PGOOD.
Note 5: Minimum pulse width is 100ns. Maximum off pulse width is 100ns.
Note 6: Current flows into the pin.
Note 7: Current limit guaranteed by design and/or correlation to static test.
Note 8: OUTx refers to OUTA, OUTA, OUTB, OUTB.
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3
LT3572
TYPICAL PERFORMANCE CHARACTERISTICS
Feedback Pin Voltage vs
Temperature
Oscillator Frequency vs
Temperature
SS Pin Current vs Temperature
1.25
1.24
1.23
2.5
2.0
1.5
1.0
0.5
0
8
7
6
5
4
3
2
1
0
RT = 13k
RT = 35k
1.22
1.21
1.20
50
TEMPERATURE (°C)
–50 –25
0
25
75 100 125 150
50 75
TEMPERATURE (°C)
50
TEMPERATURE (°C)
–50 –25
0
25
100 125 150
–50 –25
0
25
75 100 125 150
3572 G01
3572 G03
3572 G02
Quiescent Current vs Temperature
SHDN Pin Current vs Temperature
SW Current Limit vs Temperature
10
9
8
7
6
5
4
3
2
1
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
SHDN
= 5V
V
SHDN
= 2.5V
50 75
TEMPERATURE (°C)
–50 –25
0
25
100 125 150
50 75
–50
50
100 125
150
–50 –25
0
25
100 125 150
–25
0
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
3572 G04
3572 G05
3572 G06
SW Saturation Voltage vs
Temperature
Start-Up
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
I
IN
200mA/DIV
I
I
= 800mA
= 400mA
V
SW
SW
OUT
20V/DIV
V
OUTA
20V/DIV
PGOOD
5V/DIV
3572 G08
200μs/DIV
–50
50
100 125
150
–25
0
25
75
TEMPERATURE (°C)
3572 G07
3572fa
4
LT3572
PIN FUNCTIONS
SW (Pin 1): Switch Node. This pin connects to the col-
lector of an internal NPN power switch.
SHDNB (Pin 12): Shutdown Pin. Tie to 1.5V or more to
enable OUTB and OUTB. Pull low to place OUTB and OUTB
in a high impedance state.
V (Pin 2): Input Supply Pin. This pin must be locally
IN
FB (Pin 13): Feedback Pin. The LT3572 regulates this pin
to 1.225V. Connect the feedback resistors to this pin to
set the output voltage for the switching regulator.
bypassed with a capacitor.
SYNC (Pin 3): Synchronization Pin. This pin is used to
synchronize the internal oscillator to an external signal.
The synchronizing range is 15% above the free running
frequency set by the RT pin up to 2.5MHz. If not used,
this pin must be tied to GND.
SS (Pin 14): Soft-Start Pin. Place a soft-start capacitor
here. A capacitor on the soft-start pin slowly ramps the
current limit of the part from 0A to 1.3A.
PGOOD (Pin 15): This pin is an open-drain output that
pulls low when the FB pin is within 95% of its regulation
value.
RT (Pin 4): Frequency Set Pin. Place a resistor to GND
to set the internal frequency. The range of oscillation is
500kHz to 2.25MHz.
OUTB (Pin 16): The Output Driver. This node switches
GND (Pins 5, 9, 20): Ground.
between V
and GND and is inverted from OUTB.
OUT
PWMB (Pin 6): Logic Input for the Driver. A high signal
on this input sets OUTB high and OUTB low.
OUTB (Pin 17): The Output Driver. This node switches
between V and GND.
OUT
PWMA (Pin 7): Logic Input for the Driver. A high signal
on this input sets OUTA high and OUTA low.
OUTA (Pin 18): The Output Driver. This node switches
between V and GND .
OUT
V
(Pin 8): Output for the Switching Regulator and the
OUT
OUTA (Pin 19): The Output Driver. This node switches
between V and GND and is inverted from OUTA.
Input Supply for the Drivers.
OUT
SHDN (Pin 10): Shutdown Pin. Tie to 1.5V or more to
enable the switcher. Pull low to disable the switcher.
Exposed Pad (Pin 21): Ground. The Exposed Pad of the
package provides both electrical contact to ground and
good thermal contact to the printed circuit board. The
Exposed Pad must be soldered to the circuit board for
proper operation.
SHDNA (Pin 11): Shutdown Pin. Tie to 1.5V or more to
enable OUTA and OUTA. Pull low to place OUTA and OUTA
in a high impedance state.
3572fa
5
LT3572
BLOCK DIAGRAM
8
7
10
11
12
V
OUT
PWMA
SHDN SHDNA SHDNB
V
IN
START-UP/
INTERNAL BIAS
A6
2
1
Q2
Q3
L1
OUTA
OUTA
OUTB
OUTB
SW
18
19
17
16
A4
S
R
+
–
Q1
Q
A2
D1
R4
Q4
Q5
+
–
GND
GND
5
9
A3
A1
R5
GND
GND
20
21
V
OUT
1.225V
+
–
Q6
Q7
OSCILLATOR
R1
FB
R
A5
13
14
C1
C
R2
C
C
SS
Q10
C2
95%/85%
Q8
Q9
–
+
A7
PWMB RT SYNC
PGOOD
15
6
4
3
R3
3572 F01
Figure 1. Block Diagram
3572fa
6
LT3572
OPERATION
Switching Regulator
amplifier causing the current limit to slowly increase. This
helps reduce overshoot on the output and helps minimize
inrush current on the input.
The LT3572 uses a constant frequency, current mode,
controlschemetoprovideexcellentlineandloadregulation
for the output drivers. Operation can be best understood
by referring to the Block Diagram in Figure 1. A pulse
from the oscillator sets the RS flip-flop, A4, and turns on
the internal NPN bipolar power switch, Q1. Current in Q1
and the external inductor, L1, begins to increase. When
this current exceeds a level determined by the voltage at
the output of the error amplifier A1, comparator A2 resets
A4, turning Q1 off. The current in L1 flows through the
external Schottky diode D1 and begins to decrease. The
cycle begins again at the next pulse from the oscillator.
In this way, the voltage at the output of the error amplifier
controlsthecurrentthroughtheindictortotheoutput. The
soft-start capacitor, C2, clamps the output of the error
Output Drivers
The function of the driver section is to level shift the
input of the PWM pins to the voltage of the V
pin. The
OUT
drivers operate in an H-bridge fashion, where the OUTA
and OUTB pins are the same polarity as the PWMA and
PWMB pins respectively and the OUTA and OUTB are
inverted from PWMA and PWMB respectively. The OUT
pins will be high impedance until the FB pin is within
95% of its regulated voltage. The OUT pins will follow
PWMA and PWMB as long as FB stays within 85% of the
regulated voltage. If FB drops below 85%, the OUT pins
will go high impedance.
3572fa
7
LT3572
APPLICATIONS INFORMATION
Duty Cycle
10000
1000
100
The typical maximum duty cycle of the LT3572 is 95% at
1MHz. This maximum duty cycle reduces as the switch-
ing frequency is increased. The duty cycle for a given
application is given by:
VOUT + VD – VIN
DC =
VOUT + VD – VCESAT
where V is the diode forward drop, typically 0.5V and
D
10
100
V
is, in the worst case, 310mV at 0.8A. The LT3572
CESAT
RT RESISTANCE (kΩ)
can be used at higher duty cycles, but must be operated
in the discontinuous mode so that the actual duty cycle
is reduced.
3572 F02
Figure 2. RT Resistance vs Switching Frequency
15% lower than the desired synchronized frequency. If
the sync function is not used the SYNC pin must be tied
to ground.
FB Resistor Network
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the resistors
according to:
PGOOD
VOUT
1.225V
⎛
⎞
⎠
The part has a power good feature that detects when the
output boost converter is up and in regulation. When the
part is turned off or not in regulation the PGOOD pin is
in a high impedance state. When the part is within 95%
of regulation the PGOOD pin is pulled low signaling that
the output is valid. If the output then falls below 85% of
regulation the PGOOD pin is put back in a high impedance
state. Whenever the output is not in regulation the output
pins in the driver aren’t allowed to switch and are placed
in a high impedance state. The PGOOD pin is an open
drain of an NMOS devices with an impedance of 1kΩ and
R1= R2
– 1
⎜
⎝
⎟
Shutdown Pins
When held below 0.3V, SHDNA and SHDNB prevent the
drivers from switching and keep the outputs in a high
impedance state. If SHDN is held below 0.3V then the
switching regulator is prevented from turning on. When
any one of these pins are pulled above 1.5V the internal
circuitry is turned on and the respective output is allowed
to operate. When the LT3572 is not in use all three pins
should be pulled low.
should be tied to V through a resistor.
IN
Soft-Start
Oscillator
The soft-start feature limits the inrush current drawn from
thesupplyuponstart-up. Aninternalcurrentsourcewitha
nominal4.5μAcurrentsourcechargesanexternalcapacitor
C2. The voltage on the soft-start pin is used to control the
output of the error amplifier, which limits the maximum
peak current through the inductor and the inrush current
drawn from the supply during start-up.
The LT3572 can operate at switching frequencies from
500kHz up to 2.25MHz by changing the value of the re-
sistor R3 on the RT pin. Figure 2 shows a graph of RT vs
Switching Frequency.
The oscillator can be synchronized with an external clock
applied to the SYNC pin. When synchronizing the oscilla-
tor, the free running frequency must be set approximately
3572fa
8
LT3572
APPLICATIONS INFORMATION
1A without saturating, and ensure that the inductor has a
PWM
2
low DCR (copper-wire resistance) to minimize I R power
The LT3572 can PWM the output drivers at a very high
frequency. The limitation on the frequency is determined
by the internal rise in die temperature that occurs when
losses. Table 1 lists several inductor manufacturers.
Table 1. Inductor Manufacturers
driving the motor. The power delivered to the piezo motor
Sumida
TDK
(847) 956-0666
(847) 803-6100
(714) 852-2001
(408) 432-8331
www.sumida.com
www.tdk.com
2
is propotional to V
, the capacitance of the motor, and
OUT
the PWM frequency. When any of these are increased the
power dissipated in the part increases causing the internal
die temperature to increase. Driving two 2.2nF capacitors
Murata
FDK
www.murata.com
www.tdk.co.jp
with V
at 30V, the maximum PWM frequency should be
Capacitor Selection
OUT
less than 80 kHz. The LT3572 can run at a higher frequency
The small size of ceramic capacitors makes them ideal
for LT3572 applications. Only X5R or X7R types should
be used because they retain their capacitance over wider
voltage and temperature ranges than other types such as
Y5V or Z5U. A 4.7μF to 15μF output capacitor is sufficient
for stable transient response, however, more output ca-
but either V
needs to be reduced or the capacitance
OUT
needs to be lowered. A piezo motor has an associated
capacitance that cannot be reduced so the output voltage
2
mustbelowered. SincethepowerisproportionaltoV
a
OUT
reduction of V
to 25V from 30V will allow the LT3572 to
OUT
run at a maxim frequency of 115 kHz. If a different motor is
usedthemaximumPWMfrequencywillneedtobeadjusted
inversely to the equivolent capacitance of the motor.
pacitance can help limit the voltage droop on V
transients.
during
OUT
Ceramic capacitors also make a good choice for the input
decoupling capacitor, which should be placed as close as
possible to the LT3572. A 1μF to 4.7μF input capacitor
is sufficient for most applications. Table 2 shows a list
Inductor Selection
A 10μH inductor is recommended for most LT3572 ap-
plications. Choose an inductor that will handle at least
OUTA OUTB
OUTA
OUTB
D1
C1
L1
1
2
3
4
5
15 PGOOD
C2
SW
V
14
13
12
11
SS
IN
C3
GND
R2
R1
SYNC
RT
FB
SHDNB
GND
SHDNA
C
FF
PWMB
PWMA
SHDN
R4
V
OUT
3572 BD LAYOUT
3572fa
9
LT3572
APPLICATIONS INFORMATION
of several ceramic capacitor manufacturers. Consult the
manufacturers for detailed information on their entire
selection of ceramic parts.
used. Thesediodesareratedtohandleanaverageforward
current of 0.5A. For higher efficiency, use a diode with bet-
ter thermal characteristics such as the On Semiconductor
MBRM140 (a 40V diode).
Table 2. Ceramic Capacitor Manufacturers
Taiyo Yuden
AVX
(408) 573-4150
(803) 448-9411
(714) 852-2001
www.t-yuden.com
www.avxcorp.com
www.murata.com
Layout Hints
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
To maximize efficiency, switch rise and fall times are made
as short as possible. Note the vias under the Exposed Pad.
These should connect to a local ground plane for better
thermal performance.
Murata
Diode Selection
ASchottkydiodeisrecommendedforusewiththeLT3572.
The Philips PMEG 3005 is a good choice. If the switch
voltage exceeds 30V, a PMEG 4005 (a 40V diode) can be
TYPICAL APPLICATION
L1
12μH
D1
V
OUT
V
IN
30V
3V TO 5V
50mA
2
1
8
C4
20pF
R1
V
SW
V
OUT
IN
SHDN
576k
10
11
12
7
6
3
C1
10μF
13
18
19
R4
100k
SHDNA
SHDNB
PWMA
PWMB
SYNC
FB
R2
24.9k
OUTA
OUTA
LT3572
C3
4.7μF
3572 TA02
15
PGOOD
4
17
16
RT
SS
OUTB
OUTB
14
R3
34k
GND
5, 9, 20, 21
C2
10nF
3572fa
10
LT3572
PACKAGE DESCRIPTION
UF Package
20-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1710 Rev A)
0.70 p0.05
4.50 p 0.05
3.10 p 0.05
2.45 p 0.05
2.00 REF
2.45 p 0.05
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
PIN 1 NOTCH
R = 0.20 TYP
OR 0.35 s 45o
CHAMFER
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM VIEW—EXPOSED PAD
R = 0.05
TYP
R = 0.115
0.75 p 0.05
TYP
4.00 p 0.10
19 20
0.40 p 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
2.45 p 0.10
2.00 REF
4.00 p 0.10
2.45 p 0.10
(UF20) QFN 01-07 REV A
0.200 REF
0.25 p 0.05
0.50 BSC
0.00 – 0.05
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-1)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3572fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LT3572
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IN
OUT(MAX)
3mm × 3mm DFN8 and MS8E Packages
3572fa
LT 0408 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
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