C3216X5R1C226M [Linear]
38V, 10A DC/DC μModule Regulator with Advanced Input and Load Protection; 38V ， 10A DC / DC稳压器μModule高级输入和负载保护
| 型号： | C3216X5R1C226M |
| 厂家： | 
Linear |
| 描述： | 38V, 10A DC/DC μModule Regulator with Advanced Input and Load Protection |
| 文件： | 总64页 (文件大小：822K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM4641
38V, 10A DC/DC µModule
Regulator with Advanced
Input and Load Protection
DESCRIPTION
The LTM®4641 is a switch mode step-down DC/DC
µModule® (micromodule) regulator with advanced input
and load protection features. Trip detection thresholds for
the following faults are customizable: input undervoltage,
overtemperature, input overvoltage and output overvolt-
age. Select fault conditions can be set for latchoff or
hysteretic restart response—or disabled. Included in the
package are the switching controller and housekeeping
ICs,powerMOSFETs,inductor,overvoltagedrivers,biasing
circuitryandsupportingcomponents.Operatingfrominput
voltages of 4V to 38V (4.5V start-up), the device supports
output voltages from 0.6V to 6V, set by an external resis-
tor network remote sensing the point-of-load’s voltage.
FEATURES
n
Wide Operating Input Voltage Range: 4.5V to 38V
n
10A DC Typical, 12A Peak Output Current
n
Output Range: 0.6V to 6V
n
1.5ꢀ ꢁaꢂiꢃuꢃ Total Output DC Voltage Error
n
DifferentialReꢃoteSenseAꢃplifierforPOLRegulation
n
Internal Teꢃperature, Analog Indicator Output
n
OvercurrentFoldbackandOverteꢃperatureProtection
n
Current ꢁode Control/Fast Transient Response
n
Parallelable for Higher Output Current
n
Selectable Pulse-Skipping Operation
n
Soft-Start/Voltage Tracking/Pre-Bias Start-Up
n
15mm × 15mm × 5.01mm BGA Package
Input Protection
n
UVLO, Overvoltage Shutdown and Latchoff Thresholds
The LTM4641’s high efficiency design can deliver up to
10A continuous current with a few input and output ca-
pacitors. The regulator’s constant on-time current mode
controlarchitectureenableshighstep-downratiosandfast
responsetotransientlineandloadchanges. TheLTM4641
is offered in a 15mm × 15mm × 5.01mm RoHS compliant
BGA package with Pb-free finish.
n
N-Channel Overvoltage Power-Interrupt MOSFET Driver
n
Surge Stopper Capable with Few External Components
Load Protection
n
Robust, Resettable Latchoff Overvoltage Protection
N-Channel Overvoltage Crowbar Power MOSFET Driver
n
APPLICATIONS
L, LT, LTC, LTM, µModule, Burst Mode, Linear Technology and the Linear logo are registered
trademarks and LTpowerCAD is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents including
5481178, 5847554, 6100678, 6304066, 6580258, 6677210.
n
Ruggedized Electronics
Avionics and Industrial Equipment
n
TYPICAL APPLICATION
µꢁodule Regulator with Input Disconnect and Fast Crowbar Output Overvoltage Protection
4
1V Load Protected froꢃ ꢁTOP
Short-Circuit at 38VIN
V
MSP*
IN
4V TO 38V
4.5V START-UP
+
3
10µF
50V
×2
100µF
50V
SHORT-CIRCUIT APPLIED
1
V
V
V
V
SW
V
M
ING INGP INH
OUT
TOP
4
1V
V
2
INL
OUT
10A
V
, V (25V/DIV)
INL INH
100µF
3
2
×3
750k
CROWBAR (5V/DIV)
MCB**
CROWBAR
M
BOT
f
1.1V
OUT
PEAK
SET
5.49k
5.49k
+
–
UVLO
INTV
V
V
OSNS
LTM4641
CC
LOAD
DRV
CC
V
OUT
(200mV/DIV)
OSNS
RUN
GND
OV
4641 TA01a
1
TRACK/SS
PGM
5.6M
10nF
IOVRETRY OVLO FCB LATCH SGND
4641 TA01b
4µs/DIV
TESTED AT WORST-CASE CONDITION: NO LOAD
SGND CONNECTS TO GND INTERNAL TO µMODULE REGULATOR
*
**
MSP: (OPTIONAL) SERIES-PASS OVERVOLTAGE POWER INTERRUPT MOSFET, NXP PSMN014-60LS
MCB: (OPTIONAL) OUTPUT OVERVOLTAGE CROWBAR MOSFET, NXP PH2625L
4641f
1
LTM4641
TABLE OF CONTENTS
Features .................................................... 1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Absolute ꢁaꢂiꢃuꢃ Ratings.............................. 3
Order Inforꢃation.......................................... 3
Pin Configuration .......................................... 3
Electrical Characteristics................................. 4
Typical Perforꢃance Characteristics ................... 8
Pin Functions..............................................10
Siꢃplified Block Diagraꢃ ...............................15
Decoupling Requireꢃents...............................15
Operation...................................................16
Introduction............................................................ 16
Motivation............................................................... 16
Power µModule Regulator Reliability...................... 16
Overview................................................................. 16
Applications Inforꢃation—Power Supply Features .17
Overcurrent Foldback Protection ............................32
Power Good Indicator and Latching Output
Overvoltage Protection...........................................32
Power-Interrupt MOSFET (MSP), CROWBAR Pin and
Output CROWBAR MOSFET (MCB) ........................33
Fast Output Overvoltage Comparator Threshold.....34
Applications Inforꢃation—EꢁI Perforꢃance ........35
The Switching Node: SW Pin..................................35
Applications Inforꢃation—ꢁultiꢃodule Parallel
Operation...................................................36
Applications Inforꢃation—Therꢃal Considerations
and Output Current Derating ............................38
Thermal Considerations and Output Current
Derating..................................................................38
Applications Inforꢃation—Output Capacitance
Table........................................................45
Applications Inforꢃation—Safety and Layout
Guidance ...................................................46
Safety Considerations.............................................46
Layout Checklist/Example ......................................46
Typical Applications......................................48
Appendices ................................................55
Appendix A. Functional Block Diagram and Features
Quick Reference Guide............................................55
Appendix B. Start-Up/Shutdown State Diagram .....56
Appendix C. Switching Frequency Considerations and
Power (V ) and Bias (V ) Input Pins................. 17
INH
INL
Switching Frequency (On Time) Selection and
Voltage Dropout Criteria (Achievable V -to-V
IN
OUT
Step-Down Ratios).................................................. 18
Setting the Output Voltage; the Differential Remote
Sense Amplifier ......................................................21
Input Capacitors .....................................................23
Output Capacitors and Loop Stability/Loop
Compensation.........................................................23
Pulse-Skipping Mode vs Forced Continuous Mode 24
Soft-Start, Rail-Tracking and Start-Up Into
Usage of R
........................................................57
fSET
Appendix D. Remote Sensing in Harsh
Environments..........................................................58
Appendix E. Inspiration For Pulse-Skipping Mode
Operation................................................................59
Appendix F. Adjusting the Fast Output Overvoltage
Comparator Threshold............................................59
Package Description .....................................62
Package Photo ............................................62
Package Description .....................................63
Typical Application .......................................64
Related Parts..............................................64
Pre-Bias..................................................................24
INTV and DRV .................................................27
CC
CC
1V ......................................................................28
REF
TEMP, OTBH and Overtemperature Protection........28
Applications Inforꢃation—Input Protection
Features....................................................29
Input Monitoring Pins: UVLO, IOVRETRY, OVLO ....29
Start-Up/Shutdown and Run Enable; Power-On Reset
and Timeout Delay Time .........................................31
Applications Inforꢃation—Load Protection
Features....................................................32
4641f
2
LTM4641
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Terminal Voltages
INTV
V
V
CC
SGND
ING INGP
V
V
V
, V , SW, f ............................... –0.3V to 40V
INL INH
SET
M
TRACK/SS
PGOOD
V
INH
...................................................... –0.3V to 9.2V
OUT
ING
L
FCB
SGND
COMP
............................................ –0.3V to V + 20V
INH
K
J
DRV
GND
CC
INTV , DRV , RUN, TRACK/SS, PGOOD,
CC
CC
f
SW
SET
INL
CROWBAR, HYST.................................... –0.3V to 6V
V
H
G
F
+
V
OSNS
GND
OSNS
FCB, TMR................................-0.3V to INTV + 0.3V
CC
–
V
COMP ................................................... –0.3V to 2.7V
GND
+
–
+
–
V
V
, V
...................................... –0.6V to 9.7V
OSNS
OSNS
ORB
E
+
+
+
, V
..........V
– 2.7V to V
+ 0.3V
OTBH TMR RUN
V
V
ORB
OSNS
OSNS
ORB
D
C
B
A
V
OUT
–
OTBH, UVLO, IOVRETRY, OVLO,
LATCH ....................................................–0.3V to 7.5V
TEMP, OV ....................................... –0.3V to 1.5V
ORB
LATCH
SGND
1V
REF
PGM
GND
Terminal Currents
1
2
3
4
5
6
7
8
9
10 11 12
INTV (Continuous)....................................... –30mA
CC
TEMP IOVRETRY CROWBAR OV
OVLO
UVLO
HYST
PGM
INTV (Continuous; CROWBAR
CC
BGA PACKAGE
144-LEAD (15mm × 15mm × 5.01mm)
Sourcing 15mA)...............................................–15mA
T
= 125°C, θ
= 11°C/W, θ
= 2.5°C/W
CROWBAR (Continuous)..................................–15mA
JMAX
JCtop
JCbottom
θ
= 3°C/W, θ = 10.4°C/W
JA
JB
V
(Continuous) ........................... –50mA to 15mA
(Continuous)................................–1mA to 1mA
θ VALUES DETERMINED PER JESD51-12
INGP
WEIGHT = 2.9 GRAMS
1V
REF
Internal Operating Temperature Range (Note 2)
E- and I-Grades.................................. –40°C to 125°C
MP-Grade .......................................... –55°C to 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Package Body Temperature (SMT Reflow) ... 245°C
ORDER INFORMATION
LEAD FREE FINISH
LTM4641EY#PBF
LTM4641IY#PBF
LTM4641MPY#PBF
TRAY
PART ꢁARKING*
PACKAGE DESCRIPTION
TEꢁPERATURE RANGE (Note 2)
–40°C to 125°C
LTM4641EY#PBF
LTM4641IY#PBF
LTM4641MPY#PBF
LTM4641Y
144-Lead (15mm × 15mm × 5.01mm) BGA
144-Lead (15mm × 15mm × 5.01mm) BGA
144-Lead (15mm × 15mm × 5.01mm) BGA
LTM4641Y
–40°C to 125°C
LTM4641Y
–55°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
4641f
3
LTM4641
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full internal
operating teꢃperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VINH = VINL = 28V, per the typical application
shown in Figure 45, unless otherwise noted.
SYꢁBOL
PARAꢁETER
CONDITIONS
ꢁIN
4.5
TYP
ꢁAX
38
UNITS
l
l
V
V
Input DC Voltage
Output Voltage Range
V
V
IN
Use R
= R
≤ 8.2kΩ. R Values
fSET
0.6
6
OUT
SET1A
SET1B
Recommended in Table 1
4.5V ≤ V ≤ 38V, 0A ≤ I ≤ 10A
OUT
l
l
V
Output Voltage, Total Variation with
Line and Load, and Prior to UVLO
1.773 1.800 1.827
1.773 1.800 1.827
V
V
OUT(DC)
IN
V
= 4V (Ramped Down from 4.5V), I
= 0A
IN
OUT
Input Specifications
l
l
V
RUN On/Off Threshold
RUN Pull-Up Current
Run Rising, Turn On
Run Falling, Turn Off
1.25
1.15
2
V
V
RUN(ON,OFF)
0.8
l
l
I
I
V
RUN
V
RUN
= 0V
= 3.3V
–580
–220
–520
–165
–460
–110
µA
µA
RUN(ON)
RUN Pull-Down Current, Switching
Inhibited
V
=3.3V, UVLO =0V (M On)
HYST
1
nA
RUN(OFF)
RUN
l
l
l
V
V
Undervoltage Lockout
V
V
Rising
Falling
4.2
3.8
400
4.5
4
V
V
mV
INL(UVLO)
INL
INL
INL
3.5
300
Hysteresis
I
I
Input Inrush Current Through V
at Start-Up
,
C
= Open
230
mA
INRUSH(VINH)
INH
SS
Power Stage Bias Current (I
No Load
) at
I
= 0A and:
FCB ≥ 0.84V (Pulse-Skipping Mode)
FCB ≤ 0.76V (Forced Continuous Mode)
Shutdown, RUN = 0
Q(VINH)
VINH
OUT
8
29
0.2
mA
mA
mA
I
I
Control Bias Current (I
)
INTV Connected to DRV and:
CC CC
Q(VINL)
S(VINH)
VINL
V
IN
V
IN
V
IN
= 28V, I
= 0A
14.5
15.5
5
mA
mA
mA
OUT
OUT
= 28V, I
= 10A
= 28V, Shutdown, RUN = 0
Power Stage Input Current (I
Full Load
) at
VINH
I
= 10A and:
OUT
V
IN
V
IN
V
IN
= 4.5V
= 28V
= 38V
4.65
790
590
A
mA
mA
Output Specifications
l
l
l
I
Output Continuous Current Range
Line Regulation Accuracy
(Note 3)
0
10
A
%
%
OUT(DC)
V
I
from 4.5V to 38V, I
= 0A
0.02
0.04
16
0.15
0.15
∆V
∆V
/V
IN
OUT
OUT(LINE) OUT
Load Regulation Accuracy
from 0A to 10A (Note 3)
= 0A
/V
OUT
OUT
OUT(LOAD) OUT
V
Output Voltage Ripple Amplitude
Output Voltage Ripple Frequency
I
mV
P-P
OUT(AC)
f
I
I
= 0A
= 10A
290
330
kHz
kHz
S
OUT
OUT
V
Turn-On Overshoot
I
= 0A
10
3
mV
ms
OUT(START)
OUT
t
V -to-V
Start-Up Time
RUN Electrically Open Circuit, Time Between
Application of V to V Becoming Regulated,
OV
START
IN
OUT
IN
OUT
= 1.5V, C
= C = Open
PGM
TMR SS
t
RUN-to-V
Time
Turn-On Response
V Established, (TMR-Set POR Time Expired)
IN
175
400
μs
RUN(ON-DELAY)
OUT
Time Between RUN Releasing from GND to
PGOOD Going Logic High, C = Open,
SS
OV
PGM
= 1.5V
Peak Deviation for Dynamic Load
Step
I
I
from 0A to 5A at 5A/µs
from 5A to 0A at 5A/µs
40
40
mV
mV
∆V
OUT(LS)
OUT
OUT
t
Settling Time for Dynamic Load Step
I
I
from 0A to 5A at 5A/µs
from 5A to 0A at 5A/µs
20
20
μs
µs
SETTLE(LS)
OUT
OUT
4641f
4
LTM4641
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full internal
operating teꢃperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VINH = VINL = 28V, per the typical application
shown in Figure 45, unless otherwise noted.
SYꢁBOL
PARAꢁETER
CONDITIONS
ꢁIN
TYP
ꢁAX
UNITS
I
Output Current Limit
5.1kΩ Pull-Up from PGOOD to 5V Source, I
24
A
OUT(PK)
OUT
Ramped Up Until V
Below PGOOD Lower
OUT
Threshold, PGOOD Pulls Logic Low
I
Power Stage Input Current During
Output Short Circuit
V
Electrically Shorted to GND
45
mA
VINH(IOUT_SHORT)
OUT
Control Section
l
V
Differential Feedback Voltage from
OSNS
I
= 0A
591
600
609
mV
FB
OUT
+
–
V
to V
OSNS
I
TRACK/SS Pull-Up Current
FCB Threshold
V
= 0V
TRACK/SS
–0.45
0.76
–1
0.8
0
μA
V
TRACK/SS
V
0.84
1
FCB
I
t
t
FCB Pin Current
V
= 0.8V
FCB
μA
ns
ns
V
FCB
Minimum On-Time
Minimum Off-Time
(Note 4)
(Note 4)
43
75
ON(MIN)
OFF(MIN)
220
300
2.7
+
–
l
V
Remote Sense Pin-Pair Differential
Mode Input Range
Valid Differential V
(Use R
-to- V Range
OSNS
0
OSNS(DM)
OSNS
SET1B
= R
≤ 8.2k)
SET1A
–
+
l
l
V
Remote Sense Pin-Pair Common
Mode Input Range
Valid V
Valid V
(Use R
Common Mode Range
Common Mode Range
SET1B
–0.3
V
V
OSNS(CM)
OSNS
OSNS
3
= R
≤ 8.2k)
SET1A
+
R
+
Input Resistance
V to GND
OSNS
16318 16400 16482
Ω
V
IN(VOSNS
)
INTV , DRV , 1V
CC
CC
REF
l
V
Internal V Voltage
6V ≤ V ≤ 38V, INTV Not Connected to DRV ,
CC
5.1
5.3
5.4
INTVCC
CC
IN
CC
DRV = 5.3V
CC
INTV Load Regulation
RUN = 0V, INTV Not Connected to DRV ,
CC CC
∆V
CC
INTVCC(LOAD)
DRV = 5.3V and:
CC
V
INTVCC
I
I
Varied from 0mA to –20mA
Varied from 0mA to –30mA
–0.7
–1
2
3
%
%
INTVCC
INTVCC
l
V
INTV Voltage at Low Line
V
= 4.5V, R
fSET
= R
= 0Ω (~0.6V ,
OUT
4.2
4.3
V
INTVCC(LOWLINE)
CC
IN
SET1A
SET1B
R
Value Recommended in Table 1)
l
l
DRV
DRV Undervoltage Lockout
DRV Rising
3.9
3.2
4.05
3.35
4.2
3.5
V
V
CC(UVLO)
CC
CC
DRV Falling
CC
I
DRV Current
INTV Not Connected to DRV , DRV = 5.3V,
DRVCC
CC
CC
, R
CC
CC
to:
R
and R
Setting V
SET1A SET1B
SET2
OUT
≤ 10A
≤ 10A
1.8V , R
= 2MΩ, 0A ≤ I
= Open, 0A ≤ I
11
20
18
27
mA
mA
OUT fSET
OUT
OUT
6.0V , R
OUT fSET
(Use R
= R
≤ 8.2k)
SET1A
SET1B
l
l
V
1V DC Voltage Regulation
REF
I
I
= 0mA
= 1mA
0.985 1.000 1.015
0.980 1.000 1.020
V
V
1VREF(DC)
1VREF
1VREF
PGOOD Output
+
–
V
Power Good Window, Logic State
Transition Thresholds
Ramping Differential V
– V
Voltage:
PGOOD(TH)
OSNS
OSNS
Up, PGOOD Goes Logic Low → High
Up, PGOOD Goes Logic High → Low
Down, PGOOD Goes Logic Low → High
Down, PGOOD Goes Logic High → Low
533
645
621
525
556
660
644
540
579
675
667
555
mV
mV
mV
mV
+
–
V
V
Hysteresis
Differential V
– V Voltage Returning
OSNS
8
16
75
12
24
mV
mV
μs
PGOOD(HYST)
OSNS
l
Logic-Low Output Voltage
PGOOD Logic-Low Blanking Time
I
= 5mA
400
PGOOD(VOL)
PGOOD
+
–
t
Delay Between Differential V
Voltage Exiting PGOOD Valid Window to PGOOD
Going Logic Low (Note 4)
– V
OSNS OSNS
PGOOD(DELAY)
4641f
5
LTM4641
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full internal
operating teꢃperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VINH = VINL = 28V, per the typical application
shown in Figure 45, unless otherwise noted.
SYꢁBOL
PARAꢁETER
CONDITIONS
ꢁIN
TYP
ꢁAX
UNITS
Power-Interrupt ꢁOSFET Drive
l
l
l
l
V
Gate Drive Voltage for Power-
Interrupt MOSFET, MSP
V
V
V
V
V
= 4.5V, 0A ≤ I
≤ 10A, V Sourcing 1µA
11.5
35
13.3
38.4
48.4
11.5
15.5
41
51.5
14.2
V
V
V
V
VING
IN
IN
IN
IN
OUT
OUT
OUT
ING
= 28V, 0A ≤ I
= 38V, 0A ≤ I
≤ 10A, V Sourcing 1µA
ING
≤ 10A, V Sourcing 1µA
45
ING
= 4V (Ramped Down from 4.5V), I
= 0A,
10.5
OUT
Sourcing 1µA
ING
I
I
V
V
V
Pull-Up Current
V
Tied to V
, and:
VING(UP)
ING
ING
ING
ING
V
V
INGP
ING
l
l
= 4.5V, V Pulled to 6.5V
350
425
475
550
600
675
µA
µA
IN
IN
= 28V, V Pulled to 30V
ING
Pull-Down Current
OVP Pull-Down Delay
V
Tied to V
, Pulled to 33V, and:
VING_DOWN(CROWBAR
ING
INGP
l
l
RUN Pulled to 0V (CROWBAR Inactive)
OV Pulled to 0V (CROWBAR Active)
3
24
20
27
30
30
mA
mA
ACTIVE,CROWBAR
INACTIVE)
PGM
l
t
OV
Driven from 650mV to 550mV, V
ING
1.3
2.6
µs
VING(OVP_DELAY)
PGM
Discharge Response Time
I
Zener Diode Leakage Current
V
V
Driven to (V + 10V)
1
nA
V
VINGP(LEAK)
INGP
INGP
INH
V
Zener Diode Breakdown Voltage
-to-V Differential Voltage; I = 5mA
VINGP
15
INGP(CLAMP)
INH
Fault Pins and Functions
l
V
Default Output Overvoltage Program OV
Setting
Electrically Open Circuit
650
666
680
mV
OVPGM
PGM
l
l
l
I
I
OV
OV
Pull-Up Current
OV
OV
= 0V
= 1V
–2.07
0.945
647
–2
1
–1.91
1.06
683
μA
μA
OVPGM(UP)
PGM
PGM
PGM
PGM
Pull-Down Current
OVPGM(DOWN)
+
–
OVP
Output Overvoltage Protection
Inception Threshold
Ramping Up Differential V
Voltage Until CROWBAR Outputs Logic High
-to-V
OSNS
666
mV
TH
OSNS
l
l
OVP
Output Overvoltage Protection
Inception Error
Difference Between OVP and V
–12
0
12
mV
ns
ERR
TH
OVPGM
(OVP -V
)
TH OVPGM
t
CROWBAR Response Time
OVP Driven from 650mV to 550mV
400
500
CROWBAR(OVP_DELAY)
GM
V
CROWBAR Output, Active High
Voltage
OVP Pulled to 0V and:
CROWBAR(OH)
GM
l
l
I
I
= –100μA, I
= –20mA
= –20mA
4.3
4.2
4.65
4.55
5
4.9
V
V
CROWBAR
CROWBAR
INTVCC
INTVCC
= –4mA, I
l
l
l
V
V
V
V
CROWBAR Output, Passive Low
Voltage
I
= 1μA
CROWBAR
260
550
1.5
500
900
1.6
mV
mV
V
CROWBAR(OL)
CROWBAR(OVERSHOOT)
CROWBAR(TH)
TEMP
CROWBAR Peak Voltage Overshoot
V
Ramped Up from/Down to 0V
INL
at V Start-Up and Shutdown
INL
CROWBAR Latchoff Threshold
CROWBAR Ramped Up Until HYST Goes Logic
Low
1.4
TEMP Voltage
RUN = 0V, T = 25°C
950
980
585
1010
mV
mV
A
A
RUN = 0V, T = 125°C
(See Figure 10 for Reference)
l
l
l
OT
OT
TEMP Overtemperature Inception
Threshold
Ramping TEMP Downward Until HYST Outputs
Logic Low
428
501
488
438
514
500
448
527
512
mV
mV
mV
TH(INCEPTION)
TEMP Overtemperature Recovery
Threshold
Ramping TEMP Upward Until HYST Outputs
Logic High
TH(RECOVER)
UVOV
UVLO/OVLO/IOVRETRY
Undervoltage/Overvoltage Inception Until HYST Toggles Its State
Thresholds
Ramping UVLO, OVLO or IOVRETRY Positive
TH
4641f
6
LTM4641
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full internal
operating teꢃperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VINH = VINL = 28V, per the typical application
shown in Figure 45, unless otherwise noted.
SYꢁBOL
PARAꢁETER
CONDITIONS
ꢁIN
TYP
ꢁAX
UNITS
l
l
t
UVLO/OVLO/IOVRETRY/ TEMP
Response Time
50mV Overdrive (All Pins)
5mV Overdrive, UVLO/OVLO/IOVRETRY Pins
Only (Note 4)
25
125
100
500
µs
µs
UVOVD
UVOV
50
I
Input Current of UVLO, OVLO and
IOVRETRY
UVLO = 0.55V or OVLO = 0.45V or
IOVRETRY = 0.45V
30
nA
V
V
V
Housekeeping Circuitry UVLO
Voltage on INTV , INTV Rising (Note 4)
1.9
5
2
2.1
50
V
HOUSEKEEPING(UVLO)
HYST(SWITCHING ON)
HYST(SWITCHING OFF,
CC
CC
Hysteresis, INTV Returning (Note 4)
25
mV
CC
l
l
HYST Voltage (M
Logic High)
Off, RUN
Off, RUN
RUN Electrically Open Circuit
RUN = 1.8V
4.9
1.85
5.1
2.1
5.25
2.35
V
V
HYST
l
HYST Voltage (M
Logic Low)
RUN = 0V
170
350
480
mV
HYST
RUN)
l
V
HYST Voltage, Switching Action
Inhibited (M On)
UVLO < UVOV or OVLO > UVOV or
TH TH
30
65
mV
HYST(SWITCHING OFF,
FAULT)
IOVRETRY > UVOV or TEMP < OT
TH(INCEPTION)
HYST
TH
or CROWBAR > V
or
CROWBAR(TH)
UVLO(FALLING)
DRV < DRVCC
CC
(See Figures 62, 63)
l
TMR
Timeout and Power-On Reset Period
C
= 1nF, Time from Fault Clearing to HYST
5
9
14
ms
UOTO
TMR
Being Released by Internal Circuitry
l
l
l
l
l
l
l
l
V
V
LATCH Clear Threshold Input High
LATCH Clear Threshold Input Low
LATCH Input Current
1.2
V
V
LATCH(IH)
LATCH(IL)
LATCH
0.8
1
I
I
I
V
V
V
= 7.5V
= 1.6V
μA
μA
μA
mV
V
LATCH
TMR Pull-Up Current
= 0V
–1.2
1.2
–2.1
2.1
–2.8
2.8
TMR(UP)
TMR(DOWN)
TMR
TMR
TMR Pull-Down Current
V
Timer Disable Voltage
Referenced to INTV
–180
–270
TMR(DIS)
CC
OTBH
OTBH
OTBH Low Level Input Voltage
0.4
1.2
VIL
VZ
OTBH Pin Voltage When Left
Electrically Open Circuit
–10μA ≤ I
≤ 10μA
0.6
0.9
V
OTBH
l
I
Maximum OTBH Current
OTBH Electrically Shorted to SGND
30
μA
OTBH(MAX)
–40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTM4641I is guaranteed over the –40°C to 125°C operating junction
temperature range. The LTM4641MP is tested and guaranteed over the
full –55°C to 125°C operating temperature range. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
The LTM4641 SW absolute maximum rating of 40V is verified in ATE by
regulating V
while at 40V , in a controlled manner guaranteed to not
OUT
IN
affect device reliability or lifetime. Static testing of SW leakage current at
40V is performed at control IC wafer level only.
IN
Note 3: See output current derating curves for different V , V
and T .
A
IN OUT
Note 2: The LTM4641 is tested under pulsed load conditions such that
Note 4: 100% tested at wafer level only.
T ≈ T . The LTM4641E is guaranteed to meet performance specifications
J
A
from 0°C to 125°C junction temperature. Specifications over the
4641f
7
LTM4641
TYPICAL PERFORMANCE CHARACTERISTICS
(Figure 45 circuit with RfSET per Table 1 and RSET1A, RSET1B and RSET2 per Table 2, unless otherwise noted)
Efficiency vs Load Current at 36VIN
Efficiency vs Load Current at 24VIN
Efficiency vs Load Current at 12VIN
95
90
95
90
95
90
85
85
85
80
75
70
65
80
75
70
65
80
75
70
65
6.0V
5.0V
3.3V
2.5V
1.8V
1.5V
1.2V
1.0V
0.9V
6.0V
5.0V
3.3V
2.5V
1.8V
1.5V
1.2V
1.0V
0.9V
6.0V
5.0V
3.3V
2.5V
1.8V
1.5V
1.2V
1.0V
0.9V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
60
60
60
0
3
5
6
7
8
9
10
0
3
5
6
7
8
9
10
0
3
5
6
7
8
9
10
1
2
4
1
2
4
1
2
4
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
4641 G01
4641 G02
4641 G03
Pulse-Skipping vs Forced
Continuous ꢁode Efficiency,
28VIN to 3.3VOUT
Efficiency vs Load Current at 6VIN
1V Transient Response, 38VIN
90
80
70
60
50
40
30
20
10
0
95
90
V
OUT
50mV/DIV
AC-COUPLED
FCB = INTV
CC
(PULSE-SKIPPING)
85
I
OUT
80
75
70
65
2.5A/DIV
FCB = SGND
FORCED
CONTINUOUS
4641 G06
20µs/DIV
0A TO 5A LOAD STEPS AT 5A/µs
FRONT PAGE CIRCUIT WITH
3.3V
2.5V
1.8V
1.5V
1.2V
1.0V
0.9V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OV
PGM
= OPEN CIRCUIT
60
0.1
0.001
0.01
1
10
0
3
5
6
7
8
9
10
1
2
4
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
4641 G05
4641 G04
3.3V Transient Response,
28VIN to 3.3VOUT
1V Transient Response, 4.5VIN
Output Start-Up, No Load
V
OUT
V
V
OUT
OUT
1V/DIV
50mV/DIV
50mV/DIV
AC-COUPLED
AC-COUPLED
I
IN
200mA/DIV
I
I
OUT
OUT
2.5A/DIV
2.5A/DIV
RUN
5V/DIV
4641 G07
4641 G08
4641 G09
20µs/DIV
0A TO 5A LOAD STEPS AT 5A/µs
FRONT PAGE CIRCUIT WITH
20µs/DIV
0A TO 5A LOAD STEPS AT 5A/µs
FIGURE 46 CIRCUIT
800µs/DIV
V
C
= 24V
IN
IN(MLCC)
= 2 × 10µF X7R
OV
= OPEN CIRCUIT
PGM
4641f
8
LTM4641
TYPICAL PERFORMANCE CHARACTERISTICS
(Figure 45 circuit with RfSET per Table 1 and RSET1A, RSET1B and RSET2 per Table 2, unless otherwise noted)
Output Start-Up,
Pre-Bias Condition
Output Short-Circuit,
No Initial Load
Output Start-Up, 10A Load
V
OUT
V
V
OUT
OUT
1V/DIV
1V/DIV
1V/DIV
I
LOAD
I
IN
1mA/DIV
1A/DIV
I
IN
I
IN
200mA/DIV
RUN
1A/DIV
RUN
5V/DIV
5V/DIV
4641 G11
4641 G12
4641 G10
800µs/DIV
= 2 × 10µF X7R
20µs/DIV
800µs/DIV
V
C
= 24V
IN
IN(MLCC)
V
C
= 24V
IN
IN(MLCC)
V
C
= 24V
IN
IN(MLCC)
= 2 × 10µF X7R
= 2 × 10µF X7R
Output Short-Circuit,
10A Initial Load
Start-Up with VINH Shorted to SW
Node, 1VOUT(NOꢁ)
Start-Up with VINH Shorted to SW
Node, 3.3VOUT(NOꢁ)
V
IN
20V/DIV
V
V
IN
V
INH
OUT
10V/DIV
2V/DIV
1V/DIV
V
INH
5V/DIV
V
OUT
200mV/DIV
V
I
IN
OUT
1V/DIV
1A/DIV
CROWBAR
5V/DIV
CROWBAR
5V/DIV
4641 G13
4641 G14
4641 G15
20µs/DIV
400µs/DIV
800µs/DIV
V
C
= 24V
IN
IN(MLCC)
FRONT PAGE CIRCUIT WITH V
SHORT
FIGURE 46 CIRCUIT WITH V
SHORT
INH
INH
= 2 × 10µF X7R
CIRCUITED TO SW PRIOR TO POWER-UP.
CIRCUITED TO SW PRIOR TO POWER-UP.
APPLYING UP TO 38V . NO LOAD
APPLYING UP TO 38V . NO LOAD
IN
IN
Paralleled ꢁodules, Current-
Sharing Perforꢃance. cf.
Figure 66 Circuit. 28VIN
Autonoꢃous Restart with VINH
Shorted to SW Node, 3.3VOUT(NOꢁ)
Control IC Bandgap and 1VREF
Voltages vs Teꢃperature. 28VIN
V
IN
12
10
0.606
0.604
1.006
1.004
10V/DIV
V
INH
10V/DIV
8
6
0.602
1.002
U1 I
V
FB
V
OUT
OUT
1V/DIV
0.600
0.598
1.000
0.998
U2 I
OUT
V
1VREF(DC)
CROWBAR
5V/DIV
4
4641 G16
100ms/DIV
2
FIGURE 46 CIRCUIT, SHORT CIRCUITING V
INH
TO SW IN SITU, OPERATING AT 38V AND
IN
0.596
0.594
0.996
0.994
0
NO LOAD. LATCH CONNECTED TO INTV AND
CC
C
TMR
= 47nF
–2
4
8
12
20
0
16
–75 –50 –25
0
25 50 75 100 125 150
JUNCTION TEMPERATURE (°C)
TOTAL OUTPUT CURRENT (A)
4641 G17
4641 G18
4641f
9
LTM4641
PIN FUNCTIONS
SGND (A1-A3; B1-B3; C1-C4; K1, K3; L3; ꢁ1-ꢁ3): Signal
Ground Pins. This is the return ground path for all analog
control and low power circuitry. SGND is tied to GND in-
ternal to the µModule regulator in a manner that promotes
thebestinternalsignalintegrity—therefore, SGNDshould
not be connected to GND in the user’s PCB layout. See
the Layout Checklist/Example section of the Applications
Information section for more information pertaining to
SGNDandlayout. AllSGNDpinsareelectricallyconnected
to each other, internally.
may be deasserted when TEMP subsequently exceeds
514mV (nominally corresponding to a cool-off hysteresis
of~10°C), dependingontheOTBHsetting. (SeeOTBHand
the Applications Information section.)
To disable the µModule regulator’s overtemperature
shutdown feature, connect the TEMP and 1V pins. The
REF
thermal shutdown inception threshold can also be modi-
fied, see the Applications Information section.
IOVRETRY(A6):NonlatchingInputOvervoltageThreshold
Programming Pin. The LTM4641 pulls HYST low to inhibit
regulation of its output voltage when IOVRETRY exceeds
0.5V. The LTM4641 can resume switching action when
IOVRETRYisbelow0.5V.Ifnononlatchinginputovervoltage
shutdown behavior is desired, connect this pin to SGND.
Do not leave this pin open circuit.
HYST (A4): Input Undervoltage Hysteresis Programming
Pin. Normally used as an output, but can be used as an
input. If the LTM4641’s inherent, default undervoltage
lockout (UVLO) settings are satisfactory, 4.5V
IN(RISING,
, HYST can be left electrically
and 4V
MAX)
IN(FALLING, MAX)
open circuit. See the Applications Information section to
customize the LTM4641’s UVLO thresholds.
GND (A7-A12; B6-B8, B11-B12; C7-C8; D6-D8; E1-E8;
F1-F12; G1-G12; H3-H9, H11-H12; J5-J12; K5-K6, K11-
K12; L4-L6; ꢁ4-ꢁ6): Power ground pins for input and
output returns. See the Layout Checklist/Example section
of the Applications Information section. All GND pins are
electrically connected to each other, internally.
HYSTisalogic-highoutputwithmoderatepull-upstrength
that commands LTM4641’s internal control IC to regulate
the module’s output voltage when conditions on the RUN,
UVLO, OVLO, IOVRETRY, TEMP, CROWBAR, INTV and
CC
DRV pins permit it (any recent latchoff events notwith-
CC
UVLO (B4): Input Undervoltage Lockout Programming
Pin. The LTM4641 pulls HYST low to inhibit regulation
of its output voltage whenever UVLO is less than 0.5V.
The LTM4641 can resume switching action when UVLO
exceeds 0.5V. Do not leave this pin open circuit.
standing,otherwiseOTBHandLATCHcanalsoplayarole).
Whenafaultconditionisdetected,internalcircuitry(M
;
HYST
see Figure 1) drives HYST logic low and the LTM4641’s
output is turned off. HYST can be used as a fault-indicator.
See the Applications Information section.
If the LTM4641’s default UVLO settings are used,
HYST is pulled low when the RUN pin is pulled low, via
an internal Schottky diode. HYST can be driven low by
external open-collector/open-drain circuitry directly—as
an alternate to the RUN pin interface. However, external
circuitry should never drive HYST high, since doing so
(indiscriminately) could cause thermal overstress to
4.5V
and 4V
, then the UVLO
IN(RISING, MAX)
pin should be electrically connected to 1V
IN(FALLING, MAX)
or INTV .
CC
REF
Otherwise, see HYST and the Applications Information
section for using a resistor-divider network to implement
personalized UVLO rising and UVLO falling settings.
M
, when M
is on.
HYST
HYST
OVLO(B5):InputOvervoltageLatchoffProgrammingPin.
LTM4641 pulls HYST low to inhibit regulation of its output
voltage when OVLO exceeds 0.5V. If OVLO subsequently
falls below 0.5V, the module’s output remains latched
off; the LTM4641 cannot resume regulation of the output
TEꢁP (A5): Power Stage Temperature Indicator and
OvertemperatureDetectionPin.Whenleftelectricallyopen
circuit,TEMP’svoltagevariesaccordingtoaninternalNTC
(negative temperature coefficient) thermistor, residing in
close proximity to LTM4641’s power stage. When TEMP
falls below 438mV (corresponding to a thermistor and
power stage temperature of ~145°C), the LTM4641 pulls
HYST low to inhibit regulation of its output voltage. HYST
voltage until either the LATCH pin is toggled high or V
INL
is power cycled. If input overvoltage latchoff behavior is
not desired, electrically short this pin to SGND. Do not
leave this pin open circuit.
4641f
10
LTM4641
PIN FUNCTIONS
CROWBAR (B9): Crowbar Output Pin. Normally logic low,
with moderate pull-down strength to SGND.
If no latchoff faults are present when LATCH transitions
fromlogiclowtologichigh, theLTM4641immediatelyun-
latches. If any latchoff fault is present when LATCH is logic
high, a timeout delay timing requirement is imposed: the
LTM4641willnotunlatchuntilalllatchofffault-monitoring
pins meet operationally valid states for the full duration
of the timeout delay. If LATCH becomes logic low before
that timeout delay has expired, the LTM4641 remains
latched off and the timeout delay is reset. Unlatching the
LTM4641 can be reattempted by pulling LATCH logic high
at a later time.
When an output overvoltage (OOV) condition is detected,
theLTM4641’sfastOOVcomparatorpullsCROWBARlogic
high through a series-connected internal diode. If utilizing
LTM4641’s OOV feature, CROWBAR should connect to
the gate of a logic-level N-channel MOSFET configured to
crowbar the module’s output voltage (MCB, in Figure 1).
Furthermore, the LTM4641 latches off its output when
CROWBAR nominally exceeds 1.5V and latches HYST
logic low (see HYST).
The following are latchoff fault conditions:
•ꢀ CROWBARꢀactivatesꢀ(seeꢀCROWBAR)
•ꢀ Inputꢀlatchoffꢀovervoltageꢀfaultꢀ(seeꢀOVLO)
If not using the OOV protection features of the LTM4641,
leave CROWBAR electrically open circuit.
OV
(B10):OutputOvervoltageThresholdProgramming
PGꢁ
Pin. The voltage on this pin sets the trip threshold for the
inverting input pin of LTM4641’s fast OOV comparator.
When left electrically open circuit, resistors internal to the
•ꢀ Latchoffꢀovertemperatureꢀfaultꢀ(whenꢀOTBHꢀisꢀlogicꢀ
low; see TEMP and OTBH)
LATCHisahighimpedanceinputandmustnotbeleftelec-
trically open circuit. LATCH can be driven by a μController
in intelligent systems: a reasonable implementation for
unlatching the LTM4641 is to pull LATCH logic high for
themaximumanticipatedtimeoutdelaytime—afterwhich,
HYST can be observed to indicate whether the LTM4641
has become unlatched.
LTM4641nominallybiasOV
to666mV(OV )—11%
PGM
PTH
above the nominal V feedback voltage (600mV) that the
FB
controlloopstrivestopresenttothenoninvertinginputpin
of LTM4641’s fast OOV comparator. The aforementioned
voltages correspond proportionally to the module’s OOV
inception threshold and V ’s nominal voltage of regula-
OUT
tion, respectively. Altering the OV
voltage provides a
PGM
1V
(C6): Buffered 1V Reference Output Pin. Minimize
means to adjust the OOV threshold; its DC-bias setpoint
can be tightened with simple connections to external
components (see the Applications Information section).
Trace route lengths and widths to this sensitive analog
node should be minimized. Minimize stray capacitance to
this node unless altering the OOV threshold as described
in the Applications Information section and Appendix F.
REF
capacitance on this pin, to assure the OV
and TEMP
PGM
pinsareoperationalinatimelymanneratpower-up. 1V
REF
should never be externally loaded except as explained in
the Applications Information section.
V
(C9-C12; D9-D12; E9-E12): Power Output Pins of
OUT
the LTM4641 DC/DC Converter Power Stage. All V
pins
OUT
are electrically connected to each other, internally. Apply
output load between these pins and the GND pins. It is
recommended to place output decoupling capacitance
directly between these pins and the GND pins. Review
Table 9. See the Layout Checklist/Example section of the
Applications Information section.
LATCH (C5): Latchoff Reset Pin. When a latchoff fault oc-
curs, the LTM4641 turns off its output and latches M
HYST
on to indicate a fault condition has occurred (see HYST). To
configure the LTM4641 for latched off response to latchoff
faults, connect LATCH to SGND. As long as LATCH is logic
low, the LTM4641 will not unlatch. Regulation can be re-
+
+
sumed by cycling V or by toggling LATCH from logic low
INL
V
(D1): V
Readback Pin. This pin connects to
ORB
V
OSNS
+
to high. It is also permissible to connect LATCH to INTV ;
CC
internaltotheµModuleregulator.Itisrecommended
OSNS
–
this configures the LTM4641 for autonomous restart with a
to route this pin (differentially with V
) to a test point
ORB
timeout delay (programmed by C —see TMR).
TMR
so as to allow the user a way to confirm the integrity of
4641f
11
LTM4641
PIN FUNCTIONS
the remote-sense connections prior to powering up the
the LTM4641 control loop drives the differential voltage
+
+
–
LTM4641. V
can also be connected as a redundant
between V
and V
to the lesser of TRACK/
ORB
OSNS
OSNS
is connected to V
). A resistor may be needed from
for some output voltage settings. (See
+
+
+
SS and 0.6V. V
internal to
feedbackconnectiontoV
ontheuser’smotherboard.
OSNS
the module (see V
ORB
OSNS
+
–
–
ORB
V
(D2): V
Readback Pin. This pin connects to
ORB
V
OSNS
+
–
V
to V
–
OSNS
OSNS
internaltotheµModuleregulator.Itisrecommended
OSNS
the Applications Information section: Setting the Output
Voltage.) Minimize stray capacitance to this pin to protect
the integrity of the output voltage feedback signal.
+
to route this pin (differentially with V
) to a test point
ORB
so as to allow the user a way to confirm the integrity of
the remote-sense connections prior to powering up the
–
–
V
OSNS
(H2): Negative Input to the Remote Sense Dif-
LTM4641. V
feedbackconnectiontoV
can also be connected as a redundant
ORB
–
ferential Amplifier. This pin connects to the negative side
of the output voltage remote sense point (GND potential)
ontheuser’smotherboard.
OSNS
OTBH (D3): Overtemperature Behavior Programming
Pin. When an overtemperature condition is detected (see
TEMP), HYST pulls logic low to inhibit switching. If OTBH
is connected to SGND, the LTM4641 latches HYST low. If
OTBHisleftfloating,outputvoltageregulationcanresume
when the overtemperature event clears.
via a resistor (R
). When switching action is on,
SET1B
the LTM4641 control loop drives the differential voltage
+
–
between V
and V
to the lesser of TRACK/
OSNS
SS and 0.6V. V
OSNS
–
–
is connected to V
). A resistor may be needed from
internal to
OSNS
ORB
–
the module (see V
ORB
+
–
V
to V
for some output voltage settings. (See
OSNS
OSNS
the Applications Information section.) Minimize stray ca-
pacitance to this pin to protect the integrity of the output
voltage feedback signal.
TꢁR(D4):TimeoutDelayTimerandPower-OnReset(POR)
Programming Pin. Connect a capacitor (C
) from TMR
TMR
toSGNDtoprogramthePORandtimeoutdelaytimeofthe
LTM4641; 9ms delay time per nanofarad of capacitance.
The minimum delay time is ~90μs, when TMR is left
electrically open circuit. Even though they use the same
capacitor, the power-on reset and timeout delay timers
operate independently of each other. Any nonlatching fault
or latching fault will reset the respective timer to the full
delay time without impacting the other timer.
SW (H10): Switching Node of the Power Stage. Mainly
used for testing purposes, however, one may optionally
connect a snubber (series-configured capacitor C and
SW
resistorR )fromSWtoGNDtoreduceradiatedEMI—in
SW
exchange for a minor compromise to power conversion
efficiency. (See the Applications Information section.)
COꢁP(J1):CurrentControlThresholdandErrorAmplifier
CompensationPoint.Thecurrentcomparatorthresholdof
LTM4641’s valley current mode control loop—and corre-
spondingly, the commanded trough of the power inductor
current—increasesasthiscontrolvoltageincreases.Itcan
be useful to make COMP available for observation on a
PCB via or test pad with an oscilloscope probe. However,
straycapacitanceandtracelengthstothissensitiveanalog
node should be minimized.
The timeout delay time programmed by a C
capacitor
TMR
can be negated by pulling TMR to INTV .
CC
RUN (D5): Run (On/Off) Control Pin. A RUN pin voltage
below 0.8V will turn off the module. A voltage above 2V
will command the module to turn on, if HYST is not as-
. The LTM4641 contains a moderate
(10k) pull-up resistor from HYST to INTV , and a pull-up
Schottky diode from RUN to HYST (see Figure 1). When
RUN is pulled logic low, HYST is pulled logic low via the
internal Schottky diode. RUN is compatible with direct-
drive (totem-pole output drive) as well as open-collector/
open-drain interfaces.
serted low by M
HYST
CC
f
(J2): Switching Frequency Setting and Adjustment
SET
Pin. ThispininterfacesdirectlytotheI pinofLTM4641’s
ON
internal control IC. Current flow into the I pin programs
ON
theon-timeofthecontrolloop’sone-shottimerandpower
control MOSFET, M . Minimize stray capacitance and
+
TOP
V
OSNS
(H1): Positive Input to the Remote Sense Differ-
ential Amplifier. This pin connects to the positive side of
any tracelengths to this pin.
the output voltage remote sense point (V
potential) via
). When regulating the output voltage,
For applications requiring regulated output voltages of 3V
or less at any time including during voltage rail tracking,
4641f
OUT
a resistor (R
SET1A
12
LTM4641
PIN FUNCTIONS
an on-time adjustment with a resistor to f is required.
AnundervoltagelockoutdetectormonitorsDRV .HYSTis
SET
CC
Otherwise, f can be left open circuit. See the Applica-
pulledlowandswitchingactionisinhibitedifDRV isless
SET
CC
tions Information section for details.
than 4.2V rising (maximum) and 3.5V falling (maximum).
V
(J3): Input Voltage Pin, Low Current for Power
FCB(K2):ForcedContinuous/Pulse-SkippingModeOpera-
tion Programming Pin. Connect this pin to SGND to force
continuous mode operation of the synchronous power
INL
Control and Logic Bias. Feeds LTM4641’s internal 5.3V
LDO (see INTV ). Apply input voltage bias between this
CC
pin and GND. Decouple to GND with a capacitor (0.1µF
MOSFETs (M
and M ) at all output load conditions.
TOP
BOT
to 1µF). This pin powers the heart of LTM4641’s DC/DC
Connect this pin to INTV to enable pulse-skipping mode
CC
controller and internal housekeeping ICs. V bias cur-
operation: the freewheeling power switching MOSFET
INL
rent is within ~5mA of the sum of INTV and CROWBAR
(M ) is turned off of to prevent reverse flow of output
CC
BOT
loading currents.
current (I ) at light loads. See Appendix E for more
OUT
details. This is a high impedance input and must not be
Ifusingtheadvancedoutputovervoltage(OOV)protection
featuresoftheLTM4641,connectV toeitherthedrainof
left electrically open circuit.
INL
the external power-interrupt power MOSFET, identified on
the front page schematic as MSP, or a separate input bias
supply. If not making use of the advanced OOV protection
features, V and V can connect directly to the same
INTV (K4): Internal 5.3V LDO Output. LDO operates off
CC
of V . The INTVCC rail biases low power control and
INL
housekeeping circuitry. INTV is usually connected to
CC
DRV to power the MOSFET drivers interfacing to the
INL
INH
CC
input power source.
switching power MOSFETs. No decoupling capacitance is
needed on this pin unless it is being used to bias external
circuitry (not common); do not apply more than 4.7µF
( 20% tolerance) of external decoupling capacitance. The
LDO losses can be eliminated by connecting V , INTV ,
INL
CC
and DRV if a low power auxiliary ~5V rail is available to
CC
power the resulting node. (See the Applications Informa-
INTV /DRV pin pair can be overdriven by an external
CC
CC
tion section, Figure 47 and Figure 49.)
supply,fromupto6V(absolutemaximum)with50mApeak
sourcing capability, to eliminate power losses otherwise
incurredbytheLTM4641’sV -to-INTV linearregulator
DRV (J4):PowerMOSFETDriverInputPowerPin.DRV
CC
CC
isnormallyconnectedtoINTV .Itmustbekeptwithintwo
CC
INL
CC
diodeꢀdropsꢀ(2ꢀ•ꢀV or ~1.2V at 25°C) of INTV . DRV
(see the Applications Information section and Figure 51).
BE
CC
CC
powers the internal MOSFET driver that interfaces to the
V
(K7-10;L7-12;ꢁ7-8,11-12):InputVoltagePin,High
INH
switching MOSFETs (M
and M ) within LTM4641’s
TOP
BOT
Current to the Power Converter Stage of the LTM4641. All
power stage. It is pinned out separately from INTV to
CC
V
INH
pinsareelectricallyconnectedtoeachotherinternally.
allow gate-driver current to be observed, and to allow an
Devote a large copper plane to connect as many of the
pins to each other as is feasible. This will help form
auxiliary ~5V to 6V bias supply to optionally provide the
V
INH
MOSFET driver bias current. The INTV /DRV pin pair
CC
CC
a low impedance electrical connection between the input
sourceandtheLTM4641’spowerstage. Itwillalsoprovide
a thermal path for removing heat from the BGA package
and minimize junction temperature rise of the LTM4641
for a given application.
can be biased from up to 6V (absolute maximum) from
an external supply with 50mA peak sourcing capability, to
reduce the LTM4641’s INTV LDO losses (see Applica-
CC
tions Information section and Figure 51). When DRV is
CC
connected directly to INTV , no bypass capacitance is
CC
needed except in rare applications where very fast output
voltage ramp up is required (e.g., no soft-start capacitor
on TRACK/SS, or rail-tracking rails with sub-60µs turn-on
rise-time). Otherwise, ~2.2µF to 4.7μF X7R MLCC local
bypassing to GND is recommended. Higher impedance
sourcesmayrequirehigherbypasscapacitance,tomitigate
If utilizing the advanced output overvoltage (OOV) protec-
tion features of the LTM4641, connect V to the source
INH
pin(s)oftheexternalpower-interruptMOSFET,identifiedon
the front page schematic as MSP, with a short wide trace,
or preferably a small copper plane capable of adequately
DRV sag during V
start-up.
CC
OUT
4641f
13
LTM4641
PIN FUNCTIONS
handling the input current to LTM4641’s power stage.
SGND to obtain an output voltage soft-start ramp-up rate
whoseturn-ontimeis0.6mspernanofaradofcapacitance.
Alternatively, when a voltage is applied to TRACK/SS
through a resistor-divider network from another rail, the
LTM4641 output is able to track the external voltage to
satisfycoincidentandratiometricrail-voltagesequencing
requirements. See the Applications Information section.
DonotdecoupletheV pinswithanybypasscapacitance
INH
in this case. Instead, place all decoupling capacitance
directly between the drain of MSP to GND.
If not utilizing the advanced OOV protection features of
the LTM4641, do decouple the V
local ceramic and bulk decoupling capacitance (see the
Applications Information section).
pins to GND with
INH
V
(ꢁ9): Gate Drive Output Pin. If utilizing the advanced
ING
output overvoltage (OOV) protection features of the
PGOOD (L1): Output Voltage Power Good Indicator. This
is an open-drain logic output pin that is pulled to ground
whentheoutputvoltage(andaccordingly,thedivided-down
LTM4641, connect V to V and to the gate of the
externalpower-interruptN-channelMOSFETfeedingV
ING
INGP
,
INH
identified on the front page schematic as MSP; otherwise,
leave this pin electrically open circuit.
representation of the output voltage, V , as presented to
FB
the control loop) is outside 10% of the nominal target
for regulation.
V
(ꢁ10): Gate Drive Protection Pin. If utilizing the ad-
INGP
vanced OOV protection features of the LTM4641, connect
TRACK/SS (L2): Output Voltage Tracking and Soft-Start
Programming Pin. This pin has a 1.0μA pull-up current
source, typical. A capacitor can be placed from this pin to
V
toV andtothegateoftheexternalpower-interrupt
INGP
ING
N-channel MOSFET feeding V , MSP; otherwise, leave
INH
this pin electrically open circuit.
4641f
14
LTM4641
SIMPLIFIED BLOCK DIAGRAM
V
V
IN
OUT
V
INL
4V TO 38V
INTV
CC
(4.5V START-UP)
0.1µF
C
IN(MLCC)
1.3M
R
fSET
*
R
HYST
10k
HYST
UVLO
R
TUV
+
f
I
SET
ON
ENABLE
SWITCHING
ACTION
C
IN(BULK)
M
V
ING
HYST
R
BUV
MSP
V
15V
ZENER
INGP
POWER
CONTROL
V
INH
V
IN
2.2µF
M
M
TOP
0.8µH
SW
R
R
R
TOV
MOV
BOV
CONSTANT
ON-TIME
IOVRETRY
OVLO
PROTECTION
COMPARATORS
AND
V
OUT
V
OUT
VALLEY MODE
SYNCHRONOUS
BUCK
0.6V TO 6V
UP TO 10A
+
FAULT LATCHES
10µF
C
OUT(BULK)
CONTROLLER
1V
REF
BOT
C
OUT(MLCC)
3.48k
GND
TEMP
NTC
SGND
V
FB
TO E/A
OSC
OTBH
TMR
LATCH
FCB
C
C
TMR
FAST OUTPUT
OVERVOLTAGE
COMPARATOR
COMP
DRV
CC
CROWBAR
MCB
R
R
C
ENABLE
INTV
CC
PGOOD
TRACK/SS
1V
–
ORB
V
8.2k
–
8.2k
SET1B
V
OSNS
–
+
REF
SS
REF
INTERNAL
COMP
R
SET2
+
+
R
4µF
8.2k
8.2k
SET1A
V
OSNS
V
ORB
R
499k
1M
TOVPGM
OV
PGM
RSET1A 2•RSET1A
R
BOVPGM
C
VOUT = 0.6 1+
+
OVPGM
8.2kΩ
RSET2
RUN
USE R
= R
≤8.2k
SET1B
SET1A
R
SET2
R
SET2
REQUIRED FOR V
> 1.2V
OUT
OUT
NOT NECESSARY FOR V
≤ 1.2V
4641 F01
DASHED BOXES INDICATE OPTIONAL COMPONENTS
*R REQUIRED FOR CERTAIN V /V COMBINATIONS
fSET IN OUT
SEE APPLICATIONS INFORMATION SECTION
SGND CONNECTS TO GND INTERNAL TO MODULE, KEEP SGND
ROUTES/PLANES SEPARATE FROM GND, ON MOTHERBOARD
Figure 1. Siꢃplified Block Diagraꢃ. cf. Functional Block Diagraꢃ in Appendiꢂ A, Figure 62
DECOUPLING REQUIREMENTS
SYꢁBOL
PARAꢁETER
CONDITIONS
ꢁIN
TYP
ꢁAX
UNITS
C
C
+
External Input Capacitor Requirement
20
μF
I
= 10A, 2 × 10μF or 4 × 4.7μF
IN(MLCC)
IN(BULK)
OUT
C
C
+
External Output Capacitor Requirement
300
μF
I
= 10A, 3 × 100μF or 6 × 47μF
OUT(MLCC)
OUT(BULK)
OUT
4641f
15
LTM4641
OPERATION
Introduction
Power µꢁodule Regulator Reliability
TheLTM4641containsabuck-topologyregulatoremploy-
ing a constant on-time current mode control scheme,
including built-in power MOSFET devices with fast
switching speed and a power inductor. In its most basic
configuration (see Figure 45), the module operates as a
standalonenonisolatedswitchingmodeDC/DCstep-down
power supply. It can provide up to 10A of output current
with a few external input and output capacitors and output
feedback resistors. The supported output voltage range is
from0.6V DCto6V DC. The supported inputvoltage range
is4Vto38V,withamaximumstart-upvoltageof4.5V(over
temperature).Powerconversionfromlowerinputvoltages
can be realized if an auxiliary bias supply is available to
powerLTM4641’scontrolandhousekeepingbiasinputpin,
First and foremost, Linear Technology μModule products
adhere to rigorous testing and high reliability control,
fabrication, andmanufacturingprocesses—asisrequired
of all its products. Furthermore, as part of its commit-
ment to excellence, the Linear Technology Quality Control
program periodically updates its Reliability Data report
for LTM4600 series products to include cumulative data
obtained from ongoing and routine in-house testing relat-
ing to operational life, highly accelerated stress, power
and temperature cycling, thermal and mechanical shock,
and much more. To view the latest report visit http://www.
linear.com/docs/13557.
The LTM4641 easily supports high step-down ratios
with few external components. The additional protection
features when implemented provide an extra degree of
insurance beyond other μModule regulators.
V
. The LTM4641 Simplified Block Diagram is found in
INL
Figure 1. For a more detailed look, the Functional Block
Diagram is found in Appendix A, Figure 62.
Overview
ꢁotivation
When configured as shown in Figure 46, the LTM4641
can regulate an output voltage between 0.6V and 6V from
Pulsed loading conditions and abnormal disturbances
within the electrical systems found in industrial, vehicle,
aeronautic, and military applications can induce wildly
varying voltage transients (surges) on what is nominally
a 24V DC to 28V DC distributed bus (28V DC bus). The
duration of such disturbances can extend for periods of
time between a millisecond to a minute in length, with
excursions sometimes reaching (or exceeding) 40V and
falling below 6V.
an input voltage between 4V and 38V (4.5V start-up,
IN
maximum).
If an optional N-channel power MOSFET, MSP, is placed
between the input power source (V ) and the power
IN
stage input pins (V ), MSP’s role becomes that of a
INH
resettable electronic power-interrupt switch. The gate of
MSP is operated by V , and its gate-to-source voltage
ING
is assured to be clamped by a built-in 15V Zener diode
While switching buck regulators are of universal inter-
est due to their compact size and ability to deliver DC/
DC power conversion at high efficiency, FMEA (failure
modes and effects analysis) leads one to believe that
there is no way to reduce the severity rating and effects
of an electrical short from the input source to the output
load—howeverimprobable.TheLTM4641challengesthis
notion by protecting the load from seeing excessive volt-
age stress, even when its high side switching MOSFET
is short circuited.
accessed via V
. When switching action is engaged,
INGP
V
V
charges the gate of MSP to nominally 10V above
ING
INH
potential—suitablefordrivingastandard-logicMOS-
FET—and MSP becomes enhanced to pull V up to the
INH
input source supply’s electrical potential. The switching
regulator steps down V potential to V
when MSP is
INH
OUT
on. When switching action is inhibited by pulling the RUN
pin low or when a fault condition is detected by LTM4641’s
internal circuitry—such as an output overvoltage (OOV)
condition—the gate of MSP is discharged and MSP turns
off. The input source supply is thus disconnected from
LTM4641’s power stage input (V ).
INH
4641f
16
LTM4641
APPLICATIONS INFORMATION—POWER SUPPLY FEATURES
The operation of MSP as a power interrupter provides a
critical element of robust OOV protection: it removes a
means for input power to flow through a damaged power
stagetoanypreciousloadsontheoutputvoltagerail, even
when input power is cycled.
•ꢀ Selectableꢀpulse-skippingꢀmodeꢀoperation
•ꢀ Outputꢀvoltageꢀsoft-startꢀandꢀrailꢀtracking
•ꢀ Power-upꢀintoꢀpre-biasedꢀconditionsꢀwithoutꢀsinkingꢀ
current from the output capacitors
•ꢀ Adjustableꢀswitchingꢀfrequency
•ꢀ Powerꢀgoodꢀindicator
•ꢀ RUNꢀenableꢀpin
For even greater resilience to a short-circuit between V
INH
andtheSWswitchingnodeofthepowerstage, anexternal
logic-level N-channel power MOSFET, MCB, is optionally
placed—in a crowbar configuration—on the output of
the power module. When an OOV condition is detected,
CROWBAR turns on MCB (within 500ns, maximum) to
dischargetheoutputcapacitorsandtransformanyresidual
energy in LTM4641’s power stage into a trivial amount of
heat—energy which would otherwise have only served
to inject charge into (further pump up the voltage on) the
output capacitors, where precious loads reside.
Novel and simple circuit implementations with LTM4641
and a few external components enable surge ride-
through protection and overtemperature detection of a
power-interrupt MOSFET. (See Figure 47, for example.)
The aforementioned features enabled by LTM4641 are
grouped by function and described in the remainder of
the Applications Information section.
The control and monitoring circuitry within the LTM4641
power module provide the following:
Power (V ) and Bias (V ) Input Pins
INH
INL
LTM4641’s power stage (VINH) and control bias (VINL
)
•ꢀ Fast,ꢀ accurate,ꢀ latchingꢀ outputꢀ overvoltageꢀ detectorꢀ
input pins are brought out separately to allow freedom
for implementing more sophisticated system configura-
tions, such as: fully utilizing LTM4641’s advanced output
overvoltage (OOV) protection features to protect the load
(e.g., front page schematic or Figure 46); providing rudi-
mentary input surge ride-through protection (Figure 47);
performing DC/DC down conversion from a power rail
below LTM4641’s inherent UVLO thresholds (from a 3.3V
bus in Figure 49).
(<500ns response time, < 12mv threshold error)
•ꢀ N-channelꢀoutputꢀovervoltageꢀcrowbarꢀpowerꢀMOSFETꢀ
drive
•ꢀ Accurateꢀ(<±2.4%)ꢀnonlatchingꢀandꢀresettableꢀlatchingꢀ
input overvoltage shutdown thresholds
•ꢀ N-channelꢀovervoltageꢀpower-interruptꢀMOSFETꢀdrive
•ꢀ Accurateꢀ(<±2.4%)ꢀInputꢀUVLOꢀrisingꢀandꢀUVLOꢀfallingꢀ
thresholds
If V
and V are powered from separate rails, it is
INL
INH
recommended to power up V prior to or concurrently
•ꢀ Built-inꢀ andꢀ adjustableꢀ overtemperatureꢀ shutdownꢀ
protection, programmable for resettable latching or
nonlatching (hysteretic restart) response
INL
with V . V should have a final value of at minimum
INH INL
3.5V within 2ms of V exceeding 3.5V. The recommen-
INH
INL
dation to sequence V ahead of or closely with V is
INH
•ꢀ Analogꢀtemperatureꢀindicatorꢀoutputꢀpin
not related at all to module device reliability but stems
rather from a desire to assure that the control section of
LTM4641 drives the MOSFETs in LTM4641’s power stage
•ꢀ Adjustableꢀpower-onꢀresetꢀandꢀtimeoutꢀdelayꢀtime
•ꢀ Latchoffꢀbehaviorꢀthatꢀcanꢀbeꢀalteredꢀtoꢀinsteadꢀprovideꢀ
deterministically whenever any appreciable V voltage
INH
autonomous restart after timeout delay time expires
is present. It is always permissible for V voltage to be
INL
•ꢀ Parallelableꢀforꢀhigherꢀoutputꢀpower
•ꢀ DifferentialꢀremoteꢀsensingꢀofꢀPOLꢀvoltage
•ꢀ Internalꢀloopꢀcompensation
present—regardlessofthestateofV —however,realize
INH
that there is no UVLO detection on V
.
INH
To prevent the control section from trying to regulate
through a dropout condition or commencing switching
•ꢀ Outputꢀcurrentꢀfoldbackꢀprotection
activityintheabsenceofV potential,itisrecommended
INH
4641f
17
LTM4641
APPLICATIONS INFORMATION—POWER SUPPLY FEATURES
to implement a custom UVLO falling setting above the
dropout curve in Figure 4 (see also Figure 11).
scheme. During a load transient step-up, the control
loop will command a higher inductor trough current to
compensateforadeficiencyinoutputvoltage;theeffective
switching frequency will increase until the output voltage
returnstonormal(anovercurrentevent,notwithstanding).
During a load transient step-down, the control loop will
command a lower inductor trough current to compensate
for an excess of output voltage; the effective switching
frequency will decrease until the output voltage returns to
normal.Thecontrolloopperceivesinductorcurrent-sense
information via the voltage signal that appears across the
LT3010-5 is shown in Figure 47 to provide bias for V
,
INL
to enable ride-through of 80V transients on V . UVLO
IN
detection of V is realized in this example by D2 creating
IN
a discharge path for V in the event of loss of V .
INL
IN
V
and V have no specific power-down sequencing
INL
INH
requirement, only that V should stay above 3.5V when-
INL
ever V is above 3.5V.
INH
V
and V sequencing is inherently addressed by the
INH
INL
synchronous power MOSFET, M , when M
is on
BOT
BOT
LTM4641 in the Figure 45 and Figure 46 circuits.
(this is commonly referred to in the industry as R
DS(ON)
The V and V start-up and shutdown waveforms of
IN
INL
current sensing).
the Figure 47 circuit—but with 1Ω output load and TMR
The on-time of the one-shot timer—and hence the power
tied to INTV —are shown in Figure 2. The effect of the
CC
control MOSFET, M ,—is given, in units of seconds, by:
TOP
timingcapacitor,C ,thatnormallygeneratesapower-on
TMR
reset (POR) delay at start-up is negated by tying TMR to
0.7V •10pF
tON
=
(1)
INTV . The ~3ms V -to-V start-up delay time seen in
CC
IN
OUT
IION
Figure 2 is due to POR of the LTM4641’s fault-monitoring
circuitry and soft-start ramp (C ).
SS
where I
is in units of amperes. For output voltages
ION
greater than 3V, and for non-rail-tracking applications,
no external R resistor is needed, and the I current
fSET
ION
V
IN
(units: amperes) is set solely by the V voltage (units:
5V/DIV
INL
volts) and the internal 1.3MΩ V -to-f resistor:
INL
SET
V
INL
5V/DIV
V
INL
I
=
(2)
ION
V
1.3MΩ
OUT
500mV/DIV
The switching frequency of operation of the LTM4641’s
buck converter power stage at full load in this scenario
is given, in Hz, by:
4641 F02
2ms/DIV
Figure 2. Start-Up and Shutdown Waveforꢃs of Figure
47 Circuit. TꢁR Tied to INTVCC to Highlight VIN and VINL
Sequencing without POR Delay. 1Ω Load
VOUT
fSW
=
(3)
0.7V •1.3MΩ•10pF
is the desired nominal output voltage, in units
OUT
Switching Frequency (On Tiꢃe) Selection and Voltage
Dropout Criteria (Achievable V -to-V
Step-Down
where V
of volts.
IN
OUT
Ratios)
TheLTM4641controlleremploysacurrentmodeconstant
on-time architecture, in which the COMP voltage corre-
spondstothetroughinductorcurrentatwhichtheinternal
AnexternalR
resistorcanbeappliedwhensettingV
fSET OUT
greater than 3V, if desired, to obtain increased switching
frequency.Usually,increasingswitchingfrequencycomes
fromadesiretoreduceoutputvoltagerippleand/oroutput
capacitance requirement—but at a moderate penalty to
DC/DC conversion efficiency. There are some limitations
high side power MOSFET (M ) is commanded on by
TOP
the control loop—for a duration of time proportional to
controller’s I pin current (Refer to Figure 1). Regulation
ON
is maintained by a pulsed frequency modulation (PFM)
to how low an R
value can be applied in practice due
fSET
4641f
18
LTM4641
APPLICATIONS INFORMATION—POWER SUPPLY FEATURES
•ꢀ Whenꢀ V
and V
are operated from separate
to non-zero minimum off-time, dropout voltage, and
maximum achievable switching frequency of operation.
INL
supplies…
INH
…whyshouldR
ordinarilyconnecttotheV power
INH
When an R
resistor external to the LTM4641 is con-
fSET
IN
fSET
source rather than V (Figure 49)?
nected between V
and f
to decrease the default
INL
SET
on-time setting, the total I current (units: amperes) is
given by:
ON
…when is it okay for R
(Figure 47)?
to connect to V
INH
fSET
V
V
V
INL
INL
INL
For application circuits of the form found in Figure 45,
Figure 46, Figure 47 and Figure 51: see Figure 3 for the
maximum recommended value of R
of nominal target output voltage, and resulting full-load
switching frequency corresponding to those R values.
I
=
+
=
(4)
ION
1.3MΩ RfSET 1.3MΩ||RfSET
as a function
fSET
whereV isin units of volts andR
is in unitsof ohms.
INL
fSET
R
fSET
is needed for output voltage settings less than or
equal to 3V , and for rail-tracking applications.
fSET
OUT
Figure 3 can also be interpreted to provide the lowest
recommended switching frequency for a given target
output voltage. Table 1 summarizes nominal values of
Theminimumon-timetheLTM4641supportsis43ns,typi-
cal, but guard banded conservatively to 75ns, maximum.
Therefore, for a conservative design, t should be larger
ON
R
endorsed for some popular output voltages; use
fSET
than 75ns, typical. From Equation 1, it follows that I
ION
of commonly available 5% tolerance resistors or better
with 100ppm/°C temperature coefficient or better is
recommended.
should be designed to be less than 93.3μA.
When an external R
resistor is applied between V
INL
fSET
and R
(and V and V are operating from the same
fSET
INL INH
rail—Figure 45 and Figure 46), the switching frequency of
100
50
700
600
500
400
300
200
100
0
operation of the power stage at full load, in Hz, is given by:
R
NOT
fSET
R
vs V
OUT
fSET
NEEDED FOR
> 3V
REGION
V
OUT
TO AVOID
VOUT
fSW
=
(5)
is the desired nominal
0.7V • 1.3MΩ||R
•10pF
(
)
10
5
fSET
where R
is in ohms, and V
fSET
OUT
output voltage, in units of volts.
1
0.5
In the general case, the switching frequency of the buck
converter power stage at full load is given, in Hz, by:
MAX RECOMMENDED R
fSET
SWITCHING FREQUENCY
2.5 3.5 4.5 5.5
NOMINAL OUTPUT VOLTAGE (V)
0.1
VOUT
INH •tON
VOUT • I
ION
VINH •0.7V •10pF
0
0.5
1
1.5
2
3
4
5
6
fSW
=
=
(6)
V
4641 F03
See Appendix C for a detailed discussion on the following
topics:
Figure 3. ꢁaꢂiꢃuꢃ Recoꢃꢃended RfSET (Noꢃinal Values) for
Non-Tracking Applications, and Resulting Full-Load Operating
Switching Frequency vs Noꢃinal Output Voltage
•ꢀ Whyꢀshouldꢀtheꢀswitchingꢀcontrollerꢀbeꢀoperatedꢀatꢀaꢀ
higher switching frequency (i.e., programmed for a
shorter on-time with R ) than that yielded by the
fSET
internal 1.3MΩ V -to-f resistor alone…
INL
SET
…for nominal output voltages of 3V and less?
…in rail-tracking applications?
4641f
19
LTM4641
APPLICATIONS INFORMATION—POWER SUPPLY FEATURES
where:
Table 1. Endorsed RfSET Resistor Value vs Output Voltage for
Non-Tracking Applications—and Resulting Full-Load Switching
Frequency (cf. Figure 45, Figure 46, Figure 47, and Figure 51
Circuits)
•ꢀ V
is nominal output voltage in volts.
OUT
•ꢀ t
is the minimum length of time M
can
OFF(MIN)
BOT
R
fSET
(ꢁΩ) (Nearest
be on, after M
turns off. For a conservative de-
TOP
V
(V)
EIA-Standard Values)
f
(kHz)
SW
OUT(NOꢁ)
sign, use a value of 300ns, taken from the Electrical
Characteristics Table.
0.6
0.787
175
0.7
0.8
0.9
1.0
1.2
1.5
1.8
2.0
2.5
0.825
200
215
235
255
285
315
325
330
335
0.887
•ꢀ t is the on-time of the power control MOSFET,
ON
0.931
M
, as programmed by the current flowing into
ON
TOP
1.00
the I pin of LTM4641’s internal control IC.
1.13
•ꢀ R is the series resistance of the module’s power
PS
1.43
stage, from V to V . For V ≥ 6V, this is less
INH
OUT
IN
2.00
than 50mΩ, even at extreme temperatures (T ≈
J
2.55
125°C). For V < 6V, the effective series resistance
IN
5.76
increases due to drop in INTV voltage and cor-
CC
Greater Than 3.0
∞ (Not Used)
∞ (Not Used)
∞ (Not Used)
∞ (Not Used)
See Figure 2
360
responding decreased gate-drive enhancement of
3.3
5.0
6.0
M
. Printed circuit board (PCB) and/or cable
TOP
550
resistancepresentinthecopperplanesand/orwires
that physically connect the output of the module to
660
the load adds to R ’s effective value.
PS
In rail-tracking applications, it is recommended to use the
value corresponding to the lowest voltage needed
•ꢀ I
is the load current on V
in amperes.
R
fSET
OUT
OUT
to be regulated during output voltage ramp down. For
example: to ramp V down to 0.5V requires R to be
For applications of the form shown in Figure 45, Fig-
OUT
fSET
ure 46 and Figure 47: the minimum allowable V
INH
OUT
not more than 750kΩ (nominal) per Figure 3.
voltage of operation to avoid dropout for 3V < V
≤ 6V is shown in Figure 4. The curves are a result of
It is often permissible to use lower R values than those
fSET
realizing that V
equals V
(neglecting
indicated in Figure 3 and Table 1 if, for example, lower
output ripple voltage and/or a lower output capacitance
is desired. However, be aware of three guiding principles:
IN(DROPOUT)
INH
MSP voltage drop) when dropout actually occurs, and
that Equations 1 and 2 yield an expression for t as
ON
a function of V . M
will be less fully enhanced
INH
TOP
I. Minimum On-Time. Ensure I
tions 1 and 4.
< 93.3µA. See Equa-
ION
during its on-time if DRV is less than its nominal
CC
value of 5.3V (for example, when V < 6V and when
INL
II. Minimum Off-Time and Dropout Operation. The mini-
mum off-time, t , is the shortest time required
DRV bias is provided by INTV ). DRV ’s effect on
CC
CC
CC
R
PS
at low line is illustrated in Figure 4.
OFF(MIN)
for the LTM4641 to perform the following tasks: turn
on its power synchronous MOSFET (M ), trip the
III. Maximum Attainable f . The maximum attainable
SW
BOT
switching frequency of operation (in units of Hz) for a
control loop’s current comparator, and turn off M
.
BOT
givenon-time(t ,inseconds)isgovernedsimplyby:
ON
The minimum input voltage on V , in volts, that one
INH
1
can regulate the output at and still avoid dropout is
fMAX
=
(8)
given by:
tON + tOFF(MIN)
t
OFF(MIN)
where a conservative value of 300ns can be used for
V
IN(DROPOUT) = VOUT • 1+
+RPS •IOUT (7)
tON
t
.
OFF(MIN)
4641f
20
LTM4641
APPLICATIONS INFORMATION—POWER SUPPLY FEATURES
8.0
It is best to avoid operation in dropout scenarios, because
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
the control loop will rail COMP high to command M
TOP
at highest possible duty cycle. If input voltage “snaps
upwards” at a sufficiently high slew rate when COMP has
railed, the control loop may be unable provide satisfactory
line rejection.
SeeFigure11tosettheUVLOfallingresponseofLTM4641
above the computed V
voltage; this will inhibit
. Input voltage
IN(DROPOUT)
IN(DROPOUT)
switching action for V < V
IN
ripple, and any line sag between the input source supply
and the V pins—and voltage drop across the power
3
3.5
OUTPUT VOLTAGE SETTING (V)
10A OUTPUT, DRV BIASED FROM INTV (5.3V
4
4.5
5
5.5
6
4641 F04
INH
interrupt MOSFET, MSP, if used—must be taken into ac-
count by the system designer.
)
CC
CC
NOM
10A OUTPUT, DRV BIASED TO 5.3V BY EXTERNAL SUPPLY
NO LOAD, DRV ≥ 4.2V(UVLO RISING) AND 3.5V
CC
(UVLO FALLING)
CC
Setting the Output Voltage; the Differential Reꢃote
Sense Aꢃplifier
Figure 4. Line Dropout Voltage vs Output Voltage at No
Load and Full Load. Figure 45, Figure 46 and Figure 47
Circuit Applications. RfSET = Open and RSET1A, RSET1B
,
Abuilt-indifferentialremote-senseamplifierenablespreci-
sion regulation at the point-of-load (POL), compensating
for any voltage drops in the system’s output distribution
path: the total variation of LTM4641’s output DC voltage
over line, load, and temperature is better than 1.5%.
RSET2 Values Setting VOUT for Regulation at or Above 3V
GiventhatthePFMcontrolschemeincreasesswitching
frequency (to as high as f ) to maintain regulation
MAX
during a transient load step-up, the design guidance
is: set the steady-state operating frequency f to be
SW
The basic feedback connection between the POL and the
module’s feedback sense pins is shown in Figure 5.
less than f
. Furthermore, when the LTM4641 is
in dropout operation, the switching frequency of the
MAX
converter is f
.
MAX
C
, C : FEEDFORWARD CAPACITORS YEILD IMPROVED TRANSIENT
FFA FFB
RESPONSE WHEN FILTERING V
WITH ONLY MLCC OUTPUT CAPACITORS
OUT
(C
)
OUT(MLCC)
V
OUT
+
V
OUT
+
LTM4641
C
FFA
C
C
OUT(MLCC)
OUT(BULK)
ICT
TEST
POINT
V
ORB
R
8.2k
8.2k V
SET1A
V
+
FB
OSNS
TO ERROR
+
AMPLIFIER
R
LOAD
SET2
8.2k
R
SET1B
–
–
–
V
OSNS
8.2k
4641 F05
C
ICT
TEST
POINT
FFB
V
ORB
TRUE DIFFERENTIAL REMOTE
SENSE AMPLIFIER
SGND
GND
ROUTE FEEDBACK SIGNAL AS
A DIFFERENTIAL PAIR (OR
TWISTED PAIR IF USING WIRES).
SANDWICH BETWEEN GROUND
PLACE ALL
FEEDBACK
COMPONENTS
LOCAL TO THE
LTM4641
PLANES TO FORM A PROTECTIVE SHIELD
GUARDING AGAINST STRAY NOISE
SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP
MODULE SGND ROUTES/PLANES SEPARATE FROM GND
ON MOTHERBOARD
Figure 5. Basic Feedback Reꢃote Sense Connections and Techniques; Setting the Output Voltage
4641f
21
LTM4641
APPLICATIONS INFORMATION—POWER SUPPLY FEATURES
The output voltage at the POL is differentially sensed via
a symmetrical impedance-divider network. In Figure 1
and Figure 5, it is seen that the control loop regulates the
Use of 0.1% tolerance resistors (or better) for R
,
SET1A
R
, and R
are recommended—with temperature
SET1B
SET2
coefficientsofresistancesuitableforone’soperatingrange
of PCB temperature—to assure that output voltage error
introduced by resistor value variation is acceptable for the
application. SMT resistors with T.C.R.s of 25ppm/°C and
better are readily available in the marketplace.
+
–
outputvoltagesuchthatthedifferentialV
-to-V
OSNS
OSNS
feedback signal voltage is the lesser of the TRACK/SS
pin voltage or the regulator’s nominal bandgap voltage
of 600mV. The arrangement and values of the resistors
in the symmetrical impedance-divider network set the
output voltage.
For output voltage settings less than or equal to 1.2V
,
OUT
R
SET2
is not needed, and R
and R
are given by:
SET1A
SET1B
+
–
The remote sense pins (V
, V
) have redundant
OSNS
OSNS
V
0.6V
+
OUT
connectionsinternaltothemoduletoreadbackpins(V
,
RSET1A =RSET1B
=
–1 •8.2kΩ
ORB
(9)
–
V
). The readback pins provide a means to verify the
ORB
integrity of the feedback signal connection during moth-
erboard ICT (in circuit test). The importance of verifying
the integrity of the connection of the feedback signal to
the output voltage prior to powering up the input voltage
cannot be understated. If one or both feedback pins are
left electrically floating due to manufacturing assembly
defect, for example, or if the remote-sense pins are short
circuited to each other, the control loop and overvoltage-
detector circuitry have no awareness of the actual output
voltage condition. A compromised feedback connection
presents a very real danger of (1) the control loop com-
For output voltages above 1.2V , R
(and R
)
OUT SET1A
SET1B
should be set equal to 8.2kΩ (or less, if 8.2kΩ is not a
convenient value for the user), and
is then given by:
RSET2
2•RSET1A
RSET2
=
(10)
VOUT RSET1A
–
−1
0.6 8.2kΩ
It is always permissible to select a value for R
(and
SET1A
R
) less than that given by Equation 9—and then
SET1B
calculate a valid value for R
from Equation 10—as
SET2
long as R
higher resulting power dissipation.
and R
are designed to withstand the
SET1A
SET1B
manding on M at the highest possible duty cycle—due
TOP
to the lack of negative feedback—and (2) the LTM4641’s
protection circuitry being unaware of any issue. In a pro-
ductionenvironment,moderndayICTcaneasilycatchany
such stuffing or assembly errors; in a lab or prototyping
environment, an ohmmeter can do the job.
+
When V
OSNS
is in regulation, the voltages at V
and
OSNS
OUT
are given by:
–
V
0.6V
∆VGND
+
VVOSNS
=
+
(11)
8.2kΩ||RSET1A ||RSET2
R
(
)
SET1A
For many applications that use a mixture of MLCC and
bulk(lowESRtantalumorpolymer)outputcapacitors, the
symmetrical impedance-divider network that feeds back
the POL’s voltage to the module need only be constructed
• R
(
||16.4kΩ
)
SET1A
and
with resistors R
and R
SET2
, for output voltages
SET1A
and lower. R
SET1B
–
+
of 1.2V
must be present for output
V
= V
– 0.6V
(12)
OUT
VOSNS
VOSNS
voltages in excess of 1.2V . R
and R
should
SET1B
OUT SET1A
respectively. ∆V
is the voltage drop between ground at
GND
always have the same nominal value. Applications with
MLCC-only output capacitors (see Output Capacitors
and Loop Stability in following pages) will demonstrate
improved transient response when feedforward capaci-
the POL and LTM4641’s SGND pins in volts. This voltage
dropꢀisꢀusuallyꢀentirelyꢀaꢀresultꢀofꢀIꢀ•ꢀRꢀdropꢀinꢀtheꢀoutputꢀ
distribution path—largest when maximum load current
is being drawn:
tors C and C , nominally equal in value, are installed
FFA
FFB
∆V
= V
– V
SGND(LTM4641)
(13)
electricallyinparallelwithR
andR ,respectively.
SET1B
GND
GND(POL)
SET1A
4641f
22
LTM4641
APPLICATIONS INFORMATION—POWER SUPPLY FEATURES
WithR
,R
,andR
determined,double-check
closeinproximitytothemoduleaspossible(seeFigure43).
If external MOSFET MSP is not used (Figure 45), two 10μF
or four 4.7μF ceramic capacitors should be electrically
SET1A SET1B
the output voltage setting with:
SET2
RSET1A 2•RSET1A
8.2kΩ
connected directly between the V
and GND pins. If
VOUT = 0.6V • 1+
+
INH
(14)
RSET2
MSP is used (Figure 46, Figure 47 and Figure 49), then
MSP must be placed as close to the LTM4641’s V pins
INH
SomerecommendedvaluesforR
for popular output voltages are shown in Table 2.
,R
,andR
SET2
SET1A SET1B
as possible, and two 10μF or four 4.7μF ceramic capaci-
tors should be electrically connected directly between the
drain of MSP and GND (see Figure 44). A 47μF to 100μF
surface mount bulk capacitor can be used to supplement
input power bypassing, and can share the burden of any
local ceramic capacitors in filtering the power stage’s
ripple current. If low impedance power planes are used
Table 2. Recoꢃꢃended RSET1A, RSET1B and RSET2 Values
for Soꢃe Popular Output Voltages, cf. Figure 5 Feedback
Connections.
V
OUT
R
, R
R
SET2
SET1A SET1B
0.6V
0.7V
0.8V
0.9V
1.0V
1.2V
1.5V
1.8V
2.0V
2.5V
3.3V
5.0V
6.0V
0Ω
∞ (Not Used)
∞ (Not Used)
∞ (Not Used)
∞ (Not Used)
∞ (Not Used)
∞ (Not Used)
33.2kΩ
1.37kΩ
2.74kΩ
4.12kΩ
5.49kΩ
8.2kΩ
8.2kΩ
8.2kΩ
8.2kΩ
8.2kΩ
8.2kΩ
8.2kΩ
8.2kΩ
to bring V to the vicinity of the module, input source
IN
impedance will be low enough that bulk capacitors will
not be needed. A localized bulk input capacitor is needed
when an underdamped LC-resonant tank is formed by
routing long input leads or traces (low ESR inductance)
bypassed only with MLCCs (ultralow ESR capacitance).
16.5kΩ
Neglecting the inductor peak-to-peak current ripple, the
RMS current of the input capacitor can be estimated as:
12.4kΩ
7.5kΩ
I
ICIN(RMS)
=
OUT(MAX) • D• 1–D
(15)
4.7kΩ
(
)
2.61kΩ
η
2.05kΩ
whereη isthepowerconversionefficiencyoftheLTM4641
See Appendix D for a detailed discussion on the following
topics:
module and D is the duty cycle on-time of M . The bulk
TOP
capacitor can be a switcher-rated electrolytic aluminum
capacitor or a polymer capacitor.
•ꢀ Whatꢀisꢀtheꢀrationaleꢀforꢀusingꢀaꢀsymmetricalꢀresistorꢀ
network?
For a buck converter, the switching duty cycle of M
can be estimated as:
TOP
•ꢀ WhatꢀshouldꢀIꢀdoꢀifꢀIꢀcannotꢀshieldꢀtheꢀdifferentialꢀsenseꢀ
feedbacklineswithGND?(Ianticipatedifferentialmode
noise in the feedback signal?)
VOUT
D=
(16)
V
IN
•ꢀ WhatꢀshouldꢀIꢀdoꢀifꢀtheꢀmoduleꢀandꢀtheꢀload(s)ꢀareꢀ
separated by a significant distance (~50cm or more),
or if the load current flows through a cable assembly
or power connector? (I anticipate common mode noise
in the feedback signal?)
Output Capacitors and Loop Stability/Loop
Coꢃpensation
The current mode constant on-time architecture enables
very high step-down input-to-output ratios with compel-
ling transient response. It also enables cycle-by-cycle fast
current limit and foldback current limit in an overcurrent
condition.TheLTM4641isinternallycompensatedtoyield
stability over all operating conditions.
Input Capacitors
The LTM4641 module should be connected to a low AC
impedance, nominally DC output voltage source. MLCC
input bypass capacitors must be provided externally, as
4641f
23
LTM4641
APPLICATIONS INFORMATION—POWER SUPPLY FEATURES
The output capacitors C
and C
must
Pulse-Skipping ꢁode vs Forced Continuous ꢁode
OUT(BULK)
OUT(MLCC)
be chosen with low enough effective series resistance
(ESR) to meet the output voltage ripple requirements
and provide localized bypassing for the load. Although
the LTM4641 provides fast transient response, the output
voltage at the POL is reliant on nearby charge stored in a
In applications where high DC/DC conversion efficiency
at light-load currents is highly desired—when the input
voltage source is a battery, for example—pulse-skipping
modeoperationshouldbeemployed.Pulse-skippingmode
operation prevents power flow from the output capacitors
reservoir of ceramic capacitors C
to minimize
OUT(MLCC)
to the input source. Be aware, however, due to M ’s re-
BOT
sag and overshoot in the initial microseconds of a high
dI/dt transient load step-up and step-down, respectively.
sulting asynchronous operation at light load, applications
employing pulse-skipping mode may necessitate more
If used, C
can be comprised of low ESR tantalum
OUT(BULK)
output capacitance and/or a higher OV
setting than
PGM
or low ESR polymer capacitor(s); these capacitors then
serve as a local reservoir to replenish the MLCCs during
operation in forced continuous mode would.
Pulse-skipping mode is activated by connecting FCB to
transient load events. It is also possible to use C
OUT(MLCC)
INTV . Forced continuous operation is activated by con-
only, however, the use of feedforward capacitors, C ,
CC
FF
necting FCB to SGND.
shouldthenbeinstalledintheremote-sensefeedbackpath,
to obtain an optimized transient response (see Figure 5
feedback connections).
Be aware that in pulse-skipping mode and ultralight loads
(say, less than 20mA out), the V voltage may appear as
ING
a sawtooth waveform as a result of being charge-pumped
The C
ceramic capacitors should be at least
OUT(MLCC)
at a slower rate, to conserve energy.
X5R-type material. X5R-type and X7R-type MLCCs are
recommended when operating PCB temperatures are not
more than 85°C and 125°C, respectively. Both materials
are renown in the industry for having a relatively low ca-
pacitance change over their respective temperature range
of operation ( 15%). However, X5R and X7R MLCCs do
exhibit significant loss of capacitance with applied DC
voltage and are subject to aging effects, and this must
be taken into account in any system design. Refer to the
capacitor manufacturer’s specifications for details.
SeeAppendixEformoreinformationonhowpulse-skipping
mode works.
Soft-Start, Rail-Tracking and Start-Up Into Pre-Bias
The TRACK/SS pin can be used to either soft-start the
output of the LTM4641 regulator, or make LTM4641’s
output voltage track another rail coincidentally or ratio-
metrically. When RUN or HYST is low, the TRACK/SS
pin is discharged. When RUN and HYST are released,
TRACK/SS sources a microamp of current.
The typical output capacitance range is between 200μF
to 800μF. The system designer should use discretion in
determining whether additional output filtering may be
needed, if further reduction of output ripple—or output
voltage deviation during dynamic load or line transient
events—is required.
When a soft-start capacitor, C , is applied to the pin, the
SS
currentsourceisresponsibleforgeneratinganoutputvolt-
age turn-on time of 0.6ms per nanofarad of capacitance.
The power stage is high impedance (M
and M
TOP
BOT
are off) until the TRACK/SS pin voltage exceeds V , the
FB
In Table 9, guidelines are provided for output capacitor
selection, for various operating conditions. The table
optimizes total equivalent ESR and total bulk capacitance
for the transient load step performance. Stability criteria
is considered. The Linear Technology LTpowerCAD™ de-
sign tool is available for transient simulation and stability
analysis, if desired.
remote-sense differential amplifier’s output voltage. This
allowspower-upintopre-biasedoutputvoltageconditions
without sinking of current from the output capacitors.
WhenTRACK/SSexceedsthecontrolIC’s600mVbandgap
voltage, V is regulated at 600mV and V
reaches its
FB
OUT
nominal output voltage.
4641f
24
LTM4641
APPLICATIONS INFORMATION—POWER SUPPLY FEATURES
Figure 6 shows idealized output voltage waveforms for
(3) Choose output capacitors and input capacitors for the
design in the same manner as is done for nontracking
applications.
applications in which LTM4641’s output (V ) tracks
OUT
a master rail (V
respectively.
) coincidently and ratiometrically,
MASTER
To fulfill a coincident rail-tracking requirement, recognize
that when the output voltage of the master rail reaches
the tracking rail’s nominal FS voltage, the TRACK/SS pin
of the LTM4641 (tracking slave) needs to be 600mV. This
can be satisfied by forming a resistor-divider network
V
MASTER
OUT
composed of R and R , interfacing V
to
TAC
TBC
OUT_MASTER
V
TRACK/SSoftheLTM4641trackingslave,andterminating
to SGND of the LTM4641 tracking slave. In Figure 7 and
Figure 8, U1 generates a master rail while U2 generates a
coincident-tracking rail that follows U1’s output. Values
of R and R
are selected such that:
TAC
TBC
TIME
4641 F06a
V
OUT_SLAVE_C (FS OUTPUT) –1 •RTBC
(6a) Coincident Tracking
RTAC
=
(17)
0.6V
V
V
MASTER
IntheexamplecircuitofFigure7, themasterrailgenerated
by U1 ramps up its output to 1.8V. The coincident-tracking
rail is generated by U2 and has a nominal FS output
voltage of 1V. Values of R
and R
are determined
TAC
TBC
OUT
such that when U1’s output reaches 1V, the TRACK/SS
pin of U2 reaches ~600mV; choosing R
to be 10kΩ
TBC
yields R ꢀ=ꢀ(1V/0.6Vꢀ–ꢀ1)ꢀ•ꢀ10kΩ,ꢀorꢀ~6.65kΩ.ꢀItꢀisꢀ
TAC
common to choose resistor values of 10k or less for
this task, so that voltage offset errors introduced by
the 1µA current source on TRACK/SS working into the
TIME
4641 F06b
(6b) Ratioꢃetric Tracking
R
/R
network are sufficiently small.
TAC TBC
Figure 6. Two Different ꢁodes of Output Voltage Tracking
To fulfill a ratiometric rail-tracking requirement, recognize
that when the output voltage of the master rail reaches
its final FS value, the TRACK/SS pin of the LTM4641
(tracking slave) needs to reach 600mV. This can be satis-
fied by forming a resistor-divider network composed of
To configure LTM4641 for coincident or ratiometric
tracking, begin the design (initially) the same way as for
nontracking applications:
(1) Determine the R
, R
, and R
values ap-
SET2
SET1A
SET1B
R
and R , interfacing V
to TRACK/SS
TAR
TBR
OUT_MASTER
propriate for the final, “full-scale” (FS) output voltage.
of the LTM4641 tracking slave, and terminating to SGND
of the LTM4641 tracking slave. In Figure 7 and Figure 8,
U3 generates a ratiometric-tracking rail that follows U1’s
(2) Determine the R resistor needed to guarantee
fSET
ramp down of the output voltage to the desired value.
output. Values of R
and R
are selected such that:
TAR
TBR
For example, if it is necessary for V to ramp down
OUT
to 0.8V while tracking the master rail, then R
is
fSET
V
RTAR
=
OUT_MASTER (FS_OUTPUT) –1 •RTBR
recommended from Table 1 to be ~887kΩ. If ramp-
downtrackingisnotneeded,thenR canbechosen
(18)
0.6V
fSET
according to Table 1 (or Figure 3) and the FS output
voltage of the LTM4641 generated rail.
4641f
25
LTM4641
APPLICATIONS INFORMATION—POWER SUPPLY FEATURES
V
IN
4V TO 38V
(4.5V START-UP)
C
+
INM(MLCC)
C
INM(BULK)
50V
10µF
50V
×2
V
V
V
SW
V
ING INGP
INH
OUT_MASTER
1.8V
V
INL
V
OUT
C
OUTM(MLCC)
UP TO 10A
R
MfSET
2M
100µF
6.3V
×3
CROWBAR
f
SET
LATCH
C
FFMA
220pF
+
1
V
ORB
UVLO
HYST
FCB
R
SETM1A
8.2k
U1
LTM4641
+
V
OSNS
LOCAL HIGH
FREQUENCY
DECOUPLING
1
1
R
R
SETM2
SETM1B
8.2k
LOAD
INTV
DRV
CC
16.4k
–
–
V
OSNS
CC
C
V
FFMB
220pF
IOVRETRY
OVLO
ORB
TEMP
1V
REF
OVPGM
OTBH
RUN
RUN
PGOOD
U1 V
RAMP TIME
TRACK/SS
TMR COMP SGND GND
OUT
t
= 0.6ms/nF • C
SOFTSTART
SS
C
SS
4.7nF
(C IN nF)
SS
1
1
C
+
INSC(MLCC)
C
INSC(BULK)
50V
COINCEDENT TRACKING
10µF
50V
×2
OF THE 1.8V RAIL
V
V
V
SW
V
ING INGP
INH
OUT_SLAVE_C
V
INL
V
1V
OUT
C
OUTSC(MLCC)
R
UP TO 10A
CfSET
680k
100µF
6.3V
×4
CROWBAR
f
SET
LATCH
+
2
V
ORB
UVLO
HYST
FCB
R
SETC1A
U2
LTM4641
5.49k
+
V
OSNS
LOCAL HIGH
FREQUENCY
DECOUPLING
2
2
R
5.49k
SETC1B
V
LOAD
INTV
OUT_MASTER
CC
–
–
V
DRV
OSNS
CC
R
TAC
V
IOVRETRY
OVLO
ORB
6.65k
TEMP
1V
REF
R
TBC
OVPGM
OTBH
10k
RUN
RUN
PGOOD
2
TRACK/SS
TMR COMP SGND GND
2
C
+
INSR(MLCC)
C
INSR(BULK)
50V
RATIOMETRIC TRACKING
OF THE 1.8V RAIL
10µF
50V
×2
V
V
V
SW
ING INGP INH
V
OUT_SLAVE_R
V
INL
V
OUT
1.5V
C
OUTSR(MLCC)
R
UP TO 10A
RfSET
1M
100µF
6.3V
×4
CROWBAR
f
SET
LATCH
C
FFRA
220pF
+
3
V
ORB
UVLO
HYST
FCB
R
SETR1A
8.2k
U3
LTM4641
+
V
OSNS
LOCAL HIGH
FREQUENCY
DECOUPLING
3
3
R
R
SETR2 SETR1B
33.2k
8.2k
V
LOAD
INTV
OUT_MASTER
CC
–
–
V
DRV
OSNS
CC
R
TAR
C
V
FFRB
IOVRETRY
OVLO
ORB
20k
220pF
TEMP
1V
REF
R
TBR
OVPGM
OTBH
10k
RUN
RUN
PGOOD
3
TRACK/SS
TMR COMP SGND GND
4641 F07
3
U1, U2 AND U3 SGND (
) CONNECT TO GND INTERNAL TO THEIR RESPECTIVE MODULES.
,
,
3
1
2
KEEP SGND ROUTES/PLANES OF MODULES SEPARATE FROM EACH OTHER AND FROM GND ON MOTHERBOARD
Figure 7. Eꢂaꢃples of LTꢁ4641 Perforꢃing Coincident and Ratioꢃetric Rail-Tracking. cf. Figure 8 Waveforꢃs
4641f
26
LTM4641
APPLICATIONS INFORMATION—POWER SUPPLY FEATURES
pin to the MOSFET driver circuitry. In most cases, connect
IntheexamplecircuitofFigure7, themasterrailgenerated
byU1rampsupitsoutputto1.8V.Theratiometric-tracking
rail is generated by U3 and has a nominal FS output volt-
INTV to DRV . The INTV regulator can source up to
CC
CC
CC
30mA,continuous,whichissufficientforpoweringDRV ,
CC
even at the LTM4641’s highest recommended switching
age of 1.5V. Values of R and R
are determined such
TAR
TBR
frequency (6V
condition).
that when U1’s output reaches its final value, 1.8V, the
OUT
TRACK/SS pin of U3 reaches ~600mV: choosing R
to
TBR
The power loss in the LDO can be considerable at high
input voltage, given by:
be 10kΩ yields R ꢀ=ꢀ(1.8V/0.6Vꢀ–ꢀ1)ꢀ•ꢀ10kΩ,ꢀorꢀ~20kΩ.ꢀ
TAR
It is common to choose resistor values of 10k or less for
this task, so that errors introduced by the 1µA current
source on TRACK/SS are sufficiently small.
P
= (V ꢀ–ꢀ5.3V)ꢀ•ꢀ(5mAꢀ+ꢀI
) (19)
DRVCC
LOSS(INTVCC_LDO)
INL
This power loss can be virtually eliminated when a ~5V
to 6V rail is available to overdrive the INTV /DRV pins
Figure 8 shows an oscilloscope snapshot of the output
voltage waveforms of the modules configured per the
CC
CC
throughaSchottkydiode,asshownintheFigure51circuit.
This is because the LDO can only pull INTV ’s voltage
Figure 7 circuit, with 6Ω load on V
and no load
CC
OUT_MASTER
in an upward direction—that is to say, the series-pass
on the V
and V
outputs.
OUT_SLAVE_C
OUT_SLAVE_R
element turns off when INTV exceeds the LDO control
CC
loop’s regulation setpoint. Infrared thermal images in
Figures 52 to 55 illustrate operating conditions in which
up to ~5°C reduction in package surface temperature is
obtainedbyemployingthistechnique.Notetheimportance
U1 V
OUT
1V/DIV
U2 V
1V/DIV
OUT
to provide a diode-ORed path from V to V and from
IN
INL
INTV /DRV to V when INTV /DRV is overdriven
U3 V
1V/DIV
CC
CC
INL
CC
CC
OUT
byanauxiliaryrail(orV ). ThisassuresproperMOSFET
OUT
RUN
5V/DIV
driver behavior regardless of disappearance/appearance
4641 F08
2ms/DIV
of V versus V , in any combination or sequence of
INL
AUX
rail ramp-up/ramp-down events. The series-connected
Figure 8. Output Voltage Waveforꢃs of U1, U2 and U3. cf.
Figure 7 Circuit.
Schottky diode internal to the LTM4641 that feeds the
LDOfromV assuresproperMOSFETdriverandinternal
INL
logic behavior, even in the event of rapid discharging and
Forapplicationsthatdonotrequiretrackingorsequencing,
applying at least 100pF on the TRACK/SS pin is recom-
mended, corresponding to ~60μs output voltage start-up
ramptime.Theresultingsoft-startperiodwilllimitstart-up
input surge current and output voltage overshoot.
restoration of V
.
INL
A housekeeping circuit that monitors DRV voltage in-
CC
hibits switching action until DRV exceeds 4.05V. Once
CC
switching action commences, DRV is allowed to fall
CC
to 3.35V before switching action is inhibited. The DRV
CC
INTV and DRV
CC
CC
voltage monitor has glitch immunity characteristics as
shown in Figure 12.
The LTM4641 module has an internal 5.3V low dropout
regulator whose input is fed from the low current input
DRV current is proportional to switching frequency. For
CC
voltage bias pin, V , through a Schottky diode. The out-
INL
applications with extremely fast output voltage start-up
put, INTV , is used to power control and housekeeping
CC
(e.g., C < 100pF on TRACK/SS, or rail tracking very fast
SS
circuitry and the MOSFET drivers, and is up-and-running
railswithsub60μsturn-ontime),switchingfrequencymay
wheneverbiasonV ispresent.DRV isthepowerinput
INL
CC
4641f
27
LTM4641
APPLICATIONS INFORMATION—POWER SUPPLY FEATURES
conceivably approach f
at start-up, however briefly
TEꢁP, OTBH and Overteꢃperature Protection
MAX
(see Equation 8). When biasing DRV from INTV in
CC
CC
AsseeninFigure1,aresistor-NTC-dividernetworkformed
such applications, INTV may require additional bypass
CC
between 1V
and SGND generates TEMP, an analog
REF
capacitance to ride through the resulting current surge on
temperature indicator pin. The pin nominally measures
~0.98V at 25°C and colder, and ~585mV at 125°C. A
graph of the relationship between junction temperature,
NTC resistance, and TEMP voltage is found in Figure 10.
DRV . INTV can by bypassed with up to 4.7μF ( 20%
CC
CC
tolerance) of external decoupling capacitance.
1V
REF
The TEMP pin also connects indirectly to a comparator
input whose output can pull HYST low to inhibit switch-
ing action. If TEMP falls below 438mV, corresponding
to a junction temperature of ~147°C, switching action
is inhibited. If OTBH is logic low when TEMP falls below
438mV, a latchoff overtemperature event is registered.
Restarting regulation after a latchoff event has occurred
is explained in detail in the Start-Up/Shutdown section.
If OTBH is open circuit when TEMP falls below 438mV, a
nonlatching overtemperature event is registered: switch-
ing action can resume when the units cools off and the
TEMP pin rises above 514mV, corresponding to a junction
temperature of ~136°C.
A housekeeping IC internal to the LTM4641 generates
a 1V 1.5% reference voltage. This voltage reference is
generatedindependentofthecontrolIC’s600mVbandgap
voltage. The 1V should only be used to alter the OV
REF
PGM
thresholdprogrammingvoltageforthefastOOVcompara-
tor (see Fast Output Overvoltage Comparator Threshold
section) or to implement an auxiliary overtemperature
detector with an NTC having ultrahigh resistance (470k at
25°C,B-value<5000K)—inthemannershowninFigure47.
Loading 1V beyond 100μA is not recommended.
REF
1V
must become established quickly at start-up to
REF
properlybiasOV
,andthereforenoexternalcapacitance
PGM
should be applied to this pin. To minimize disturbance to
the OV voltage, dynamic step-loading of the 1V is
The LTM4641’s overtemperature protection feature is in-
tended to protect the device during momentary overload
conditions.RecognizethattheLTM4641isratedfor125°C
junction,absolutemaximum,andthatjunctiontemperature
exceeds125°Cwhenovertemperatureprotectionisactive.
Continuous operation above the specified maximum op-
erating junction temperature may impair device reliability.
PGM
REF
not recommended. Figure 9 shows the step response of
1V to a 0μA to 100μA step load with 100A/s slew rates,
REF
and the resulting impact to OV
’s voltage waveform.
PGM
1V
REF
100mV/DIV
The overtemperature protection circuit can be disabled
AC-COUPLED
by connecting TEMP to 1V . With moderate linear cir-
REF
I
1VREF
50µA/DIV
cuit analysis, the information in Figure 10 and Figure 62
(Appendix A) can be used to alter the overtemperature
inception and recovery thresholds. If desired, the thresh-
olds can be increased by applying a resistor from TEMP to
OV
PGM
10mV/DIV
AC-COUPLED
4641 F09
20µs/DIV
1V , or decreased by applying a resistor from TEMP to
REF
SGND. The overtemperature comparator contains built-in
filtering, yielding glitch immunity characteristics shown
in Figure 12.
Figure 9. Response of 1VREF to 0μA ⇔ 100μA Load Steps
Applied at 100A/s—and Resulting Disturbance and Recovery
of OVPGꢁ. Figure 43 Circuit. Do Not Load 1VREF Arbitrarily
4641f
28
LTM4641
APPLICATIONS INFORMATION—INPUT PROTECTION FEATURES
1000000
100000
10000
1000
are not suitable. For example, it can be convenient to ap-
ply customized UVLO settings to inhibit switching prior to
enteringaregionofpossibledropoutoperation(Figure51).
It may be desirable to set a very large UVLO hysteresis,
if line sag is problematic. UVLO is highly recommended
to be customized to monitor the source supply feeding
0.95
0.85
0.75
0.65
0.55
0.45
0.35
0.25
V
when V is biased from an auxiliary rail (Figure 49).
INH
INL
The UVLO pin input may also be used to provide novel
circuit solutions such as one found in Figure 47: to detect
anovertemperatureeventinMSP—sensedviaanexternal
NTC in close proximity to the power interrupt MOSFET,
MSP;andtorespondtoMSPovertemperaturebyinhibiting
switching action and turning off MSP until the MOSFET
returns to normal temperatures.
–55 –15
25
65
105
145
185
JUNCTION TEMPERATURE (°C)
4641 F10
Figure 10. Relationship of NTC Resistance to Junction
Teꢃperature and Resulting TEꢁP Voltage. Curves for
Noꢃinal Values and Calculated Eꢂtreꢃe Values Shown
IOVRETRY is primarily used to set the input voltage (V )
IN
Input ꢁonitoring Pins: UVLO, IOVRETRY, OVLO
threshold above which switching action is inhibited, but
not latch off. OVLO is primarily used to set the input volt-
The UVLO pin feeds directly into the inverting input of a
comparator whose trip threshold is 0.5V. The behavior
of the UVLO pin is an example of a nonlatching fault:
when the UVLO pin falls below 0.5V, HYST is pulled low
and switching action is inhibited; when the UVLO pin
exceeds 0.5V, HYST goes logic high and switching action
can resume. The IOVRETRY and OVLO pins each feed
directly into noninverting inputs of comparators whose
trip thresholds are 0.5V. The behavior of the IOVRETRY
pin is also an example of a nonlatching fault pin: when
the IOVRETRY pin exceeds 0.5V, HYST is pulled low and
switching action is inhibited; when IOVRETRY falls below
0.5V, switching action can resume. The behavior of the
OVLO pin is an example of a latchoff fault pin: when the
OVLO pin exceeds 0.5V, HYST is pulled low and switching
action is inhibited; when OVLO subsequently falls below
0.5V, HYST remains latched low, and switching action
cannot occur until the latch has been reset. Restarting
regulation after a latchoff event has occurred is explained
in detail in the Start-Up/Shutdown section.
age (V ) threshold above which switching action latches
IN
off. Just as the UVLO pin can be used in versatile ways,
so can IOVRETRY and OVLO.
Consult Appendix A to see the UVLO/IOVRETRY/OVLO
pins’ functions in greater detail.
The most common arrangement of components connect-
ing V to UVLO, HYST, IOVRETRY and OVLO is shown
IN
in Figure 11.
V
IN
C
+
IN(MLCC)
10µF
C
IN(BULK)
×2
V
INH
V
INL
R
R
TUV
BUV
UVLO < 0.5V = OFF
UVLO
LTM4641
HYST
R
HYST
HYST PULLS UP WHEN
ON, HYST PULLS DOWN
WHEN OFF
R
R
R
TOV
MOV
BOV
IOVRETRY > 0.5V = OFF
IOVRETRY
OVLO > 0.5V = LATCHOFF
OVLO
SGND
These three pins give added flexibility to tailor some be-
haviors of the LTM4641. The UVLO pin input is primarily
used to set customized UVLO rising and UVLO falling
thresholds, utilizing a high impedance connection to the
HYST pin to obtain hysteresis. There are times when the
LTM4641’sdefaultUVLOrisingandUVLOfallingthresholds
of 4.5V rising (maximum) and 4V falling (maximum)
GND
4641 F11
SGND CONNECTS TO GND INTERNAL TO MODULE.
KEEP SGND ROUTES/PLANES SEPARATE FROM GND
ON MOTHERBOARD
Figure 11. Setting the LTꢁ4641 Custoꢃ UVLO Rising and
UVLO Falling Thresholds, Nonlatching Input Overvoltage
Threshold, and Latching Input Overvoltage Threshold
IN
IN
4641f
29
LTM4641
APPLICATIONS INFORMATION—INPUT PROTECTION FEATURES
Variables to define up-front are as follows:
and it is inferred (in that scenario) that V
closer to 4.1V, when RUN is floating.
would be
HYST
•ꢀ V : V start-up voltage, in volts. This is the custom-
SU IN
ized UVLO rising voltage.
It is the moderately weak pull-up strength of HYST (10kΩ
pull-up to INTV ), and the desire for any loading of
CC
•ꢀ V : V shutdown voltage, in volts. This is the custom-
SD IN
the HYST signal to negligibly alter the HYST logic-high
output voltage level (less than ~50mV), that motivates
a high impedance (~1MΩ) hysteresis-setting resistor to
interface between HYST and UVLO, when custom UVLO
settings are desired.
ized UVLO falling voltage.
•ꢀ V
: The value of the voltage on the HYST pin (in
HYST
volts) when switching action is on and just prior to the
input voltage (V ) falling below V .
IN
SD
•ꢀ R
: The hysteresis-setting resistor. If used, R
is
HYST
HYST
ThecustomizedUVLOstart-upandshutdowninputvoltage
settings can be double-checked with:
recommended to take on a value of 1MΩ or higher, so
that the HYST voltage is negligibly affected by external
loading.
RTUV
VSU =UVOVTH •
+1
(22)
(23)
RBUV ||RHYST
•ꢀ V : The input voltage above which a latchoff input
OV
overvoltage event occurs.
VHYST
RHYST
VSD = VSU –
•RTUV
•ꢀ V : The input voltage above which a nonlatching input
RT
overvoltage event occurs.
To set the input overvoltage (latching and nonlatching)
thresholds,choosefirsthowmuchcurrent,I ,tocontinu-
TOV MOV BOV
string for this function, at ultrahigh line. 10μA to 20µA is
a normal amount to allocate.
Then, R
and R
are given by:
TUV
BUV
DIV
VSU − VSD
VHYST
ally have drawn by the R /R
/R
resistor-divider
RTUV
and
RBUV
=
•RHYST
(20)
(21)
The total resistance of the divider string is then given by:
UVOVTH
VSU −UVOVTH UVOVTH
=
VOV
IDIV
RTOT
=
(24)
–
RTUV
RHYST
Then, the resistors in the input overvoltage divider are
given by:
UVOV is nominally 0.5V, from the Electrical Characteris-
TH
tics Table. The value of V
used in the above equations
HYST
RTOT •UVOVTH
requires more careful consideration. Review Figure 1 and
assess system details of the specific application in which
the LTM4641 is being placed. It is known from the Electri-
cal Characteristics table that when V ≥ 6V that INTV
RBOV
=
,
(25)
VOV
INL
CC
1
1
V
OV
RMOV =UVOVTH •RTOT
•
–
,
(26)
(27)
= 5.3V; and we see the voltage on the HYST pin, when
V
RT
switching action is on, is V , 5.1V—
HYST(SWITCHING_ON)
nominally. Observe that if the RUN pin were driven high
R
TOV
= R – R – R
TOT M B
by 3.3V logic, however, that V would be a Schottky
HYST
It may be tempting to try rearranging these equations
so that R ’s value is fixed, first, and to compute R
diode forward-voltage drop above 3.3V—and V
in
IN
HYST
TOV
MOV
that instance would be 3.6V. If V is targeted below 6V ,
SD
and R
subsequently. However, due to large divide-
BOV
it is necessary to consider that V
’s pull-up voltage,
HYST
down ratio (usually) of ultrahigh line input voltage down
INTV , is decreasing with V . For example, at V
=
CC
INL
INL
to these pins with ~0.5V thresholds, the rounding off of
4.5V input, INTV is nominally 4.3V (V
),
CC
INTVCC(LOWLINE)
R
MOV
and R
to nearest EIA standard values after fixing
BOV
4641f
30
LTM4641
APPLICATIONS INFORMATION—INPUT PROTECTION FEATURES
R
IN
’s value in place often significantly alters one or both
The LTM4641 powers up its output when the following
conditions are met:
TOV
V referred overvoltage thresholds. It is more efficient to
work through Equations 24 to 27 in the sequence shown
and iterate (if necessary) towards finding convenient (EIA
standard) resistor values.
•ꢀꢀ RUNꢀexceedsꢀ1.25Vꢀ(nominal;ꢀ2V,ꢀovertemperature);ꢀ
power-on reset (POR) and timeout delay times do not
apply to RUN.
The latchoff input overvoltage threshold can be double-
checked with:
•ꢀ Allꢀnonlatchingꢀfault-monitorꢀpinsꢀhaveꢀbeenꢀinꢀtheirꢀ
operationally valid states for the full duration of the
POR delay time, set optionally by C
(the capacitor
TMR
RTOV +RMOV
VOV =UVOVTH •
+1
(28)
on the TMR pin). Explicit pins and operationally valid
thresholds follow:
RBOV
The nonlatching overvoltage threshold can be double-
checked with:
a. DRV > 4.05V. In the circuits of Figures 45 and
CC
46, this is guaranteed for V ≥ 4.5V, minimum. In
INL
Figure 49, this requirement is met when the auxiliary
bias supply exceeds 4.05V.
RTOV
VRT =UVOVTH •
+1
(29)
RMOV +RBOV
(
)
b. UVLO > 500mV
The UVLO, IOVRETRY and OVLO pins do not require any
filter capacitance due to built-in filtering in the LTM4641’s
housekeeping IC. This results in glitch immunity with
characteristics shown in Figure 12.
c. IOVRETRY < 500mV
d. TEMP > 514mV (when OTBH is electrically open
circuit)
•ꢀꢀ Noꢀlatchoffꢀfaultꢀconditionsꢀareꢀpresent,ꢀandꢀtheꢀLTM4641ꢀ
isnotina“latchedoff”statefromanypreviouslydetected
latchoff fault condition. If a latchoff fault condition oc-
curs/occurred,theLTM4641mustbeunlatchedbyalogic
highLATCHsignal:ifalllatchofffault-monitoringpinsare
inoperationallyvalidstateswhenLATCHtransitionsfrom
logic low to high, the LTM4641 becomes immediately
unlatched; if, instead, any latchoff fault-monitoring pin
is outside its operationally valid state when LATCH is
logic high, the LTM4641 becomes unlatched if LATCH
remains logic high after all latchoff fault-monitoring
pins have been in their operationally valid states for the
full duration of the timeout delay time (set optionally by
700
600
RESPECTIVE
500
400
300
200
100
0
FAULT CONDITION
BECOMES DETECTED
GLITCH
IGNORED
0.1
1
10
100
COMPARATOR OVERDRIVE PAST THRESHOLD (%)
4641 F12
Figure 12. Transient Duration vs Coꢃparator Overdrive
Glitch Iꢃꢃunity Characteristics. ꢁonitored Signals: UVLO,
IOVRETRY, OVLO, TEꢁP, CROWBAR and DRVCC
C
). Explicit pins and operationally valid thresholds
TMR
follow:
a. OVLO < 500mV
Start-Up/Shutdown and Run Enable; Power-On Reset
and Tiꢃeout Delay Tiꢃe
b. TEMP > 514mV (when OTBH is logic low)
c. CROWBAR < 1.5V
The LTM4641 is a feature-rich and versatile self-contained
DC/DC converter system, and includes multiple on-board
supply monitors. The inputs to several monitors are avail-
able to the user for system customization (UVLO, OVLO,
IOVRETRY and TEMP).
The POR and timeout delay time is 9ms per nanofarad
of C
capacitance. If C
is not used, the POR and
TMR
TMR
timeout delay time is ~90μs.
4641f
31
LTM4641
APPLICATIONS INFORMATION—LOAD PROTECTION FEATURES
Overcurrent Foldback Protection
If any nonlatching fault conditions occur, internal circuitry
pullsHYSTlowandswitchingactionisinhibited.Thepower
stagewillbehighimpedanceuntiltheaforementionedstart-
upconditionsaremet.Ifanylatchofffaultconditionoccurs,
HYST is latched low and switching action is inhibited until
the LTM4641 is unlatched (by pulling LATCH logic high)
TheLTM4641hasovercurrentprotection(OCP). Inashort
circuit from V
to GND, the internal current comparator
OUT
threshold folds back during a short to reduce the output
current, progressively down to about one-third of its
normal value (down from 24A to 8A, typical). To recover
from foldback current limit, the excessive load or low
impedance short needs to be removed. Foldback current
limiting action is disabled during soft-start and tracking
start-up.
or V power is recycled (with INTV falling below 2V).
INL
CC
The LTM4641 can be configured to restart autonomously
after an adjustable timeout delay time—instead of ex-
hibiting latchoff behavior—by leaving LATCH logic high
(connected to INTV , for example) and setting the hiccup
CC
Power Good Indicator and Latching Output
Overvoltage Protection
retry timeout delay time with C
reminded that use of C
(see Figure 47). Be
TMR
also introduces POR behavior,
TMR
yet the POR and timeout delay timers operate indepen-
dently. The effect of C can be negated by pulling the
Internalovervoltageandundervoltagecomparatorsassert
theopen-drainPGOODoutputlogiclowiftheoutputvoltage
is outside 10% of nominal, after a 12μs “blanking time”.
The blanking time allows the output voltage to experience
brief excursions (due to large load-step transients, for
example) without nuisance-tripping PGOOD. The PGOOD
output is deasserted without any deliberate blanking time
when the output voltage returns to (or enters) the power
good window, with ~2% to 3% of hysteresis. If the feed-
back voltage exceeds the upper PGOOD valid limit, the
TMR
TMR pin to INTV .
CC
Switching action will be inhibited if any of the following
occur:
•ꢀ RUNꢀisꢀlessꢀthanꢀ1.15Vꢀ(nominal;ꢀ0.8V,ꢀovertemperature).ꢀ
Not a fault; no POR or timeout delay time is imposed.
•ꢀ Anyꢀnonlatchingꢀfaultsꢀoccur:
a. DRV falls below 3.35V. In the Figure 45 and
CC
synchronous power MOSFET, M , turns on (with no
BOT
Figure46circuits,thishappensatV <4V,maximum.
INL
blanking time)—to try sinking current from the output to
GND,throughLTM4641’spowerinductor—untiltheoutput
voltage returns to the PGOOD valid region. If the output
b. UVLO falls below 0.5V.
c. IOVRETRY exceeds 0.5V.
voltage exceeds an adjustable threshold set by OV
,
PGM
d. TEMP falls below 438mV when OTBH is electrically
open circuit.
whose default value corresponds to 11% above nominal,
the LTM4641 pulls its CROWBAR output logic high imme-
diately(500nsresponsetime,maximum)andlatchesoffits
outputvoltage:thepowerstagebecomeshighimpedance,
•ꢀ Anyꢀlatchoffꢀfaultsꢀoccur:
a. OVLO exceeds 0.5V.
with both M
and M
turning off and staying latched
TOP
BOT
off; furthermore, MSP’s gate is pulled to V potential
b. CROWBAR exceeds 1.5V.
INH
rapidly (<2.6μs response time, maximum), to disconnect
the input source voltage from the module’s power stage.
Restarting regulation after a latchoff event has occurred
is explained in detail in the Start-Up/Shutdown section.
c. TEMP falls below 438mV when OTBH is logic low.
The LTM4641’s state diagram is provided in Appendix B.
Start-up and shutdown mechanisms for any given op-
erating scenario are identified in the state diagram. The
The behavior of turning on the synchronous MOSFET dur-
ing detection of an output overvoltage is a rudimentary
andpopularkindofoutputovervoltageprotectionscheme
commonly found in the power supply and semiconductor
control IC industry. It can provide mediocre overvoltage
TEMP andDRV pinshavebuilt-in hysteresis. The UVLO,
CC
IOVRETRY, OVLO, TEMP, CROWBAR and DRV pins con-
CC
nect to comparators with built-in glitch immunity, with
characteristics indicated in Figure 12.
4641f
32
LTM4641
APPLICATIONS INFORMATION—LOAD PROTECTION FEATURES
protection during severe load current step-down events,
but is not very effective at protecting loads from genuine
fault conditions such as a short circuited high side power
switching MOSFET. Furthermore, such schemes tend to
be implemented with the overvoltage detector’s threshold
dependent on the same bandgap voltage that the output is
being regulated to. Applications needing superior output
overvoltage and load protection require the performance
achievedwiththeoutputcrowbarMOSFET,MCBandpower
interruptswitch,MSP,andLTM4641’suseofanindependent
on the CROWBAR output; internal circuitry interfacing to
CROWBAR presents itself as a ~10kΩ load (see Figure 62
in Appendix A). The use of the PN diode and 10nF capaci-
tor creates a way for the CROWBAR output to stay logic
high, even if the duration of OOV is very brief, and assures
the glitch immunity of the latchoff detection circuitry is
overcome. The 10kΩ load and 10nF capacitor provide an
upper bound for the duration of time MCB might be on
after CROWBAR activates: 400μs, or four time constants.
Parasitic capacitance on the gate of MCB may increase
this time, slightly.
reference voltage(1V ) to generate an OOV threshold.
REF
Observe that when HYST is low, the noninverting input
to the fast OOV comparator (see Appendix A) is clamped
by a Schottky diode. (When RUN is low, the noninverting
input to the fast OOV comparator is clamped by two series
Schottky diodes.) This differs from when switching ac-
tion is engaged, where the noninverting input to the fast
Power-Interrupt ꢁOSFET (ꢁSP), CROWBAR Pin and
Output CROWBAR ꢁOSFET (ꢁCB)
Within 500ns (maximum) of the control-loop-referred
feedback signal, V , exceeding the voltage on OV
FB
PGM
(plus-or-minus OVP ), an OOV event is detected, and
ERR
OOV comparator is normally the V signal. Therefore, be
the CROWBAR output swings high enough to turn on an
FB
aware that the CROWBAR output is nominally inhibited
when switching action is inhibited.
optional crowbaring device (MCB) residing on V . No
OUT
more than 2.6µs after OOV detection, V is discharged
ING
and an optional power interrupt switch, MSP, disconnects
the LTM4641’s power stage from the input source supply.
Restarting regulation after a latchoff event has occurred
is explained in detail in the Start-Up/Shutdown section.
When MCB and MSP are used in conjunction as shown in
the Figure 46 circuit, the LTM4641 is able to provide best-
in-classoutputovervoltageprotectionagainstarguablythe
mostdespisedfailuremodehighstep-downbuckconvert-
ers can theoretically suffer: an electrical short between
the input source to the output, via the switching node.
Turning on MCB upon detection of OOV helps discharge
the output capacitors and prevent any further positive ex-
cursion of output voltage by transforming residual energy
in LTM4641’s power stage into heat; meanwhile, turning
off MSP removes a path for current flow between the in-
put power source and the output—preventing hazardous
(input) voltage from reaching the precious load.
MCBshouldbeplacedclosetothemajorityoftheload(s)’s
bulkandMLCClocalbypasscapacitors.CROWBARshould
be connected to the gate of MCB with a generous signal
tracewidth(20mils,or0.5mm),tosupportdrivingthepeak
currentneededtoturnonMCBuponOOVdetection. Atthe
instant that MCB turns on, it typically draws hundreds of
amps from the output capacitors which are mainly located
near the load. When MCB turns off, the B-field that may
have been built up in the parasitic inductance in the cop-
per plane between the output capacitors and MCB cannot
vanish instantaneously, and the collapsing of that B-field
caninduceanegativevoltageacrosstheoutputcapacitors
and load. Closer proximity of MCB to the majority of the
output capacitors minimizes this parasitic inductance and
hencetheresultingmagnitudeofthenegativevoltagespike.
It should be noted that when an OOV event is detected,
CROWBAR is not held high (equivalently, MCB is not left
turned on) indefinitely. The act of pulling CROWBAR high
(above 1.5V nominal), whether due to internal or external
circuitry,invokesalatchoffresponseandstrongdischarge
MCB must be selected according to the following criteria:
•ꢀ MCBꢀmustꢀbeꢀaꢀlogic-levelꢀN-channelꢀMOSFET
ofV ;HYSTislatchedlowandswitchingactionisinhibited
ING
•ꢀ Theꢀdrain-to-sourceꢀratingꢀofꢀMCBꢀmustꢀbeꢀgreaterꢀthanꢀ
after CROWBAR overcomes the glitch immunity require-
ment (see Figure 12). The fast OOV comparator’s output
is fed through a blocking PN diode into a 10nF capacitor
the maximum output voltage, V
OUT(PEAK,OOV_DETECTED)
4641f
33
LTM4641
APPLICATIONS INFORMATION—LOAD PROTECTION FEATURES
•ꢀ The drain-to-source breakdown voltage of MSP must
be greater than the maximum input source voltage.
Consult the MOSFET vendor’s data sheet and consider
temperature effects.
•ꢀ WhenꢀCROWBARꢀgoesꢀlogicꢀhigh,ꢀtheꢀpeakꢀdrainꢀcur-
rent in MCB will be given by V
/
OUT(PEAK,OOV_DETECTED)
. The peak drain current, and its duration, must
R
DS(ON)
not exceed the maximum safe operating area of the
MOSFET; consult the MOSFET vendor’s data sheet. An
upper bound for MCB’s on-time is 400μs. However, this
worst-caseconductiontimecanonlyhappeniftheoutput
•ꢀ Inꢀorderꢀtoꢀsupportꢀveryꢀfastꢀturn-onꢀofꢀoutputꢀvolt-
age (e.g., sub 1ms ramp up), MSP should be turned
on quickly to bring up V quickly. Therefore, a gate
INH
capacitance on V
is extraordinarily large. The length
OUT
input capacitance (C ) below 4.7nF is preferred (less
ISS
of time that MCB can possibly conduct ultrahigh drain
currentꢀisꢀalsoꢀboundedꢀbyꢀ4ꢀ•ꢀR ꢀ•ꢀC
is better).
.
OUT(TOTAL)
DS(ON)
•ꢀ MSPꢀ mustꢀ beꢀ ableꢀ toꢀ conductꢀ theꢀ maximumꢀ inputꢀ
current to the LTM4641’s power stage without getting
too hot. Choose a suitable MOSFET package size and
In a majority of applications, output capacitance is low
enough that MCB does not conduct ultrahigh drain
current for longer than a few microseconds, as seen
on the front page.
R
that results in reasonable MOSFET junction
DS(ON)
temperature rise. Be mindful that I
during low line operation.
is highest
Q(VINH)
•ꢀ MCB’sꢀ junctionꢀ temperatureꢀ mustꢀ notꢀ exceedꢀ itsꢀ
specified maximum at any time. Consult the MOSFET
vendor’s data sheet for device thermal characteristics
for “single shot” thermal transients or “single pulse”
Blowingaseries-passinputfusewithacrowbaringSCRcan
be an effective overvoltage protection scheme for higher
output voltages, e.g., 5V, but a crowbaring MOSFET on the
output of the converter is more effective at clamping the
output voltage. For the same current, the power MOSFET
will have much less voltage drop than the PN-junction
voltage drop of an SCR. SCR-based circuits involving the
LTM4641 are not presented here. Evaluation of induced or
simulated overvoltage events on a demo board (such as
DC1543) is recommended to ensure the end result meets
the user’s expectations.
power-handling capability. The peak power sustained
2
by MCB is V
/R
.
OUT(PEAK,OOV_DETECTED)
DS(ON)
If MCB is used and it is expected that LATCH will be
toggled high (to unlatch the LTM4641) or held logic high
continuously (for automatic LTM4641 restart after fault-
off), recognize that peak power sustained by MCB during
CROWBAR activity may not be single pulse anymore.
Therefore, to prevent MCB thermal overstress in such
applications, it is recommended to use C
to set a rea-
TMR
Fast Output Overvoltage Coꢃparator Threshold
sonable cool-down period for the MOSFET. Additionally,
one may opt to implement a circuit that shuts down the
LTM4641 when MCB temperature is detected to be too
high: a minor modification to Figure 47, RT1 would be
located as close in proximity to MCB as possible (instead
of MSP), and R1, R2, and R3 would be experimentally
determined. Consult the MOSFET vendor’s data sheet for
maximum rated junction temperature and device thermal
characteristics for repeated pulsed-power transients.
O
V
is nominally biased by internal circuitry to
PGM
666mV, according to a 499kΩ and 1MΩ resistor-divider
network internal to the LTM4641 driven from the 1V
.
REF
This pin connects directly to the inverting input of the
fast OOV comparator—setting the trip threshold that
the control-loop-referred feedback voltage, V , would
FB
have to exceed to result in CROWBAR becoming logic
high. Recall that the control-loop pulse frequency modu-
lates M
such that V is driven to the lesser of the
TOP
FB
When using MSP, connect V to V
and to the gate of
INGP
ING
TRACK/SSpinorthebandgapreferencevoltageof600mV.
When TRACK/SS (and hence, the output voltage) has
MSP.SeetheInputCapacitorssection(earlier)forinforma-
tion on the input bypassing technique when MSP is used.
been fully ramped up, the 666mV on OV
represents
PGM
an OOV setting 11% above nominal output voltage. To
increase the OOV threshold, a resistor can be connected
MSP must be selected according to the following criteria:
•ꢀ MSPꢀcanꢀbeꢀeitherꢀaꢀstandardꢀlogicꢀorꢀaꢀlogic-levelꢀ
externally from 1V
to OV
; to decrease the OOV
REF
PGM
N-channel MOSFET.
threshold, a resistor can be connected externally from
4641f
34
LTM4641
APPLICATIONS INFORMATION—EMI PERFORMANCE
OVPGM to SGND. Furthermore, the OV
trip voltage
whereV
isthemaximuminputvoltagethattheinput
PGM
INH(MAX)
can be made more accurate than its default setting by
paralleling the existing (internal) OV resistor-divider
to the power stage (V ) will see in the application, and
INH
f
is the DC/DC converter’s full load switching frequency
PGM
SW
with an external resistor divider comprised of low T.C.R.
0.1%-tolerance resistors, for example. See Appendix F
for details on how to adjust or tighten the fast OOV
comparator trip threshold.
of operation. C should be NPO, C0G or X7R-type (or
SW
better) material.
The snubber resistor (R ) value is then given by:
SW
5nH
CSW
RSW
=
The Switching Node: SW Pin
(31)
The SW pin provides access to the midpoint of the power
MOSFETs in LTM4641’s power stage.
The snubber resistor should be low ESL and capable of
withstanding the pulsed currents present in snubber cir-
cuits. A value between 0.7Ω and 4.2Ω is normal.
Connecting an optional series RC network from SW to
GND can dampen high frequency (~30MHz+) switch node
ringing caused by parasitic inductances and capacitances
in the switched-current paths. The RC network is called
a snubber circuit because it dampens (or “snubs”) the
resonance of the parasitics, at the expense of higher
power loss.
EMIperformanceofLTM4641(onDC1543)withandwith-
out a snubber is compared and contrasted in Figures 13 to
16. In the examples shown, the snubber networks reduce
EMI signal amplitude by as much as ~5dB.
Access to SW is also provided to make it possible to
deliberately induce a short circuit between the input of
To use a snubber, choose first how much power to allocate
to the task and how much PCB real estate is available to
implement the snubber. For example, if PCB space al-
lows a low inductance 1W resistor to be used—derated
LTM4641’s power stage (V ) and its switch node—to
INH
evaluate, in hardware, the performance of the LTM4641
when a high side MOSFET fault condition is simulated.
conservatively to 600mW (P
)—then the capacitor in
SNUB
the snubber network (C ) is computed by:
SW
70
60
50
PSNUB
CSW
=
(30)
2
V
•fSW
INH(MAX)
EN55022
40
CLASS B
70
LIMIT
30
60
50
40
30
20
10
0
20
10
EN55022
CLASS B
LIMIT
0
–10
30
814.8
1010
226.2
422.4
618.6
FREQUENCY (MHz)
4641 F13
Figure 14. Radiated Eꢃissions Scan of LTꢁ4641 Producing
5VOUT at 10A, froꢃ 12VIN. DC1543 Hardware with Ad Hoc
Snubber Network Installed Directly Between SW Probe Point
and GND, CSW = 10nF, RSW = 1Ω (1W-Rated). fSW = 550kHz.
CIN(BULK) = 2 × 100μF, CIN(ꢁLCC) = 4 × 10μF X7R + 2 × 4.7μF
X7R. ꢁeasured in a 10 ꢁeter Chaꢃber. Quasi-Peak Detect
ꢁethod
–10
30
618.6
FREQUENCY (MHz)
814.8
1010
226.2
422.4
4641 F13
Figure 13. Radiated Eꢃissions Scan of LTꢁ4641 Producing
5VOUT at 10A, froꢃ 12VIN. DC1543 Hardware with No Snubber
Network Installed. fSW = 550kHz. CIN(BULK) = 2 × 100μF,
CIN(ꢁLCC) = 4 × 10μF X7R + 2 × 4.7μF X7R. ꢁeasured in a
10 ꢁeter Chaꢃber. Quasi-Peak Detect ꢁethod
4641f
35
LTM4641
APPLICATIONS INFORMATION—EMI PERFORMANCE
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
–10
–10
30
814.8
1010
30
814.8
1010
226.2
422.4
618.6
FREQUENCY (MHz)
226.2
422.4
618.6
FREQUENCY (MHz)
4641 F15
4641 F16
Figure 15. Radiated Eꢃissions Scan of LTꢁ4641 Producing
2.5VOUT at 10A, froꢃ 24VIN. DC1543 Hardware with No Snubber
Network Installed. fSW = 335kHz. CIN(BULK) = 2 × 100μF,
CIN(ꢁLCC) = 4 × 10μF X7R + 2 × 4.7μF X7R. ꢁeasured in a 10
ꢁeter Chaꢃber. Quasi-Peak Detect ꢁethod
Figure 16. Radiated Eꢃissions Scan of LTꢁ4641 Producing
2.5VOUT at 10A, froꢃ 24VIN. DC1543 Hardware with Ad Hoc
Snubber Network Installed Directly Between SW Probe Point
and GND, CSW = 2.2nF, RSW = 2.2Ω (1W Rated). fSW = 335kHz.
CIN(BULK) = 2 × 100μF, CIN(ꢁLCC) = 4 × 10μF X7R + 2 × 4.7μF
X7R. ꢁeasured in a 10 ꢁeter Chaꢃber. Quasi-Peak Detect
ꢁethod
APPLICATIONS INFORMATION—MULTIMODULE PARALLEL OPERATION
The LTM4641 device is a current mode controlled device,
so paralleled modules demonstrate good current sharing.
This helps equilibrate power losses and reduce thermal
differences between paralleled modules.
For loads that demand more than 10A of load current,
multiple LTM4641 devices can be paralleled to provide
more output current. See Figures 56 and 66 for examples
of four or two LTM4641 operating in parallel to deliver 40A
or 20A load current, respectively, while providing robust
output overvoltage protection.
The following pins should be connected to all correspond-
ing LTM4641s’ pin(s) when paralleling LTM4641 outputs:
The LTM4641 does not support phase interleaving or
clock synchronization, and therefore no ripple-current
cancelationeffectandnomultiplicationeffectontheoutput
voltage ripple frequency occurs when modules are paral-
leled. Therefore, it should be anticipated that paralleled
applicationscontainbeatfrequenciesintheoutputvoltage
waveform and are contained in the reflected input current.
For example, if one module operates freely at 400kHz
while its paralleled sibling operates freely at 410kHz, the
conducted EMI content will include not only the switching
fundamentalfrequencies—400kHzand410kHz—butalso
a beat frequency at the difference of those frequencies,
10kHz. The system designer may be motivated to apply an
external LC (or “pi”) filter on the input to each LTM4641
if attenuation of the reflected input currents is desired.
•ꢀ V
OUT
•ꢀ GND
•ꢀ V
•ꢀ V
INH
INL
•ꢀ HYSTꢀ(toꢀsynchronizeꢀstart-upꢀandꢀshutdown)
•ꢀ TRACK/SS
•ꢀ COMPꢀ(toꢀaccomplishꢀcurrentꢀsharing)
•ꢀ CROWBARꢀ (toꢀ synchronizeꢀ outputꢀ overvoltageꢀ
response)
•ꢀ LATCH (to reset all modules after a latchoff event)
•ꢀ V , if MSP is used
ING
4641f
36
LTM4641
APPLICATIONS INFORMATION—MULTIMODE PARALLEL OPERATION
+
–
•ꢀ V
, differentially bussed with V
; use GND
When paralleling n modules, for V
not larger than that given by:
≤1.2V, select R
OUT SET1A
OSNS
OSNS
shielding
–
+
•ꢀ V
, differentially bussed with V
; use GND
V
0.6V
8.2kΩ
OSNS
OSNS
OUT
RSET1A =RSET1B
=
–1 •
(32)
shielding
n
•ꢀ PGOOD,ꢀifꢀused
ForV >1.2V,selectR
notlargerthanthatgivenby:
(33)
OUT
SET1A
Pullinganyonemodule’sRUNpinlowwillpullallmodule’s
HYSTpinslow,toceaseswitchingandoutputvoltageregu-
lation. When paralleling LTM4641 outputs, each module
8.2kΩ
RSET1A =RSET1B
=
n
shouldhaveitsownR
resistorlocally(ifneeded)toset
fSET
Then, determine R
by:
SET2
the on time (I ) consistent with the output voltage set-
ION
2•RSET1A
–n•
ting (cf. Table 1 and Figure 3). Customized UVLO settings,
latchingandnonlatchinginputovervoltagethresholds,and
output overvoltage thresholds need only be configured on
RSET2
=
(34)
VOUT
0.6
RSET1A
8.2kΩ
–1
one LTM4641. INTV and DRV should be connected to
CC
CC
The output voltage setting can be double-checked by:
each other, separatelyoneach module (seeFigures 56 and
66)—or,ifpoweringDRV fromanauxiliarybiasrail,then
CC
RSET1A 2•RSET1A
VOUT = 0.6V 1+n•
+
(35)
by applying the technique of Figure 51 to each module.
8.2kΩ
RSET2
If MSP is used, only one V
need be connected to
INGP
+
The voltage on the V
pins of the modules during
the gate of MSP. The routing of MSP’s source pins to
OSNS
regulation become:
the V of all modules may be difficult to accomplish in
INH
layout without introducing significant loop area; it may be
necessary then to use one MSP MOSFET on the input to
each LTM4641 power stage for practical routing. Also, the
0.6V
∆V
R
GND
(36)
VVOSNS+
=
+
8.2kΩ
+
–
SET1A
||RSET1A ||RSET2
connections of V
and V
to multiple modules
OSNS
OSNS
n
can be difficult to shield, in practice, so leaving provision
for differential-mode filtering of the remote sense signal
16.4kΩ
• RSET1A ||
(C
, C
) local to each modules’ remote-sense input
DM1 DM2
pins is advisable.
n
In multimodule parallel scenarios, V
still given by Equations 12 and 13, respectively.
– and ∆V
are
OSNS
GND
Be aware that the loading of the paralleled remote sense
amplifiers on the bussed feedback signal alters the equa-
tions for setting output voltage as follows.
Lastly, be aware that the total charge current on the
TRACK/SSꢀnetꢀwillꢀbeꢀnꢀ•ꢀ1μA.ꢀ
4641f
37
LTM4641
APPLICATIONS INFORMATION—THERMAL CONSIDERATIONS AND
OUTPUT CURRENT DERATING
Therꢃal Considerations and Output Current Derating
2
θ
, the thermal resistance from junction to the
JCbottom
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottomofthepackage.InthetypicalµModuleregulator,
the bulk of the heat flows out the bottom of the pack-
age, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value
may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those param-
eters defined by JESD51-12 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board de-
fined by JESD51-9 (“Test Boards for Area Array Surface
MountPackageThermalMeasurements”).Themotivation
for providing these thermal coefficients is found in JESD
51-12 (“Guidelines for Reporting and Using Electronic
Package Thermal Information”).
3
θ
, the thermal resistance from junction to top of
JCtop
the product case, is determined with nearly all of the
componentpowerdissipationflowingthroughthetopof
the package. As the electrical connections of the typical
µModule regulator are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
Manydesignersmayopttouselaboratoryequipmentanda
testvehiclesuchasthedemoboardtopredicttheµModule
regulator’s thermal performance in their application at
various electrical and environmental operating conditions
to compliment any FEA activities. Without FEA software,
the thermal resistances reported in the Pin Configuration
section are in-and-of themselves not relevant to providing
guidance of thermal performance; instead, the derating
curves provided later in this data sheet can be used in
a manner that yields insight and guidance pertaining to
one’s application-usage, and can be adapted to correlate
thermal performance to one’s own application.
As in the case of θ
for comparing packages but the test conditions don’t
generally match the user’s application.
, this value may be useful
JCbottom
4
θ , the thermal resistance from junction to the printed
JB
circuit board, is the junction-to-board thermal resis-
tance where almost all of the heat flows through the
bottom of the µModule regulator and into the board,
and is really the sum of the θ
and the thermal
JCbottom
resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from the
package, using a two sided, two layer board. This board
is described in JESD 51-9.
The Pin Configuration section gives four thermal coeffi-
cients explicitly defined in JESD 51-12; these coefficients
are quoted or paraphrased below:
1
θ , the thermal resistance from junction to ambient, is
JA
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo-
sure.Thisenvironmentissometimesreferredtoas“still
air”althoughnaturalconvectioncausestheairtomove.
This value is determined with the part mounted to a
JESD 51-9 defined test board, which does not reflect
an actual application or viable operating condition.
A graphical representation of the aforementioned thermal
resistances is given in Figure 17; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule package.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
4641f
38
LTM4641
APPLICATIONS INFORMATION—THERMAL CONSIDERATIONS AND
OUTPUT CURRENT DERATING
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a µModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bot-
tom of the µModule package—as the standard defines
rect material coefficients along with accurate power loss
source definitions; (2) this model simulates a software-
definedJEDECenvironmentconsistentwithJSED51-9and
JESD51-12topredictpowerlossheatflowandtemperature
readings at different interfaces that enable the calculation
of the JEDEC-defined thermal resistance values; (3) the
model and FEA software is used to evaluate the LTM4641
with heat sink and airflow; (4) having solved for and
analyzed these thermal resistance values and simulated
various operating conditions in the software model, a
thorough laboratory evaluation replicates the simulated
conditions with thermocouples within a controlled envi-
ronment chamber while operating the device at the same
power loss as that which was simulated. The outcome of
this process and due diligence yields the set of derating
curves provided in later sections of this data sheet, along
withwell-correlatedJESD51-12-definedθ valuesprovided
in the Pin Configuration section of this data sheet.
for θ
and θ
, respectively. In practice, power
JCtop
JCbottom
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4641, be aware there are multiple power
devices and components dissipating power, with a con-
sequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—
but also, not ignoring practical realities—an approach
has been taken using FEA software modeling along with
laboratory testing in a controlled-environment chamber
to reasonably define and correlate the thermal resistance
valuessuppliedinthisdatasheet:(1)Initially,FEAsoftware
is used to accurately build the mechanical geometry of
the LTM4641 and the specified PCB with all of the cor-
The 6V, 3.3V and 1.5V power loss curves in Figures 18,
19 and 20 respectively can be used in coordination with
the load current derating curves in Figures 21 to 42 for
calculating an approximate θ thermal resistance for the
JA
LTM4641withvariousheatsinkingandairflowconditions.
These thermal resistances represent demonstrated per-
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
AMBIENT
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
4641 F17
µMODULE DEVICE
Figure 17. Graphical Representation of JESD51-12 Therꢃal Coefficients
4641f
39
LTM4641
APPLICATIONS INFORMATION—THERMAL CONSIDERATIONS AND
OUTPUT CURRENT DERATING
formance of the LTM4641 on DC1543 hardware; a 4-layer
FR4 PCB measuring 96mm × 87mm × 1.6mm using outer
and inner copper weights of 2oz and 1oz, respectively. The
power loss curves are taken at room temperature, and are
increased with multiplicative factors with ambient tem-
perature. These approximate factors are listed in Table 3.
(Compute the factor by interpolation, for intermediate
temperatures.) The derating curves are plotted with the
outputcurrentstartingat10Aandtheambienttemperature
at 40°C. The output voltages are 6V, 3.3V and 1.5V. These
are chosen to include the lower and higher output voltage
rangesforcorrelatingthethermalresistance.Thermalmod-
els are derived from several temperature measurements
in a controlled temperature chamber along with thermal
modeling analysis. The junction temperatures are
monitoredwhileambienttemperatureisincreasedwithand
without air flow, and with and without a heat sink attached
with thermally conductive adhesive tape. The BGA heat
sinks evaluated in Table 7 (and attached to the LTM4641
with thermally conductive adhesive tape listed in Table 8)
yield very comparable performance in laminar airflow
despite being visibly different in construction and form
factor. The power loss increase with ambient temperature
change is factored into the derating curves. The junctions
are maintained at 120°C maximum while lowering output
currentorpowerwhileincreasingambienttemperature.The
decreasedoutputcurrentwilldecreasetheinternalmodule
loss as ambient temperature is increased. The monitored
junction temperature of 120°C minus the ambient operat-
ing temperature specifies how much module temperature
rise can be allowed. As an example in Figure 38, the load
current is derated to ~8A at ~81°C ambient with no air or
8A
condition is ~3.1W. The 3.74W loss is calculated
OUT
with the ~3.1W room temperature loss from the 36V to
IN
1.5V
power loss curve at 8A (Figure 20), and the 1.205
OUT
multiplying factor at 81°C ambient (interpolating from
Table 3). If the 81°C ambient temperature is subtracted
from the 120°C junction temperature, then the difference
of 39°C divided by 3.74W yields a thermal resistance, θ ,
JA
of 10.4°C/W—in good agreement with Table 6. Tables 4,
5 and 6 provide equivalent thermal resistances for 6V,
3.3V and 1.5V outputs with and without air flow and heat
sinking. The derived thermal resistances in Tables 4, 5
and 6 for the various conditions can be multiplied by the
calculatedpowerlossasafunctionofambienttemperature
to derive temperature rise above ambient, thus maximum
junction temperature. Room temperature power loss can
be derived from the efficiency curves in the Typical Per-
formance Characteristics section and adjusted with the
above ambient temperature multiplicative factors.
Table 3. Power Loss ꢁultiplicative Factors vs Aꢃbient
Teꢃperature
POWER LOSS ꢁULTIPLICATIVE
AꢁBIENT TEꢁPERATURE
FACTOR
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
Up to 40°C
50°C
60°C
70°C
80°C
90°C
100°C
110°C
120°C
heat sink and the power loss for this 36V to 1.5V
at
IN
OUT
4641f
40
LTM4641
APPLICATIONS INFORMATION—THERMAL CONSIDERATIONS AND
OUTPUT CURRENT DERATING
6
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
8
7
6
5
4
3
2
1
0
5
4
3
2
1
0
36V
24V
12V
6V
36V
24V
12V
6V
IN
IN
IN
IN
IN
IN
36V
24V
12V
IN
IN
IN
IN
IN
4
5
0
1
2
3
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
10
6
7
8
9
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
4641 F18
4146 F19
4641 F20
Figure 18. 6VOUT Power Loss,
fSW = 660kHz at Full Load,
FCB Tied to SGND
Figure 19. 3.3VOUT Power Loss,
fSW = 360kHz at Full Load,
FCB Tied to SGND
Figure 20. 1.5VOUT Power Loss,
fSW = 315kHz at Full Load,
FCB Tied to SGND
10
9
8
7
6
5
4
3
2
1
0
10
10
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
40
80
100 110
120
50 60 70
90
110
100
40
80
100 110
40
80
50 60 70
90
120
50 60 70
90
120
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4146 F22
4146 F21
4146 F23
Figure 21. 12VIN to 6VOUT, No Heat
Sink, fSW = 660kHz at Full Load
Figure 22. 24VIN to 6VOUT, No Heat
Sink, fSW = 660kHz at Full Load
Figure 23. 36VIN to 6VOUT, No Heat
Sink, fSW = 660kHz at Full Load
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
40
80
100 110
40
80
100 110
40
80
100 110
120
50 60 70
90
120
50 60 70
90
120
50 60 70
90
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4146 F24
4146 F25
4146 F26
Figure 24. 12VIN to 6VOUT with Heat
Sink, fSW = 660kHz at Full Load
Figure 25. 24VIN to 6VOUT with Heat
Sink, fSW = 660kHz at Full Load
Figure 26. 36VIN to 6VOUT with Heat
Sink, fSW = 660kHz at Full Load
4641f
41
LTM4641
APPLICATIONS INFORMATION—THERMAL CONSIDERATIONS AND
OUTPUT CURRENT DERATING
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
40
80
100 110
40
80
100 110
40
80
100 110
120
50 60 70
90
120
50 60 70
90
120
50 60 70
90
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4146 F27
4146 F28
4146 F29
Figure 27. 6VIN to 3.3VOUT No Heat
Sink, fSW = 360kHz at Full Load
Figure 28. 12VIN to 3.3VOUT No Heat
Sink, fSW = 360kHz at Full Load
Figure 29. 24VIN to 3.3VOUT No Heat
Sink, fSW = 360kHz at Full Load
10
9
8
7
6
5
4
3
2
1
0
10
10
9
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
40
80
100 110
40
80
100 110
40
80
100 110
120
50 60 70
90
120
50 60 70
90
120
50 60 70
90
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4146 F30
4146 F31
4146 F32
Figure 30. 36VIN to 3.3VOUT, No
Heat Sink, fSW = 360kHz at Full Load
Figure 31. 6VIN to 3.3VOUT, with
Heat Sink, fSW = 360kHz at Full Load
Figure 32. 12VIN to 3.3VOUT, with
Heat Sink, fSW = 360kHz at Full Load
10
10
10
9
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
400LFM
200LFM
1
0LFM
0
40
80
100 110
40
80
100 110
120
50 60 70
90
120
50 60 70
90
40
110
120
50 60 70 80 90 100
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4146 F33
4146 F34
4146 F35
Figure 33. 24VIN to 3.3VOUT with
Heat Sink, fSW = 360kHz at Full Load
Figure 34. 36VIN to 3.3VOUT with
Heat Sink, fSW = 360kHz at Full Load
Figure 35. 6VIN to 1.5VOUT No Heat
Sink, fSW = 315kHz at Full Load
4641f
42
LTM4641
APPLICATIONS INFORMATION—THERMAL CONSIDERATIONS AND
OUTPUT CURRENT DERATING
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
40
80
100 110
120
50 60 70
90
40
80
100 110
40
80
100 110
120
50 60 70
90
120
50 60 70
90
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4146 F38
4146 F36
4146 F37
Figure 38. 36VIN to 1.5VOUT No Heat
Sink, fSW = 315kHz at Full Load
Figure 36. 12VIN to 1.5VOUT No Heat
Sink, fSW = 315kHz at Full Load
Figure 37. 24VIN to 1.5VOUT No Heat
Sink, fSW = 315kHz at Full Load
10
9
10
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
400LFM
400LFM
200LFM
0LFM
200LFM
1
0LFM
0
40
80
100 110
120
50 60 70
90
40
80
100 110
120
50 60 70
90
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4146 F39
4146 F40
Figure 39. 6VIN to 1.5VOUT, with
Heat Sink, fSW = 315kHz at Full Load
Figure 40. 12VIN to 1.5VOUT, with
Heat Sink, fSW = 315kHz at Full Load
10
10
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
40
80
100 110
40
80
100 110
120
50 60 70
90
120
50 60 70
90
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4146 F41
4146 F42
Figure 41. 24VIN to 1.5VOUT, with
Heat Sink, fSW = 315kHz at Full Load
Figure 42. 36VIN to 1.5VOUT with
Heat Sink, fSW = 315kHz at Full Load
4641f
43
LTM4641
APPLICATIONS INFORMATION—THERMAL CONSIDERATIONS AND
OUTPUT CURRENT DERATING
Table 4. 6V Output, Switching Frequency Noꢃinally 660kHz at Full Load
DERATING CURVE
Figure 21 to Figure 23
Figure 21 to Figure 23
Figure 21 to Figure 23
Figure 24 to Figure 26
Figure 24 to Figure 26
Figure 24 to Figure 26
V
POWER LOSS CURVE
Figure 18
AIRFLOW (LFꢁ)
HEAT SINK
None
θ
θ
θ
(°C/W)
IN
JA
12V, 24V, 36V
12V, 24V, 36V
12V, 24V, 36V
12V, 24V, 36V
12V, 24V, 36V
12V, 24V, 36V
0
10.1
8.2
6.8
8.1
6.5
5.5
Figure 18
200
400
0
None
Figure 18
None
Figure 18
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
Figure 18
200
400
Figure 18
Table 5. 3.3V Output, Switching Frequency Noꢃinally 360kHz at Full Load
DERATING CURVE
Figure 27 to Figure 30
Figure 27 to Figure 30
Figure 27 to Figure 30
Figure 31 to Figure 34
Figure 31 to Figure 34
Figure 31 to Figure 34
V
IN
POWER LOSS CURVE
Figure 19
AIRFLOW (LFꢁ)
HEAT SINK
None
(°C/W)
JA
6V, 12V, 24V, 36V
6V, 12V, 24V, 36V
6V, 12V, 24V, 36V
6V, 12V, 24V, 36V
6V, 12V, 24V, 36V
6V, 12V, 24V, 36V
0
10.4
8.4
7.1
8.6
6.8
5.8
Figure 19
200
400
0
None
Figure 19
None
Figure 19
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
Figure 19
200
400
Figure 19
Table 6. 1.5V Output, Switching Frequency Noꢃinally 315kHz at Full Load
DERATING CURVE
Figure 35 to Figure 38
Figure 35 to Figure 38
Figure 35 to Figure 38
Figure 39 to Figure 42
Figure 39 to Figure 42
Figure 39 to Figure 42
V
IN
POWER LOSS CURVE
Figure 20
AIRFLOW (LFꢁ)
HEAT SINK
None
(°C/W)
JA
6V, 12V, 24V, 36V
6V, 12V, 24V, 36V
6V, 12V, 24V, 36V
6V, 12V, 24V, 36V
6V, 12V, 24V, 36V
6V, 12V, 24V, 36V
0
10.3
8.4
7.2
9.0
7.0
5.8
Figure 20
200
400
0
None
Figure 20
None
Figure 20
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
Figure 20
200
400
Figure 20
Table 7. Heat Sink Vendors (with Therꢃally Conductive Adhesive Tape Pre-Attached)
HEAT SINK ꢁANUFACTURER
Wakefield Engineering
Aavid Thermalloy
PART NUꢁBER
LTN20069
WEBSITE
www.wakefield.com
www.aavid.com
375424B00034G
Table 8. Therꢃally Conductive Adhesive Tape Vendor
THERꢁALLY CONDUCTIVE ADHESIVE
TAPE ꢁANUFACTURER
PART NUꢁBER
WEBSITE
Chomerics
T411
www.chomerics.com
4641f
44
LTM4641
APPLICATIONS INFORMATION—OUTPUT CAPACITANCE TABLE
Table 9. Transient Perforꢃance (Typical Values) vs Recoꢃꢃended Output Capacitance. Figure 45 and Figure 46 Circuits
C
C
OUT(ꢁLCC)
OUT(BULK)
V
VENDOR
PART NUꢁBER
VENDOR
PART NUꢁBER
OUT
≤ 3.3V AVX
12106D107MAT2A (100µF, 6.3V, 1210 Case Size) Sanyo POSCAP 6TPE680MI (680µF, 6.3V, 18mΩ ESR, D4 Case Size)
12066D226MAT2A (22µF, 6.3V, 1206 Case Size)
Taiyo Yuden
JMK325BJ107MM-T (100µF, 6.3V, 1210 Case Size)
JMK316BJ226ML-T (22µF, 6.3V, 1206 Case Size)
TDK
C3225X5R0J107MT (100µF, 6.3V, 1210 Case Size)
C3216X5R0J226MT (22µF, 6.3V, 1206 Case Size)
> 3.3V AVX
1206YD226MAT2A (22µF, 16V, 1206 Case Size)
Sanyo POSCAP 10TPF150ML (150µF, 10V, 15mΩ ESR, D3L Case Size)
Taiyo Yuden
LMK316BJ476ML-T (47µF, 10V, 1206 Case Size)
EMK316BJ226ML-T (22µF, 16V, 1206 Case Size)
TDK
C3216X5R1A476M (47µF, 10V, 1206 Case Size)
C3216X5R1C226M (22µF, 16V, 1206 Case Size)
LOAD
STEP TRANSIENT
TRANSIENT,
R
,
SLEW DROOP, 0A PEAK-TO-PEAK,
SET1A
V
R
R
R
C
C *
IN
C
C
OUT1
C ,
FFA
FFB
RATE TO 5A LOAD 0A TO 5A TO 0A RECOVERY
OUT
fSET
SET1B
SET2
IN
OUT2
(V)
V
(V)
(ꢁΩ) (kΩ) (kΩ) (CERAꢁIC) (BULK) (CERAꢁIC) (BULK)
C
(A/µs) STEP (ꢃV) STEP (ꢃV )
PK-PK
TIꢁE (µs)
IN
0.9 5, 12, 24, 36 0.931 4.12
0.9 5, 12, 24, 36 0.931 4.12
–
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
680µF
–
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
60
60
130
140
135
150
140
170
155
190
170
215
230
290
275
420
450
570
500
660
25
2 × 10µF
2 × 10µF
2 × 10µF
2 × 10µF
2 × 10µF
2 × 10µF
2 × 10µF
2 × 10µF
2 × 10µF
2 × 10µF
2 × 10µF
2 × 10µF
2 × 10µF
2 × 10µF
2 × 10µF
2 × 10µF
2 × 10µF
2 × 10µF
3 × 22µF
4 × 100µF
3 × 22µF
4 × 100µF
3 × 22µF
4 × 100µF
3 × 22µF
4 × 100µF
3 × 22µF
3 × 100µF
3 × 22µF
3 × 100µF
3 × 22µF
3 × 100µF
2 × 22µF
3 × 47µF
2 × 22µF
3 × 47µF
–
–
680µF
–
–
–
–
–
–
–
25
1
1
5, 12, 24, 36 1.00
5, 12, 24, 36 1.00
5.49
5.49
8.2
8.2
8.2
8.2
8.2
8.2
8.2
8.2
8.2
8.2
8.2
8.2
8.2
8.2
–
65
25
–
70
25
1.2 5, 12, 24, 36 1.13
1.2 5, 12, 24, 36 1.13
1.5 5, 12, 24, 36 1.43
1.5 5, 12, 24, 36 1.43
1.8 5, 12, 24, 36 2.00
1.8 5, 12, 24, 36 2.00
2.5 5, 12, 24, 36 5.76
2.5 5, 12, 24, 36 5.76
–
680µF
–
70
25
–
80
30
33.2
33.2
16.5
16.5
7.5
7.5
4.7
4.7
2.61
2.61
2.05
2.05
680µF
–
75
30
220pF
–
90
30
680µF
–
80
40
220pF
–
100
100
140
140
200
220
250
240
300
30
680µF
–
50
220pF
–
30
3.3 5, 12, 24, 36
3.3 5, 12, 24, 36
–
–
–
–
–
–
680µF
–
60
100pF
30
5
5
6
6
12, 24, 36
12, 24, 36
12, 24, 36
12, 24, 36
150µF 220pF
100pF
150µF 220pF
100pF
50
–
30
55
–
30
*Bulk Capacitance is optional if V has very low input impedance.
IN
4641f
45
LTM4641
APPLICATIONS INFORMATION—SAFETY AND LAYOUT GUIDANCE
The majority of C
should be located close to
Safety Considerations
OUT(MLCC)
the load to provide high quality bypassing.
The LTM4641 modules do not provide galvanic isolation
•ꢀ Toꢀminimizeꢀtheꢀviaꢀconductionꢀlossꢀandꢀreduceꢀmoduleꢀ
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
from V to V . There is no internal fuse. If fusing is
IN
OUT
required,aslowblowfusewitharatingtwicethemaximum
input current needs to be provided. The LTM4641 sup-
ports overcurrent protection and two kinds of overvoltage
protection (see the Power Good Indicator and Latching
Output Overvoltage Protection section).
•ꢀ Doꢀnotꢀputꢀviasꢀdirectlyꢀunderꢀanyꢀpads,ꢀunlessꢀtheyꢀ
are capped or plated over.
•ꢀ UseꢀaꢀseparatedꢀSGNDꢀgroundꢀcopperꢀareaꢀforꢀcompo-
nentsconnectingtosignalpins.Componentsconnecting
to SGND should be placed as close to the module as
possible and routed with minimum trace lengths and
trace widths, for best noise immunity.
Layout Checklist/Eꢂaꢃple
The high integration of LTM4641 makes the PCB board
layout very straightforward. To optimize its electrical and
thermal performance, some layout considerations are
necessary. Figure 43 and Figure 44 show recommended
layouts for the circuits shown in Figure 45 and Figure 46,
respectively.
•ꢀ NoteꢀthatꢀthereꢀareꢀtwoꢀclustersꢀofꢀSGNDꢀpinsꢀonꢀtheꢀ
module: one, formed by Pins A1-A3, B1-B3, C1-C4
(A1-quadrant); and a second formed by Pins K1, K3,
L3, and M1-M3 (M1-quadrant). It is good PCB design
practice to provide a copper plane connecting all
A1-quadrant SGND pins together and another plane
connecting all M1-quadrant SGND pins together. It is
not necessary to connect these two clusters of SGND
copper planes to each other in the PCB layout, because
all SGND pins are electrically connected to each other
internal to the module.
•ꢀ Referꢀtoꢀtheꢀfollowingꢀdocumentꢀforꢀdeviceꢀlandꢀpatternꢀ
and stencil design: http://www.linear.com/docs/40146.
•ꢀ TheꢀgerberꢀfileꢀforꢀdemoꢀboardꢀDC1543ꢀcanꢀbeꢀdown-
loaded at http://www.linear.com/demo
•ꢀ UseꢀaꢀsolidꢀcopperꢀGNDꢀplaneꢀdirectlyꢀunderneathꢀtheꢀ
module. This will help form the return path electrical
connections to the input source and output load. It will
also provide a thermal path for removing heat from the
BGA package and minimize junction temperature rise
of the LTM4641 for a given application. For consistent
rippleandnoisefromapplicationtoapplication,connect
the output GND plane (the one that conducts load side
return current back to the module) and the input GND
plane (the one that conducts module return current
back to the input source) underneath the module, only.
•ꢀ Doꢀnot connect the any SGND pins or SGND plane(s)
to the GND plane; the electrical star connection is made
internal to the module.
•ꢀ Forꢀ parallelꢀ moduleꢀ operation,ꢀ seeꢀ theꢀ Multimoduleꢀ
Parallel Operation section for a list of interconnecting
pins across paralleled modules. Circuit Figures 56 and
66 show four and two LTM4641 devices operating in
parallel, respectively. Route signal-level (non-power)
nets on an internal layer, with GND planes overlapping
signal routes to shield them from noise. It is even
more effective to surround module-to-module signal
connections on the internal layer containing the signal
routeswithadjacentGNDplanesorroutes, andperiodi-
cally “punching-through” GND via connections to GND
plane shields on adjacent layers. This practice forms
the equivalent of a “coaxial cable” structure within the
PCB,andishighlyeffectiveatshieldingsensitivesignals
from noise sources. Maintain differential routing of the
•ꢀ UseꢀlargeꢀPCBꢀcopperꢀareasꢀforꢀhighꢀcurrentꢀpaths,ꢀ
including V and V
.
INH
OUT
•ꢀ Placeꢀhighꢀfrequencyꢀceramicꢀinputꢀandꢀoutputꢀcapaci-
tors next to the V , GND and V
pins to minimize
INH
OUT
high frequency noise. V exception: If MSP is used,
INH
(1) place MSP as close to the V pins of the LTM4641
INH
as possible and (2) bypass the drain of MSP—and not
V
—to GND pins of the LTM4641. Only one or two
INH
high frequency MLCCs (C
) need be placed
OUT(MLCC)
directly next to the V
to minimize high frequency noise close to the source.
and GND pins of the LTM4641,
OUT
+
–
V
/V
OSNS
pin pair.
OSNS
4641f
46
LTM4641
APPLICATIONS INFORMATION—SAFETY AND LAYOUT GUIDANCE
•ꢀ Placeꢀallꢀfeedbackꢀcomponentsꢀasꢀcloseꢀtoꢀtheꢀmoduleꢀ
an example of routing the VOUT/GND remote-sense
pin pair in Layer 3 of DC1543.
as possible, giving layout priority first to capacitors
C
, C , C
, C
and C (if used)—followed
FFA FFB CMA CMB DM
•ꢀ Toꢀfacilitateꢀstuffingꢀverification,ꢀandꢀtestꢀandꢀdebugꢀac-
tivities,considerroutingcontrolsignalsoftheLTM4641
with short traces to localized test points, test pads or
test vias—as PCB layout space permits. Both in-house
and contract manufacturers enjoy gaining electrical
access to all non low impedance (≥10Ω) pins of an IC
or μModule regulator to improve in-circuit test (ICT)
coverage.
nextbyR
, R
andR
(ifused). SeeFigure5
SET2
SET1A SET1B
in the Applications Information section and Figure 64
in Appendix D for more details. Maintain differential
routing of the remote-sense lines between the load
and the module. Form a “coaxial cable” structure that
surrounds the remote-sense lines with GND potential
within the PCB, to the extent that layout permits. See
Figure 43. Recoꢃꢃended PCB Layout, Figure 45 Circuit. View of the LTꢁ4641 froꢃ Top of Package
Figure 44. Recoꢃꢃended PCB Layout, Figure 46 Circuit. View of the LTꢁ4641 froꢃ Top of Package
4641f
47
LTM4641
TYPICAL APPLICATIONS
V
IN
4V TO 38V
(4.5V START-UP)
C
+
IN(MLCC)
C
IN(BULK)
10µF
50V
×2
50V
V
V
V
SW
V
1.8V
10A
ING INGP
INH
OUT
V
INL
V
OUT
C
OUT(MLCC)
R
fSET
47µF
10V
×6
2M
CROWBAR
f
SET
UVLO
HYST
FCB
LATCH
R
SET1A
8.2k
+
V
ORB
+
V
OSNS
LOCAL HIGH
FREQUENCY
DECOUPLING
LTM4641
R
R
SET2
SET1B
8.2k
LOAD
INTV
DRV
CC
16.4k
–
–
V
OSNS
CC
V
IOVRETRY
OVLO
ORB
TEMP
1V
REF
OVPGM
OTBH
PGOOD
RUN
TRACK/SS
TMR
COMP SGND GND
C
C
TMR
N/U
SS
4641 F45
4.7nF
SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP SGND
ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD
Figure 45. 4VIN to 38VIN, LTM4641 Basic Configuration, 1.8V Output at 10A
4.5V START-UP
OPERATION
MSP
C
+
C
IN(MLCC)
IN(BULK)
UP TO 38V
IN
10µF
100µF
50V
50V
×2
V
V
V
SW
V
ING INGP
INH
OUT
V
f
V
3.3V
INL
OUT
C
FFA
100µF
6.3V
×3
10A
100pF
MCB
CROWBAR
SET
UVLO
HYST
FCB
LATCH
R
SET1A
8.2k
+
V
ORB
+
V
OSNS
LOCAL HIGH
FREQUENCY
DECOUPLING
LTM4641
R
R
SET2
SET1B
8.2k
LOAD
INTV
DRV
CC
4.7k
–
–
V
OSNS
CC
C
V
FFB
IOVRETRY
OVLO
ORB
100pF
TEMP
1V
REF
OVPGM
OTBH
PGOOD
RUN
MCB: NXP PSMN5R0-30YL
MSP: NXP PSMN7R0-60YS
TRACK/SS
TMR
COMP SGND GND
C
SS
4641 F46
22nF
SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP SGND
ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD
Figure 46. LTM4641 Delivering 3.3V Output at 10A, and Providing Robust Output
Overvoltage Protection from up to 38VIN. Dropout Operation May Occur Below 4.8VIN. See
Figure 11 to Implement Custom UVLO Rising/Falling Settings to Avoid Dropout Operation
4641f
48
LTM4641
TYPICAL APPLICATIONS
R1
20k
When V Exceeds ~36V, D1 Ensures MSP Is Operated
IN
4.5V START-UP
RT1
NTC
in Its Linear Region and Provides Rudimentary Surge
Ride-Through Protection for LTM4641.
OPERATION UP TO 28V
IN
CONTINUOUS, TRANSIENT
PROTECTED TO 80V
IN
Optional: RT1, R1, R2, R3.To Enable RT1’s Detection of
Thermal Overstress in MSP During Sustained Input Voltage
MSP
+
C
IN(BULK)
C
Surge Events, Place RT1 in Extremely Close Proximity to
MSP in PCB Layout. Experimentally Determine the Vaules
of R1, R2 and R3 That Yield Desired Overtemperature
Shutdown Inception and Restart Recovery Thresholds
Consistent with MSP’s Rated Operating Junction
Temperature and Safe Operating Area
IN(MLCC)
100µF
100V
10µF
100V
×2
D1
36V
2%
R2
8.25k
R
fSET
1M
5V
V
V
V
SW
V
ING INGP
INH
OUT
1V
V
V
INL
OUT
100µF
6.3V
×4
10A
f
SET
MCB
CROWBAR
D2 Enables Detection
UVLO
of V UVLO Falling
IN
5V
R3
2.7M
LATCH
D2
R
+
SET1A
V
ORB
5.49k
HYST
FCB
+
V
OSNS
LOCAL HIGH
FREQUENCY
DECOUPLING
LTM4641
R
SET1B
5.49k
V
IN
OUT
LT®3010-5
LOAD
–
–
INTV
DRV
CC
V
OSNS
SHDN
SENSE
GND
CC
V
ORB
IOVRETRY
TEMP
1V
R
ROV
4.7M
REF
OVPGM
OTBH
PGOOD
OVLO
RUN
MSP and Switching Action Are Temporarily
Latched Off When a Module Overtemperature
or Output Overvoltage (OOV) Condition is
Detected--Additionally, the Crowbar MOSFET MCB
is Turned On to Protect the Load Upon OOV Detection.
Autonomous Restart Attempts Occur in 9 Second
Intervals When Conditions Return to Normal
R
BOV
Switching Action Is
Temporarily Latched Off if
29.4k
TRACK/SS
TMR
COMP SGND GND
V
Exceeds 80V; Autonomous
IN
Restart Attemps Occur in
C
C
TMR
1µF
SS
4641 F47
9 Second Intervals When Input
1nF
Voltage Returns Below 80V. Note
LT3010-5 is Rated for 80V, Absolute
Maximum. See Note 1.
D2: CENTRAL SEMI CMMSH1-100G
MCB: NXP PSMN5R0-30YL
MSP: NXP PSMN028-100YS
SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP SGND
ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD
RT1: MURATA NCP15WM474J03RC
Figure 47. LTM4641 Generating 1V Output at 10A, Surge Protected up to 80VIN Transients.
Start-Up and Shutdown Waveforms with TMR = INTVCC Shown In Figure 2
V
IN
20V/DIV
V
INH
20V/DIV
V
OUT
20mV/DIV
AC-COUPLED
/INTV /DRV /LATCH
V
INL
CC
CC
5V/DIV
4641 F48
2ms/DIV
Figure 48. Oscilloscope Snap-Shot of Figure 47 Circuit Riding Through
80VIN Transient While Delivering 1VOUT at 10A to the Load
4641f
49
LTM4641
TYPICAL APPLICATIONS
3.3V NOMINAL
IN
MSP
3V RISING START-UP
IN
C
+
IN(MLCC)
2.3V FALLING SHUTDOWN
IN
47µF
6.3V
×2
C
IN(BULK)
V
V
V
SW
V
0.9V
10A
ING INGP
INH
OUT
5V
LOW POWER BIAS
<50mA PEAK
V
INL
V
OUT
R
fSET
360k
100µF
6.3V
×4
R
TUV
MCB
R
CROWBAR
150k
f
SET
UVLO
LATCH
R
R
HYST
1M
+
BUV
SET1A
4.12k
V
ORB
30.9k
+
HYST
FCB
V
OSNS
LOCAL HIGH
FREQUENCY
DECOUPLING
LTM4641
R
SET1B
4.12k
LOAD
–
–
V
OSNS
INTV
CC
V
DRV
ORB
CC
TEMP
1V
IOVRETRY
OVLO
REF
MCB: NXP PH2625L
MSP: NXP PSMN013-30LL
OVPGM
OTBH
PGOOD
100k
RUN
TRACK/SS
TMR
COMP SGND GND
C
SS
4.7nF
4641 F49
SGND CONNECTS TO GND INTERNAL TO MODULE, KEEP SGND
ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD
Figure 49. LTM4641 Producing 0.9VOUT at 10A, from 3.3VIN, and Providing Advanced Output Overvoltage
Protection. VINL, INTVCC, and DRVCC Biased from a Low Power Auxiliary 5V Rail
V
IN
1V/DIV
V
OUT
1V/DIV
HYST
5V/DIV
PGOOD
5V/DIV
4641 F50
4ms/DIV
Figure 50. Oscilloscope Snap-Shot of Figure 49 Circuit, 2Ω Load on VOUT
.
3.3VIN Applied Briefly to Highlight UVLO Rising and Falling Thresholds
4641f
50
LTM4641
TYPICAL APPLICATIONS
LDO Losses in the LTM4641 Can Be Greatly Reduced When an Auxilliary ~5V to 6V Source (V ) Is Available to
AUX
V
AUX
Drive DRV Through a Schottky Diode as Shown (D1c). When LTM4641 Is Configured to Produce ~5V
to 6V ,
C
C
O
U
T
OUT
its Output Can Be V . Provide a Current Path to V from V and INTV /DRV Whenever Overdriving INTV /DRV
AUX
INL
IN
CC
CC
CC
CC
with V –Accomplished Here with D1a and D1b
AUX
V
IN
8.5V TO 38V
(10V START-UP)
+
C
IN(MLCC)
10µF
C
IN(BULK)
50V
a
c
~5V
OUT
V
V
V
INH
SW
×2
ING INGP
V
TO 6V
OUT
OUT
D1
V
f
INL
C
C
OUT(MLCC)
OUT(BULK)
UP TO 10A
C
0.1µF
50V
VINL
47µF
10V
×2
150µF
10V
b
R
CROWBAR
TUV
294k
SET
LATCH
UVLO
+
R
SET1A
8.2k
V
ORB
R
R
HYST
1M
BUV
15.8k
+
V
OSNS
HYST
FCB
LTM4641
R
R
SET2
~2.05k TO 2.61k
SET1B
8.2k
LOAD
D2
–
V
OSNS
INTV
CC
–
V
DRV
ORB
TEMP
1V
CC
C
IOVRETRY
OVLO
DRVCC
2.2µF
REF
OVPGM
OTBH
PGOOD
D1, D2: CENTRAL SEMI CMKSH2-4LR
SOT-363 PACKAGE
RUN
TRACK/SS
TMR
COMP SGND GND
4641 F51
C
SS
47nF
SGND CONNECTS TO GND INTERNAL TO MODULE, KEEP SGND
ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD
Figure 51. Over-Driving INTVCC/DRVCC to Reduce VINL-to-INTVCC Linear Regulator Losses (cf. Figures 52 to 54)
Figure 52. Thermal Image of U1 from Figure 51 Circuit.
Delivering 5VOUT at 10A from 36VIN, with INTVCC Connected
to DRVCC and D1c = Open and D2 = Open. TA = 25°C, Bench
Testing, No Airflow
Figure 54. Thermal Image of U1 from Figure 51 Circuit.
Delivering 5VOUT at 10A from 36VIN, with 5VOUT Feeding
INTVCC/DRVCC Through D1c Diode. TA = 25°C, Bench Testing,
No Airflow
Figure 55. Thermal Image of U1 from Figure 51 Circuit.
Delivering 6VOUT at 10A from 36VIN, with 6VOUT Feeding
INTVCC/DRVCC Through D1c Diode. TA = 25°C, Bench Testing,
No Airflow
Figure 53. Thermal Image of U1 from Figure 51 Circuit.
Delivering 6VOUT at 10A from 36VIN, with INTVCC Connected
to DRVCC and D1c = Open and D2 = Open. TA = 25°C, Bench
Testing, No Airflow
4641f
51
LTM4641
TYPICAL APPLICATIONS
4.5V START-UP
IN
OPERATION UP TO 38V
AND DOWN TO 4V
MSP
C
C
IN(MLCC)
IN(BULK)
100µF
50V
×2
10µF
50V
×4
V
V
V
SW
V
ING INGP INH
OUT
V
V
1V
INL
OUT
C
R
FF1
100pF
40A
MLCC(OUT)
fSET1
750k
MCB
CROWBAR
C
f
SET
100µF
6.3V
×12
UVLO
HYST
FCB
LATCH
R
+
SET1A
1.37k
V
ORB
+
V
OSNS
LOCAL HIGH
FREQUENCY
DECOUPLING
U1
LTM4641
1
1
R
C
SET1B
1.37k
DM1
10pF
LOAD
INTV
DRV
CC
–
–
V
OSNS
CC
C
V
FF2
100pF
IOVRETRY
OVLO
ORB
TEMP
1V
REF
OVPGM
OTBH
RUN ENABLE
RUN
PGOOD
1
TRACK/SS
TMR COMP SGND GND
FAULT INDICATOR
LATCHOFF RESET
TO SYSTEM µP
(OPTIONAL)
C
SS
22nF
C
TMR1
N/U
1
1
1
PULL LATCH NORMALLY LOW FOR
LATCHOFF RESPONSE TO OUTPUT
OVERVOLTAGE AND OVER-
TEMPERATURE EVENTS. PULL
LATCH HIGH TO RESTART 1V OUTPUT
V
V
V
SW
ING INGP
INH
V
V
OUT
INL
R
fSET2
750k
CROWBAR
f
SET
ALTERNATIVELY, CONNECT LATCH
UVLO
HYST
FCB
LATCH
TO INTV AND INSTALL C
,
CC
, C
TMR1
TO SET
+
V
ORB
C
AND C
TMR2 TMR3
1V OUTPUT FOR TIMED
TMR4
+
V
OSNS
U2
LTM4641
2
2
AUTONOMOUS RESTART AFTER
FAULT SHUTDOWN EVENTS
C
DM2
10pF
INTV
DRV
CC
–
–
V
OSNS
CC
MCB: NXP PSMN5R0-30YL
MSP: NXP PSMN3R0-60BS
V
IOVRETRY
OVLO
ORB
TEMP
1V
REF
OVPGM
OTBH
PGOOD
RUN
2
TRACK/SS
TMR COMP SGND GND
C
TMR2
N/U
2
2
V
V
V
SW
ING INGP
INH
V
V
OUT
INL
R
fSET3
750k
CROWBAR
f
SET
UVLO
HYST
FCB
LATCH
+
V
ORB
+
V
OSNS
U3
LTM4641
3
3
C
DM3
10pF
INTV
DRV
CC
–
–
V
OSNS
CC
V
IOVRETRY
OVLO
ORB
TEMP
1V
REF
OVPGM
OTBH
RUN
PGOOD
3
TRACK/SS
TMR COMP SGND GND
C
TMR3
N/U
3
3
V
V
V
SW
ING INGP
INH
V
V
OUT
INL
R
fSET4
750k
CROWBAR
f
SET
UVLO
HYST
FCB
LATCH
+
V
ORB
+
V
OSNS
U4
LTM4641
4
4
C
DM4
10pF
INTV
DRV
CC
–
–
V
OSNS
CC
V
IOVRETRY
OVLO
ORB
TEMP
1V
REF
OVPGM
OTBH
RUN
PGOOD
4
TRACK/SS
TMR COMP SGND GND
C
TMR4
N/U
4
4641 F56
4
) CONNECT TO GND INTERNAL TO THEIR RESPECTIVE MODULES. KEEP MODULE
4
U1, U2, U3 AND U4 SGND (
,
,
,
3
1
2
SGND ROUTES/PLANES SEPARATE FROM OTHER MODULES AND FROM GND ON MOTHERBOARD
Figure 56: 1V, 40A Fault-Protected Load Powered by Four Parallel LTM4641—from Up to 38VIN. cf. Figure 57
4641f
52
LTM4641
TYPICAL APPLICATIONS
12
10
8
6
4
2
U1 OUTPUT CURRENT
U2 OUTPUT CURRENT
U3 OUTPUT CURRENT
U4 OUTPUT CURRENT
0
–2
8
16
24
40
0
32
TOTAL OUTPUT CURRENT (A)
4641 F57
Figure 57: Current-Sharing Performance of Four Paralleled LTM4641. Figure 56 Circuit, Operating at 28VIN
FOR MORE INFORMATION ABOUT CONFIGURING STEP-DOWN BUCK
OPERATION
UP TO 32.8V
CONVERTERS AS BUCK-BOOST CONVERTERS, FOR GENERATING
IN
+
C
NEGATIVE V , SEE http://www.linear.com/docs/39881
IN(MLCC)
OUT
4.5V START-UP
C
IN(BULK)
10µF
50V
×4
50V
V
V
V
SW
ING INGP INH
V
INL
V
OUT
CROWBAR
f
SET
UVLO
HYST
FCB
LATCH
R
SET1A
+
V
8.2k
ORB
+
V
OSNS
LOCAL HIGH
FREQUENCY
DECOUPLING
U1
LTM4641
R
R
SET1B
8.2k
SET2
LOAD
D1
INTV
DRV
CC
2.46k
–
–
V
OSNS
CC
V
IOVRETRY
OVLO
ORB
TEMP
1V
REF
OVPGM
OTBH
RUN
PGOOD
100k
TRACK/SS
TMR COMP SGND GND
C
SS
C
OUT(MLCC)
10nF
47µF
10V
×4
V
OUT
–5.2V AT
UP TO 10A
D1: CENTRAL SEMI CMPSH1-4LE
SGND CONNECTS TO GND INTERNAL TO MODULE, KEEP SGND
ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD
4641 F58
Figure 58. Negative Output Application. Delivering –5.2VOUT at Up to 10A, from Up to 32.8VIN. cf. Figure 59
V
IN
10V/DIV
HYST 2V/DIV
PGOOD 2V/DIV
V
OUT
2V/DIV
*
4641 F59
20ms/DIV
Figure 59. Pulsed Application of VIN. Figure 58 Circuit with 500Ω Load.
*Ultralow VF of D1 Minimizes VOUT Overshoot Upon Energization
4641f
53
LTM4641
TYPICAL APPLICATIONS
MSP
4.5V < V < 15V
IN
+
C
C
IN(MLCC)
IN(BULK)
22µF
25V
×2
100µF
25V
V
V
V
SW
V
ING INGP INH
OUT
V
V
1.2V NOMINAL
INL
OUT
R
UP TO 10A OUTPUT
fSET
1.13M
MCB
CROWBAR
100µF
6.3V
×4
f
SET
LATCHOFF
UVLO
HYST
FCB
LATCH
RESET
ADDITIONAL
FAULT INDICATOR
R
SET1A
8.2k
+
V
ORB
+
V
LOCAL HIGH
FREQUENCY
DECOUPLING
OSNS
LTM4641*
R
SET1B
8.2k
LOAD
INTV
DRV
CC
–
V
OSNS
CC
–
V
IOVRETRY
OVLO
ORB
TEMP
R30
35.7k
MSP: NXP PSMN017-30LL
MCB: NXP PSMN5R0-30YL
1V
REF
OVPGM
OTBH
PGOOD
V
PWR
V
IN_SNS
†
3.3V
RUN
V
DD33
V
OUT_EN0
TRACK/SS
TMR COMP SGND GND
TO UPSTREAM
V
IN_EN
SYSTEM ENABLE
C
SS
4.7nF
SDA
LTC2978**
PMBus
INTERFACE
SCL
ALERT
V
DACPO
CONTROL0
V
SENSEPO
V
SENSEMO
WP
WRITE PROTECT
V
DACMO
*LTM4641 SGND CONNECTS TO GND INTERNAL TO MODULE.
KEEP SGND ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD
TO/FROM
OTHER
LTC2978s
FAULTOO
SHARE_CLK
PWRGD
WDI/RESET
ASELO ASEL1
TO µP RESET INPUT
**ONLY ONE OF EIGHT LTC2978 CHANNELS SHOWN. LTC2978 PULL-UPS,
BYPASSING COMPONENTS, AND SOME PINS NOT SHOWN. FOR DETAILS
OF LTC2978 IMPLEMENTATION, SEE LTC2978 DATA SHEET
WATCHDOG TIMER INTERRUPT
GND
†
LTC2978 MAY BE POWERED FROM EITHER AN EXTERNAL 3.3V
SUPPLY OR THE SYSTEM BUS
Figure 60. Fault-Protected Load with Power Supply Management. LTM4641’s Fast Output Overvoltage Latchoff Trip
Threshold Remains Consistently 11% Above LTC2978-Commanded Target VOUT, Even as VOUT is Margined Via I2C
V
V
OUT
200mV/DIV
OUT
200mV/DIV
V
V
DACPO
500mV/DIV
DACPO
500mV/DIV
SDA, SCL
2V/DIV
SDA, SCL
2V/DIV
4641 F61a
4641 F61b
20ms/DIV
20ms/DIV
(61a) PMBus OPERATION (Reg. 0x01): 0x80 → 0xA8 (Margin High)
(61b) PMBus OPERATION (Reg. 0x01): 0xA8 → 0x80 (Margin Off)
V
V
OUT
OUT
200mV/DIV
200mV/DIV
V
V
DACPO
DACPO
500mV/DIV
500mV/DIV
SDA, SCL
2V/DIV
SDA, SCL
2V/DIV
4641 F61d
4641 F61c
20ms/DIV
20ms/DIV
(61c) PMBus OPERATION (Reg. 0x01): 0x80 → 0x98 (Margin Low)
(61d) PMBus OPERATION (Reg. 0x01): 0x98 → 0x80 (Margin Off)
Figure 61. LTM4641’s VOUT Margined High/Low by LTC2978 Via I2C Commands. Figure 60 Circuit. 12VIN.
VOUT_COMMAND (0x21) = 1.20V, VOUT_MARGIN_HIGH (0x25) = 1.32V, VOUT_MARGIN_LOW (0x26) = 1.08V
4641f
54
LTM4641
APPENDICES
Appendix A. Functional Block Diagram and Features Quick Reference Guide
4641f
55
LTM4641
APPENDICES
Appendix B. Start-Up/Shutdown State Diagram
4641f
56
LTM4641
APPENDICES
Appendix C. Switching Frequency Considerations and
(3) Inrail-trackingapplications,LTM4641’soutputvoltage
Usage of R
must track a reference voltage not only during V
fSET
OUT
ramp up but also during V
ramp down; fulfilling
OUT
There exist many scenarios in which a resistor, R
,
fSET
the latter requires LTM4641 to sink current from the
output capacitors. A value of R should be used
should be connected externally to LTM4641’s f pin—to
SET
fSET
decrease the on-time of M : most commonly, when the
TOP
that assures the output voltage can be ramped down
to one’s minimum desired output voltage of regula-
tion—not just the intended nominal output voltage.
Figure 3 provides this guidance.
output voltage setting is less than or equal to 3V, and in
rail-tracking applications; and less commonly, when V
INL
and V are operating from different source supplies. In
INH
the former cases, R
is usually applied from f to V
fSET
SET INL
(Figure 45 and front page application circuit); in the latter,
is usually applied from f to the voltage source
feeding LTM4641’s power stage—upstream of MSP, if a
power-interrupt input MOSFET is used (Figure 49). There
are several motivations and considerations behind this
guidance:
(4) In order to maintain a relatively constant switching
frequency for a given output voltage (across the full
R
fSET
SET
line voltage), the on-time of M
should be inversely
TOP
proportional to the voltage source feeding the V
INH
power stage—upstream of MSP, if a power-interrupt
MOSFET is used (Figure 46). When V and V are
INL
INH
operated from different rails, this goal can be accom-
(1) Inherent to LTM4641’s constant on-time architec-
ture, the switching frequency of LTM4641 decreases
as output voltage decreases. In order to maintain a
reasonable output capacitor value solution size and
output voltage ripple—even at lower output voltages
plished satisfactorily by placing R between f
fSET
SET
and the power V input source (see Figure 49: the
IN
connectionistoV andnotV ,andusuallynotV ,
IN
INL
INH
but see a counterexample in Figure 47 and explana-
tion in item number 5 of this list). A minor error term
to the on-time is introduced by the internal 1.3MΩ
(≤3V )—R
shouldbeapplied,sothatthecontrol-
OUT
fSET
ler’sI pincurrentandtheresultingnominalswitching
ON
V
-to-f -connected resistor in such scenarios, so
INL
SET
frequency is higher than the on-time dictated by the
calculation of I at all operating input voltage corner
ION
internal V -to-f -connected 1.3MΩ resistor.
INL
SET
cases (power, V and control bias, V extremes)
INH
INL
(2) ThePFMcontrolschemeemployedbyLTM4641yields
a switching frequency at zero load current (“no-load
operation”) that is typically 20% to 25% lower than
what it is at full load. As a result, inductor ripple cur-
rent is proportionally higher at no load than what it is
and the resulting switching frequency range of opera-
tion, given by Equation 6, should be considered.
(5) When MSP is used, and when V
and V
are
INL
INH
operated from different rails—here is the reason it
is recommended to connect R from f to the
fSET
SET
at heavy load. Recall that LTM4641 employs R
DS(ON)
drain of MSP rather than V : prior to start-up, MSP
INH
currentsensing;furthermore,realizethatitisessential
forthecontroller’scurrent-senseamplifiertobeableto
perceive and command sufficiently negative inductor
troughcurrent,enoughtomaintainamaximumaverage
inductor current of 0A, so that output voltage can be
is off, and V
INH
is discharged. Connecting R
to
INH
fSET
V
would set the on-time at the instant switching
activity commenced to be much lower than intended.
The on-time would not reach its final settling value
until V
INH
circuitry had turned on MSP enough for
ING
properly regulated down to no load. A value of R
fSET
V
to become pulled up to V potential. It should
IN
should be used to assure that switching frequency is
high enough (or on-time is small enough) at no load
sothatthecurrent-senseinformationrepresentingthe
trough of choke current is never too large in ampli-
tude. Figure 3 provides conservative guidance on the
become apparent that a mechanism may exist for
dynamic interaction between how rapidly the output
voltagerampsup(dependingonTRACK/SSpinusage)
versushowrapidlyMSPmightturnon. Weknowfrom
item number 2 of this list that on-time should not be
arbitrarily large. In general, to avoid any undesirable
maximumvalueofR
ON
(orequivalently,theminimum
fSET
I
current) that assures proper no-load operation.
4641f
57
LTM4641
APPENDICES
thermore, using an R
(and R
) value of 8.2kΩ
SET1B
interactions—which might at worst result in exces-
sive output voltage ripple or non-monotonic output
voltage ramp-up, a sufficiently slow output voltage
SET1A
for 1.2V
and larger assures that the common mode
OUT
range of the remote-sense pins is within their valid range
of–0.3V,minimum,to3V,maximum—evenifvoltagedrop
between the module’s ground deviates from the POL’s
ground by as much as 0.6V.
ramp-up time can eliminate the danger of V
and
INH
on-time settling interactions influencing output volt-
age ripple—but properly, this requires investigation
and hardware evaluation on a case-by-case basis.
The differential remote-sense feedback signal is routed
from the load as a differential pair on PCB traces (or
twisted pair, if wires are used) to R
components. It is very important to place R
andallothercomponentsformingthefeedbackimpedance-
dividernetworkasclosetoLTM4641asispossible.Ground
shieldingofthedifferentialremote-sensesignalisstrongly
recommended, to prevent stray noise from contaminating
the feedback information.
Figure 47 shows an example where R
connects
fSET
between f and V —rather than the input source
SET
INH
/R
feedback
/R
SET1A SET1B
supply. Because MSP limits the V voltage during
INH
ON
SET1A SET1B
the input voltage surge, the correct I programming
current can only be made with a resistor interface to
V , in that example.
INH
Appendix D. Remote Sensing in Harsh Environments
Therationaleforusingthesymmetricalresistornetworkis
toprovideaconsistentfeedbackstructurethatenablesfully
differentialremote-senseofoutputvoltagesbetween0.6V
and 6V with the flexibility to filter differential and common
mode noise in harsh environments. See Figure 64. The
If good shielding of the feedback signals cannot be pro-
vided, it is proactive to leave space in one’s layout for a
+
small filtercapacitor, C , placed directly between V
DM
OSNS
–
and V
, as close to the pins of the module as pos-
sible—in anticipation of the possible need to attenuate
OSNS
useofnotgreaterthan8.2kΩnominalresistorsforR
SET1A
differential mode noise.
(and R
) assures that the remote-sense signal is not
SET1B
Finally, if the POL is very far from the LTM4641, such as:
attenuated at frequencies of interest by the pole formed
by the feedback resistors and parasitic capacitances. Fur-
the output power connection (V
and GND) is made
OUT
C
, C : If Appreciable Cable Length Connects the LTM4641’s Output
CMA CMB
to the Load (e.g., Through Several Feet of Wire), Leave Provision
for High Frequency Decoupling of Common Mode Ground Noise with
These Capacitors. These Are Not Needed in Purely PCB-Based Designs,
Where the LTM4641 Is Close to the Load
C
, C : Feedforward Capacitors
FFA FFB
Yeild Improved Transient Response
When Filtering V
Output Capacitors (C
with Only MLCC
OUT
)
OUT(MLCC)
V
OUT
V
OUT
+
LTM4641
C
FFA
C
C
OUT(MLCC)
OUT(BULK)
ICT
TEST
POINT
+
V
ORB
C
CMA
R
8.2k
8.2k V
SET1A
V
+
FB
OSNS
TO ERROR
AMPLIFIER
+
R
C
LOAD
SET2
C
DM
8.2k
R
SET1B
–
–
–
V
OSNS
8.2k
4641 F064
C
ICT
TEST
POINT
FFB
V
CMB
ORB
TRUE DIFFERENTIAL REMOTE
SENSE AMPLIFIER
SGND
GND
Route Feedback Signals as
a Differential Pair (or
Twisted Pair if Using Wires).
Sandwich Between Ground
Planes to Form a Protective Shield,
Guarding Against Stray Noise
Place All Feedback
Components Local
To The LTM4641
SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP SGND
ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD
If Effective Ground Shielding of the Feedback Signals Cannot
Be Implemented, Leave Provision for a Small Capacitor (C
To Attenuate Differential Mode Noise if Necessary
)
DM
Figure 64. Feedback Remote Sense Connections and Techniques for Harshest Operating Environments
4641f
58
LTM4641
APPENDICES
operation (FCB logic high), the inductor ripple current at
light loads appears as an asymmetrical truncated triangle
waveform; inductor current does not go below 0A.
through a board-to-board connector; an inductive length
of cable (say, 50cm in length, or more); or, if the load is
highly inductive—then it is proactive to leave provision
in one’s layout for a pair of small filter capacitors, C
CMA
Appendix F. Adjusting the Fast Output Overvoltage
Comparator Threshold
and C
OSNS
. C
and C
should be placed directly from
CMB CMA
CMB
OSNS
+
–
V
to SGND and V
to SGND, respectively—as
close to the pins of the module as possible. Configured
The output overvoltage inception threshold (OV
volt-
PGM
in this manner, C
and C
can be used to attenuate
CMA
CMB
age) can be adjusted or tightened from its default value.
The following guidelines must be followed, however:
common mode noise in the remote-sense signal pin pair.
•ꢀ ItꢀisꢀnotꢀrecommendedꢀtoꢀchangeꢀtheꢀOV
voltage
Appendix E. Inspiration For Pulse-Skipping Mode
Operation
PGM
dynamically because the fast OOV comparator has no
glitch immunity beyond what is provided by OV ’s
PGM
canmake
When M
is turned on—for a duration of time propor-
TOP
internal47pFcapacitor, androutingofOV
it vulnerable to electrostatic noise.
PGM
tionaltoI current—inductorcurrentisrampedupwards,
ION
and energy is built up in the inductor’s B-field. Ultimately,
a “packet” of energy is transferred from the input capaci-
tors to the output capacitors. In forced continuous mode
•ꢀ Theꢀ15.6μsꢀtimeꢀconstantꢀfilterꢀformedꢀbyꢀOV
’s in-
PGM
ternal47pFcapacitoranddefault499kΩ||1MΩresistor-
dividernetworkshouldbemaintainedforpracticalvalues
operation (FCB logic low), M
and M
are operated in
TOP
BOT
of OV
voltage: 0.6V < V
< 0.9V. Capacitive
apurelysynchronousfashion, meaning:whenM
ison,
PGM
OVPGM
TOP
filtering of OV must not be applied indiscriminately.
M
is off—and vice versa. Observe that when M
is
PGM
TOP
BOT
The OV
voltage must come up very rapidly with the
PGM
turnedoff,theB-fieldintheinductorcannotinstantaneously
1V atstart-up, topreventaraceconditionthatwould
vanish: the collapsing B-field forces inductor current to
flow through M ’s on-die Schottky diode—resulting in
unwanted freewheeling diode power loss; M
on for lower power loss, instead. With M
REF
otherwise result in nuisance OOV detection and a faulty
BOT
latchoff event—so any externally applied capacitance
is turned
BOT
on, inductor
cannot be arbitrarily high. On the other hand, OV
PGM
BOT
must have some filtering from switching noise sources
and should be sufficiently insulated from any possible
current ramps downward as energy in its B-field wanes.
In steady-state forced continuous mode operation, the
inductor ripple current appears as a triangle waveform
whose average value equates to the load’s current. Forced
continuous mode operation (forcing synchronous opera-
dynamic activity on 1V . (See Figure 9.)
REF
•ꢀ Externalꢀresistor(s)ꢀappliedꢀbetweenꢀOV
and 1V
/
REF
PGM
SGNDshouldberelativelyhighimpedance, tominimize
loading on the 1V output. Then, small values of
tion of M
and M ) provides a mechanism for consis-
REF
TOP
BOT
C
achieveaconsistenttimeconstantasOVPGM’s
resistance-divider network is altered.
tent output voltage ripple, regardless of the load current.
However, in this mode of operation, at light load currents
(say, less than 2A out), observe that the inductor current
is periodically negative—which means some packets of
energythataretransferredfromtheinputcapacitorstothe
output are recirculated and transferred back to the input
capacitors. This is a source of inefficiency that brings
about the motivation for pulse-skipping mode operation,
OVPGM
Figure 65 shows the optional network one can apply to
alter or tighten the OV
setpoint.
PGM
1V
REF
R
TOVPGM
LTM4641
OV
PGM
to turn off M
when the inductor current ramps down
BOT
C
R
BOVPGM
OVPGM
to 0A. This concept is also described in the industry as
“diode emulation”, because M is made to mimic the
SGND
4641 F65
BOT
behavior of a Schottky rectifier. In pulse-skipping mode
Figure 65. Optional OVPGM Network to Alter or Tighten VOVPGM
4641f
59
LTM4641
APPENDICES
To nudge the OV
setpoint downward, to a new OOV
100kΩ, low T.C.R. resistor. Using tolerances of 0.1%
and a T.C.R. of 25ppm/ꢀC can provide a considerable
improvementinaccuracyoverthedefaultdividernetwork,
PGM
inception threshold voltage at OV
—using an
PGM(NEW)
R
resistor, only—calculate:
BOVPGM
over temperature. Next, decide the new value of V
OVPGM
1
RBOVPGM
=
desired—OV
—withinapracticalwindowof0.6V<
(37)
PGM(NEW)
<0.9V.Then,computeR
1V –OVPGM(NEW)
1
–
OV
accordingto:
PGM(NEW)
TOVPGM
OVPGM(NEW) •499kΩ 1MΩ
RTOVPGM
=
The new OV
threshold can then be double-checked by
PGM
1
(42)
OVPGM(NEW)
1
1V • 1MΩ||R
499kΩ+1MΩ||R
(
)
BOVPGM
–
OVPGM(NEW)
=
(38)
499kΩ
1V –OVP
• 1MΩ||R
BOVPGM
(
)
(
)
GM(NEW)
(
)
BOVPGM
The new OV
setting can be double-checked by:
When lowering the OV
BOVPGM
setpoint with application of
PGM
PGM
R
only, it is not necessary to apply a C
OVPGM
1V • 1MΩ||R
499kΩ||RTOVPGM +1MΩ||RBOVPGM
(
)
BOVPGM
OVPGM(NEW)
=
(43)
capacitor, because: for an extreme OVPGM(NEW) setting
(
)
of 600mV, which is not practical since that is the voltage
of V during normal regulation, the time-constant of the
FB
PGM
Then, use the next smallest standard value of C
available, computed by:
OVPGM
OV
network would have changed by less than 2μs
from its default value.
COVPGM(NEW)
=
To nudge the OV trip threshold upward to set a new
PGM
15.6µs
499kΩ||1MΩ||RTOVPGM ||RBOVPGM
—using
(39)
(44)
OOV inception threshold voltage at OV
–47pF
PGM(NEW)
(
)
an R
resistor only—calculate:
TOVPGM
1
For example, the OV
nominal value of 666mV—but with better accuracy—by
using 0.1% precision resistors with 25ppm/ꢀC T.C.R.
setpoint can be kept at its
PGM(NEW)
R
=
TOVPGM
OV
1
PGM(NEW)
–
499kΩ
1V – OV
•1MΩ
(
)
PGM(NEW)
for R
OV
= 100k and R
= 49.9k, and bypassing
BOVPGM
TOVPGM
toSGNDwithC
=470pF.TheresultingV
OVPGM
The new OV
setting can then be double-checked by:
PGM
OVPGM
PGM
OOV setpoint threshold becomes better than 1.8%, over
1V •1MΩ
OVPGM(NEW)
=
temperature. The vast majority of the remaining variation
(40)
499kΩ||R
+1MΩ
(
)
TOVPGM
in the threshold setting comes variation of the 1V —a
REF
1.5% reference, over temperature.
If R
is computed in Equation 39 to be smaller than
TOVPGM
10kΩ, connect OV
to 1V
and do not apply any
The extreme values of the OOV setpoint voltage, plus
PGM
REF
C
capacitor; this will yield an OOV setting of 167%
the OVP
term—which is the offset voltage of the fast
OVPGM
ERR
of nominal. Otherwise, use the next smallest standard
comparator( 12mVmaximum,overtemperature)—gives
guidanceonwhattheminimumandmaximumvoltageV
value of C
available, computed by:
OVPGM
FB
can be at which the CROWBAR output would swing logic
high and invoke latchoff overvoltage protection.
15.6µs
499kΩ||1MΩ||R
COVPGM
=
–47pF
(41)
(
)
TOVPGM
One must take care to set the OV
level and not too aggressively. If OV
the system will demonstrate nuisance output overvoltage
latchoff behavior. The output voltage of any switching
voltage to a practical
PGM
PGM
The default V
setpoint is 665mV 2.26%, over
is set too low,
OVPGM
temperature. To tighten the OV
setpoint, begin by
PGM
choosing R
to be a commonly available precision
BOVPGM
4641f
60
LTM4641
APPENDICES
regulator can witnesses transient excursions above its
ideal DC voltage operating point routinely, owing to:
short-circuit testing (shorting V to SW on evaluation
INH
hardware such as DC1543, for example) does not clamp
the output voltage to one’s satisfaction, be aware that
increasing output capacitance can reduce the maximum
output voltage excursion. The reason follows: the larger
the output capacitance, the longer it takes for the output
voltage to be ramped up, even in the extreme case of
•ꢀ ControlꢀICꢀbandgapꢀreferenceꢀaccuracy
•ꢀ Outputꢀvoltageꢀrippleꢀandꢀnoise
•ꢀ Loadꢀcurrentꢀstep-downꢀtransientꢀevents—includingꢀ
recovery from a short-circuit condition
deliberately short circuiting V to SW. The capacitance
INH
•ꢀ Steepꢀlineꢀvoltageꢀstep-up
on V
is mainly what prevents the output voltage from
shooting up to V —until CROWBAR turns on MCB.
OUT
•ꢀ Start-upꢀovershootꢀ(littleꢀorꢀnoꢀsoft-startingꢀofꢀV ),
INH
OUT
or rail-tracking a fast master rail
Multimodule parallel applications also have better output
voltage overshoot during high side MOSFET short-circuit
testing, owing to the fact that the sibling modules whose
high side MOSFETs are not short circuited are able to help
pull the output voltage down by turning on their low side
power MOSFETs. Examples of paralleled LTM4641 power-
ing and protecting loads are shown in Figures 56 and 66.
The Linear Technology LTpowerCAD design tool can help
quantify some of these dynamic values; LTM4641’s total
DC error (including bandgap reference variation) is better
than 1.5%, over temperature.
If OV
has been decreased to its lowest practical level
PGM
and output voltage overshoot during high side MOSFET
4641f
61
LTM4641
PACKAGE DESCRIPTION
Table 10. LTM4641 Component BGA Pinout
PIN ID FUNCTION PIN ID
FUNCTION
SGND
SGND
SGND
UVLO
OVLO
GND
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
+
A1
A2
SGND
SGND
SGND
HYST
TEMP
IOVRETRY
GND
B1
B2
C1
C2
SGND
SGND
SGND
SGND
LATCH
1VREF
GND
D1
D2
VORB
VORB
E1
E2
GND
GND
GND
GND
GND
GND
GND
GND
VOUT
VOUT
VOUT
VOUT
F1
F2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
–
A3
B3
C3
D3
OTBH
TMR
RUN
GND
GND
GND
VOUT
VOUT
VOUT
VOUT
E3
F3
A4
B4
C4
D4
E4
F4
A5
B5
C5
D5
E5
F5
A6
B6
C6
D6
E6
F6
A7
B7
GND
C7
D7
E7
F7
A8
GND
B8
GND
C8
GND
D8
E8
F8
A9
GND
B9
CROWBAR
OVPGM
GND
C9
VOUT
D9
E9
F9
A10
A11
A12
GND
B10
B11
B12
C10
C11
C12
VOUT
D10
D11
D12
E10
E11
E12
F10
F11
F12
GND
VOUT
GND
GND
VOUT
PIN ID FUNCTION PIN ID
FUNCTION
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
+
G1
G2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
H1
H2
VOSNS
J1
J2
COMP
fSET
K1
K2
SGND
FCB
L1
L2
PGOOD
TRACK/SS
SGND
GND
M1
M2
SGND
SGND
SGND
GND
GND
GND
VINH
–
VOSNS
G3
H3
GND
GND
GND
GND
GND
GND
GND
SW
J3
VINL
K3
SGND
INTVCC
GND
GND
VINH
L3
M3
G4
H4
J4
DRVCC
GND
GND
GND
GND
GND
GND
GND
GND
K4
L4
M4
G5
H5
J5
K5
L5
GND
M5
G6
H6
J6
K6
L6
GND
M6
G7
H7
J7
K7
L7
VINH
M7
G8
H8
J8
K8
VINH
L8
VINH
M8
VINH
G9
H9
J9
K9
VINH
L9
VINH
M9
VING
G10
G11
G12
H10
H11
H12
J10
J11
J12
K10
K11
K12
VINH
L10
L11
L12
VINH
M10
M11
M12
VINGP
VINH
GND
GND
GND
GND
VINH
VINH
VINH
PACKAGE PHOTO
4641f
62
LTM4641
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
Z
/ / b b b
Z
6 . 9 8 5 0
5 . 7 1 5 0
4 . 4 4 5 0
3 . 1 7 5 0
1 . 9 0 5 0
0 . 6 3 5 0
0 . 0 0 0 0
0 . 6 3 5 0
1 . 9 0 5 0
3 . 1 7 5 0
4 . 4 4 5 0
5 . 7 1 5 0
6 . 9 8 5 0
a a a
Z
4641f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
63
LTM4641
TYPICAL APPLICATION
4.5V START-UP
IN
OPERATION UP TO 38V
AND DOWN TO 4V
MSP
C
C
IN(MLCC)
IN(BULK)
100µF
50V
×2
10µF
50V
×4
V
V
V
SW
V
ING INGP INH
OUT
V
V
1V
INL
OUT
C
R
FF1
100pF
20A
MLCC(OUT)
fSET1
750k
MCB
CROWBAR
C
f
SET
100µF
6.3V
×6
UVLO
HYST
FCB
LATCH
R
+
SET1A
2.74k
V
ORB
+
V
OSNS
LOCAL HIGH
FREQUENCY
DECOUPLING
U1
LTM4641
1
1
R
C
SET1B
2.74k
DM1
22pF
LOAD
INTV
DRV
CC
–
–
V
OSNS
CC
C
V
FF2
100pF
IOVRETRY
OVLO
ORB
TEMP
1V
REF
OVPGM
OTBH
RUN ENABLE
RUN
PGOOD
1
TRACK/SS
TMR COMP SGND GND
FAULT INDICATOR
LATCHOFF RESET
TO SYSTEM µP
(OPTIONAL)
C
SS
22nF
C
TMR1
N/U
1
1
1
PULL LATCH NORMALLY LOW FOR
LATCHOFF RESPONSE TO OUTPUT
OVERVOLTAGE AND OVER-
TEMPERATURE EVENTS. PULL
LATCH HIGH TO RESTART 1V OUTPUT
V
V
V
SW
ING INGP
INH
V
V
OUT
INL
R
fSET2
750k
CROWBAR
f
SET
ALTERNATIVELY, CONNECT LATCH
UVLO
HYST
FCB
LATCH
TO INTV AND INSTALL C
TMR2
AUTONOMOUS RESTART AFTER
FAULT SHUTDOWN EVENTS
AND
CC
TO SET 1V OUTPUT FOR TIMED
TMR1
+
V
ORB
C
+
V
OSNS
U2
LTM4641
2
2
C
DM2
22pF
INTV
DRV
CC
–
–
V
OSNS
CC
MCB: NXP PSMN5R0-30YL
MSP: NXP PSMN7R0-60YS
V
IOVRETRY
OVLO
ORB
TEMP
1V
REF
OVPGM
OTBH
PGOOD
RUN
2
TRACK/SS
TMR COMP SGND GND
C
TMR2
N/U
2
4641 F66
2
) CONNECT TO GND INTERNAL TO THEIR RESPECTIVE MODULES. KEEP MODULE
2
U1 AND U2 SGND (
SGND ROUTES/PLANES SEPARATE FROM OTHER MODULES AND FROM GND ON MOTHERBOARD
,
1
Figure 66. 1V, 20A Fault-Protected Load Powered by Paralleled LTM4641—from Up to 38VIN. cf. Typical Performance Characteristics
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
Up to 100A with Four Devices; 4.5V ≤ V ≤ 16V; 0.6V ≤ V
LTM4620
Dual 13A, Single 26A µModule
Regulator
≤ 2.5V. See LTM4620A for Higher
OUT
IN
V
; 15mm × 15mm × 4.41mm LGA
OUT
LTM4613
LTM4627
LTM8027
LTM4609
LT4356
EN55022B Certified 36V, 8A
5V ≤ V ≤ 36V; 3.3V ≤ V
≤ 15V; Synchronizable, Parallelable,
OUT
IN
Step-Down µModule Regulator
15mm × 15mm × 4.32mm LGA
4.5V ≤ V ≤ 20V; 0.6V ≤ V ≤ 5V; Synchronizable, Parallelable,
20V, 15A Step-Down µModule
Regulator
IN
OUT
Remote Sensing, 15mm × 15mm × 4.32mm LGA or 15mm × 15mm × 4.92mm BGA
60V, 4A Step-Down µModule
Regulator
4.5V ≤ V ≤ 60V; 2.5V ≤ V
≤ 24V; Synchronizable,
IN
OUT
15mm × 15mm × 4.32mm LGA
4.5V ≤ V ≤ 36V; 0.8V ≤ V
36V, 4A Buck-Boost µModule
Regulator
≤ 34V; Synchronizable, Parallelable, Up to 4A in Boost Mode
OUT
IN
and 10A in Buck Mode, 15mm × 15mm × 2.82mm LGA or 15mm × 15mm × 3.42mm BGA
High Voltage Surge Stopper
100V Overvoltage and Overcurrent Protection, Latchoff and Auto-Retry Options
IN
4641f
LT 1012 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
64
●
●
LINEAR TECHNOLOGY CORPORATION 2012
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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