CSHD3-40 [Linear]
36V, 2.6A Monolithic Buck; 36V ， 2.6A单片式降压型
| 型号： | CSHD3-40 |
| 厂家： | 
Linear |
| 描述： | 36V, 2.6A Monolithic Buck |
| 文件： | 总28页 (文件大小：333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3694/LT3694-1
36V, 2.6A Monolithic Buck
Regulator With Dual LDO
FEATURES
DESCRIPTION
The LT®3694/LT3694-1 are monolithic, current mode
DC/DC converters with dual, low dropout regulator con-
trollers. The switching converter is a step-down converter
capable of generating up to 2.6A at its output. Each regu-
lator has independent track/soft-start circuits simplifying
power supply sequencing and interfacing with micro-
controllers and DSPs.
n
Wide Input Range: 4V to 36V
n
Overvoltage Shutdown Protects Circuit Through
70V Transients
n
2.6A Output Switching Regulator with Internal
Power Switch
n
Dual, Low Dropout, Linear Regulator Controllers
with Programmable Current Limit
n
Tracking/Soft-Start Inputs and Power Good Output
The switching frequency is set with a single resistor with a
range of 250kHz to 2.5MHz. The high switching frequency
permits the use of small inductors and ceramic capacitors
leadingtoverysmalltripleoutputsolutions. Theconstant-
switching frequency, combined with low impedance ce-
ramic capacitors, results in low, predictable output ripple.
Protectioncircuitrysensesthecurrentinthepowerswitch
and external Schottky catch diode to protect the LT3694
against short-circuit conditions. Frequency foldback and
thermal shutdown provide additional protection.
Simplify Soft-Start and Supply Sequencing
n
Uses Small Inductors and Ceramic Capacitors
n
V
= 0.75V (Buck and LDOs)
OUT(MIN)
n
n
Adjustable 250kHz to 2.5MHz Switching Frequency
Accurate Enable Threshold Allows User
Programmable Undervoltage Lockout
n
n
Options for Clock Synchronization (LT3694) or Clock
Output to Enable Synchronization to Other Switching
Regulators (LT3694-1)
Thermally Enhanced 28-Lead 4mm × 5mm QFN and
20-Lead TSSOP Packages
With its wide input voltage range of 4V to 36V, the LT3694
regulatesabroadarrayofpowersourcesfrom4-cellbatteries
and5Vlogicrailstounregulatedwalltransformers,leadacid
batteriesanddistributedpowersupplies.TheLT3694canbe
synchronized to an external clock with the SYNC pin while
the LT3694-1 offers a CLKOUT pin allowing other DC/DC
converters to synchronize to the LT3694-1 clock.
APPLICATIONS
n
Automotive
n
Industrial
n
DSL and Cable Modems
n
Distributed Power Regulation
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective owners.
n
Wall Transformer Regulation
TYPICAL APPLICATION
V
IN
Efficiency at VOUT = 3.3V
4.5V TO 36V
4.7µF
V
EN/UVLO
BIAS BST
IN
100
0.22µF
B340A
f
= 800kHz
SW
4.7µH
OUT1
3.3V
1.7A
TRK/SS1
TRK/SS2
TRK/SS3
SW
V
V
= 4.5V
= 12V
IN
90
80
70
60
50
1nF
34k
10k
IN
DA
FB1
0.1Ω
47µF
V
= 36V
LT3694
IN
330pF
OUT1
LIM2
DRV2
41.2k
V
C1
OUT2
2.5V
450mA
OUT1
LIM3
DRV3
0.1Ω
24.9k
10.7k
OUT3
1.8V
450mA
2.2µF
FB2
SYNC
15.4k
2.2µF
FB3
PGOOD
RT
0
1
2
3
51.1k
11k
I
(A)
OUT
GND
36941 TA01b
f
= 800kHz
SW
36941 TA01a
36941fb
1
LT3694/LT3694-1
ABSOLUTE MAXIMUM RATINGS (Note 1)
V , EN/UVLO (Note 6)............................... –0.3V to 70V
Operating Junction Temperature Range (Notes 2 and 5)
LT3694E............................................. –40°C to 125°C
LT3694I.............................................. –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 Sec)
IN
BST...........................................................................55V
BST Above SW..........................................................25V
PGOOD......................................................................16V
TRK/SS, V , FB, RT, SYNC Pins...................................6V
C
BIAS, LIM2, LIM3 Pins ...............................................7V
(TSSOP Only) ................................................... 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
V
1
2
3
4
5
6
7
8
9
20
19
18
17
16
SW
IN
28 27 26 25 24 23
EN/UVLO
SYNC(CLKOUT)
PGOOD
DA
EN/UVLO
SYNC (CLKOUT)
PGOOD
1
2
3
4
5
6
7
8
22
21
20
19
18
17
16
15
DA
BST
BIAS
BST
BIAS
29
GND
RT
V
C1
RT
V
21
GND
C1
TRK/SS1
TRK/SS2
FB2
TRK/SS1
TRK/SS2
FB2
FB1
15 FB1
TRK/SS3
FB3
14
13
12
11
TRK/SS3
FB3
DRV2
DRV3
DRV2
DRV3
LIM3
9
10 11 12 13 14
UFD PACKAGE
LIM2 10
FE PACKAGE
20-LEAD PLASTIC TSSOP
θ
= 38°C/W
28-LEAD (4mm × 5mm) PLASTIC QFN
JA
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
LT3694-1 PINOUT IS SHOWN IN PARENTHESIS
θ
JA
= 34°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
LT3694-1 PINOUT IS SHOWN IN PARENTHESIS
ORDER INFORMATION
LEAD FREE FINISH
LT3694EUFD#PBF
LT3694IUFD#PBF
LT3694EFE#PBF
TAPE AND REEL
PART MARKING*
3694
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3694EUFD#TRPBF
LT3694IUFD#TRPBF
LT3694EFE#TRPBF
LT3694IFE#TRPBF
LT3694-1EUFD#TRPBF
LT3694-1IUFD#TRPBF
LT3694-1EFE#TRPBF
LT3694-1IFE#TRPBF
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
20-Lead Plastic TSSOP
3694
LT3694FE
LT3694FE
36941
LT3694IFE#PBF
20-Lead Plastic TSSOP
LT3694-1EUFD#PBF
LT3694-1IUFD#PBF
LT3694-1EFE#PBF
LT3694-1IFE#PBF
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
20-Lead Plastic TSSOP
36941
LT3694FE-1
LT3694FE-1
20-Lead Plastic TSSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
36941fb
2
LT3694/LT3694-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, VBIAS = 3V, unless otherwise noted. (Notes 2, 9)
PARAMETER
Internal Undervoltage Lockout
CONDITIONS
MIN
3.5
36
TYP
3.8
38
MAX
4
UNITS
V
l
l
V
IN
Overvoltage Shutdown Threshold
Input Quiescent Current
40
2
V
Not Switching
Not Switching
1
mA
mA
µA
mV
V
Bias Quiescent Current
2
3.5
2
Shutdown Current
V
= 0.1V
0.1
500
1.2
0.01
1.0
EN/UVLO
EN/UVLO Threshold, Bias On
EN/UVLO Threshold, Switching On
Reference Voltage Line Regulation
Switching Frequency
350
l
1.16
1.23
5V < V < 36V
%/V
MHz
MHz
V
IN
l
l
l
l
l
l
R = 40.2k
T
0.9
0.25
1.5
1.1
2.5
SYNC Input Frequency Range
LT3694 Only
LT3694 Only
LT3694 Only
V , SYNC
IH
V , SYNC
IL
0.35
2.6
V
V
V
, CLKOUT
I
I
I
= –50µA, LT3694-1 Only
= 50µA, LT3694-1 Only
= 250µA
1.6
V
OH
CLKOUT
CLKOUT
PGOOD
, CLKOUT
0.3
V
OL
PGOOD Output Voltage Low
PGOOD Leakage
0.2
10
90
0.4
V
V
= 2V
1000
94
nA
%
PGOOD
PGOOD Threshold (Relative to V
Switching Regulator
)
(Note 8)
86
FB
l
l
Feedback Pin Voltage
735
750
–50
350
600
–3
765
mV
nA
µS
V/V
µA
mV
µA
µA
V
Feedback Pin Bias Current
–500
Error Amplifier Transconductance
Error Amplifier Voltage Gain
TRK/SS Pull-Up Current
–2
35
–4
70
TRK/SS Threshold to Start Switching
50
V
C1
V
C1
V
C1
V
C1
V
C1
Source Current
V = 0.6V
–20
28
C
Sink Current
V = 0.6V
C
Clamp Voltage
2
Switching Threshold
to Switch Current Gain
0.75
3.6
0.01
1.8
4.9
600
60
V
A/V
µA
V
Switch Leakage Current
V
IN
= 36V
10
2.5
6
Minimum Boost Voltage Above Switch
Switch Current Limit (Note 3)
(Note 4)
l
(Note 3) 10% Duty Cycle
3.5
2.6
A
Switch V
I
I
I
= 3A
mV
mA
V
CESAT
SW1
SW1
BST
BST Operating Current
V , BST Diode
= 3A
= 100mA
0.8
1
F
I BST Diode
L
V
BST
– V = 36V
BIAS
µA
A
l
l
DA Current Limit
3.6
4.5
Minimum Switch Off-Time
140
ns
36941fb
3
LT3694/LT3694-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, VBIAS = 3V, unless otherwise noted. (Notes 2, 9)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
LDO Regulator
l
l
Feedback Pin Voltage
735
750
–50
2800
–3
765
mV
nA
Feedback Pin Bias Current
Error Amplifier Voltage Gain
TRK/SS Pull-Up Current
TRK/SS Threshold to Shut Down LDO
Line Regulation
–500
–2
35
–4
70
µA
mV
50
5V < V < 36V
0.025
0.5
15
%/V
mV/mA
mA
IN
Load Regulation
I
From 0.1mA to 10mA
DRV
l
l
Base Drive
10
47
22
20
70
Current Limit Threshold
Short-Circuit Current Limit Threshold
Minimum BIAS to DRV Voltage (Note 7)
60
mV
V
FB
= 0
26
30
mV
l
l
I
I
= 10mA
= 10mA
0.3
2.0
0.9
2.3
V
DRV
DRV
Minimum V to DRV Voltage
V
IN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3694E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3694I is guaranteed to meet performance specifications from –40°C to
125°C junction temperature.
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions.
Junction temperature will exceed the maximum operating range when
overtemperature protection is active. Continuous operation above the
specified maximum operating junction temperature may impair
device reliability.
Note 6: Absolute Maximum Voltage at V and EN/UVLO pins is 70V for
IN
non-repetitive, 1 second transients and 36V for continuous operation.
Note 7: The LDO will function if the BIAS to DRV differential is not met,
but the base drive current will be drawn from V instead of BIAS.
IN
Note 3: Current limit is guaranteed by design and/or correlation to static
test. Slope compensation reduces current limit at higher duty cycles.
Note 8: The PGOOD pin will pull low when the voltage on any of the three
FB pins is lower than the PGOOD threshold value.
Note 4: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 9: Positive currents flow into pins, negative currents flow out of pins.
Minimum and maximum values refer to absolute values.
36941fb
4
LT3694/LT3694-1
VIN = 12V, TA = 25°C, unless otherwise noted.
BST Pin Current
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency at VOUT = 5V
Switch VCESAT vs Switch Current
vs Switch Current
100
90
80
70
60
50
70
60
50
40
30
20
10
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
f
= 800kHz
SW
V
= 6.3V
IN
V
= 12V
IN
V
= 36V
IN
2
3
0
1
2
3
0
1
0
1
2
3
I
(A)
OUT
36941 G01
SWITCH CURRENT (A)
SWITCH CURRENT (A)
36941 G02
36941 G03
Switch Current Limit
vs Duty Cycle
Switch Minimum On-Time and
Off-Time vs Temperature
Switch Current Limit
vs Temperature
5.0
4.5
4.0
3.5
3.0
5.0
4.5
4.0
3.5
3.0
160
140
120
100
80
I
= 1A
SW
25°C
–45°C
MINIMUM
ON-TIME
150°C
MINIMUM
OFF-TIME
60
40
20
0
–50
0
100
150
0
20
40
60
80
100
50
–50
0
100
TEMPERATURE (°C)
150
50
TEMPERATURE (°C)
SWITCH DUTY CYCLE (%)
36941 G04
36941 G06
36941 G05
Frequency Shift vs Temperature
VFB vs Temperature
Frequency vs RT
3.0
2.5
2.0
1.5
1.0
0.5
0
760
758
756
754
752
750
748
746
744
742
740
5
4
R
T
= 200k
R
=
T
3
40.2k
2
1
R
T
= 10.7k
0
–1
–2
–3
–4
–5
0
50
100
(k)
150
200
–50
0
100
150
50
–50
0
100
150
50
R
TEMPERATURE (°C)
TEMPERATURE (°C)
T
36941 G07
36941 G08
36941 G09
36941fb
5
LT3694/LT3694-1
VIN = 12V, TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
EN/UVLO Thresholds
Minimum Input Voltage
vs Load Current (VIN to Start)
7.0
ITRK/SS vs Temperature
vs Temperature
4.0
3.5
3.0
2.5
2.0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= 5V
OUT
f
= 800kHz
SW
UVLO SWITCHING THRESHOLD
6.5
6.0
5.5
5.0
4.5
4.0
TO START
TO RUN
BIAS CURRENT
SHUTDOWN THRESHOLD
0.001
0.01
0.1
1
–50
0
100
150
–50
0
100
150
50
50
LOAD CURRENT (A)
TEMPERATURE (°C)
TEMPERATURE (°C)
36941 G10
36941 G11
36941 G12
LDO Minimum VIN to DRV Voltage
vs DRV Current
LDO Current Limit
vs VFB (Foldback)
LDO Current Limit vs Temperature
60
50
40
30
20
10
0
2.5
2.0
1.5
1.0
0.5
0
5
4
+150°C
–40°C
3
2
1
0
–1
–2
–3
–4
–5
0.4
0.6
0.8
0
0.2
8
10
0
2
4
6
–50
0
100
150
50
FEEDBACK VOLTAGE (V)
36941 G14
DRV CURRENT (mA)
TEMPERATURE (°C)
36941 G13
36941 G15
LDO Minimum BIAS to DRV
Voltage vs DRV Current
10Hz to 100kHz LDO Output Noise
0.5
0.4
0.3
0.2
0.1
0
V
I
= 2.5V
= 0.25A
ZXTCM322
PASS XSTR
V
V
= 5V
OUT
OUT
IN
BIAS
= 4.4V
10mV/DIV
36941 G17
8
10
0
2
4
6
1ms/DIV
DRV CURRENT (mA)
36941 G16
36941fb
6
LT3694/LT3694-1
PIN FUNCTIONS (FE/UFD)
V (Pin 1/Pins 27, 28): The V pin supplies power to the
for the LDO regulators. The DRV pins can provide up to
6V of base drive.
IN
IN
internal switch of the 2.6A regulator and to the LT3694’s
internal reference and start-up circuitry. This pin must be
locally bypassed.
LIM2,LIM3(Pins10,11/Pins9,14):TheLIMpinsprovide
current limiting on the LDO pass transistors by sensing
a voltage on an external sense resistor connected to the
BIAS pin. These pins should be connected to BIAS if this
function is not used.
EN/UVLO (Pin 2/Pin 1): The EN/UVLO pin is used to shut
down the LT3694. It can be driven from a logic level or
used as an undervoltage lockout by connecting a resistor
divider from V .
IN
GND (Pins 10, 11, 12, 13, 25, 26) UFD Package Only:
Power and Signal Ground.
CLKOUT (Pin 3/Pin 2): Digital Clock Output. The CLKOUT
pin allows synchronization of other switching regulators
(LT3694-1 only).
V
(Pin 16/Pin 19): Output of the Internal Error Amp.
C1
The voltage on this pin controls the peak switch cur-
rent. This pin is normally used to compensate the
control loop. The switching regulator can be shut
SYNC (Pin 3/Pin 2): Frequency Synchronization Input.
Connectafrequencysourcetothisinputifsynchronization
is desired. Connect SYNC to ground if not used (LT3694
only).
down by pulling the V pin to ground with an NMOS
C1
or NPN transistor.
PGOOD (Pin 4/Pin 3): Open Collector Output. PGOOD is
BIAS (Pin 17/Pin 20): The BIAS pin supplies the current
to the LT3694’s internal regulator and boost circuits. This
must be connected to a voltage source above 3V, usually
pulled low when any of the three regulators drops out of
regulation (V < 90% of nominal value).
FB
to V
. The LDO pass transistor base current will also
OUT1
RT (Pin 5/Pin 4): The RT pin requires a resistor to ground
tosettheoperatingfrequencyoftheLT3694.Ifsynchroniz-
ing the LT3694 to an external clock, the resistor should
be set to program the frequency at least 20% below the
synchronization frequency.
come from the BIAS pin if it is at least 1.8V above the
LDO output.
BST (Pin 18/Pin 21): The BST pin is used to provide a
drive voltage, higher than the input voltage, to the internal
bipolar NPN power switch.
TRK/SS1, TRK/SS2 , TRK/SS3 (Pins 6, 7, 14/Pins 5, 6, 17):
The TRK/SS pins allow a regulator to track the output of
another regulator. When the TRK/SS pin is below 0.75V,
the FB pin regulates to the TRK/SS voltage. This pin can
also beusedasasoft-startbyconnectingacapacitorfrom
TRK/SS to ground. The TRK/SS pins should be left open
if neither feature is used.
DA (Pin 19/Pin 22): The DA pin senses the catch diode
current to prevent excessive inductor current in output
overload or short-circuit conditions.
SW (Pin 20/Pins 23, 24): Output of the Internal Power
Switch. Connect this pin to the inductor and switching
diode.
FB1, FB2, FB3 (Pins 15, 8, 13/Pins 18, 7, 16): Negative
Inputs of the Error Amplifiers. The LT3694 regulates each
feedback pin to the lesser of 0.75V or the corresponding
TRK/SS pin voltage. Connect the feedback resistor divider
taps to these pins.
Exposed Pad (Pin 21/Pin 29): Ground. The underside
exposed pad metal of the package provides both electrical
contact to ground and a conductive thermal path to the
printedcircuitboard.TheExposedPadmustbesolderedto
a grounded pad on the circuit board for proper operation.
DRV2, DRV3 (Pins 9, 12/Pins 8, 15): The DRV pins
provide the base drive for the external NPN transistors
36941fb
7
LT3694/LT3694-1
BLOCK DIAGRAM
RT
SYNC
(LT3694)
CLKOUT
(LT3694-1)
BIAS
OUT1
V
IN
CLK
PGOOD
EN/UVLO
+
–
OVERVOLTAGE
SHUTDOWN
INT REG
AND REF
MASTER
OSC
0.5V
–
+
THERMAL
SHUTDOWN
1.2V
LDO
OUT1
60mV
–
+
60mV
LDO
OUT1
–
R
LIM3
LIM3
DRV3
R
LIM2
PG1
LIM2
DRV2
+
3µA
3µA
TRK/SS3
OUT3
+
+
TRK/SS2
SD
0.75V
OUT2
+
+
SD
FB3
0.75V
–
FB2
–
–
+
0.68V
–
+
0.68V
BUCK
V
IN
V
IN
+
–
C
IN
BIAS
0.9V
+
–
Σ
BST
R
S
O
SLOPE
COMP
C3
D1
L1
SW
DA
OUT1
CLK
C1
+
–
R1
FB1
–
V
C1
ERROR
AMP
+
+
R2
C
f
0.75V
R
C
–
+
3µA
I
C
C
LIMIT
CLAMP
GND
–
TRK/SS1
0.68V
2V
PG1
+
36941 F01
Figure 1. LT3694 Block Diagram with Typical External Components
36941fb
8
LT3694/LT3694-1
OPERATION
Unless specifically noted, this data sheet refers to both the
LT3694 and the LT3694-1 generically as the LT3694.
thecurrentthroughtheinductortotheoutput. Theinternal
error amplifier regulates the output voltage by continually
adjusting the V pin voltage. The threshold for switching
C1
The LT3694 is a constant-frequency, current mode, buck
regulator with an internal power switch plus two low
dropout linear regulator controllers. The three regulators
share common circuitry including input source, voltage
reference, undervoltage lockout, and enable, but are oth-
erwise independent. Operation can be best understood by
referring to the Block Diagram (Figure 1).
on the V pin is 0.75V and an active clamp of 2V limits
C1
the output current.
Overcurrent protection is provided by the DA comparator.
The DA comparator senses the catch diode current and
will delay the switch-on cycle if the diode current is too
high at the beginning of a cycle.
If the EN/UVLO pin is below 0.35V (min), the LT3694 is
shut down and draws <2µA from the input source tied to
IN1
The TRK/SS pins override the 0.75V reference for the FB
pins when the TRK/SS pins are below 0.75V. This allows
eithercoincidentorratiometricsupplytrackingonstart-up
as well as a soft-start capability.
V
. If the EN/UVLO pin is driven above 0.5V (typ), the
internalbiascircuitsturnon,includingtheinternalregulator,
reference and master oscillator. The switching regulator
will only begin to operate when the EN/UVLO pin reaches
>1.20V (typ). The EN/UVLO pin can be driven from a logic
gate or can be used as an undervoltage lockout by using
The switch driver operates either from V or from the BST
IN
pin. An external capacitor is used to generate a voltage at
the BST pin that is higher than the input supply. This al-
lows the driver to saturate the internal bipolar NPN power
switch for efficient operation.
a resistor divider to V .
IN
Theswitcherisacurrentmoderegulator.Insteadofdirectly
modulatingthedutycycleofthepowerswitch,thefeedback
loop controls the peak current in the switch during each
cycle. Compared to voltage mode control, current mode
control improves loop dynamics and provides cycle-by-
cycle current limit.
The BIAS pin allows the internal circuitry to draw its cur-
rent from a voltage supply lower than V , reducing power
IN
dissipation and increasing efficiency. If the voltage on the
BIAS pin falls below 2.7V, then its quiescent current will
flow from V .
IN
TheLDOregulatorusesanexternalNPNpasstransistorto
form a linear regulator. The loop is internally compensated
tobestablewithaminimumloadcapacitanceof2.2µF.The
LDOalsohasafoldbackcurrentlimiteravailabletoprotect
the external transistor under overload conditions
A pulse from the oscillator sets the RS flip-flop and turns
on the internal NPN bipolar power switch. Current in the
switch and the external inductor begins to increase. When
this current exceeds a level determined by the voltage
at V , the current comparator resets the RS flip-flop,
C1
turning off the switch. The current in the inductor flows
through the external, Schottky, catch diode, and begins to
decrease.Thecyclebeginsagainatthenextpulsefromthe
The overvoltage detection shuts down the LT3694 if the
input voltage goes above 38V. This will prevent the switch
from turning on under high voltage conditions and allows
the LT3694 to survive transient input voltages up to 70V.
oscillator. In this way, the voltage on the V pin controls
C1
36941fb
9
LT3694/LT3694-1
APPLICATIONS INFORMATION
STEP DOWN SWITCHING REGULATOR
each clock cycle if there is sufficient voltage across the
boostcapacitor(C3inFigure 1)tofullysaturatetheoutput
switch. A forced switch off for a minimum time will only
occur at the end of a clock cycle when the boost capaci-
tor needs to be recharged. This operation has the same
effect as lowering the clock frequency for a fixed off time,
resulting in a higher duty cycle and lower minimum input
voltage. The resultant duty cycle depends on the charging
times of the boost capacitor and can be approximated by
the following equation:
Feedback Resistor Network
The output voltage is programmed with a resistor divider
(refertotheBlockDiagraminFigure1)betweentheoutput
and the FB pin. Choose the resistors according to:
VOUT
750mV
R1= R2
− 1
The parallel combination of R1 and R2 should be 10k or
less to avoid bias current errors.
B
B+ 1
DCMAX
=
Input Overvoltage Lockout
where B is the output current divided by the typical
boost current from the BST Pin Current vs Switch Cur-
rent curve in the Typical Performance Characteristics
section.
An important feature of the LT3694 is the ability to survive
transient surges on the input voltage of up to 70V. This is
accomplished by shutting off the regulators to keep this
high voltage off the critical components. The overvoltage
lockout trips when the input voltage exceeds 38V.
Themaximumvoltage, V , forconstant-frequencyopera-
IN
tion is determined by the minimum duty cycle DC
:
MIN
Input Voltage Range
VOUT + VF
DCMIN
Theminimumoperatingvoltageisdeterminedeitherbythe
LT3694’sinternalundervoltagelockoutorbyitsmaximum
duty cycle. The duty cycle is the fraction of time that the
internal switch is on and is determined by the input and
output voltage:
VIN(MAXCF)
=
− VF + VSW
with DC = t
• f
MIN
ON(MIN) SW
Thus, both the maximum and minimum input voltages
for constant-frequency operation are a function of the
switching frequency and output voltage. Therefore, the
maximum switching frequency must be set to a value that
accommodates the input and output voltage parameters
and must meet both of the following criteria:
VOUT + VF
DC=
VIN − VSW + VF
where V is the forward voltage drop of the catch diode
F
and V is the voltage drop of the internal switch (~0.3V
SW
at maximum load). This leads to a minimum input
VOUT + VF
IN(MAXCF) − VSW + V
1
fMAX1
=
•
voltage of:
V
tON(MIN)
F
VOUT + VF
DCMAX(CF)
VIN(MINCF)
=
− VF + VSW
VOUT + VF
VIN(MINCF) − VSW + V
1
fMAX2 = 1−
•
tOFF(MIN)
F
The duty cycle is the fraction of time that the internal
switchisonduringaclockcycle. Themaximumdutycycle
The values of t
SW
ance Characteristics section). Worst-case values for
switchcurrentsgreaterthan0.5Aaret
and t
are functions of
OFF(MIN)
ON(MIN)
for constant-frequency operation given by DC
= 1
I
and temperature (see chart in the Typical Perform-
MAX(CF)
– t
• f . However, unlike most fixed frequency
OFF(MIN)
SW
regulators, the LT3694 will not switch off at the end of
=130nsand
ON(MIN)
36941fb
10
LT3694/LT3694-1
APPLICATIONS INFORMATION
t
=140ns.f
isthefrequencyatwhichthemini-
OFF(MIN)
MAX1
Table 1: RT for Common Frequencies
mumdutycycleisexceeded.TheregulatorwillskipONpulses
inordertoreducetheoveralldutycycleatfrequenciesabove
MAX1
SWITCHING FREQUENCY (MHz)
R (k)
T
0.25
0.5
0.75
1
193
90.2
56.6
40.2
30.5
23.8
19.6
16.0
13.5
11.4
f
. It will continue to regulate but with increased
inductor current and greatly increased output ripple. The
increased peak inductor current in pulse-skipping will
also stress the switch transistor at high voltages and high
1.25
1.5
1.75
2
switching frequency. f
is the frequency at which the
MAX2
maximum duty cycle is exceeded. If there is sufficient
charge on the BST capacitor, the regulator will skip OFF
periods to increase the overall duty cycle at frequencies
2.25
2.5
above f
. It will continue to regulate but will not have
MAX2
constant-frequency operation.
Note that the restriction on the operating input voltage
referstosteady-statelimitstokeeptheoutputinregulation
in constant-frequency mode; the circuit will tolerate input
voltage transients up to the absolute maximum rating.
For external clocks applied to the SYNC pin (LT3694 only),
the circuit will support V logic levels from 1.8V to 5V
H
CMOS or TTL. The duty cycle needs a minimum on time of
100ns and a minimum off time of 100ns. When operating
Switching Frequency
in sync mode, R should be set to provide a frequency at
T
least 20% below the minimum sync frequency.
Once the upper limit for the switching frequency is found
from the duty cycle requirements, the frequency may be
chosen below the upper limit. Lower frequencies result in
lower switching losses, but require larger inductors and
capacitors. The user must decide the best trade-off. The
switching frequency is set by a resistor connected from
the RT pin to ground, or by forcing a clock signal into the
SYNC pin (LT3694 only). The LT3694 applies a voltage of
0.75V across this resistor and uses the current to set the
oscillator speed. The switching frequency is given by the
following formula:
Inductor Selection and Maximum Output Current
A good first choice for the inductor value is:
VOUT + V
1.25A • f
F
L =
wherefistheswitchingfrequencyinMHz,Listheinductor
value in µH, V
is the output voltage and V is the catch
OUT
F
diode voltage drop.
The current in the inductor is a triangle wave with an
average value equal to the load current. The peak switch
current is equalto the outputcurrentplus half thepeak-to-
peak inductor ripple current. The LT3694 limits its switch
current in order to protect itself and the system from
overload faults. Therefore, the maximum output current
that the LT3694 will deliver depends on the switch current
limit, the inductor value and the input and output voltages.
When the switch is off, the potential across the inductor
is the output voltage plus the catch diode drop. This gives
the peak-to-peak ripple current in the inductor:
49.8
RT + 8.8
fSW
=
where f
is in MHz and R is in kΩ. The formula is
SW
T
accurate within 2% over the frequency range. Table 1
shows the typical measured value of R for several com-
T
mon switching frequencies.
VOUT + VF
∆IL = (1− DC)
L • f
36941fb
11
LT3694/LT3694-1
APPLICATIONS INFORMATION
where f is the switching frequency of the LT3694 and L
is the value of the inductor. The peak inductor and switch
This analysis is valid for continuous mode operation
(I > I /2). For details of maximum output current in
OUT
LIM
current is:
discontinuous mode operation, see the Linear Technol-
∆IL
2
ogy Application Note 44. Finally, for duty cycles greater
ISWPK = ILPK = IOUT
+
than 50% (V /V > 0.5), a minimum inductance is
OUT IN
requiredtoavoidsubharmonicoscillations.Thisminimum
To maintain output regulation, this peak current must be
inductance is:
less than the LT3694’s switch current limit, I . I is at
LIM LIM
(VOUT + VF )
2A • fSW
least 3.5A at low duty cycles (0.1) and decreases linearly
LMIN
with L
=
to 2.8A at DC = 0.8.
The minimum inductance can now be calculated as:
in μH and f in MHz. A detailed discussion
MIN
SW
of subharmonic oscillations can be found in the Linear
Technology Application Note 19.
VOUT + VF
ILIM − IOUT
1− DCMIN
2• f
LMIN
=
•
Input Capacitor Selection
However, it’s generally better to use an inductor larger
than the minimum value. The minimum inductor has large
ripple currents which increase core losses and require
large output capacitors to keep output voltage ripple low.
Bypass the input of the LT3694 circuit with a ceramic
capacitor of X7R or X5R type. Y5V types have poor
performance over temperature and applied voltage, and
should not be used. A 4.7µF to 22μF ceramic capacitor
is adequate to bypass the LT3694 and will easily handle
the ripple current. Use a 22µF capacitor with f between
250kHz and 800kHz. Use a 10µF capacitor with f be-
tween 800kHz and 1.6MHz. Use a 4.7µF capacitor above
1.6MHz. Always check for sufficient margin by reducing
thecapacitorvalueuntilthedropoutincreasesby>500mV.
If the input power source has high impedance, or there
is significant inductance due to long wires or cables,
additional bulk capacitance may be necessary. This
can be provided with a lower performance electrolytic
capacitor.
Select an inductor greater than L
that keeps the ripple
MIN
current below 30% of I
.
LIM
SW
For input voltages greater than 30V, use an inductor with
a saturation current of 6A or greater and an inductance
value of 3.3µH or greater.
SW
Theinductor’sRMScurrentratingmustbegreaterthanthe
maximum load current and its saturation current should
be greater than I . For highest efficiency, the series
LPK
resistance (DCR) should be less than 0.1Ω. Table 2 lists
several vendors and types that are suitable.
Table 2. Inductors
INDUCTANCE
RANGE (µH)
CURRENT
RANGE (A)
Step-down regulators draw current from the input sup-
ply in pulses with very fast rise and fall times. The input
capacitor is required to reduce the resulting voltage
ripple at the LT3694 and to force this very high frequency
switching current into a tight local loop, minimizing EMI.
A 10μF capacitor is capable of this task, but only if it is
placed close to the LT3694 and the catch diode (see the
PCB Layout section). A second precaution regarding the
ceramic input capacitor concerns the maximum input
voltage rating of the LT3694. A ceramic input capacitor
combined with trace or cable inductance forms a high
SERIES
MANUFACTURER
WE-HC
1 to 6.5
6 to 15
Würth Elektronik
www.we-online.com
MSS1048
CDRH103R
VLF
0.8 to 8
4 to 8
Coilcraft
www.coilcraft.com
0.8 to 10
2.2 to 10
2.8 to 8.3
3.8 to 7.7
Sumida
www.sumida.com
TDK
www.component.tdk.
com
IHLP-2525CZ-11
1 to 10
2.5 to 9.5
Vishay
www.vishay.com
36941fb
12
LT3694/LT3694-1
APPLICATIONS INFORMATION
quality (under damped) tank circuit. If the LT3694 circuit
is plugged into a live supply, the input voltage can ring to
twice its nominal value, possibly exceeding the LT3694’s
maximum input voltage rating. See Linear Technology
Application Note 88 for more details.
The low ESR and small size of ceramic capacitors make
them the preferred type for LT3694 applications. Not all
ceramic capacitors are the same, however. Many of the
higher value capacitors use poor dielectrics with high
temperature and voltage coefficients. In particular, Y5V
and Z5U types lose a large fraction of their capacitance
withappliedvoltageandattemperatureextremes.Because
loop stability and transient response depend on the value
Output Capacitor Selection
Theoutputcapacitorfilterstheinductorcurrenttogenerate
an output with low voltage ripple. It also stores energy in
order to satisfy transient loads and stabilize the LT3694’s
control loop. Because the LT3694 operates at a high
frequency, minimal output capacitance is necessary. In
addition, the control loop operates well with or without
the presence of output capacitor series resistance (ESR).
Ceramic capacitors, which achieve very low output ripple
and small circuit size, are therefore an option.
of C , this loss may be unacceptable. Use X7R and X5R
OUT
types instead.
Electrolytic capacitors are also an option. The ESRs of
most aluminum electrolytic capacitors are too large to
deliver low output ripple. Surge rated tantalum capacitors
or low ESR, organic, electrolytic capacitors intended for
power supply use are suitable. Choose a capacitor with a
sufficientlylowESRfortherequiredoutputripple.Because
the volume of the capacitor determines its ESR, both the
size and the value will be larger than a ceramic capacitor
that would give similar ripple performance. One benefit
is that the larger capacitance may give better transient
response for large changes in load current. Table 3 lists
several capacitor vendors.
Output ripple can be estimated with the following
equations:
∆IL
VRIPPLE
=
; Ceramic
8 • f •COUT
VRIPPLE = ∆IL • ESR ; Electrolytic
Table 3. Low ESR Surface Mount Capacitors
whereΔI isthepeak-to-peakripplecurrentintheinductor.
L
SERIES
TYPE
MANUFACTURER
The RMS content of this ripple is very low so the RMS
current rating of the output capacitor is usually not of
concern. It can be estimated with the formula:
Ceramic
Taiyo Yuden
www.t-yuden.com
TPM, TPS
Ceramic, Tantalum
AVX
www.avx.com
∆IL
12
IC(RMS)
=
T494, T495,
T510, T520,
T525, T530,
A700
Ceramic, Tantalum,
Tantalum Organic Polymer,
Aluminum Organic Polymer
Kemet
www.kemet.com
Another constraint on the output capacitor is that it must
havegreaterenergystoragethantheinductor;ifthestored
energyintheinductortransferstotheoutput, theresulting
voltage step should be small compared to the regulation
voltage. For a 5% overshoot, this requirement indicates:
POSCAP,
OS-CON
Tantalum Organic Polymer,
Aluminum Organic Polymer
Sanyo
www.sanyo.com
SP-CAP
Ceramic,
Aluminum Organic Polymer
Panasonic
www.panasonic.com
Ceramic
TDK
www.tdk.com
2
ILIM
COUT > 10 •L •
V
OUT
36941fb
13
LT3694/LT3694-1
APPLICATIONS INFORMATION
Diode Selection
V pin, as shown in Figure 2. Generally a capacitor (C )
C C
and a resistor (R ) in series to ground are used. In addi-
C
The catch diode (D1 from Figure 1) conducts current only
during switch off time. Average forward current in normal
operation can be calculated from:
tion, there may be lower value capacitor in parallel. This
capacitor (C ) is not part of the loop compensation but
F
is used to filter noise at the switching frequency, and is
VIN − VOUT
required only if a phase-lead capacitor (C ) is used or if
PL
ID(AVG) = IOUT
•
the output capacitor (C1) has high ESR.
VIN
LT3694
Consider a diode with a larger current rating than I
D(AVG)
CURRENT MODE
POWER STAGE
SW
when the part must survive a shorted output. The DA pin
monitors the current in the diode and prevents the switch
from turning on at the beginning of a charge cycle if the
diode current is above the DA limit. Therefore, under
overload conditions, the average diode current will in-
crease to the average of the switch current limit and the
DA current limit.
OUTPUT
ERROR
AMPLIFIER
g
= 7.5S
m
C
PL
R1
FB
–
g
=
m
350µS
ESR
+
0.75V
C1
+
3M
C1
POLYMER
OR
CERAMIC
Peakreversevoltageisequaltotheregulatorinputvoltage,
so use a diode with a reverse voltage rating greater than
themaximuminputvoltage.TheinternalOVLOcanprotect
thediodefromexcessivereversevoltagebyshuttingdown
the regulator if the input voltage exceeds 38V. Table 4 lists
several Schottky diodes and their manufacturers.
V
GND
C
TANTALUM
R
C
R2
C
F
C
C
36941 F02
Figure 2. Model for Loop Response
Table 4. Schottky Diodes (40V, 3A)
PART NUMBER
V at 3A (V)
OUTLINE
MANUFACTURER
f
Loop compensation determines the stability and transient
performance. The best values for the compensation net-
work depend on the application and in particular the type
of output capacitor. A practical approach is to start with
one of the circuits in this data sheet that is similar to your
applicationandtunethecompensationnetworktooptimize
theperformance.Stabilityshouldthenbecheckedacrossall
operatingconditions, includingloadcurrent, inputvoltage
and temperature. The LT1375 data sheet contains a more
thorough discussion of loop compensation and describes
how to test the stability using a transient load. Figure 2
shows an equivalent circuit for the LT3694 control loop.
The error amplifier is a transconductance amplifier with
finite output impedance.
MBRS340
MBRD340
0.5
0.6
SMC
D-PAK
ON Semiconductor
www.onsemi.com
B340
SMB340
0.5
0.5
SMC
Diodes, Inc.
Powermite 3 www.diodes.com
CMSH3-40
CSHD3-40
0.5
0.65
SMC
D-PAK
Central Semiconductor
www.centralsemi.com
Frequency Compensation
The LT3694 uses current mode control to regulate the
output.Thissimplifiesloopcompensation.Inparticular,the
LT3694doesnotrequiretheESRoftheoutputcapacitorfor
stability,sotheuserisfreetoemployceramiccapacitorsto
achieve low output ripple and small circuit size. Frequency
compensation is provided by the components tied to the
36941fb
14
LT3694/LT3694-1
APPLICATIONS INFORMATION
The power section, consisting of the modulator, power
switch and inductor, is modeled as a transconductance
amplifier generating an output current proportional to
capacitor. A 2.5V output presents a special case because it
is marginally adequate to support the boosted drive stage
while using the internal boost diode. For reliable BST pin
operation with 2.5V outputs, use a good external Schottky
diode (such as the ON Semi MBR0540), and a 1μF boost
capacitor (see Figure 4b). For lower output voltages, the
BIAS pin can be tied to the input (Figure 4c), or to another
the voltage at the V pin. Note that the output capacitor
C1
integrates this current, and that the capacitor on the V
C1
pin (C ) integrates the error amplifier output current,
C
resulting in two poles in the loop. In most cases a zero
supply greater than 2.8V. Tying BIAS to V reduces the
is required and comes from either the output capacitor
IN
maximum input voltage to 7V. The circuit in Figure 4a is
more efficient because the BST pin current and BIAS pin
quiescent current comes from a lower voltage source.
One must also ensure that the maximum voltage ratings
of the BST and BIAS pins are not exceeded. The minimum
ESR or from a resistor R in series with C . This simple
C
C
model works well as long as the value of the inductor is
not too high and the loop crossover frequency is much
lower than the switching frequency. A phase lead capaci-
tor (C ) across the feedback divider may improve the
PL
transient response.
V
OUT
Figure 3 shows the transient response when the load
current steps from 1A to 2.6A and back to 1A.
BIAS BST
LT3694
V
IN
V
IN
C3
SW
GND
4.7µF
V
OUT
100mV/DIV
(4a) For V
> 2.8V
OUT
V
OUT
D2
I
BIAS
BST
L
1A/DIV
V
IN
V
LT3694
IN
C3
SW
36941 F03
GND
4.7µF
100µs/DIV
Figure 3. Transient Load Response of the LT3694
Front Page Application as the Load Current Is
Stepped from 1A to 2.6A. VOUT = 3.3V
(4b) For 2.5V < V
< 2.8V
OUT
BST and BIAS Pin Considerations
V
OUT
BIAS BST
V
CapacitorC3andtheinternalboostSchottkydiode(seethe
Block Diagram in Figure 1) are used to generate a boost
voltage that is higher than the input voltage. In most cases
a 0.22μF capacitor will work well. Figure 4 shows three
ways to arrange the boost circuit. The BST pin must be
more than 2.3V above the SW pin for best efficiency. For
outputs of 3V and above, the standard circuit (Figure 4a)
is best. For outputs between 2.8V and 3V, use a 1μF boost
V
IN
LT3694
IN
C3
SW
GND
4.7µF
36941 FO4
(4c) For V
< 2.5V; V
= 7V
OUT
IN(MAX)
Figure 4. Three Circuits for Generating the Boost Voltage
36941fb
15
LT3694/LT3694-1
APPLICATIONS INFORMATION
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
operating voltage of an LT3694 application is limited by
the minimum input voltage (4V) and by the maximum
duty cycle as outlined in a previous section. For proper
start-up, the minimum input voltage is also limited by the
boost circuit. If the input voltage is ramped slowly, or the
LT3694 is turned on with its EN/UVLO or TRK/SS pin when
theoutputisalreadyinregulation,thentheboostcapacitor
may not be fully charged. Because the boost capacitor is
charged with the energy stored in the inductor, the circuit
will rely on some minimum load current to get the boost
circuit running properly. This minimum load will depend
on input and output voltages, and on the arrangement of
the boost circuit. The minimum load generally goes to
zero once the circuit has started. Figure 5 shows a plot
of input voltage to start and to run as a function of load
current. In many cases the discharged output capacitor
will present a load to the switcher, which will allow it to
start. The plots show the worst-case situation in which
V
f
= 3.3V
OUT
SW
TO START
TO RUN
= 800kHz
0.001
0.01
0.1
1
LOAD CURRENT (A)
7.0
6.5
6.0
5.5
5.0
4.5
4.0
V
SW
= 5V
OUT
f
= 800kHz
TO START
TO RUN
V is ramping very slowly. For lower start-up voltage, the
IN
boost diode can be tied to V , however, this restricts the
IN
input range to one-half of the absolute maximum rating
of the BST pin.
0.001
0.01
0.1
1
At light loads, the inductor current becomes discontinu-
ous and the effective duty cycle can be very high. This
reduces the minimum input voltage to approximately
LOAD CURRENT (A)
36941 F05
Figure 5. The Minimum Input Voltage Depends on
Output Voltage, Load Current and Boost Circuit
300mV above V . At higher load currents, the inductor
OUT
current is continuous and the duty cycle is limited by the
maximum duty cycle of the LT3694, requiring a higher
input voltage to maintain regulation.
Enable and Programmable Undervoltage Lockout
The EN/UVLO pin provides both logic enable and pro-
grammable undervoltage lockout functions. There are
two thresholds on the EN/UVLO pin. The first threshold is
at 500mV (typ). When EN/UVLO is below this threshold,
the LT3694 is in complete shutdown and the quiescent
current drops below 2µA.
Internal Undervoltage Lockout
The LT3694 features an internal undervoltage lockout that
will shut off all three regulators if the input voltage drops
toolowtomaintainregulationoftheinternalcircuitry. This
lockout trips when V drops below 3.8V (typ).
IN
36941fb
16
LT3694/LT3694-1
APPLICATIONS INFORMATION
Once EN/UVLO climbs above the first threshold, the inter-
nal circuitry of the LT3694 is turned on but the switching
regulator and LDOs remain shut off. A 2µA current sink
on the EN/UVLO pin is activated to provide hysteresis for
the programmable undervoltage function.
EN/UVLO
+
INTERNAL
CIRCUITRY
0.5V
1.2V
–
2µA
The second threshold is an accurate 1.2V derived from the
internal reference. When EN/UVLO is above the second
threshold, the regulators turn on and the 2µA current sink
turns off. This allows an accurate programmable UVLO
+
SHUTDOWN
REGULATORS
–
functionbyplacingaresistordividerbetweenV ,EN/UVLO
IN
and ground. Figure 6a shows the EN/UVLO block diagram
and Figure 6b shows connections for the programmable
UVLO function.
(6a) EN/UVLO Block Diagram
UNDERVOLTAGE TRIP LEVEL
The trip level is set by the resistor ratio:
V
V
IN
IN
(R1 + R2)
R2
1.2V •
R1
R2
LT3694
EN/UVLO
R1+ R2
VIN(UVTRIP) = 1.2V
UVLO HYSTERESIS
R2
2µA • R1
36941 FO4
The hysteresis is set by R1:
VIN(UVHYS) = 2µA •R1
(6b) Programmable UVLO Application
Figure 6. Programmable UVLO Application
The EN/UVLO pin may be driven with a logic output if the
programmable UVLO is not needed. The requirements for
the logic output are a low output voltage less than 0.35V
(to insure low current shutdown) and a high output volt-
age greater than 1.25V.
The base drive voltage has a maximum voltage of 6V.
This will limit the maximum output of the regulator to
6V–V
whereV
isthebase-emittersaturation
BE(SAT)
BE(SAT)
voltage of the pass transistor.
Low Dropout Regulator
Table 5. Low VCESAT Transistors
Each low dropout regulator comprises an error amp, loop
compensation and a base drive amp. It uses the same
0.75V reference as the switching regulators. It requires
an external NPN pass transistor and 2.2μF of output ca-
pacitance for stability.
V
at
CESAT
C
PART NUMBER
I = 1A
OUTLINE
MANUFACTURER
ZXTN25012EZ
ZXTN25020DG
0.06
0.075
SOT-89
SOT-223
Zetex
www.diodes.com
NSS20201JT1G
NSS12201LT1G
0.22
0.08
SC-89
SOT-23
ON Semiconductor
www.onsemi.com
Thedropoutcharacteristicswillbedeterminedbythepass
transistor. The collector-emitter saturation characteristics
will limit the dropout voltage. Table 5 lists some suitable
NPN transistors with their saturation specifications.
CTLT3410-M621
0.28
Central Semiconductor
www.central-semi.com
1mm × 2mm
TLM621
36941fb
17
LT3694/LT3694-1
APPLICATIONS INFORMATION
The LDO may be shut down if it is unused by pulling the
FB pin up with a resistor that will source at least 30μA. The
FB pin will clamp at about 1.25V and the LDO will shut off
reducingpowerconsumption.Thispull-upcanbesourced
from one of the LT3694 outputs provided that channel is
always on when the other channels are on.
LDO Current Limit
The LDO has a current limit available to reduce the power
consumption of the NPN transistor under overload condi-
tions.ThecurrentlimitrequirestheNPNtransistorcollector
to be connected to the BIAS pin through a low resistance
sense resistor. The current limit circuit senses the voltage
drop across this resistor and reduces the base drive cur-
rent when the limit voltage exceeds 60mV. This will limit
The output stage of the LDO will drive the NPN base from
the BIAS voltage if it is at least 1.8V above the LDO DRIVE
voltage, otherwise the NPN base current comes from V .
the output current to 60mV/R
.
SENSE
IN
The base drive current is limited to 15mA.
If the overload causes the output voltage to drop, the limit
voltage is folded back to reduce power in the NPN transis-
tor. The limit circuit monitors the FB voltage and ramps
LDO FB Resistor Network
The output voltage of the LDO regulator is programmed
with a resistor divider (refer to the Block Diagram in
Figure 7) between the emitter of the external NPN pass
resistor and the feedback pin, FB2 or FB3. Choose the
resistors according to:
the limit voltage down once V drops to 0.6V. The limit
FB
voltage will fold back to 26mV when V has dropped to
FB
0V. The current foldback is disabled until the associated
TRK/SSpinrisesabove0.68V.Thisinsuresproperstart-up
under full load conditions. Figure 7 shows the LDO circuit
with current limit.
V
0.75
OUT
R1= R2
− 1
Properlyroutingthecurrentlimitsenseresistorsiscritical
to minimize errors in the current limit. The sense con-
nections are the BIAS pin (both channels) on the high
side and LIM2 or LIM3 on the bottom side. These sense
leads must be routed separately from all current carrying
traces. Figure 9 shows a layout that minimizes trace re-
sistance errors. The current limit sense resistors (RLIM2
and RLIM3) are placed close together and the BIAS pin
The parallel combination of R1 and R2 should be 10k or
less to avoid bias current errors.
OUT1
LT3694
BIAS
60mV
R
SENSE
+
–
trace is connected to V
at their junction. The bottom
OUT1
sides of these resistors have a separate via and trace to
the LIM2 and LIM3 pins.
LIM2
DRV2
Thefoldbackcandramaticallyreducethepowerdissipation
of the NPN pass transistor under short-circuit conditions.
+
–
OUT2
0.75V
For example, an application that has V
= 3.3V and
OUT1
R1
R2
FB2
V
OUT2
= 2.5V will nominally have 0.8V across the pass
transistor V . Under short-circuit conditions, the pass
CE
transistor V will increase to 3.3V. Without foldback the
CE
36941 FO7
power dissipation in the pass transistor will increase by
more than 4x, but with foldback the power dissipation
only increases by 78%.
Figure 7. LDO with Current Limit
36941fb
18
LT3694/LT3694-1
APPLICATIONS INFORMATION
If the current feeding the collector of the NPN through the
sense resistor comes from a supply that is not connected
to BIAS, the current limit cannot be used and the LIM pin
must be connected to BIAS to disable the current limit.
Shorted and Reversed Input Protection
If an inductor is chosen that will not saturate excessively,
an LT3694 buck regulator will tolerate a shorted output.
There is another situation to consider in systems where
the output will be held high when the input to the LT3694
is absent. This may occur in battery charging applications
or in battery backup systems where a battery or some
other supply is diode ORed with the LT3694’s output. If
Tracking and Soft-Start
The output of the LT3694 regulates to the lowest voltage
present at either the TRK/SS pin or an internal 0.75V
reference. A capacitor from the TRK/SS pin to ground is
charged by an internal 3μA current source resulting in a
linear output ramp from 0V to the regulated output whose
duration is given by:
the V pin is allowed to float and the EN/UVLO pin is held
IN
high (either by a logic signal or because it is tied to V ),
IN
then the LT3694’s internal circuitry will pull its quiescent
current through its SW pin. This is fine if the system
can tolerate a few mA in this state. If the EN/UVLO pin
is grounded, the SW pin current will drop to essentially
CTRKSS •0.75V
tRAMP
=
3µA
zero. However, if the V pin is grounded while the output
IN
is held high, then parasitic diodes inside the LT3694 can
At power-up or at any shutdown event, the TRK/SS pins
are internally pulled to ground through 100Ω to insure
the soft-start capacitors are discharged. The pins clamp
at 1.3V.
pull large currents from the output through the SW pin
and the V pin. The circuit in Figure 8 runs only when the
IN
input voltage is present—and protects against a shorted
or reversed input.
Ratiometric tracking is achieved by tying the TRK/SS pins
tied together and connecting to a single capacitor. The
charge current is multiplied by the number of TRK/SS
pins connected.
D4
V
V
BST
SW
IN
IN
LT3694
EN/UVLO
V
OUT
V
C
Coincident tracking is accomplished by adding an addi-
tional resistor divider to the master regulator output and
connecting it to the TRK/SS pin of the slave regulator. The
resistor divider should be equal to the slave’s feedback
GND FB
BACKUP
divider. Keep in mind that the LDO pass transistor V
CE(SAT)
36941 F08
will limit how well the LDO output can coincidentally track
Figure 8. Diode D4 Prevents a Shorted Input from
the switching regulator output.
Discharging a Backup Battery Tied to the Output. It Also
Protects the Circuit from a Reversed Input. The LT3694
Runs Only When the Input Is Present
The TRK/SS pin has a low voltage detect that insures
the regulator is shut off when TRK/SS is pulled low. The
threshold low voltage is nominally 50mV. This allows
independent on/off control of the LDOs using the TRK/SS
pins. The logic drive should be open collector or have
series resistance because the TRK/SS pins are internally
pulled to ground during any shutdown event.
36941fb
19
LT3694/LT3694-1
APPLICATIONS INFORMATION
PCB Layout
additional vias to reduce thermal resistance further. With
these steps, the thermal resistance from die (or junction)
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Figure 9 shows
the recommended component placement with trace,
ground plane and via locations. Note that large, switched
to ambient can be reduced to θ = 34°C/W (UFD) or
JA
θ =38°C/W(FE20).With100LFPMairflow,thisresistance
JA
can fall by another 25%. Further increases in airflow will
lead to lower thermal resistance.
currents flow in the LT3694’s V , DA, and SW pins, the
IN
BecauseofthelargeoutputcurrentcapabilityoftheLT3694,
it is possible to dissipate enough heat to raise the junc-
tion temperature beyond the absolute maximum. When
operating at high ambient temperatures, the maximum
loadcurrentshouldbederatedastheambienttemperature
catch diode (D1) and the input capacitor (C ). The loop
IN
formed by these components should be as small as pos-
sible. These components, along with the inductor and
output capacitor, should be placed on the same side of
the circuit board, and their connections should be made
on that layer. Place a local, unbroken ground plane below
these components. The SW and BST nodes should be as
approaches T
.
J(MAX)
Power dissipation within the LT3694 can be estimated
by calculating the total power loss from an efficiency
measurement and subtracting the catch diode loss
and inductor loss. The die temperature is calculated by
multiplying the LT3694 power dissipation by the thermal
resistance from junction-to-ambient. Keep in mind other
heat sources—such as the catch diode, inductor and LDO
pass transistors.
small as possible. Finally, keep the FB and V nodes small
C
so that the ground traces will shield them from the SW
and BST nodes.
The exposed pad on the bottom of the package must be
soldered to ground so that the pad acts as a heat sink. To
keep thermal resistance low, extend the top side ground
plane as much as possible, and add thermal vias under
and near the LT3694 to additional ground planes within
the circuit board and on the bottom side.
Other Linear Technology Publications
Application Notes 19, 35 and 44 contain more detailed
descriptions and design information for buck regulators
and other switching regulators. The LT1376 data sheet
has a more extensive discussion of output ripple, loop
compensation and stability testing. Design Note 318
shows how to generate a bipolar output supply using a
buck regulator.
High Temperature Considerations
The PCB must provide heat sinking to keep the LT3694
cool. The Exposed Pad on the bottom of the package must
be soldered to a ground plane. This ground should be tied
to large copper layers below with thermal vias; these lay-
ers will spread the heat dissipated by the LT3694. Place
36941fb
20
LT3694/LT3694-1
APPLICATIONS INFORMATION
V
GND
IN
L1
C
V
OUT1
OUT1
C
IN
D1
R
LIM2
R
LIM3
Q3
Q2
V
V
OUT3
OUT2
36941 F09
PCB BOTTOM SIDE IS A SOLID GROUND PLANE
THERMAL VIAS TO GROUND PLANE
SIGNAL VIAS TO INNER LAYERS
VIAS TO LIM2/LIM3
VIAS TO BIAS
VIAS TO Q2 COLLECTOR
Figure 9. A Good PCB Layout Ensures Proper, Low EMI Operation
36941fb
21
LT3694/LT3694-1
TYPICAL APPLICATIONS
Automotive Input Range (6V to 16V) to 3.3V, 2.5V, 1.8V
V
IN
6V TO 16V
TRANSIENT TO 70V
UVLO 5.8V
100k
4.7µF
26.7k
V
EN/UVLO
BIAS BST
SW
IN
0.1µF
1.2µH
OUT1
3.3V
1.7A
TRK/SS1
TRK/SS2
TRK/SS3
1nF
B340A
34k
10k
DA
FB1
0.1Ω
100pF
LIM2
DRV2
OUT1
34k
10µF
ZXTN25012EZ
V
C1
LT3694
OUT2
2.5V
450mA
0.1Ω
OUT1
LIM3
DRV3
24.9k
2.2µF
ZXTN25012EZ
14k
FB2
OUT3
1.8V
SYNC
PGOOD
RT
450mA
10.7k
16k
2.2µF
FB3
10k
GND
36941 TA02
f
= 2MHz
SW
36941fb
22
LT3694/LT3694-1
TYPICAL APPLICATIONS
Wide Input Range to (6.3V to 36V) to 5V, 3.3V, 2.5V With Independent On/Off Control of the LDOs
V
IN
6.3V TO 36V
TRANSIENT TO 70V
10µF
V
EN/UVLO
BIAS BST
SW
ENABLE
IN
0.22µF
B340A
5.4µH
OUT1
TRK/SS1
TRK/SS2
TRK/SS3
5V
ENLD02
ENLD03
1.7A
57.6k
DA
1nF
1nF
1nF
FB1
10.2k
22µF
1000pF
0.1Ω
0.1Ω
20k
LIM2
DRV2
V
OUT1
LT3694
C1
ZXTN25020DG
2.2µF
OUT2
2.5V
450mA
OUT1
LIM3
DRV3
24.9k
10.7k
ZXTN25020DG
OUT3
3.3V
450mA
2.2µF
FB2
SYNC
PGOOD
RT
34k
10k
FB3
66.5k
GND
SYNC
36941 TA03
CLKIN
f
= 800kHz
SW
36941fb
23
LT3694/LT3694-1
TYPICAL APPLICATIONS
Wide Input Range (6V to 36V) to 1.8V, 2.5V and 3.3V
V
IN
6V TO 36V
TRANSIENT TO 70V
UVLO 5.8V
OUT2
22µF
100k
26.7k
V
EN/UVLO
BIAS BST
SW
IN
0.22µF
B340A
3.3µH
OUT1
1.8V
2.6A
TRK/SS1
TRK/SS2
TRK/SS3
4.7nF
14k
10k
DA
FB1
470pF
LT3694
47µF
25.5k
LIM2
DRV2
V
C1
ZXTN25020DG
V
OUT2
LIM3
DRV3
IN
OUT2
3.3V
ZXTN25020DG
34k
OUT3
2.5V
2.2µF
FB2
24.9k
10.7k
2.2µF
PGOOD
FB3
10k
90.2k
RT
GND
SYNC
36941 TA04
f
= 500kHz
SW
THE LDO OUTPUT CURRENT CAPABILITY IS LIMITED BY THE POWER DISSIPATION OF THE NPN PASS TRANSISTORS
36941fb
24
LT3694/LT3694-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 ± 0.05
4.50 ± 0.05
3.10 ± 0.05
2.50 REF
2.65 ± 0.05
3.65 ± 0.05
PACKAGE OUTLINE
0.25 ± 0.05
0.50 BSC
3.50 REF
4.10 ± 0.05
5.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
R = 0.05
TYP
0.75 ± 0.05
4.00 ± 0.10
(2 SIDES)
27
28
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ± 0.10
(2 SIDES)
3.50 REF
3.65 ± 0.10
2.65 ± 0.10
(UFD28) QFN 0506 REV B
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
36941fb
25
LT3694/LT3694-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev I)
Exposed Pad Variation CB
6.40 – 6.60*
3.86
(.152)
(.252 – .260)
3.86
(.152)
20 1918 17 16 15 14 1312 11
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
6.40
(.252)
BSC
2.74
(.108)
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE20 (CB) TSSOP REV I 0211
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
36941fb
26
LT3694/LT3694-1
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
01/11 Corrected the Pin Configuration drawing and Package Description for the TSSOP package.
2
B
03/12 Added SYNC Input Layout Frequency Range, added conditions to SYNC and CLKOUT I/O specs.
Fixed typo in Exposed Pad description.
3
7
Updated FE20 package
26
36941fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3694/LT3694-1
TYPICAL APPLICATION
6V to 28V Input Range with Cascaded Step Down — 3.3V, 2.5V and 1.8V Outputs
Plus Independently Enabled 1.8V, 1.5V and 1.2V Outputs
V
IN
6V TO 28V
TRANSIENT TO 70V
10µF
200k
52.3k
V
EN/UVLO
BIAS BST
SW
IN
0.1µF
2.2µH
TRK/SS1
TRK/SS2
TRK/SS3
OUT1
3.3V
500mA
1nF
B340A
34k
10k
DA
FB1
270pF
LT3694-1
30.9k
22µF
0.1Ω
V
C1
LIM2
DRV2
OUT1
0.2Ω
ZXTN25012EZ
OUT1
LIM3
DRV3
OUT2
2.5V
450mA
ZXTN25012EZ
2.2µF
OUT3
1.8V
200mA
24.9k
10.7k
2.2µF
FB2
14k
10k
CLKOUT
FB3
PGOOD RT GND
f
= 1MHz
SW
40.2k
10µF
10µF
GNDA
PGND
1.5µH
OUT5
V
PV
IN
SW2
IN
EN4
RUN1
1.2V
20pF
226k
800mA
PGOOD1
RUN2
PGOOD2
RUN3
EN5
EN6
V
FB2
10µF
226k
1.5µH
LTC3545
SYNC/MODE
1.5µH
OUT4
1.8V, 800mA
OUT6
1.5V, 800mA
SW1
SW3
20pF
301k
20pF
511k
2.2µF
10µF
V
GNDA
PGND
V
FB3
FB1
255k
200k
36941 TA05
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
V : 3.6V to 38V, V
LT3480
LT3500
LT3507
LT3685
LT3970
LT3980
36V with Transient Protection to 60V, 2A (I ), 2.4MHz, High
= 0.78V, I = 70µA, I < 1µA,
OUT(MIN) Q SD
OUT
IN
Efficiency Step-Down DC/DC Converter with Burst Mode® Operation 3mm× 3mm DFN-10 and MSOP-10E Packages
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IN
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Q
SD
Converter and LDO Controller
3mm× 3mm DFN-10 Package
36V, 2.5MHz, Triple (2.4A + 1.5A + 1.5A (I )) with LDO Controller V : 4V to 36V, V
High Efficiency Step-Down DC/DC Converter
= 0.8V, I = 7mA, I < 1µA,
OUT
IN
OUT(MIN)
Q
SD
5mm× 7mm QFN-38 Package
36V with Transient Protection to 60V, 2A (I ), 2.4MHz, High
Efficiency Step-Down DC/DC Converter
V : 3.6V to 38V, V = 0.78V, I = 70µA, I < 1µA,
OUT
IN
OUT(MIN)
Q
SD
3mm× 3mm DFN-10 and MSOP-10E Packages
40V, 350mA, 2MHz High Efficiency Micropower Step-Down
DC/DC Converter
V : 4V to 40V, Transient to 60V, V = 1.21V, I = 2µA,
IN
SD
OUT(MIN)
Q
I
< 1µA, 3mm× 2mm DFN-10 and MSOP-10 Packages
58V with Transient Protection to 80V, 2A (I ), 2.4MHz, High
Efficiency Step-Down DC/DC Converter with Burst Mode Operation
V : 3.6V to 58V, Transient to 80V, V
= 0.8V, I = 85µA,
OUT(MIN) Q
OUT
IN
I
< 1µA, 3mm× 4mm DFN-16 and MSOP-16E Packages
SD
36941fb
LT 0312 REV B • PRINTED IN USA
28 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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