LCLK [Linear]
Photofl ash Chargers with Adjustable Input Current and IGBT Drivers; Photofl灰充电器，可调节输入电流和IGBT驱动器
| 型号： | LCLK |
| 厂家： | 
Linear |
| 描述： | Photofl ash Chargers with Adjustable Input Current and IGBT Drivers |
| 文件： | 总20页 (文件大小：416K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3585-0/LT3585-1
LT3585-2/LT3585-3
Photoflash Chargers with
Adjustable Input Current
and IGBT Drivers
U
DESCRIPTIO
FEATURES
The LT®3585 series are highly integrated ICs designed to
charge photoflash capacitors in digital and film cameras.
A new control technique allows for the use of extremely
small transformers. Each part contains an on-chip high
voltage NPN power switch. Output voltage detection is
completely contained within the part, eliminating the need
for any discrete zener diodes or resistors. The output volt-
age can be adjusted by simply changing the turns ratio
of the transformer.
■
Adjustable Input Current
■
Integrated IGBT Driver
■
No Output Voltage Divider Needed
Uses Small Transformers: 5.8mm × 5.8mm × 3mm
Fast Photoflash Charge Times
Charges Any Size Photoflash Capacitor
Supports Operation from Single Li-Ion Cell, Two AA
Cells or any Supply from 1.5V Up to 16V
■
■
■
■
■
Small 10-Lead (3mm × 2mm) DFN Package
Fast Charge Time
The CHRG/IADJ pin gives full control of the part to the
user. Driving CHRG/IADJ low puts the part in low power
shutdown. The CHRG/IADJ pin can also be used to reduce
theinputcurrentofthecharger,usefulinextendingbattery
life. The DONE pin indicates when the part has completed
charging.
NORMAL MODE REDUCED MODE
INPUT
CHARGE TIME
(Sec)
CHARGE TIME
(Sec)
VERSION
LT3585-3
LT3585-0
LT3585-2
LT3585-1*
CURRENT (mA)
800/400
550/275
400/200
250/115
3.3
4.6
5.8
5.0
6.6
9.2
12.6
14.6
The LT3585 series of parts are housed in tiny 3mm ×
2mm DFN packages.
100µF capacitor, 320V, V = V = 3.6V
IN
BAT
*50µF capacitor, 320V, V = V = 3.6V
IN
BAT
U
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
APPLICATIO S
■
Digital/Film Camera Flash
■
PDA/Cell Phone Flash
■
Emergency Strobe
U
TYPICAL APPLICATIO
LT3585-1 Photoflash Charger Uses High Efficiency
2mm Tall Transformers with Tunable IGBT Gate Drive
LT3585-1 Charging Waveform
Normal Input Current Mode
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
V
BAT
1:10:2
320V
2 AA OR
1
2
4
5
1 TO 2 Li-Ion
•
4.7µF
1M
+
50µF
PHOTOFLASH
CAPACITOR
•
2.2µF
600V
A
V
OUT
V
SW
GND
50V/DIV
BAT
TRIGGER T
FLASHLAMP
C
DONE
1
3
2
CHRG/IADJ
LT3585-1
V
IN
5V
V
IN
0.22µF
I
IGBTPWR
IGBTIN
IN
500mA/DIV
IGBTPU
IGBTPD
3585 TA01b
TO GATE OF IGBT
V
C
= 3.6V
= 50µF
1sec/DIV
BAT
OUT
20Ω TO
160Ω
3585 TA01a
3585f
1
LT3585-0/LT3585-1
LT3585-2/LT3585-3
W W U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
V Voltage................................................................16V
BATT
IN
V
Voltage............................................................16V
1
2
3
4
5
10
9
IGBTIN
IGBTPWR
GND
IGBTPU
IGBTPD
SW
SW Voltage ...............................................................60V
SW Pin Negative Current...........................................–1A
CHRG/IADJ Voltage...................................................10V
IGBTPWR Voltage.....................................................10V
IGBTIN Voltage .........................................................10V
IGBTPU Voltage ........................................................10V
IGBTPD Voltage ........................................................10V
DONE Voltage ...........................................................10V
Current Into DONE Pin............................... 0.2mA/–1mA
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range (Note 2) ... –40°C to 85°C
Storage Temperature Range................... –65°C to 125°C
11
8
7
V
CHRG/IADJ
DONE
IN
6
V
BAT
DDB PACKAGE
10-LEAD (3mm × 2mm) PLASTIC DFN
= 125°C, θ = 76°C/W
T
JMAX
JA
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
ORDER PART NUMBER
LT3585EDDB-0
DDB PART MARKING
LCLK
LT3585EDDB-1
LT3585EDDB-2
LT3585EDDB-3
LCLJ
LCLH
LCFX
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = V = V = 3V unless otherwise noted (Note 2). Specifications
CHRG
A
IN
BAT
are for the LT3585-0, LT3585-1, LT3585-2, LT3585-3 unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Quiescent Current
V
CHRG
V
CHRG
= 3V, Not Switching
= 0V, In Shutdown
5
0
8
1
mA
µA
●
●
V
V
Voltage Range
2.5
1.5
16
16
V
V
IN
Voltage Range
BAT
Switch Current Limit
LT3585-3 (Note 3)
LT3585-0 (Note 3)
LT3585-2 (Note 3)
LT3585-1 (Note 3)
1.55
1.1
0.75
0.45
1.7
1.2
0.85
0.55
1.85
1.3
0.95
0.65
A
A
A
A
Switch V
LT3585-3, I = 1.4A
485
330
230
140
mV
mV
mV
mV
CESAT
SW
LT3585-0, I = 1A
SW
LT3585-2, I = 700mA
SW
LT3585-1, I = 400mA
SW
V
V
Comparator Trip Voltage
Comparator Overdrive
Measured as V – V
31
31.5
31.5
32
V
V
OUT
OUT
SW
BAT
●
30.5
32.5
300ns Pulse Width
200
130
400
180
mV
mV
DCM Comparator Trip Voltage
CHRG/IADJ Pin Current
Measured as V – V
80
SW
BAT
V
CHRG
V
CHRG
= 3V
= 0V
45
0
70
0.1
µA
µA
●
●
Switch Leakage Current
V
BAT
= V = 5V, In Shutdown
0.01
1
µA
V
SW
CHRG/IADJ Minimum Enable Voltage
1.1
3585f
2
LT3585-0/LT3585-1
LT3585-2/LT3585-3
ELECTRICAL CHARACTERISTICS The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = V = V = 3V unless otherwise noted (Note 2). Specifications
CHRG
A
IN
BAT
are for the LT3585-0, LT3585-1, LT3585-2, LT3585-3 unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CHRG/IADJ Three-State Voltage for Reduced Input
Current
CHRG/IADJ > 1.1V then Float
1.1
1.28
1.4
V
●
●
CHRG/IADJ Voltage Range for Normal Input Current
CHRG/IADJ Low Voltage
1.6
10
V
V
0.3
Delay Time for Reduced Input Current Mode
CHRG/IADJ Pin Three Stated:
V
BAT
V
BAT
V
BAT
V
BAT
= 4.2V, Fresh Li-Ion Cell
= 2.8V, Dead Li-Ion Cell
= 3V, Fresh 2 AA Cells
= 2V, Dead 2 AA Cells
5.2
7.2
6.8
9.5
µs
µs
µs
µs
Minimum CHRG/IADJ Pin Low Time
DONE Output Signal High
DONE Output Signal Low
DONE Leakage Current
IGBTPWR Voltage Range
IGBT Input High Level
High→Low→High
20
3
µs
V
100kΩ from V to DONE
IN
33µA into DONE Pin
120
1
200
100
10
mV
nA
V
V
= 3V, DONE NPN Off
DONE
●
●
●
2.5
1.5
V
IGBT Input Low Level
0.5
V
IGBT Output Rise Time
IGBTPU Pin, C
= 4000pF,
0.4
µs
OUT
IGBTPWR = 5V, IGBTIN = 0V→1.5V, 10%→90%
IGBT Output Fall Time
IGBTPD Pin, C = 4000pF,
0.13
µs
OUT
IGBTPWR = 5V, IGBTIN = 1.5V→0V, 90%→10%
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. Ratings are for DC levels only.
Note 2: The LT3585 series is guaranteed to meet performance
specifications from 0°C to 85°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls.
Note 3: Current limit is guaranteed by design and/or correlation to static
test.
3585f
3
LT3585-0/LT3585-1
LT3585-2/LT3585-3
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LT3585-0 curves use Figure 11, LT3585-1 curves
use Figure 12, LT3585-2 curves use Figure 13 and LT3585-3 curves use Figure 14 unless otherwise noted.
LT3585-0 Charging Waveform
Normal Input Current Mode
LT3585-1 Charging Waveform
Normal Input Current Mode
LT3585-2 Charging Waveform
Normal Input Current Mode
V
V
V
OUT
OUT
OUT
50V/DIV
50V/DIV
50V/DIV
AVERAGE
INPUT
AVERAGE
INPUT
AVERAGE
INPUT
CURRENT
CURRENT
CURRENT
3585 G01
3585 G03
3585 G02
1A/DIV V
= 3.6V
= 50µF
0.5s/DIV
1A/DIV V
= 3.6V
= 50µF
1s/DIV
500mA/DIV V
C
= 3.6V
= 50µF
2s/DIV
BAT
OUT
BAT
OUT
BAT
OUT
C
C
LT3585-3 Charging Waveform
Normal Input Current Mode
LT3585-0 Charging Waveform
Reduced Input Current Mode
LT3585-1 Charging Waveform
Reduced Input Current Mode
V
V
V
OUT
50V/DIV
OUT
OUT
50V/DIV
50V/DIV
AVERAGE
INPUT
AVERAGE
INPUT
AVERAGE
INPUT
CURRENT
CURRENT
CURRENT
3585 G04
3585 G05
3585 G06
1A/DIV V
= 3.6V
= 50µF
0.5s/DIV
1A/DIV V
= 3.6V
= 50µF
0.5s/DIV
500mA/DIV V
C
= 3.6V
= 50µF
2s/DIV
BAT
OUT
BAT
OUT
BAT
OUT
C
C
LT3585-2 Charging Waveform
Reduced Input Current Mode
LT3585-3 Charging Waveform
Reduced Input Current Mode
Charge Time*
Normal Input Current Mode
8
7
6
5
4
3
2
1
0
LT3585-0
LT3585-1
LT3585-2
LT3585-3
V
V
OUT
OUT
50V/DIV
50V/DIV
AVERAGE
INPUT
CURRENT
1A/DIV V
AVERAGE
INPUT
CURRENT
1A/DIV V
3585 G07
3585 G08
= 3.6V
= 50 F
1s/DIV
= 3.6V
= 50µF
0.5s/DIV
BAT
OUT
BAT
OUT
C
C
6
7
2
3
4
5
8
9
10
3585 G09
V
(V)
BAT
*USING RUBYCON 330V, 50µF PHOTOFLASH
OUTPUT CAPACITOR (FW SERIES)
3585f
4
LT3585-0/LT3585-1
LT3585-2/LT3585-3
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LT3585-0 curves use Figure 11, LT3585-1 curves
use Figure 12, LT3585-2 curves use Figure 13 and LT3585-3 curves use Figure 14 unless otherwise noted.
Charge Time*
Reduced Input Current Mode
LT3585-0 Input Current
Normal Input Current Mode
LT3585-1 Input Current
Normal Input Current Mode
700
600
500
300
250
200
150
100
50
25
LT3585-0
LT3585-1
LT3585-2
LT3585-3
20
15
400
300
200
100
0
10
5
V
V
V
= 4.2V
= 3.6V
= 2.5V
V
V
V
= 4.2V
= 3.6V
= 2.5V
BAT
BAT
BAT
BAT
BAT
BAT
0
0
100
200
300
100
200
300
0
0
6
2
3
4
5
7
8
9
10
V
(V)
V
(V)
OUT
3585 G10
V
(V)
OUT
BAT
3585 G11
3585 G12
*USING RUBYCON 330V, 50µF PHOTOFLASH
OUTPUT CAPACITOR (FW SERIES)
LT3585-2 Input Current
Normal Input Current Mode
LT3585-3 Input Current
Normal Input Current Mode
LT3585-0 Input Current
Reduced Input Current Mode
450
400
350
300
250
200
150
100
50
900
800
700
600
500
400
300
200
100
0
350
300
250
200
150
100
50
V
V
V
= 4.2V
= 3.6V
= 2.5V
V
V
V
= 4.2V
= 3.6V
= 2.5V
V
V
V
= 4.2V
= 3.6V
= 2.5V
BAT
BAT
BAT
BAT
BAT
BAT
BAT
BAT
BAT
0
0
100
200
300
0
100
200
300
0
100
200
300
0
V
(V)
V
(V)
V
(V)
OUT
OUT
OUT
3585 G13
3585 G14
3585 G15
LT3585-1 Input Current
Reduced Input Current Mode
LT3585-2 Input Current
Reduced Input Current Mode
LT3585-3 Input Current
Reduced Input Current Mode
120
100
80
60
40
20
0
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
V
= 4.2V
= 3.6V
= 2.5V
V
= 4.2V
= 3.6V
= 2.5V
V
V
V
= 4.2V
= 3.6V
= 2.5V
BAT
BAT
BAT
BAT
BAT
BAT
BAT
BAT
BAT
V
V
V
V
0
0
100
200
300
100
200
300
0
0
100
200
300
0
V
(V)
V
(V)
OUT
V
(V)
OUT
OUT
3585 G16
3585 G17
3585 G18
3585f
5
LT3585-0/LT3585-1
LT3585-2/LT3585-3
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LT3585-0 curves use Figure 11, LT3585-1 curves
use Figure 12, LT3585-2 curves use Figure 13 and LT3585-3 curves use Figure 14 unless otherwise noted.
LT3585-0 Efficiency
Normal Input Current Mode
LT3585-1 Efficiency
Normal Input Current Mode
LT3585-2 Efficiency
Normal Input Current Mode
90
80
70
60
90
80
70
60
90
80
70
60
USING KIJIMA SBL-5.6-1 TRANSFORMER
USING KIJIMA SBL-5.6S-1 TRANSFORMER
USING KIJIMA SBL-5.6-1 TRANSFORMER
V
V
V
= 4.2V
= 3.6V
= 2.5V
V
V
V
= 4.2V
= 3.6V
= 2.5V
V
V
V
= 4.2V
= 3.6V
= 2.5V
BAT
BAT
BAT
BAT
BAT
BAT
BAT
BAT
BAT
50
50
50
50
100
150
V
200
(V)
250
300
50
100
150
V
200
(V)
250
300
50
100
150
V
200
(V)
250
300
OUT
OUT
OUT
3585 G19
3585 G19
3585 G21
LT3585-3 Efficiency
Normal Input Current Mode
LT3585-0 Efficiency
Reduced Input Current Mode
LT3585-1 Efficiency
Reduced Input Current Mode
90
80
70
60
90
80
70
60
90
80
70
60
USING KIJIMA SBL-5.6S-1 TRANSFORMER
USING KIJIMA SBL-5.6-1 TRANSFORMER
USING TDK LDT565630T-041
TRANSFORMER
V
V
V
= 4.2V
= 3.6V
= 2.5V
V
V
V
= 4.2V
= 3.6V
= 2.5V
V
V
V
= 4.2V
= 3.6V
= 2.5V
BAT
BAT
BAT
BAT
BAT
BAT
BAT
BAT
BAT
50
50
50
50
100
150
V
200
(V)
250
300
50
100
150
V
200
(V)
250
300
50
100
150
V
200
(V)
250
300
OUT
OUT
OUT
3585 G24
3585 G23
3585 G22
LT3585-2 Efficiency
Reduced Input Current Mode
LT3585-3 Efficiency
Reduced Input Current Mode
LT3585-0 Output Voltage
90
80
70
60
330
328
326
324
90
80
70
60
USING KIJIMA SBL-5.6-1 TRANSFORMER
USING TDK LDT565630T-041
TRANSFORMER
V
V
V
= 4.2V
= 3.6V
= 2.5V
V
V
V
= 4.2V
= 3.6V
= 2.5V
T
T
T
= –40°C
= 25°C
= 85°C
BAT
BAT
BAT
BAT
BAT
BAT
A
A
A
50
322
50
50
100
150
V
200
(V)
250
300
2
3
4
5
6
7
8
50
100
150
V
200
(V)
250
300
V
(V)
OUT
BAT
OUT
3585 G25
3585 G27
3585 G26
3585f
6
LT3585-0/LT3585-1
LT3585-2/LT3585-3
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LT3585-0 curves use Figure 11, LT3585-1 curves
use Figure 12, LT3585-2 curves use Figure 13 and LT3585-3 curves use Figure 14 unless otherwise noted.
LT3585-1 Output Voltage
LT3585-2 Output Voltage
LT3585-3 Output Voltage
322
320
318
316
314
312
310
326
324
322
330
318
316
314
330
328
326
324
322
320
T
T
T
= –40°C
= 25°C
= 85°C
A
A
A
T
T
T
= –40°C
= 25°C
= 85°C
T
T
T
= –40°C
= 25°C
= 85°C
A
A
A
A
A
A
2
4
5
6
7
8
3
2
4
5
6
7
8
2
4
5
6
7
8
3
3
V
(V)
3585 G28
V
(V)
V
(V)
BAT
BAT
BAT
3585 G29
3585 G30
LT3585-0 Switch Waveform
Normal Input Current Mode
LT3585-0 Switch Waveform
Reduced Input Current Mode
LT3585-0 Switch Waveform
Normal Input Current Mode
V
SW
10V/DIV
V
V
SW
10V/DIV
SW
10V/DIV
I
I
PRI
1A/DIV
PRI
I
PRI
1A/DIV
1A/DIV
3585 G31
3585 G32
3585 G33
V
V
= 3.6V
= 100V
2µs/DIV
V
V
= 3.6V
= 100V
2µs/DIV
V
V
= 3.6V
= 300V
2µs/DIV
BAT
OUT
BAT
OUT
BAT
OUT
LT3585-0/LT3585-1/LT3585-2/
LT3585-3 Switch Breakdown
Voltage
LT3585-0 Switch Waveform
Reduced Input Current Mode
Switch DC Current Limit*
1.8
1.5
1.2
0.9
0.6
0.3
0
10
9
8
7
6
5
4
3
2
1
0
SW PIN IS RESISTIVE UNTIL BREAKDOWN
VOLTAGE DUE TO INTEGRATED RESISTORS.
THIS DOES NOT INCREASE QUIESCENT
CURRENT OF THE PART
LT3585-3
LT3585-0
V
SW
10V/DIV
T
T
T
= –40°C
= 25°C
= 85°C
A
A
A
LT3585-2
LT3585-1
I
PRI
1A/DIV
3585 G34
V
V
= 3.6V
= 300V
2µs/DIV
BAT
OUT
30 40 60
–50 –30 –10 10 20
TEMPERATURE (°C)
80
3585 G35
0
10 20 30 40 50 60 70 80 90 100
SWITCH VOLTAGE (V)
*DYNAMIC CURRENT LIMIT IS HIGHER
THAN DC CURRENT LIMIT
3585 G36
3585f
7
LT3585-0/LT3585-1
LT3585-2/LT3585-3
U
U
U
PI FU CTIO S
IGBTIN (Pin 1): Logic Input for the IGBT Driver. When this
pin is driven higher than 1.5V, the output goes high. When
the pin is below 0.5V, the output will go low.
voltage on this pin should be driven high ( >1.1V ) and
then floated. (For more information refer to the Operation
section of this data sheet.) To enter normal mode, the
voltage should be driven higher than 1.6V.
IGBTPWR (Pin 2): Supply Pin for the IGBT Driver. Must be
locallybypassedwithagoodqualityceramiccapacitor.The
minimum operating voltage for the IGBT driver is 2.5V.
SW (Pin 8): Switch Pin. This is the collector of the internal
NPNPowerswitch.Minimizethemetaltraceareaconnected
to this pin to minimize EMI. Tie one side of the primary
of the transformer to this pin. The target output voltage
is set by the turns ratio of the transformer.
GND (Pin 3): Ground. Tie directly to local ground plane.
V
(Pin 4): Input Supply Pin. Must be locally bypassed
IN
with a good quality ceramic capacitor. The minimum
Choose turns ratio N by the following equation:
operating voltage for V is 2.5V.
IN
VOUT +2
N=
V
(Pin5):BatterySupplyPin. Mustbelocallybypassed
BAT
31.5
with a good quality ceramic capacitor. The minimum
operating voltage for V is 1.5V.
BAT
where V
is the desired output voltage.
OUT
DONE (Pin 6): Open NPN Collector Indication Pin. When
target output voltage is reached, NPN turns on. This pin
needs a proper pull-up resistor or current source.
IGBTPD (Pin 9): Pull-down Output for IGBT Gate. Connect
this pin to the IGBT Gate. Add a series resistor to increase
the turn-off time to protect the IGBT.
CHRG/IADJ (Pin 7): Charge and Input Current Adjust Pin.
A low (<0.3V) to high (>1.1V) transition on this pin puts
the part into power delivery mode. Once the target output
voltage is reached, the part will stop charging the output.
Toggle this pin to start charging again. Ground to shut
down. To enter into the input current reduction mode, the
IGBTPU (Pin 10): Pull-up Output for IGBT Gate. Connect
this pin to the gate of the IGBT.
ExposedPad(Pin11):Ground.Tiedirectlytolocalground
plane.
3585f
8
LT3585-0/LT3585-1
LT3585-2/LT3585-3
W
W
SI PLIFIED BLOCK DIAGRA
D1
T1
V
OUT
TO BATTERY
C1
•
V
IN
C2
•
6
4
5
8
SW
V
V
BAT
DONE
IN
CHIP
POWER
R2
60k
2.5V
MAX
1.5V
MAX
–
–
DCM
COMPARATOR
+
+
–
+
A5
A4
UVLO
+
A3
C
OUT
+
130mV
Q3
–
Q2
Q1
ENABLE
MASTER
LATCH
R1
2.5k
UVLO
Q
S
Q
R
VARIABLE
DELAY
+
–
DRIVER
A2
S
1.25V
REFERENCE
R SWITCH Q
LATCH
Q1
V
OUT
COMPARATOR
CHRG/IADJ
IGBTPWR
IGBTIN
RESET
DOMINANT
+
–
7
2
1
ONE SHOT
R
A1
20mV
M
+
–
GND
3
IGBTPU
IGBTPD
10
9
IGBT DRIVE
CIRCUITRY
3585 F01
LT3585-3, R = 12mΩ
M
LT3585-0, R = 17mΩ
M
LT3585-2, R = 24mΩ
M
LT3585-1, R = 36mΩ
M
Figure 1
3585f
9
LT3585-0/LT3585-1
LT3585-2/LT3585-3
U
OPERATIO
The LT3585 series of parts operate on the edge of dis-
continuous conduction mode. When CHRG/IADJ is driven
higher than 1.1V, the master latch is set. This enables the
part to deliver power to the photoflash capacitor. When
the power switch, Q1, is turned on, current builds up in
the primary of the transformer. When the desired current
level is reached, the output of comparator A1 goes high,
resetting the switch latch that controls the state of Q1, and
the output of the DCM comparator goes low. Q1 now turns
off and the flyback waveform on the SW node quickly rises
added between when A3 goes high and the switch latch
is set, see Figure 2. If the part is enabled, and the CHRG/
IADJ pin is floated, internal circuitry drives the voltage on
the pin to 1.28V. This allows a single I/O port pin, which
can be three-stated, to enable or disable the part as well
as place the part into the input current reduction mode.
This feature effectively reduces the average input current
into the flyback transformer. The magnitude of the delay
decreases with increasing V . This causes the reduced
BAT
averageinputcurrenttoremainrelativelyflatwithchanges
toalevelproportionaltoV .Thesecondarycurrentflows
in V . When CHRG/IADJ is brought higher than 1.6V,
OUT
BAT
through high voltage diode(s), D1, and into the photoflash
capacitor. When the secondary current decays to zero,
the voltage on the SW node collapses. When this voltage
no delay is added. The CHRG/IADJ pin functionality is
shown in Figure 3.
BothV andV haveundervoltagelockout(UVLO).When
BAT
IN
reaches 130mV higher than V , the output of A3 goes
BAT
one of these pins goes below its UVLO voltage, the DONE
high. This sets the switch latch and the power switch, Q1,
pingoeslow.WithaninsufficientbypasscapacitoronV
BAT
turnsbackon. ThiscyclerepeatsuntilthetargetV
level
OUT
or V , the ripple on the pin is likely to activate UVLO and
IN
is reached. When the target V
is reached, the master
OUT
terminate the charge. The applications circuits in the data
sheet suggest values adequate for most applications.
latch resets and the DONE pin goes low.
The input current of an LT3585 series circuit can be
reduced by changing the voltage of the CHRG/IADJ pin.
When this pin is between 1.1V and 1.4V, a time delay is
The LT3585 series also includes an integrated IGBT driver.
There are two output pins, IGBTPU and IGBTPD. The
IGBTPU pin is used to pull the gate of the IGBT up. This
should be done quickly to guarantee proper Xenon lamp
ignition. Tie this pin directly to the gate of the IGBT. The
IGBTPD pin is pinned out separately to allow for greater
flexibilityinchoosingaseriesresistorbetweenthepinand
the gate of the IGBT. This resistor can be used to slow
down the turn off of the IGBT.
Normal Operation
CHRG/IADJ ≥ 1.6V
I
PRI
TIME
V
SW
V
OUT
100V/DIV
TIME
Reduced Input Current
DONE
2V/DIV
CHRG/IADJ Three Stated
I
PRI
CHRG/IADJ
2V/DIV
TIME
LT3585-1
1sec/DIV
Extra Delay Added
V
C
= 3.6V
BAT
OUT
(~5.2µs at V
= 4.2V)
BAT
= 50µF
V
CHRG/IADJ PIN STATE
SW
THREE
STATE*
<0.3V
3V
<0.3V
3V
<0.3V
3585 F02
TIME
3585 F03
*MUST TAKE CHRG/IADJ PIN ABOVE 1.1V, THEN FLOAT
Figure 3. Basic Operation
Figure 2. Normal and Reduced Input Current Waveforms
3585f
10
LT3585-0/LT3585-1
LT3585-2/LT3585-3
W U U
APPLICATIO S I FOR ATIO
U
Choosing the Right Device
drop across the output diode(s). Thus, for a 320V output,
N should be 322/31.5 or 10.2. For a 300V output, choose
N equal to 302/31.5 or 9.6. The next parameter that needs
(LT3585-0/LT3585-1/LT3585-2/LT3585-3)
The only difference between the four versions of the
LT3585 series is the peak current level. For the fastest
possible charge time, use the LT3585-3. The LT3585-1
has the lowest peak current capability, and is designed
for applications that need a more limited drain on the
batteries. Due to the lower peak current, the LT3585-1
can use a physically smaller transformer. The LT3585-0
and LT3585-2 have a current limit in between that of the
LT3585-1 and the LT3585-3.
to be set is the primary inductance, L . Choose L
PRI
PRI
according to the following formula:
VOUT •200•10–9
LPRI
≥
N•IPK
where V
is the desired output voltage. N is the trans-
OUT
former turns ratio. I is 1.4 (LT3585-0), 0.7 (LT3585-1),
PK
1 (LT3585-2) and 2 (LT3585-3). L needs to be equal
PRI
or larger than this value to ensure that the LT3585 series
has adequate time to respond to the flyback waveform.
All other parameters need to meet or exceed the recom-
mendedlimitsasshowninTable1.Aparticularlyimportant
Transformer Design
TheflybacktransformerisakeyelementforanyLT3585-0/
LT3585-1/LT3585-2/LT3585-3design.Itmustbedesigned
carefullyandcheckedthatitdoesnotcauseexcessivecur-
rentorvoltageonanypinofthepart. Themainparameters
that need to be designed are shown in Table 1. The first
transformer parameter that needs to be set is the turns
ratio, N. The LT3585-0/LT3585-1/LT3585-2/LT3585-3
accomplish output voltage detection by monitoring the
flyback waveform on the SW pin. When the SW voltage
parameter is the leakage inductance, L
. When the
LEAK
power switch of the LT3585 series turns off, the leakage
inductance on the primary of the transformer causes a
voltage spike to occur on the SW pin. The height of this
spike must not exceed 50V, even though the absolute
maximum rating of the SW pin is 60V. The 60V absolute
maximum rating is a DC blocking voltage specification,
which assumes that the current in the power NPN is zero.
Figure 4 shows the SW voltage waveform for the circuit
of Figure 8 (LT3585-0). Note that the absolute maximum
rating of the SW pin is not exceeded. Make sure to check
reaches 31.5V higher than the V voltage, the part halts
BAT
powerdelivery.Thus,thechoiceofNsetsthetargetoutput
voltage and changes the amplitude gain of the reflected
voltagefromtheoutputtotheSWpin.ChooseNaccording
to the following equation:
the SW voltage waveform with V
near the target output
OUT
voltage, as this is the worst-case condition for SW volt-
age. Figure 5 shows the various limits on the SW voltage
during switch turn off.
VOUT +2
N=
31.5
where V
is the desired output voltage. The number 2
OUT
in the numerator is used to include the forward voltage
Table 1. Recommended Transformer Parameters
TYPICAL RANGE
TYPICAL RANGE
LT3585-1
TYPICAL RANGE
LT3585-2
TYPICAL RANGE
LT3585-3
PARAMETER
NAME
LT3585-0
UNITS
µH
L
L
Primary Inductance
Primary Leakage Inductance
Secondary/Primary Turns Ratio
>5
>10
200 to 500
8 to 12
>500
>7
>3.5
100 to 300
8 to 12
>500
PRI
100 to 300
8 to 12
>500
200 to 500
8 to 12
>500
nH
LEAK
N
V
Secondary to Primary Isolation
Voltage
V
ISO
I
Primary Saturation Current
Primary Winding Resistance
Secondary Winding Resistance
>1.6
<300
<40
>0.8
<500
<80
>1.0
<400
<60
>2
A
mΩ
Ω
SAT
R
R
<200
<30
PRI
SEC
3585f
11
LT3585-0/LT3585-1
LT3585-2/LT3585-3
W U U
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APPLICATIO S I FOR ATIO
Output Diode Selection
The rectifying diode(s) should be low capacitance type
with sufficient reverse voltage and forward current rat-
ings. The peak reverse voltage that the diode(s) will see
is approximately:
V
SW
10V/DIV
V
= V
+ (N • V
)
PK(R)
OUT
BAT
The peak current of the diode is simply:
3585 F04
2
N
V
V
= 3.6V
= 320V
100ns/DIV
BAT
OUT
IPK(SEC)
IPK(SEC)
IPK(SEC)
IPK(SEC)
=
=
=
=
LT3585-3
(
)
Figure 4. LT3585 SW Voltage Waveform
1.4
N
LT3585-0
(
)
B
MUST BE
LESS THAN 60V
MUST BE
1
N
A
LT3585-2
(
)
LESS THAN 50V
V
SW
0.7
N
LT3585-1
(
)
0V
For the circuit of Figure 8 with V of 5V, V
is 371V
BAT
PK(R)
3585 F05
and I
is 137mA. The GSD2004S dual silicon diode
PK(SEC)
Figure 5. New Transformer Design Check
is recommended for most applications. Table 3 shows
the various diodes and relevant specifications. Use the
appropriate number of diodes to achieve the necessary
reverse breakdown voltage.
It is important not to minimize the leakage inductance to
a very low level. Although this would result in a very low
leakagespikeontheSWpin,theparasiticcapacitanceofthe
transformerwouldbecomelarge.Thiswilladverselyaffect
thechargetimeofthephotoflashcircuit.LinearTechnology
hasworkedwithseveralleadingmagneticcomponentman-
ufacturers to produce predesigned flyback transformers
forusewiththeLT3585-0/LT3585-1/LT3585-2/LT3585-3.
Table2showsthedetailsofseveralofthesetransformers.
Capacitor Selection
For the input bypass capacitors, high quality X5R or X7R
types should be used. Make sure the voltage capability of
the part is adequate.
Table 2. Predesigned Transformers—Typical Specifications Unless Otherwise Noted
FOR USE
WITH
TRANSFORMER
DESIGNATION
SIZE
(W × L × H) (mm)
LPRI
(µH)
LPRI LEAKAGE
(nH )
R
R
SEC
(Ω)
PRI
N
(mΩ)
VENDOR
LT3585-1
LT3585-0/
LT3585-2
SBL-5.6S-1
SBL-5.6-1
5.6 × 8.5 × 3.0
5.6 × 8.5 × 4.0
24
10
400 Max
200 Max
10.2
10.2
305
103
55
26
Kijima Musen
Hong Kong Office
852-2489-8266
LT3585-1
LT3585-0
LT3585-1
LT3585-2
LT3585-3
LDT565620ST-203
LDT565630T-001
LDT565630T-002
LDT565630T-003
LDT565630T-041
5.8 × 5.8 × 2.0
5.8 × 5.8 × 3.0
5.8 × 5.8 × 3.0
5.8 × 5.8 × 3.0
5.8 × 5.8 × 3.0
8.2
6
14.5
10.5
4.7
390 Max
200 Max
500 Max
550 Max
150 Max
10.2
10.4
10.2
10.2
10.4
370 Max
100 Max
240 Max
210 Max
90 Max
11.2 Max TDK
10 Max
Chicago Sales Office
16.5 Max (847) 803-6100
14 Max
6.4 Max
www.components.tdk.com
LT3585-0
LT3585-1
LT3585-2
LT3585-3
TTRN-0530-000-T
TTRN-0530-012-T
TTRN-0530-021-T
TTRN-0530-022-T
5.0 × 5.0 × 3.0
5.0 × 5.0 × 3.0
5.0 × 5.0 × 3.0
5.0 × 5.0 × 3.0
6.6
16.0
11.8
4.0
200 Max
400 Max
300 Max
300 Max
10.3
10.3
10.3
10.3
128 Max
515 Max
256 Max
102 Max
28 Max
32 Max
37 Max
16 Max
Tokyo Coil Engineering
Japan Office
0426-56-6262
3585f
12
LT3585-0/LT3585-1
LT3585-2/LT3585-3
W U U
APPLICATIO S I FOR ATIO
U
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
IGBTIN
1V/DIV
IGBTOUT
2V/DIV
3585 F06
I
C
R
= 5V
500ns/DIV
GBTPWR
OUT
PD
0
50
100
(Ω)
150
200
= 4000pF
= 50Ω
R
PD
3585 F07
Figure 6. IGBT Driver Output with 4000pF Load
Figure 7. IGBT Turn-Off Delay vs R
PD
Table 3. Recommended Output Diodes
MAX REVERSE
MAX CONTINUOUS
FORWARD CURRENT (mA)
PART
VOLTAGE (V)
CAPACITANCE (pF)
VENDOR
GSD2004S
2 × 300
225
225
225
5
Vishay
(DUAL DIODE)
(402) 563-6866
www.vishay.com
CMSD2004S
(DUAL DIODE)
2 × 300
2 × 350
5
5
Central Semiconductor
(631) 435-1110
www.centralsemi.con
MMBD3004S
(DUAL DIODE)
Diodes, Inc
(816) 251-8800
www.diodes.com
IGBT Drive
safe operation of the IGBT. The IGBT gate is a network of
resistors and capacitors, as shown in Figure 9. When the
gate terminal is pulled low, the capacitance closest to the
terminal goes low but the capacitance further from the
terminal remains high. This causes a smaller portion of
the device to handle a larger portion of the current, which
can damage the device. The pull-down circuitry needs to
pull down slower than the internal RC time constant in
the gate of the IGBT. This is easily accomplished with a
resistor placed in series with the IGBTPD pin.
The IGBT is a high current switch for the 100A+ current
through the photoflash lamp. To create a redeye effect or
to adjust the light output, the lamp current needs to be
stopped or quenched with an IGBT before discharging
the photoflash capacitor fully. The IGBT device also con-
trols the 4kV trigger pulse required to ionize the Xenon
gas in the photoflash lamp. Figure 8 is a schematic of a
fully functional photoflash application with the LT3585-0
serving as the IGBT driver. An IGBT driver charges the
gate capacitance to start the flash. The IGBT driver does
not need to pull up the gate significantly fast because of
the inherently slow nature of the IGBT. A rise time of 2µs
is sufficient to charge the gate of the IGBT and create a
trigger pulse. With slower rise times, the trigger circuitry
will not have a fast enough edge to create the required
4kV pulse. The fall time of the IGBT driver is critical to the
TheLT3585seriesintegratedIGBTdrivecircuitisindepen-
dent of the charging function and draws its power from
the IGBTPWR pin. The drive pulls high to within 200mV
of IGBTPWR and pulls down to 100mV. The circuit’s
switching waveform is shown in Figure 6. The rise and fall
times are measured using a 4000pF output capacitor. The
typical 10% to 90% rise time is 320ns when IGBTPWR
3585f
13
LT3585-0/LT3585-1
LT3585-2/LT3585-3
W U U
U
APPLICATIO S I FOR ATIO
to drop to approximately 0.1µA during idle conditions.
The pull-down circuit will clamp the output below 0.8V for
currents not exceeding 10mA in its idle state. The pull-up
network is always active when the IGBTIN is greater than
1.5V. Table 4 is a list of recommended IGBT devices for
strobe applications. These devices are all packaged in
8-lead TSSOP packages unless otherwise noted.
is 5V and IGBTIN is driven by a 5V signal. The typical
90% to 10% fall time is 125ns but varies with R given
PD
by Figure 7. The IGBT driver pulls a peak of 50mA when
driving an IGBT with minimal quiescent current. In the
low state, an active pull-down network is used during the
initial transition but is deactivated after an internal time
constant. This allows the IGBT driver’s quiescent current
Table 4. Recommended IGBTs
COLLECTOR CURRENT
PART
DRIVE VOLTAGE (V)
BREAKDOWN VOLTAGE (V)
(PULSED) (A)
VENDOR
CY25CAH-8F*
CY25CAJ-8F*
CY25BAH-8F
CY25BAJ-8F
2.5
4
2.5
4
400
400
400
400
150
150
150
150
Renesas
(408) 382-7500
www.renesas.com
GT8G133
4
400
150
Toshiba Semiconductor
(949) 623-2900
www.semicon.toshiba.co.jp/eng
*Packaged in 8-lead VSON-8 pacakge.
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
T1
D1
V
BAT
1:10:2
320V
2 AA OR
1
2
4
5
C1
4.7 F
R1
1M
1 TO 2 Li-Ion
•
C2
50 F
+
C4
•
2.2 F
600V
A
PHOTOFLASH
CAPACITOR
V
SW
GND
BAT
TRIGGER T
FLASHLAMP
C
DONE
1
3
2
CHRG/IADJ
LT3585-0
V
IN
V
IN
5V
C3
0.22 F
IGBTPWR
IGBTIN
IGBTPU
IGBTPD
TO GATE OF IGBT
R
PD
20 TO 160
3585 F08
Figure 8. Complete Xenon Circuit
GATE
3585 F09
EMITTER
Figure 9. IGBT Gate
3585f
14
LT3585-0/LT3585-1
LT3585-2/LT3585-3
W U U
APPLICATIO S I FOR ATIO
U
Board Layout
it will effectively increase the leakage inductance of T1,
which may result in an overvoltage condition on the SW
pin. The CHRG/IADJ pin trace should be kept as short as
possible while minimizing the adjacent edge with the SW
pintrace.ThiswilleliminatefalsetogglingoftheCHRG/IADJ
pin during sharp transitions on the SW pin. Thermal vias
should be added underneath the Exposed Pad, Pin 11, to
enhance the LT3585’s thermal performance. These vias
should go directly to a large area of ground plane. Acting
as a heat sink, the thermal vias/ground plane will lower
the device’s operating temperature.
The high voltage operation of these parts demand care-
ful attention to board layout. You will not get advertised
performance with careless layout. Figure 10 shows the
recommendedcomponentplacement.Keeptheareaforthe
highvoltageendofthesecondaryassmallaspossible.Also
note the larger than minimum spacing for all high voltage
nodesinordertomeetbreakdownvoltagerequirementsfor
the circuit board. It is imperative to keep the electrical path
formed by C1, the primary of T1, and the LT3585 series IC
as short as possible. If this path is haphazardly made long,
THERMAL
VIAS
TO GATE OF IGBT
V
BAT
C1
IGBTIN
D1 (DUAL DIODE)
1
2
3
4
5
10
9
T1
R2
IGBTPWR
GND
8
11
V
OUT
7
V
IN
PHOTOFLASH
CAPACITOR
6
V
BAT
R1
C2
3585 F10
GND
DONE CHRG
Figure 10. LT3585 Suggested Layout
3585f
15
LT3585-0/LT3585-1
LT3585-2/LT3585-3
U
TYPICAL APPLICATIO S
T1
1:10.4
D1
V
BAT
320V
1.5V TO 8V
C1
4.7µF
•
+
C
OUT
•
PHOTOFLASH
CAPACITOR
R1
100k
V
SW
GND
BAT
DONE
DONE
CHARGE
CHRG/IADJ
LT3585-0
V
IN
V
IN
2.5V TO 8V
C2
0.22µF
IGBTPWR
IGBTIN
IGBTPU
IGBTPD
TO GATE OF IGBT
3585 F11
R2
20Ω TO 160Ω
C1: 4.7µF, 10V, X5R OR X7R
C2: 0.22µF, 10V, X5R OR X7R
OUT
C
: RUBYCON 330V, 50µF PHOTOFLASH OUTPUT CAPACITOR (FW SERIES)
D1: VISHAY GSD2004S DUAL DIODE CONNECTED IN SERIES
R1: PULL-UP RESISTOR NEEDED IF DONE PIN USED
T1: TDK LDT565630T-001, L = 6µH, N = 10.4
PRI
Figure 11. LT3585-0 Photoflash Charger Uses High Efficiency 3mm Tall Transformer
T1
1:10.2
D1
V
BAT
320V
1.5V TO 8V
C1
4.7µF
•
C
+
OUT
•
PHOTOFLASH
CAPACITOR
R1
100k
V
SW
GND
BAT
DONE
DONE
CHARGE
CHRG/IADJ
LT3585-1
V
IN
V
IN
2.5V TO 8V
C2
0.22µF
IGBTPWR
IGBTIN
IGBTPU
IGBTPD
TO GATE OF IGBT
3585 F12
R2
20Ω TO 160Ω
C1: 4.7µF, 10V, X5R OR X7R
C2: 0.22µF, 10V, X5R OR X7R
OUT
C
: RUBYCON 330V, 50µF PHOTOFLASH OUTPUT CAPACITOR (FW SERIES)
D1: VISHAY GSD2004S DUAL DIODE CONNECTED IN SERIES
R1: PULL-UP RESISTOR NEEDED IF DONE PIN USED
T1: LTD565620ST-203, L = 8.2µH, N = 10.2
PRI
Figure 12. LT3585-1 Photoflash Charger Uses High Efficiency 2mm Tall Transformer
3585f
16
LT3585-0/LT3585-1
LT3585-2/LT3585-3
U
TYPICAL APPLICATIO S
T1
D1
1:10.2
V
BAT
320V
1.5V TO 8V
C1
4.7µF
•
+
C
OUT
PHOTOFLASH
CAPACITOR
•
R1
100k
V
SW
GND
BAT
DONE
DONE
CHARGE
CHRG/IADJ
LT3585-2
V
IN
V
IN
2.5V TO 8V
C2
0.22µF
IGBTPWR
IGBTIN
IGBTPU
IGBTPD
TO GATE OF IGBT
3585 F13
R2
20Ω TO 160Ω
C1: 4.7µF, 10V, X5R OR X7R
C2: 0.22µF, 10V, X5R OR X7R
RUBYCON 330V, 50µF PHOTOFLASH OUTPUT CAPACITOR (FW SERIES)
D1: VISHAY GSD2004S DUAL DIODE CONNECTED IN SERIES
R1: PULL-UP RESISTOR NEEDED IF DONE PIN USED
T1: TDK LDT565630T-003, L = 10.5µH, N = 10.2
PRI
Figure 13. LT3585-2 Uses High Efficiency 3mm Tall Transformers
T1
1:10.4
D1
V
BAT
320V
1.5V TO 8V
C1
4.7µF
•
C
+
OUT
•
PHOTOFLASH
CAPACITOR
R1
100k
V
SW
GND
BAT
DONE
DONE
CHARGE
CHRG/IADJ
LT3585-3
V
IN
V
IN
2.5V TO 8V
C2
0.22µF
IGBTPWR
IGBTIN
IGBTPU
IGBTPD
TO GATE OF IGBT
3585 F14
R2
20Ω TO 160Ω
C1: 4.7µF, 10V, X5R OR X7R
C2: 0.22µF, 10V, X5R OR X7R
RUBYCON 330V, 50µF PHOTOFLASH OUTPUT CAPACITOR (FW SERIES)
D1: VISHAY GSD2004S DUAL DIODE CONNECTED IN SERIES
R1: PULL-UP RESISTOR NEEDED IF DONE PIN USED
T1: TDK LDT565630T-041, L = 4.7µH, N = 10.4
PRI
Figure 14. LT3585-3 Uses High Efficiency 3mm Tall Transformers
3585f
17
LT3585-0/LT3585-1
LT3585-2/LT3585-3
U
TYPICAL APPLICATIO S
The LT3585 series can be auto-refreshed using the addi-
tional circuitry shown in Figure 15 with its basic operation
shown in Figure 16. The ENABLE pin is used to enable
or disable the auto-refresh charging mode. Without an
auto-refresh circuit, the output voltage will droop due to
output capacitor and output diode leakage currents. The
circuit in Figure 15 uses the DONE and CHRG/IADJ pins
to form an open-loop control scheme. The output voltage
target is sensed through the DONE pin with the PFET of
U1, Panasonic UP04979 composite transistor. When the
DONE pin goes low during the V
trip condition, the
OUT
PFET charges the auto-refresh timing node comprised
of R and C , and in turn, pulls the CHRG/IADJ pin low
T
T
through a NFET and disables the LT3585 series part. The
DONE pin immediately goes high in shutdown, releasing
the timing node and allowing the voltage at Pins 2 and 3
to decay. After approximately a R C time constant, the
T T
CHRG/IADJ pin is released and the LT3585 series part is
enabled. This cycle is repeated to maintain a constant DC
output voltage. The open-loop control method places a
constraint on the control loop dominant time constant,
R • C , given by:
R1
ENABLE
T
T
5k
1/10W
0402
TO
2 •IPK2 •LPRI
ILK • VBAT
V
IN
CHRG/IADJ
RTCT >
R3
6
1
4
3
100k
1/10W
0402
U1
TO
DONE
where I is the known leakage current, I is the trans-
former peak primary current, and L is the transformer
primary inductance. If this condition is not met, a runaway
condition could occur. The LT3585 series part would
continue to charge the output voltage past the internal
output trip voltage. Figure 17 shows the AC ripple of a
typical auto-refresh circuit with the proper selection of
5
LK
PK
PRI
2
R
T
C
T
0.1 F
100k
3585 F15
U1: PANASONIC UP04979 COMPOSITE TRANSISTORS
R and C .
T
T
Figure 15. Auto Refresh Application
V
OUT
V
OUT
100V/DIV
2V/DIV
AC RIPPLE
CHRG/IADJ
2V/DIV
CHRG/IADJ
2V/DIV
ENABLE
2V/DIV
3585 F17
LT3585-1
= 50µF
2sec/DIV
LT3585-1
C = 50µF
OUT
200ms/DIV
C
OUT
ENABLE > 1.1V AUTO ENABLE ENABLE
NORMAL OP. REFRESH <0.3V >1.1V
Figure 17. V
AC Ripple in Auto Refresh Mode
OUT
ENABLE < 0.3V
ENABLE < 0.3V
3585 F16
AUTO
REFRESH
Figure 16. Auto Refresh Basic Operation
3585f
18
LT3585-0/LT3585-1
LT3585-2/LT3585-3
U
PACKAGE DESCRIPTIO
DDB Package
10-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1722 Rev Ø)
0.64 0.05
(2 SIDES)
0.70 0.05
2.55 0.05
1.15 0.05
PACKAGE
OUTLINE
0.25 0.05
0.50 BSC
2.39 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
0.40 0.10
10
3.00 0.10
(2 SIDES)
TYP
6
R = 0.05
TYP
2.00 0.10
(2 SIDES)
PIN 1 BAR
TOP MARK
PIN 1
R = 0.20 OR
0.25 × 45°
CHAMFER
(SEE NOTE 6)
0.64 0.05
(2 SIDES)
5
1
(DDB10) DFN 0905 REV Ø
0.25 0.05
0.75 0.05
0.200 REF
0.50 BSC
2.39 0.05
(2 SIDES)
0 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
3585f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT3585-0/LT3585-1
LT3585-2/LT3585-3
U
TYPICAL APPLICATIO
T1
1:10.3
D1
V
BAT
320V
1.5V TO 8V
C1
4.7µF
•
C
+
OUT
•
PHOTOFLASH
CAPACITOR
R1
100k
V
SW
GND
BAT
DONE
DONE
CHARGE
CHRG/IADJ
LT3585-3
V
IN
V
IN
2.5V TO 8V
C2
0.22µF
IGBTPWR
IGBTIN
IGBTPU
IGBTPD
TO GATE OF IGBT
3585 F18
R2
20Ω TO 160Ω
C1: 4.7µF, 10V, X5R OR X7R
C2: 0.22µF, 10V, X5R OR X7R
OUT
C
: RUBYCON 330V, 50µF PHOTOFLASH OUTPUT CAPACITOR (FW SERIES)
D1: VISHAY GSD2004S DUAL DIODE CONNECTED IN SERIES
R1: PULL-UP RESISTOR NEEDED IF DONE PIN USED
T1: TOKYO COIL TTRN-0530-022-T, L = 4µH, N = 10.3
PRI
Figure 18. LT3585-3 Typical Application
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC®3407
Dual 600mA (I ), 1.5MHz, Synchronous Step-Down
96% Efficiency, V : 2.5V to 5.5V, V : 0.6V to 5V, I = 40µA,
IN OUT Q
OUT
DC/DC Converter
Converter I <1µA, 10-Lead MSE/10-Lead DFN Packages
SD
LT3420/LT3420-1
1.4A/1A, Photoflash Capacitor Chargers with Charges
Automatic Top-Off
Charges 220µF to 320V in 3.7 Seconds from 5V, Automatic Top-Off
V : 2.2V to 16V, I = 90µA, I < 1µA, 10-Lead MS/10-Lead DFN
IN
Q
SD
Packages
LTC3425
3A (I ), 8MHz, 4-Phase Synchronous Step-Up
95% Efficiency, V : 0.5V to 4.5V, V : 2.4V to 5.25V, I = 12µA,
IN OUT Q
SD
OUT
DC/DC Converter
I
< 1µA, 32-Lead 5mm × 5mm QFN Package
LTC3440
600mA (I ), Synchronous Buck-Boost DC/DC
95% Efficiency, V : 2.5V to 5.5V, V : 2.5V to 5.5V,
IN OUT
Converter I = 25µA, I < 1µA, 10-Lead MS/10-Lead DFN Packages
Q SD
OUT
Converter
LT3463/LT3463A
LT3468
Dual Boost (250mA)/Inverting (250mA/400mA) DC/DC Integrated Schottkys, V : 2.4V to 15V, V
=
40V, DC/DC
IN
OUT(MAX)
Converter for CCD Bias
Converter for CCD Bias, I = 40µA, I < 1µA, 10-LeadDFN Package
Q
SD
Photoflash Capacitor Charger in ThinSOTTM Package
Charges 100µF to 320V in 4.6 Seconds from 3.6V, V : 2.5V to 16V,
IN
I = 5mA, I < 1µA, 5-Lead TSOT-23 Package
Q
SD
LT3472
Dual 34V, 1.2MHz Boost (350mA)/Inverting (400mA)
DC/DC Converter for CCD Bias
Integrated Schottkys, V : 2.2V to 16V, V
=
34V, DC/DC
IN
OUT(MAX)
Converter for CCD Bias I = 2.8mA, I < 1µA, 10-Lead DFN Package
Q
SD
LT3484-0/LT3484-1
LT3484-2
Photoflash Capacitor Chargers
Charges 100µF to 320V in 4.6 Seconds from 3.6V,
LT3484-0 V : 2.5V to 16V, V : 1.8V to 16V, I = 5mA, I < 1µA,
IN
BAT
Q
SD
6-lead 2mm × 3mm DFN Package
LT3485-0/LT3485-1
LT3485-2/LT3485-3
Photoflash Capacitor Charger with Output Voltage
Monitor and Integrated IGBT Drive
Charges 100µF Capacitor to 320V in 2.5 Seconds from 3.6V.
V : 1.8V to 10V, I = 5mA, I < 1µA, 10-Lead 3mm × 3mm DFN
IN
Q
SD
Package
ThinSOT is a trademark of Linear Technology Corporation.
3585f
LT 0706 • PRINTED IN USA
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
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