LCXY [Linear]
Boost/Inverting DC/DC Converter with 2A Switch, Soft-Start, and Synchronization; 升压/负输出DC / DC转换器，具有2A开关，软起动和同步
| 型号： | LCXY |
| 厂家： | 
Linear |
| 描述： | Boost/Inverting DC/DC Converter with 2A Switch, Soft-Start, and Synchronization |
| 文件： | 总28页 (文件大小：458K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3580
Boost/Inverting DC/DC
Converter with 2A Switch,
Soft-Start, and Synchronization
FEATURES
DESCRIPTION
The LT®3580 is a PWM DC/DC converter containing an
internal 2A, 42V switch. The LT3580 can be configured
as either a boost, SEPIC or inverting converter. Capable
of generating 12V at 550mA or –12V at 350mA from a 5V
input, the LT3580 is ideal for many local power supply
designs.
n
2A Internal Power Switch
n
Adjustable Switching Frequency
n
Single Feedback Resistor Sets V
OUT
n
Synchronizable to External Clock
High Gain SHDN Pin Accepts Slowly Varying
Input Signals
n
n
n
n
n
n
n
Wide Input Voltage Range: 2.5V to 32V
The LT3580 has an adjustable oscillator, set by a resistor
from the RT pin to ground. Additionally, the LT3580 can
be synchronized to an external clock. The free running or
synchronized switching frequency range of the part can
be set between 200kHz and 2.5MHz.
Low V
Switch: 300mV at 1.5A (Typical)
CESAT
Integrated Soft-Start Function
Easily Configurable as a Boost or Inverting Converter
User Configurable Undervoltage Lockout (UVLO)
Tiny 8-Lead 3mm × 3mm DFN and 8-Lead MSOP
Packages
The LT3580 also features innovative SHDN pin circuitry
that allows for slowly varying input signals and an adjust-
able undervoltage lockout function.
APPLICATIONS
n
Additional features such as frequency foldback and soft-
start are integrated. The LT3580 is available in tiny 3mm
× 3mm 8-lead DFN and 8-lead MSOP packages.
VFD Bias Supplies
n
TFT-LCD Bias Supplies
n
GPS Receivers
DSL Modems
Local Power Supply
n
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
n
TYPICAL APPLICATION
1.2MHz, 5V to 12V Boost Converter Achieves over 88% Efficiency
Efficiency and Power Loss
95
90
85
80
75
70
65
60
55
50
1200
1000
800
600
400
200
0
4.2μH
V
OUT
V
5V
IN
12V
550mA
10μF
V
SW
GND
IN
SHDN
130k
LT3580
RT
FB
VC
SYNC
SS
10k
1nF
75k
2.2μF
0.1μF
3580 TA01
0
100
200
300
600
400
500
LOAD CURRENT (mA)
3580 TA01b
3580fc
1
LT3580
ABSOLUTE MAXIMUM RATINGS
IN
SW Voltage ................................................–0.4V to 42V
RT Voltage....................................................–0.3V to 5V
SS and FB Voltage.....................................–0.3V to 2.5V
VC Voltage ...................................................–0.3V to 2V
SHDN Voltage ............................................–0.3V to 32V
(Note 1)
V Voltage.................................................–0.3V to 32V
SYNC Voltage............................................–0.3V to 5.5V
Operating Junction Temperature Range
LT3580E (Notes 2, 5).........................–40°C to 125°C
LT3580I (Notes 2, 5)..........................–40°C to 125°C
Storage Temperature Range...................–65°C to 150°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
FB
1
2
3
4
8
7
6
5
SYNC
SS
FB
VC
1
2
3
4
8 SYNC
7 SS
VC
9
9
6
5
V
IN
RT
SHDN
V
RT
IN
SW
SW
SHDN
MS8E PACKAGE
8-LEAD PLASTIC MSOP
DD PACKAGE
T
= 125°C, θ = 35°C/W TO 40°C/W
JA
JMAX
8-LEAD (3mm × 3mm) PLASTIC DFN
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
T
= 125°C, θ = 43°C/W
JMAX
JA
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LT3580EDD#PBF
LT3580IDD#PBF
TAPE AND REEL
PART MARKING*
LCXY
PACKAGE DESCRIPTION
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead Plastic MSOP
TEMPERATURE RANGE
LT3580EDD#TRPBF
LT3580IDD#TRPBF
LT3580EMS8E#TRPBF
LT3580IMS8E#TRPBF
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
LCXY
LT3580EMS8E#PBF
LT3580IMS8E#PBF
LTDCJ
LTDCJ
8-Lead Plastic MSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3580fc
2
LT3580
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN unless otherwise noted. (Note 2)
PARAMETER
CONDITIONS
MIN
2.5
1.195
0
TYP
MAX
32
UNITS
V
l
l
l
l
l
Operating Voltage Range
Positive Feedback Voltage
Negative Feedback Voltage
Positive FB Pin Bias Current
Negative FB Pin Bias Current
Error Amplifier Transconductance
Error Amplifier Voltage Gain
Quiescent Current
1.215
5
1.230
12
V
mV
μA
V
V
= Positive Feedback Voltage, Current Into Pin
= Negative Feedback Voltage, Current Out of Pin
81
83.3
83.3
230
70
85
FB
FB
81
85.5
μA
μmhos
V/V
mA
μA
V
V
= 2.5V, Not Switching
= 0V
1
1.5
1
SHDN
SHDN
Quiescent Current in Shutdown
Reference Line Regulation
0
2.5V ≤ V ≤ 32V
0.01
0.05
%/V
IN
l
l
Switching Frequency, f
R = 45.3k
T
1.8
180
2
200
2.2
220
MHz
kHz
OSC
T
R = 464k
Switching Frequency in Foldback
Switching Frequency Set Range
SYNC High Level for Synchronization
SYNC Low Level for Synchronization
SYNC Clock Pulse Duty Cycle
Recommended Minimum SYNC Ratio f
Minimum Off-Time
Compared to Normal f
1/4
Ratio
kHz
V
OSC
l
l
l
SYNCing or Free Running
200
1.3
2500
0.4
65
V
V
= 0V to 2V
35
%
SYNC
/f
3/4
60
SYNC OSC
nS
nS
Minimum On-Time
100
l
l
Switch Current Limit
Minimum Duty Cycle (Note 3)
Maximum Duty Cycle (Notes 3, 4)
2.2
1.6
2.5
1.9
2.8
2.6
A
A
Switch V
I
= 1.5A
SW
300
0.01
6
mV
μA
μA
CESAT
Switch Leakage Current
V
V
= 5V
1
8
SW
SS
l
Soft-Start Charging Current
= 0.5V
4
l
l
SHDN Minimum Input
Voltage High
Active Mode, SHDN Rising
Active Mode, SHDN Falling
1.27
1.24
1.32
1.29
1.38
1.33
V
V
l
SHDN Input Voltage Low
SHDN Pin Bias Current
Shutdown Mode
0.3
V
V
V
V
= 3V
= 1.3V
= 0V
40
11.6
0
60
13.4
0.1
μA
μA
μA
SHDN
SHDN
SHDN
9.7
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3580E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3580I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 3: Current limit guaranteed by design and/or correlation to static test.
Note 4: Current limit measured at equivalent switching frequency of
2.5MHz.
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is
active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
3580fc
3
LT3580
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified
Switch Current Limit at Minimum
Duty Cycle
Switch Current Limit at 1MHz
Switch Saturation Voltage
400
350
300
250
200
150
100
50
2.5
2.0
1.5
1.0
0.5
0
2.5
2.0
1.5
1.0
0.5
0
0
0
400
600
800
1000 1200
200
60 70
10 20 30 40 50
DUTY CYCLE (%)
1
80 90
0
0.5
1.5
2
SS VOLTAGE (mV)
SWITCH CURRENT (A)
3580 G03
3580 G01
3580 G02
Switch Current Limit at Minimum
Duty Cycle
Switching Waveforms for
Figure 14 Circuit
Positive Feedback Voltage
3.0
2.5
1.24
1.23
1.22
1.21
1.20
1.19
V
OUT
50mV/DIV
AC COUPLED
2.0
1.5
V
SW
10V/DIV
1.0
0.5
0
I
L
0.5A/DIV
3580 G06
–50
0
50
100
200ns/DIV
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
3580 G04
3580 G05
Oscillator Frequency During
Soft-Start
Oscillator Frequency
Internal UVLO
2.40
2.38
2.36
2.34
2.32
2.30
2.28
2.26
2.24
2.22
2.20
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
1
R
T
= 35.7k
T
A
= 35°C
T
A
= 100°C
T
= 25°C
A
1/2
1/3
1/4
INVERTING
CONFIGURATIONS
BOOSTING
CONFIGURATIONS
R
= 75k
T
0
–50
0
50
100
50
0
TEMPERATURE (°C)
–50
100
0
0.2
0.4
0.6
0.8
1.0
1.2
TEMPERATURE (°C)
FB VOLTAGE (V)
3580 G09
3580 G07
3580 G08
3580fc
4
LT3580
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified
SHDN Pin Current
SHDN Pin Current
Active/Lockout Threshold
1.40
1.38
1.36
1.34
1.32
1.30
1.28
1.26
1.24
1.22
1.20
30
25
300
250
200
150
–50°C
20°C
100°C
20
15
SHDN RISING
SHDN FALLING
10
5
100
50
0
–50°C
20°C
100°C
0
–50
0
50
100
0
0.5
1
1.5
2
20
SHDN VOLTAGE (V)
30
0
5
10
15
25
TEMPERATURE (°C)
SHDN VOLTAGE (V)
3580 G12
3580 G10
3580 G11
PIN FUNCTIONS
FB (Pin 1): Positive and Negative Feedback Pin. For a
RT (Pin 6): Timing Resistor Pin. Adjusts the switching
frequency. Place a resistor from this pin to ground to set
the frequency to a fixed free running level. Do not float
this pin.
boost or inverting converter, tie a resistor from the FB pin
to V
according to the following equations:
OUT
V
ꢀ1.215
(
)
OUT
RFB =
RFB =
; Boost or SEPIC Converter
SS(Pin7):Soft-StartPin.Placeasoft-startcapacitorhere.
Upon start-up, the SS pin will be charged by a (nominally)
275k resistor to about 2.2V.
83.3•10ꢀ6
V
83.3•10ꢀ6
+ 5mV
(
)
OUT
; Inverting Converter
SYNC (Pin 8): To synchronize the switching frequency to
an outside clock, simply drive this pin with a clock. The
high voltage level of the clock needs to exceed 1.3V, and
the low level should be less 0.4V. Drive this pin to less than
0.4V to revert to the internal free running clock. See the
Applications Information section for more information.
VC (Pin 2): Error Amplifier Output Pin. Tie external com-
pensation network to this pin.
V (Pin 3): Input Supply Pin. Must be locally bypassed.
IN
SW (Pin 4): Switch Pin. This is the collector of the internal
NPN Power switch. Minimize the metal trace area con-
nected to this pin to minimize EMI.
Exposed Pad (Pin 9): Ground. Must be soldered directly
to local ground plane.
SHDN (Pin 5): Shutdown Pin. In conjunction with the
UVLO (undervoltage lockout) circuit, this pin is used
to enable/disable the chip and restart the soft-start
sequence. Drive below 1.24V to disable the chip. Drive
above 1.38V to activate chip and restart the soft-start
sequence. Do not float this pin.
3580fc
5
LT3580
BLOCK DIAGRAM
R
C
V
IN
C
C
C
IN
SS
C
7
2
SHDN
SS
VC
5
–
+
DISCHARGE
DETECT
L1
1.3V
275k
D1
UVLO
SR2
SW
VC
I
SOFT-
START
4
V
OUT
R
COMPARATOR
LIMIT
SR1
S
Q2
Q
–
+
DRIVER
C1
V
S
IN
A3
R
Q
Q1
1.215V
REFERENCE
3
+
–
+
R
FB
14.6k
A4
∑
0.01Ω
GND
A1
A2
–
RAMP
GENERATOR
FB
9
1
+
–
÷N
FREQUENCY
FOLDBACK
ADJUSTABLE
OSCILLATOR
14.6k
SYNC
BLOCK
SYNC
RT
8
6
R
T
3580 BD
3580fc
6
LT3580
OPERATION
The LT3580 uses a constant-frequency, current mode
control scheme to provide excellent line and load regula-
tion. Refer to the Block Diagram which shows the LT3580
in a boost configuration. At the start of each oscillator
cycle, the SR latch (SR1) is set, which turns on the power
switch, Q1. The switch current flows through the internal
current sense resistor generating a voltage proportional
to the switch current. This voltage (amplified by A4) is
added to a stabilizing ramp and the resulting sum is fed
into the positive terminal of the PWM comparator A3.
When this voltage exceeds the level at the negative input
of A3, the SR latch is reset, turning off the power switch.
The level at the negative input of A3 (VC pin) is set by the
error amplifier A1 (or A2) and is simply an amplified ver-
sion of the difference between the feedback voltage (FB
pin) and the reference voltage (1.215V or 5mV depending
on the configuration). In this manner, the error amplifier
sets the correct peak current level to keep the output in
regulation.
configuration, the FB pin is pulled down to 5mV by the
R
resistor connected from V
to FB. Comparator
FB
OUT
A1 becomes inactive and comparator A2 performs the
noninverting amplification from FB to VC.
SEPIC Topology
The LT3580 can be configured as a SEPIC (single-ended
primary inductance converter). This topology allows for
the input to be higher, equal, or lower then the desired
output voltage. Output disconnect is inherently built into
the SEPIC topology, meaning no DC path exists between
the input and output. This is useful for applications requir-
ing the output to be disconnected from the input source
when the circuit is in shutdown.
Inverting Topology
The LT3580 can also work in a dual inductor inverting
topology. The part’s unique feedback pin allows for the
inverting topology to be built by simply changing the
connection of external components. This solution results
in very low output voltage ripple due to inductor L2 in
serieswiththeoutput.Abruptchangesinoutputcapacitor
current are eliminated because the output inductor deliv-
ers current to the output during both the off-time and the
on-time of the LT3580 switch.
The LT3580 has a novel FB pin architecture that can be
used for either boost or inverting configurations. When
configured as a boost converter, the FB pin is pulled up
to the internal bias voltage of 1.215V by the R resistor
FB
connected from V
to FB. Comparator A2 becomes
OUT
inactive and comparator A1 performs the inverting ampli-
fication from FB to VC. When the LT3580 is in an inverting
C2
C2
L1
L2
L1
D1
R1
V
V
V
> V
= V
< V
•
•
IN
OUT
OR
OUT
OR
•
V
IN
V
V
OUT
OUT
•
L2
IN
IN
V
SW
V
SW
IN
IN
D1
+
+
OUT
C1
LT3580
C1
LT3580
R1
SHDN
FB
SHUTDOWN
SHDN
FB
SHUTDOWN
RT
GND
VC
+
RT
GND
VC
C3
C3
+
SYNC
SS
SYNC
SS
RC
CC
RC
CC
RT
C
RT
C
SS
SS
3580 F02
3580 F01
Figure 1. SEPIC Topology Allows for the Input to Span
the Output Voltage. Coupled or uncoupled inductors
can be used. Follow noted phasing if coupled.
Figure 2. Dual Inductor Inverting Topology Results in
Low Output Ripple. Coupled or uncoupled inductors
can be used. Follow noted phasing if coupled.
3580fc
7
LT3580
OPERATION
Start-Up Operation
Current Limit and Thermal Shutdown Operation
The LT3580 has a current limit circuit not shown in the
Block Diagram. The switch current is consistently moni-
tored and not allowed to exceed the maximum switch
current at a given duty cycle (see the Electrical Charac-
teristics table). If the switch current reaches this value,
the SR latch (SR1) is reset regardless of the state of the
comparator (A1/A2). Also not shown in the Block Diagram
is the thermal shutdown circuit. If the temperature of the
part exceeds approximately 165°C, the SR2 latch is set
regardless of the state of the comparator (A1/A2). A full
soft-start cycle will then be initiated. The current limit and
thermalshutdowncircuitsprotectthepowerswitchaswell
as the external components connected to the LT3580.
Several functions are provided to enable a very clean
start-up for the LT3580.
• First, the SHDN pin voltage is monitored by an internal
voltagereferencetogiveapreciseturn-onvoltagelevel.
Anexternalresistor(orresistordivider)canbeconnected
from the input power supply to the SHDN pin to provide
a user-programmable undervoltage lockout function.
• Second, the soft-start circuitry provides for a gradual
ramp-upoftheswitchcurrent. Whenthepartisbrought
out of shutdown, the external SS capacitor is first
discharged (providing protection against SHDN pin
glitches and slow ramping), then an integrated 275k
resistor pulls the SS pin up to ~2.2V. By connecting an
external capacitor to the SS pin, the voltage ramp rate
on the pin can be set. Typical values for the soft-start
capacitor range from 100nF to 1μF.
• Finally,thefrequencyfoldbackcircuitreducestheswitch-
ing frequency when the FB pin is in a nominal range of
350mV to 900mV. This feature reduces the minimum
duty cycle that the part can achieve thus allowing better
control of the switch current during start-up. When the
FB voltage is pulled outside of this range, the switching
frequency returns to normal.
3580fc
8
LT3580
APPLICATIONS INFORMATION
Setting Output Voltage
Inductor Selection
The output voltage is set by connecting a resistor (R )
General Guidelines: The high frequency operation of the
LT3580allowsfortheuseofsmallsurfacemountinductors.
For high efficiency, choose inductors with high frequency
core material, such as ferrite, to reduce core losses. To
improve efficiency, choose inductors with more volume
for a given inductance. The inductor should have low DCR
FB
from V
to the FB pin. R is determined from the
OUT
FB
following equation:
|VOUT ꢀ VFB |
RFB =
83.3μA
2
(copperwireresistance)toreduceI Rlosses,andmustbe
where V is 1.215V (typical) for non-inverting topologies
FB
able to handle the peak inductor current without saturat-
ing. Note that in some applications, the current handling
requirements of the inductor can be lower, such as in the
SEPIC topology, where each inductor only carries a frac-
tion of the total switch current. Molded chokes or chip
inductors usually do not have enough core area to sup-
port peak inductor currents in the 2A to 3A range. To
minimize radiated noise, use a toroidal or shielded induc-
tor. Note that the inductance of shielded types will drop
more as current increases, and will saturate more easily.
See Table 1 for a list of inductor manufacturers.
(i.e., boost and SEPIC regulators) and 5mV (typical) for
inverting topologies (see the Electrical Characteristics).
Power Switch Duty Cycle
In order to maintain loop stability and deliver adequate
current to the load, the power NPN (Q1 in the Block Dia-
gram) cannot remain “on” for 100% of each clock cycle.
The maximum allowable duty cycle is given by:
(TP ꢀMinOffTime)
DCMAX
=
•100%
TP
Table 1.Inductor Manufacturers
where T is the clock period and Min Off Time (found in
P
Coilcraft
DO3316P, MSS7341 and LPS4018
Series
www.coilcraft.com
the Electrical Characteristics) is typically 60ns.
Coiltronics DR, LD and CD Series
www.coiltronics.com
www.murata.com
www.sumida.com
The application should be designed so that the operating
Murata
Sumida
LQH55D and LQH66S Series
duty cycle does not exceed DC
.
MAX
CDRH5D18B/HP, CDR6D23MN,
CDRH6D26/HP, CDRH6D28,
CDR7D28MN and CDRH105R Series
Duty cycle equations for several common topologies are
given below, where V is the diode forward voltage drop
D
and V
is typically 300mV at 1.5A.
TDK
RLF7030 and VLCF4020 Series
WE-PD and WE-PD2 Series
www.tdk.com
CESAT
Würth
www.we-online.com
For the boost topology:
OUT ꢁ V + VD
Minimum Inductance: Although there can be a tradeoff
with efficiency, it is often desirable to minimize board
space by choosing smaller inductors. When choosing an
inductor, there are two conditions that limit the minimum
inductance; (1) providing adequate load current, and (2)
avoidance of subharmonic oscillation.
V
IN
DC ꢀ
V
OUT + VD ꢁ VCESAT
For the SEPIC or dual inductor inverting topology (see
Figures 1 and 2):
VD+|VOUT
V + |VOUT | + VD ꢁ VCESAT
|
DC ꢀ
Adequate Load Current: Small value inductors result in
increased ripple currents and thus, due to the limited peak
switch current, decrease the average current that can be
IN
The LT3580 can be used in configurations where the duty
cycle is higher than DC , but it must be operated in
provided to a load (I ). In order to provide adequate
MAX
OUT
the discontinuous conduction mode so that the effective
duty cycle is reduced.
load current, L should be at least:
DC • V
IN
L >
ꢂ
ꢄ
ꢃ
OUT ꢅ
|VOUT |• I
2(f) ILIM ꢀ
ꢇ
V • ꢁ
ꢆ
IN
3580fc
9
LT3580
APPLICATIONS INFORMATION
for boost, coupled inductor SEPIC and coupled inductor
inverting topologies, or:
thus causing duty cycle jitter and/or poor regulation. The
maximum inductance can be calculated by:
DC • V
VIN – VCESAT
IMINꢀRIPPLE
DC
f
IN
L1 L2>
LMAX
=
•
ꢂ
ꢅ
ꢀ IOUT ꢇ
ꢆ
VOUT • IOUT
2(f) ꢄILIM ꢀ
V • ꢁ
ꢃ
IN
where L
is L1||L2 for dual inductor topologies and a
MAX
good choice for I
is 300mA.
MIN-RIPPLE
for the uncoupled inductor SEPIC and uncoupled inductor
inverting topologies.
Current Rating: Finally, the inductor(s) must have a rating
greater than its peak operating current to prevent inductor
saturation resulting in efficiency loss. In steady state, the
peakinputinductorcurrent(continuousconductionmode
only) is given by:
where:
DC = switch duty cycle (see previous section)
I
= switch current limit, typically about 2.4A at 50%
dutycycle(seetheTypicalPerformanceCharacteristics
LIM
VOUT •IOUT
V •DC
2•L1• f
IN
section).
IL1ꢀPEAK
=
+
V • ꢁ
IN
η = power conversion efficiency (typically 88% for
boost and 75% for dual inductor topologies at high
currents).
for the boost, uncoupled inductor SEPIC and uncoupled
inductor inverting topologies, or:
|VOUT •IOUT
|
V •DC
f = switching frequency
IN
IL1ꢀPEAK ꢁ
+
V • ꢂ•DC 2•L1• f
IN
Negative values of L
indicate that the output load
MIN1
current I
exceeds the switch current limit capability
OUT
for the coupled inductor SEPIC and coupled inductor
inverting topology.
of the LT3580.
AvoidingSubharmonicOscillations:TheLT3580’sinternal
slopecompensationcircuitwillpreventsubharmonicoscil-
lations that can occur when the duty cycle is greater than
50%, provided that the inductance exceeds a minimum
value. In applications that operate with duty cycles greater
than 50%, the inductance must be at least:
For dual inductor topologies, the peak output inductor
current is given by:
VOUT • 1–DC
(
)
IL2ꢀPEAK =IOUT +
2•L2• f
for the uncoupled inductor topologies, or
V • 2•DC –1
(1ꢀDC)•(f)•0.8
(
)
IN
L >
VOUT • 1–DC
(
)
IOUT
1–DC
I
L2ꢀPEAK ꢁ
+
2•L2• f
for boost, coupled inductor SEPIC, and coupled inductor
inverting topologies, or:
for the coupled inductor topologies
V • 2•DC –1
(1ꢀDC)•(f)•0.8
(
)
IN
L1 L2>
Capacitor Selection
Low ESR (equivalent series resistance) capacitors should
beusedattheoutputtominimizetheoutputripplevoltage.
Multilayer ceramic capacitors are an excellent choice, as
they have an extremely low ESR and are available in very
small packages. X5R or X7R dielectrics are preferred, as
thesematerialsretaintheircapacitanceoverwidervoltage
for the uncoupled inductor SEPIC and uncoupled inductor
inverting topologies.
Maximum Inductance: Excessive inductance can reduce
currentrippletolevelsthataredifficultforthecurrentcom-
parator (A3 in the Block Diagram) to cleanly discriminate,
3580fc
10
LT3580
APPLICATIONS INFORMATION
and temperature ranges. A 4.7μF to 20μF output capaci-
tor is sufficient for most applications, but systems with
very low output currents may need only a 1μF or 2.2μF
output capacitor. Always use a capacitor with a sufficient
voltage rating. Many capacitors rated at 2.2μF to 20μF,
par ticularly 0805 or 0603 case sizes, have greatly reduced
capacitance at the desired output voltage. Solid tantalum
or OS-CON capacitors can be used, but they will occupy
more board area than a ceramic and will have a higher
ESR with greater output ripple.
Compensation—Adjustment
To compensate the feedback loop of the LT3580, a series
resistor-capacitornetworkinparallelwithasinglecapacitor
should be connected from the VC pin to GND. For most
applications, the series capacitor should be in the range
of 470pF to 2.2nF with 1nF being a good starting value.
The parallel capacitor should range in value from 10pF to
100pF with 47pF a good starting value. The compensation
resistor, R , is usually in the range of 5k to 50k. A good
C
technique to compensate a new application is to use a
Ceramic capacitors also make a good choice for the input
decoupling capacitor, which should be placed as closely as
possible to the LT3580. A 2.2μF to 4.7μF input capacitor
is sufficient for most applications.
100kΩ potentiometer in place of series resistor R . With
C
the series capacitor and parallel capacitor at 1nF and 47pF
respectively, adjust the potentiometer while observing the
transient response and the optimum value for R can be
C
found.Figures3ato3cillustratethisprocessforthecircuit
of Figure 14 with a load current stepped between 400mA
and 500mA. Figure 3a shows the transient response with
Table2showsalistofseveralceramiccapacitormanufac-
turers.Consultthemanufacturersfordetailedinformation
on their entire selection of ceramic parts.
R equal to 1k. The phase margin is poor, as evidenced
C
Table 2. Ceramic Capacitor Manufacturers
by the excessive ringing in the output voltage and induc-
Kemet
www.kemet.com
www.murata.com
www.t-yuden.com
tor current. In Figure 3b, the value of R is increased to
C
Murata
3k, which results in a more damped response. Figure 3c
Taiyo Yuden
showstheresultswhenR isincreasedfurtherto10k. The
C
transientresponseisnicelydampedandthecompensation
procedure is complete.
V
V
OUT
OUT
200mV/DIV
200mV/DIV
AC COUPLED
AC COUPLED
I
I
L
L
0.5A/DIV
0.5A/DIV
3580 F03a
3580 F03b
R
C
= 1k
200μs/DIV
R
C
= 3k
200μs/DIV
Figure 3a. Transient Response Shows Excessive Ringing
Figure 3b. Transient Response Is Better
V
OUT
200mV/DIV
AC COUPLED
I
L
0.5A/DIV
3580 F03c
R
C
= 10k
200μs/DIV
Figure 3c. Transient Response Is Well Damped
3580fc
11
LT3580
APPLICATIONS INFORMATION
Compensation—Theory
From Figure 4, the DC gain, poles and zeros can be cal-
culated as follows:
Like all other current mode switching regulators, the
LT3580 needs to be compensated for stable and efficient
operation. Two feedback loops are used in the LT3580—
a fast current loop which does not require compensation,
and a slower voltage loop which does. Standard bode plot
analysis can be used to understand and adjust the voltage
feedback loop.
2
Output Pole: P1=
2• ꢀ •RL •COUT
1
Error AmpPole: P2=
2• ꢀ •RO •CC
1
Error Amp Zero: Z1=
As with any feedback loop, identifying the gain and phase
contribution of the various elements in the loop is critical.
Figure 4 shows the key equivalent elements of a boost
converter. Because of the fast current control loop, the
power stage of the IC, inductor and diode have been re-
2• ꢀ •RC •CC
DC Gain:
VREF
1
4
A =
• V •gma •RO •gmp •RL •
IN
2
VOUT
placed by the equivalent transconductance amplifier g
.
mp
1
g
acts as a current source where the output current is
mp
ESR Zero: Z2=
RHP Zero: Z3=
2• ꢀ •RESR •COUT
proportional to the VC voltage.
–
V
2 •RL
2• ꢀ • VOUT2 •L
IN
g
mp
V
OUT
+
C
R
R
L
PL
ESR
fS
3
HighFrequency Pole: P3>
C
OUT
1.215V
REFERENCE
+
–
V
C
g
ma
R1
R2
1
R
R
O
Phase Lead Zero: Z4=
C
2• ꢀ •R1•CPL
C
C
3580 F04
1
C : COMPENSATION CAPACITOR
Phase Lead Pole: P4=
C
C
C
g
: OUTPUT CAPACITOR
R1•R2
R1+R2
OUT
2• ꢀ •CPL •
: PHASE LEAD CAPACITOR
PL
ma
mp
: TRANSCONDUCTANCE AMPLIFIER INSIDE IC
: POWER STAGE TRANSCONDUCTANCE AMPLIFIER
g
R : COMPENSATION RESISTOR
C
R : OUTPUT RESISTANCE DEFINED AS V
DIVIDED BY I
LOAD(MAX)
Thecurrentmodezero(Z3)isaright-halfplanezerowhich
canbeanissueinfeedbackcontroldesign, butismanage-
able with proper external component selection.
L
O
OUT
R : OUTPUT RESISTANCE OF g
ma
R1, R2: FEEDBACK RESISTOR DIVIDER NETWORK
: OUTPUT CAPACITOR ESR
R
ESR
Figure 4. Boost Converter Equivalent Model
Note that the ma ximum output currents of g andg are
mp
ma
finite.Thelimitsforg areintheElectricalCharacteristics
mp
section (switch current limit), and g is nominally limited
ma
to about 12μA.
3580fc
12
LT3580
APPLICATIONS INFORMATION
UsingthecircuitinFigure14asanexample, Table3shows
the parameters used to generate the bode plot shown in
Figure 5. Note that R2 is 14.6k ||14.6k = 7.3k which is the
effective small signal resistance looking into the FB pin
of the LT3580.
Diode Selection
Schottky diodes, with their low forward voltage drops and
fast switching speeds, are recommended for use with the
LT3580. The Microsemi UPS120 is a very good choice.
Wheretheinput-to-outputvoltagedifferentialexceeds20V,
use the UPS140 (a 40V diode). These diodes are rated to
handle an average forward current of 1A.
Table 3. Bode Plot Parameters
PARAMETER
VALUE
21.8
10
UNITS
Ω
COMMENT
Application Specific
Application Specific
Application Specific
Not Adjustable
Adjustable
R
L
Oscillator
C
μF
OUT
R
R
10
The operating frequency of the LT3580 can be set by the
internal free-running oscillator. When the SYNC pin is
driven low (< 0.4V), the frequency of operation is set by a
mΩ
kΩ
pF
ESR
O
305
1000
0
C
C
C
resistor from R to ground. An internally trimmed timing
T
pF
Optional/Adjustable
Adjustable
PL
capacitor resides inside the IC. The oscillator frequency
R
10
kΩ
kΩ
kΩ
V
C
is calculated using the following formula:
R1
R2
130
7.3
Adjustable
Not Adjustable
Not Adjustable
Application Specific
Application Specific
Not Adjustable
Not Adjustable
Application Specific
Adjustable
91.9
fOSC
=
V
V
V
1.215
12
REF
OUT
IN
(RT +1)
is in MHz and R is in kΩ. Conversely, R
T
V
where f
OSC
T
5
V
(in kΩ) can be calculated from the desired frequency (in
g
g
L
230
7
μmho
mho
μH
ma
MHz) using:
mp
4.2
1.2
91.9
fOSC
RT =
ꢀ1
f
MHz
S
In Figure 5, the phase is –140° when the gain reaches 0dB
giving a phase margin of 40°. The crossover frequency
is 10kHz, which is more than three times lower than the
frequency of the RHP zero to achieve adequate phase
margin.
Clock Synchronization
The operating frequency of the LT3580 can be synchro-
nized to an external clock source. To synchronize to the
external source, simply provide a digital clock signal into
the SYNC pin. The LT3580 will operate at the SYNC clock
frequency. The LT3580 will revert to the internal free-run-
ning oscillator clock after SYNC is driven low for a few
free-running clock periods.
180
160
140
120
0
–20
–40
–60
PHASE
100
80
–80
Driving SYNC high for an extended period of time effec-
tively stops the operating clock and prevents latch SR1
from becoming set (see the Block Diagram). As a result,
the switching operation of the LT3580 will stop.
–100
40° AT
60
40
–120
–140
–160
–180
–200
10kHz
GAIN
100
20
The duty cycle of the SYNC signal must be between 35%
and 65% for proper operation. Also, the frequency of the
SYNC signal must meet the following two criteria:
0
–20
10
1k
10k
100k
1M
FREQUENCY (Hz)
3580 F05
Figure 5. Bode Plot for Example Boost Converter
3580fc
13
LT3580
APPLICATIONS INFORMATION
(1) SYNC may not toggle outside the frequency range of
200kHz to 2.5MHz unless it is stopped low to enable
the free-running oscillator.
to ~200mV before charging resumes, thus assuring that
the soft-start occurs after every reactivation of the chip.
Shutdown
(2) The SYNC frequency can always be higher than the
The SHDN pin is used to enable or disable the chip. For
most applications, SHDN can be driven by a digital logic
source. Voltages above 1.38V enable normal active op-
eration. Voltages below 300mV will shutdown the chip,
resulting in extremely low quiescent current.
free-running oscillator frequency, f , but should not
OSC
be less than 25% below f
.
OSC
Operating Frequency Selection
There are several considerations in selecting the operat-
ing frequency of the converter. The first is staying clear
of sensitive frequency bands, which cannot tolerate any
spectral noise. For example, in products incorporating RF
communications, the 455kHz IF frequency is sensitive to
any noise, therefore switching above 600kHz is desired.
Some communications have sensitivity to 1.1MHz, and in
thatcase, a1.5MHzswitchingconverterfrequencymaybe
employed. The second consideration is the physical size
of the converter. As the operating frequency goes up, the
inductor and filter capacitors go down in value and size.
The tradeoff is efficiency, since the switching losses due
to NPN base charge (see Thermal Calculations), Schottky
diode charge, and other capacitive loss terms increase
proportionally with frequency.
While the SHDN voltage transitions through the lockout
voltage range (0.3V to 1.24V) the power switch is disabled
and the SR2 latch is set (see the Block Diagram). This
causesthesoft-startcapacitortobegindischarging,which
continues until the capacitor is discharged and active op-
eration is enabled. Although the power switch is disabled,
SHDN voltages in the lockout range do not necessarily
reduce quiescent current until the SHDN voltage is near
or below the shutdown threshold.
Also note that SHDN can be driven above V or V
as
IN
OUT
long as the SHDN voltage is limited to less than 32V.
ACTIVE
(NORMAL OPERATION)
1.38V
Soft-Start
(HYSTERESIS AND TOLERANCE)
1.24V
TheLT3580containsasoft-startcircuittolimitpeakswitch
currents during start-up. High start-up current is inherent
in switching regulators in general since the feedback loop
LOCKOUT
(POWER SWITCH OFF,
SS CAPACITOR DISCHARGED)
is saturated due to V
being far from its final value. The
OUT
0.3V
SHUTDOWN
(LOW QUIESCENT CURRENT)
regulator tries to charge the output capacitor as quickly
as possible, which results in large peak currents.
0.0V
3580 F06
The start-up current can be limited by connecting an
external capacitor (typically 100nF to 1μF) to the SS pin.
This capacitor is slowly charged to ~2.2V by an internal
275k resistor once the part is activated. SS pin voltages
below ~1.1V reduce the internal current limit. Thus, the
gradualrampingoftheSSvoltagealsograduallyincreases
the current limit as the capacitor charges. This, in turn,
allows the output capacitor to charge gradually toward its
final value while limiting the start-up current.
Figure 6. Chip States vs SHDN Voltage
Configurable Undervoltage Lockout
Figure 7 shows how to configure an undervoltage lock-
out (UVLO) for the LT3580. Typically, UVLO is used in
situations where the input supply is current-limited, has
a relatively high source resistance, or ramps up/down
slowly. A switching regulator draws constant power from
the source, so source current increases as source voltage
drops. This looks like a negative resistance load to the
source and can cause the source to current-limit or latch
In the event of a commanded shutdown or lockout (SHDN
pin), internal undervoltage lockout (UVLO) or a thermal
lockout,thesoft-startcapacitorisautomaticallydischarged
low under low source voltage conditions. UVLO prevents
3580fc
14
LT3580
APPLICATIONS INFORMATION
To activate the LT3580 for V voltage greater than 4.5V
IN
V
IN
V
IN
using the double resistor configuration, choose R
= 10k and:
UVLO2
ACTIVE/
LOCKOUT
1.3V
–
+
R
UVLO1
SHDN
4.5V ꢀ1.32V
RUVLO1
=
= 22.1k
11.6μA
AT 1.3V
R
1.32V
10k
ꢁ
ꢂ
ꢄ
ꢅ
UVLO2
(OPTIONAL)
+11.6μA
ꢃ
ꢆ
GND
3580 F07
Internal Undervoltage Lockout
The LT3580 monitors the V supply voltage in case V
IN
IN
Figure 7. Configurable UVLO
drops below a minimum operating level (typically about
2.3V). When V is detected low, the power switch is
the regulator from operating at source voltages where
these problems might occur.
IN
deactivated, and while sufficient V voltage persists, the
IN
soft-start capacitor is discharged. After V is detected
IN
Theshutdownpincomparatorhasvoltagehysteresiswith
typical thresholds of 1.32V (rising) and 1.29V (falling).
high, the power switch will be reactivated and the soft-
start capacitor will begin charging.
Resistor R
is optional. R
can be included to
UVLO2
UVLO2
reducetheoverallUVLOvoltagevariationcausedbyvaria-
Thermal Considerations
tions in SHDN pin current (see the Electrical Character-
FortheLT3580todeliveritsfulloutputpower, itisimpera-
tive that a good thermal path be provided to dissipate the
heat generated within the package. This is accomplished
bytakingadvantageofthethermalpadontheundersideof
the IC. It is recommended that multiple vias in the printed
circuit board be used to conduct heat away from the IC
and into a copper plane with as much area as possible.
istics). A good choice for R
UVLO2 UVLO1
mined from either of the following:
is ≤10k 1%.
can be deter-
UVLO2
, R
After choosing a value for R
+
V
ꢀ1.32V
IN
RUVLO1
=
=
ꢁ
ꢄ
1.32V
+11.6μA
ꢃ
ꢆ
R
ꢂ
UVLO2 ꢅ
or
Thermal Lockout
ꢀ
If the die temperature reaches approximately 165°C, the
part will go into thermal lockout, the power switch will be
turned off and the soft-start capacitor will be discharged.
The part will be enabled again when the die temperature
has dropped by ~5°C (nominal).
V
ꢀ1.29V
IN
RUVLO1
ꢁ
ꢄ
1.29V
+11.6μA
ꢃ
ꢆ
R
ꢂ
UVLO2 ꢅ
+
–
where V and V are the V voltages when rising or
IN
IN
IN
falling respectively.
Thermal Calculations
For example, to disable the LT3580 for V voltages below
Power dissipation in the LT3580 chip comes from four
IN
2
3.5V using the single resistor configuration, choose:
primary sources: switch I R loss, NPN base drive (AC),
NPN base drive (DC), and additional input current. The
following formulas can be used to approximate the power
losses. These formulas assume continuous mode opera-
3.5V ꢀ1.29V
RUVLO1
=
=190.5k
1.29V
ꢂ
ꢃ
ꢅ
ꢇ
+11.6μA
ꢄ
ꢆ
ꢁ
3580fc
15
LT3580
APPLICATIONS INFORMATION
tion, so they should not be used for calculating efficiency
in discontinuous mode or at light load currents.
V Ramp Rate
IN
While initially powering a switching converter application,
theV ramprateshouldbelimited.HighV rampratescan
VOUT •IOUT
IN
IN
Average Switch Current: ISW
=
causeexcessiveinrushcurrentsinthepassivecomponents
of the converter. This can lead to current and/or voltage
overstress and may damage the passive components or
the chip. Ramp rates less than 500mV/μs, depending on
componentparameters,willgenerallypreventtheseissues.
Also, be careful to avoid hotplugging. Hotplugging occurs
when an active voltage supply is “instantly” connected or
switchedtotheinputoftheconverter. Hotpluggingresults
in very fast input ramp rates and is not recommended.
Finally, for more information, refer to Linear application
note AN88, which discusses voltage overstress that can
occur when an inductive source impedance is hotplugged
to an input pin bypassed by ceramic capacitors.
V • ꢀ
IN
Switch I2R Loss: PSW =(DC)(ISW)2(RSW
Base Drive Loss (AC): PBAC =13n(ISW)(VOUT )(f)
)
(V )(ISW)(DC)
IN
Base Drive Loss (DC): PBDC
=
50
Input Power Loss: PINP = 7mA(V )
IN
where:
R
SW
= switch resistance (typically 200mΩ at 1.5A)
DC = duty cycle (see the Power Switch Duty Cycle
section for formulas)
Layout Hints
η = power conversion efficiency (typically 88% at high
As with all high frequency switchers, when considering
layout, care must be taken to achieve optimal electrical,
thermalandnoiseperformance.Onewillnotgetadvertised
performance with a careless layout. For maximum effi-
ciency, switch rise and fall times are typically in the 5ns to
10nsrange.Topreventnoise,bothradiatedandconducted,
the high speed switching current path, shown in Figure 8,
must be kept as short as possible. This is implemented in
the suggested layout of a boost configuration in Figure 9.
Shortening this path will also reduce the parasitic trace
inductance. At switch-off, this parasitic inductance pro-
duces a flyback spike across the LT3580 switch. When
operatingathighercurrentsandoutputvoltages,withpoor
layout, thisspikecangeneratevoltagesacrosstheLT3580
that may exceed its absolute maximum rating. A ground
plane should also be used under the switcher circuitry to
prevent interplane coupling and overall noise.
currents)
Example: boost configuration, V = 5V, V
= 12V, I
OUT
IN
OUT
= 0.5A, f = 1.25MHz, V = 0.5V:
D
I
= 1.36A
SW
DC = 61.5%
P
P
P
P
= 228mW
= 270mW
= 84mW
= 35mW
SW
BAC
BDC
INP
Total LT3580 power dissipation (P ) = 617mW
TOT
ThermalresistancefortheLT3580isinfluencedbythepres-
ence of internal, topside or backside planes. To calculate
die temperature, use the appropriate thermal resistance
number and add in worst-case ambient temperature:
The VC and FB components should be kept as far away
as practical from the switch node. The ground for these
components should be separated from the switch cur-
rent path. Failure to do so can result in poor stability or
subharmonic oscillation.
T = T + θ • P
TOT
J
A
JA
where T = junction temperature, T = ambient tempera-
J
A
ture, θ = 43°C/W for the 3mm × 3mm DFN package and
JA
35°C/W to 40°C/W for the MSOP Exposed Pad package.
P
is calculated above.
TOT
3580fc
16
LT3580
APPLICATIONS INFORMATION
C2, for best load regulation. You can tie the local ground
into the system ground plane at the C3 ground terminal.
Board layout also has a significant effect on thermal re-
sistance. The exposed package ground pad is the copper
plate that runs under the LT3580 die. This is a good thermal
path for heat out of the package. Soldering the pad onto
theboardreducesdietemperatureandincreasesthepower
capability of the LT3580. Provide as much copper area as
possible around this pad. Adding multiple feedthroughs
around the pad to the ground plane will also help. Figures
9 and 10 show the recommended component placement
for the boost and SEPIC configurations, respectively.
The cut ground copper at D1’s cathode is essential to
obtain low noise. This important layout issue arises due
to the chopped nature of the currents flowing in Q1 and
D1. If they are both tied directly to the ground plane be-
fore being combined, switching noise will be introduced
into the ground plane. It is almost impossible to get rid
of this noise, once present in the ground plane. The solu-
tion is to tie D1’s cathode to the ground pin of the LT3580
before the combined currents are dumped in the ground
plane as drawn in Figure 2, Figure 12 and Figure 13. This
single layout technique can virtually eliminate high
frequency “spike” noise, so often present on switching
regulator outputs.
Layout Hints for Inverting Topology
Figure 11 shows recommended component placement for
the dual inductor inverting topology. Input bypass capaci-
tor, C1, should be placed close to the LT3580, as shown.
The load should connect directly to the output capacitor,
L1
D1
C1
V
OUT
SW
LT3580
HIGH
FREQUENCY
SWITCHING
PATH
V
IN
C2 LOAD
GND
3580 F08
Figure 8. High Speed “Chopped” Switching Path for Boost Topology
3580fc
17
LT3580
APPLICATIONS INFORMATION
GND
GND
SYNC
1
2
3
4
8
7
6
5
9
C1
SYNC
1
2
3
4
8
7
6
5
9
V
IN
C1
SHDN
V
IN
L1
L2
SHDN
SW
L1
SW
C2
VIAS TO GROUND
PLANE REQUIRED
TO IMPROVE
D1
C2
VIAS TO GROUND
PLANE REQUIRED
TO IMPROVE
D1
C3
THERMAL
PERFORMANCE
3580 F09
THERMAL
V
OUT
PERFORMANCE
3580 F10
V
OUT
Figure 9. Suggested Component Placement for Boost Topology
(Both DFN and MSOP Packages. Not to Scale). Pin 9 (Exposed
Pad) must be soldered directly to the local ground plane for
adequate thermal performance. Multiple vias to additional
ground planes will improve thermal performance.
Figure 10. Suggested Component Placement for SEPIC Topology
(Both DFN and MSOP Packages. Not to Scale). Pin 9 (Exposed
Pad) must be soldered directly to the local ground plane for
adequate thermal performance. Multiple vias to additional
ground planes will improve thermal performance.
GND
SYNC
1
2
3
4
8
9
C1
7
V
IN
6
SHDN
5
L1
SW
C2
D1
L2
VIAS TO GROUND
PLANE REQUIRED
TO IMPROVE
C3
THERMAL
PERFORMANCE
3580 F11
V
OUT
Figure 11. Suggested Component Placement for Inverting Topology (Both DFN and MSOP Packages. Not to Scale).
Note cut in ground copper at diode’s cathode. Pin 9 (Exposed Pad) must be soldered directly to local ground plane
for adequate thermal performance. Multiple vias to additional ground planes will improve thermal performance.
3580fc
18
LT3580
APPLICATIONS INFORMATION
V
–(V + ⏐V ⏐)
IN OUT
CESAT
C2
L1
L2
SW
SWX
V
–V
OUT
IN
D1
Q1
+
C1
C3
R
LOAD
+
3580 F12
Figure 12. Switch-On Phase of an Inverting Converter. L1 and L2 Have Positive dI/dt.
V
IN
+ ⏐V ⏐+ V
V
D
OUT
D
C2
L1
L2
SW
SWX
V
–V
OUT
IN
D1
Q1
+
C1
C3
R
LOAD
+
3580 F13
Figure 13. Switch-Off Phase of an Inverting Converter. L1 and L2 Currents Have Negative dI/dt.
L1
4.2μH
D1
V
OUT
V
5V
IN
12V
550mA
C2
10μF
V
SW
GND
IN
SHDN
130k
LT3580
RT
FB
VC
SYNC
SS
10k
1nF
C1
2.2μF
75k
0.1μF
3580 F14
C1: 2.2μF, 25V, X5R, 1206
C2: 10μF, 25V, X5R, 1206
D1: MICROSEMI UPS120
L1: SUMIDA CDR6D23MN-4R2
Figure 14. 1.2MHz, 5V to 12V Boost Converter
3580fc
19
LT3580
TYPICAL APPLICATIONS
750kHz, 5V to 40V, 150mA Boost Converter
L1
47μH
D1
V
OUT
V
5V
IN
40V
150mA
C2
2.2μF
V
SW
GND
IN
SHDN
464k
LT3580
RT
FB
VC
SYNC
SS
10k
4.7nF
47pF
C1
2.2μF
121k
0.1μF
3580 TA02
C1, C2: 2.2μF, 25V, X5R, 1206
D1: MICROSEMI UPS140
L1: SUMIDA CDRH105R-470
Wide Input Range SEPIC Converter with 5V Output Switches at 2.5MHz
C3
L1
1μF
D1
4.7μH
V
IN
V
OUT
2.6V TO 12V
OPERATING
5V, 600mA (V = 5V OR HIGHER)
IN
500mA (V = 4V)
IN
IN
IN
L2
4.7μH
C2
10μF
12V TO 32V
TRANSIENT
400mA (V = 3V)
V
SW
GND
IN
300mA (V = 2.6V)
SHDN
46.4k
LT3580
RT
FB
VC
SYNC
SS
10k
1nF
C1
2.2μF
22pF
35.7k
0.1μF
3580 TA03a
C1: 2.2μF, 35V, X5R, 1206
C2: 10μF, 10V, X5R, 1206
C3: 1μF, 50V, X5R, 0805
D1: MICROSEMI UPS140
L1, L2: TDK VLCF4020T-4R7N1R2
Transient Response with 400mA to 500mA Output Load Step
V
OUT
100mV/DIV
AC COUPLED
I
+I
L1 L2
0.5A/DIV
3580 TA03b
V
IN
= 12V
100μs/DIV
3580fc
20
LT3580
TYPICAL APPLICATIONS
VFD (Vacuum Flourescent Display) Power Supply Switches at 2MHz to Avoid AM Band
Danger High Voltage! Operation by High Voltage Trained Personnel Only
D1
D3
V
OUT2
95V
R2
C5
80mA
D2
D4
10Ω
1μF
C7
1μF
L1
10μH
V
OUT1
64V
V
IN
R1
10Ω
40mA
C4
1μF
9V TO 16V
3.3V
C6
1μF
V
SW
IN
D5
C3
1μF
SHDN
LT3580
C1
4.7μF
GND
383k
RT
FB
VC
C2
4.7μF
SYNC
SS
10k
2.2nF
47pF
45.3k
0.1μF
3580 TA04
C1, C2: 4.7μF, 25V, X5R, 1206
C3-C7: 1μF, 50V, X5R, 0805
D1-D4: ON SEMICONDUCTOR MBR0540
D5: MICROSEMI UPS140
L1: SUMIDA CDR6D28MNNP-100
R1, R2: 0.5W
3580fc
21
LT3580
TYPICAL APPLICATIONS
High Voltage Positive Power Supply Uses Tiny 5.8mm × 5.8mm × 3mm Transformer and Switches at 200kHz
Danger High Voltage! Operation by High Voltage Trained Personnel Only
V
T1
OUT
V
350V
4.5mA (V = 5V)
IN
1:10.4
3.3V TO 5V
7, 8
4.7μH
5, 6
1
4
IN
IN
•
2.5mA (V = 3.3V)
D1
•
C2
68nF
D2
V
SW
IN
FOR ANY V
BETWEEN 50V TO
OUT
GND
350V, CHOOSE R ACCORDING TO
FB
SHDN
R
4.22M*
FB
LT3580
V
– 1.215
OUT
R
=
RT
FB
FB
83.3μA
VC
FOR 5V INPUT, KEEP MAXIMUM
OUTPUT POWER AT 1.58W
FOR 3.3V INPUT, KEEP MAXIMUM
OUTPUT POWER AT 0.88W
SYNC
SS
10k
100pF
C1
2.2μF
464k
0.47μF
10nF
*MAY REQUIRE MULTIPLE SERIES
RESISTORS TO COMPLY WITH
MAXIMUM VOLTAGE RATINGS
3580 TA05a
C1: 2.2μF, 25V, X5R, 1206
C2: TDK C3225X7R2J683M
D1: VISHAY GSD2004S DUAL DIODE CONNECTED IN SERIES
D2: ON SEMICONDUCTOR MBR0540
T1: TDK LDT565630T-041
Start-Up Waveforms
I
PRIMARY
1A/DIV
V
OUT
50V/DIV
3580 TA05b
5V INPUT
NO LOAD
2ms/DIV
Switching Waveforms
V
OUT
2V/DIV
AC COUPLED
I
PRIMARY
1A/DIV
3580 TA05c
5V INPUT
4.5mA LOAD
2μs/DIV
3580fc
22
LT3580
TYPICAL APPLICATIONS
High Voltage Negative Power Supply Uses Tiny 5.8mm × 5.8mm × 3mm Transformer and Switches at 200kHz
Danger High Voltage! Operation by High Voltage Trained Personnel Only
T1
1:10.4
D1
V
IN
3.3V TO 5V
7, 8
4.7μH
5, 6
1
4
•
•
C2
68nF
FOR ANY V
BETWEEN –50V TO
FB
OUT
D2
–350V, CHOOSE R ACCORDING TO
V
OUT
R
=
FB
V
SW
IN
83.3μA
SHDN
GND
FOR 5V INPUT, KEEP MAXIMUM
OUTPUT POWER AT 1.58W
FOR 3.3V INPUT, KEEP MAXIMUM
OUTPUT POWER AT 0.88W
*MAY REQUIRE MULTIPLE SERIES
RESISTORS TO COMPLY WITH
MAXIMUM VOLTAGE RATINGS
R
4.22M*
FB
LT3580
V
OUT
RT
FB
–350V
VC
4.5mA (V = 5V)
2.5mA (V = 3.3V)
IN
IN
SYNC
SS
10k
100pF
C1
2.2μF
464k
0.47μF
10nF
3580 TA06
C1: 2.2μF, 25V, X5R, 1206
C2: TDK C3225X7R2J683M
D1: VISHAY GSD2004S DUAL DIODE CONNECTED IN SERIES
D2: ON SEMICONDUCTOR MBR0540
T1: TDK LDT565630T-041
3580fc
23
LT3580
TYPICAL APPLICATIONS
5V to 12V Boost Converter Switches at 2.5MHz and Uses a Tiny 4mm × 4mm × 1.7mm Inductor
L1
3.3μH
D1
V
OUT
V
5V
IN
12V
500mA
C2
4.7μF
V
SW
GND
IN
SHDN
130k
LT3580
RT
FB
VC
SYNC
SS
10k
2.2nF
47pF
C1
4.7μF
35.7k
0.1μF
3580 TA07a
C1, C2: 4.7μF, 25V, X5R, 1206
D1: MICROSEMI UPS120
L1: COILCRAFT LPS4018-332ML
Efficiency and Power Loss
vs Load Current
1400
95
90
85
80
75
70
65
60
55
1200
1000
800
600
400
200
0
50
0
100
200
300
600
400
500
LOAD CURRENT (mA)
3580 TA07b
Transient Response with 400mA to
500mA to 400mA Output Load Step
Start-Up Waveforms
V
OUT
5V/DIV
V
OUT
0.5V/DIV
AC COUPLED
I
L
1A/DIV
I
L
0.5A/DIV
V
SHDN
1V/DIV
3580 TA07d
3580 TA07c
500mA LOAD
2ms/DIV
100μs/DIV
3580fc
24
LT3580
TYPICAL APPLICATIONS
–5V Output Inverting Converter Switches at 2.5MHz and Accepts Inputs Between 3.3V to 12V
C3
1μF
L1
4.7μH
L2
4.7μH
V
OUT
V
IN
–5V
3.3V TO 12V
800mA (V = 12V)
IN
620mA (V = 5V)
IN
C2
10μF
D1
V
SW
GND
450mA (V = 3.3V)
IN
IN
SHDN
60.2k
LT3580
RT
FB
VC
SYNC
SS
10k
100pF
C1
2.2μF
35.7k
0.1μF
2.2nF
3580 TA08a
C1: 2.2μF, 25V, X5R, 1206
C2: 10μF, 25V, X5R, 1206
C3: 1μF, 50V, X5R, 0805
D1: CENTRAL SEMI CMMSH1-40
L1, L2: COILCRAFT LSP4018-472ML
Efficiency and Power Loss
vs Load Current
1200
85
80
75
70
65
60
55
50
45
V
= 5V
IN
1000
800
600
400
200
0
40
0
100 200 300
600 700
400 500
LOAD CURRENT (mA)
3580 TA08b
3580fc
25
LT3580
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
0.675 ±0.05
3.5 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
0.38 ± 0.10
TYP
5
8
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD) DFN 1203
4
1
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.50 BSC
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
3580fc
26
LT3580
PACKAGE DESCRIPTION
MS8E Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1662)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.06 ± 0.102
(.081 ± .004)
1
1.83 ± 0.102
(.072 ± .004)
0.889 ± 0.127
(.035 ± .005)
2.794 ± 0.102
(.110 ± .004)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
2.083 ± 0.102
(.082 ± .004)
8
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.52
(.0205)
REF
0.65
(.0256)
BSC
0.42 ± 0.038
(.0165 ± .0015)
TYP
8
7 6 5
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4
0.53 ± 0.152
(.021 ± .006)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ± 0.0508
(.004 ± .002)
0.65
(.0256)
BSC
MSOP (MS8E) 0307 REV D
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3580fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresenta-
t ion t h a t t he in ter c onne c t ion o f i t s cir cui t s a s de s cr ib e d her ein w ill no t in fr inge on ex is t ing p a ten t r igh t s.
27
LT3580
TYPICAL APPLICATION
Efficiency and Power Loss
vs Load Current
2MHz Inverting Converter Generates –12V from a 5V to 12V Input
C3
90
85
80
75
70
65
60
55
50
1400
1200
1000
800
600
400
200
0
L1
L2
V
= 5V
IN
1μF
10μH
22μH
V
OUT
V
IN
–12V
5V TO 12V
500mA (V = 12V)
350mA (V = 5V)
IN
IN
C2
10μF
D1
V
SW
GND
IN
SHDN
147k
LT3580
RT
FB
VC
SYNC
SS
47pF
10k
2.2nF
C1
2.2μF
45.3k
0.1μF
3580 TA09a
C1: 2.2μF, 25V, X5R, 1206
C2: 10μF, 25V, X5R, 1206
C3: 1μF, 50V, X5R, 0805
200 250
300 350 400
LOAD CURRENT (mA)
0
50 100 150
D1: CENTRAL SEMI CMMSH1-40
L1: SUMIDA CDRH6D28NP-100NC
L2: SUMIDA CDRH3D28NP-220NC
3580 TA09b
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
V : 2.3V to 16V, V
LT1310
2A (I ), 40V, 1.2MHz High Efficiency Step-Up DC/DC
= 40V, I = 3mA, I < 1μA,
OUT(MAX) Q SD
SW
IN
Converter
ThinSOTTM Package
LT1613
550mA (I ), 1.4MHz High Efficiency Step-Up DC/DC
V : 0.9V to 10V, V
= 34V, I = 3mA, I < 1μA,
Q SD
SW
Converter
IN
OUT(MAX)
OUT(MAX)
OUT(MAX)
ThinSOT Package
LT1618
1.5A (I ), 1.25MHz High Efficiency Step-Up DC/DC Converter V : 1.6V to 18V, V
= 35V, I = 1.8mA, I < 1μA,
Q SD
SW
IN
MS10 Package
LT1930/LT1930A
1A (I ), 1.2MHz/2.2MHz High Efficiency Step-Up DC/DC
V : 2.6V to 16V, V
= 34V, I = 4.2mA/5.5mA, I
<
<
SW
IN
Q
SD
SD
Converter
1μA,
ThinSOT Package
LT1931/LT1931A
LT1935
1A (I ), 1.2MHz/2.2MHz High Efficiency Inverting DC/DC
V : 2.6V to 16V, V
= 34V, I = 4.2mA/5.5mA, I
OUT(MAX) Q
SW
IN
Converter
1μA,
ThinSOT Package
2A (I ), 40V, 1.2MHz High Efficiency Step-Up DC/DC
V : 2.3V to 16V, V
= 40V, I = 3mA, I < 1μA,
Q SD
SW
IN
OUT(MAX)
OUT(MAX)
OUT(MAX)
OUT(MAX)
Converter
ThinSOT Package
LT1944/LT1944-1 Dual Output 350mA (I ), Constant Off-Time, High Efficiency
(Dual)
V : 1.2V to 15V, V
= 34V, I = 20μA, I < 1μA,
Q SD
SW
IN
Step-Up DC/DC Converter
MS10 Package
LT1945 (Dual)
Dual Output Pos/Neg 350mA (I ), Constant Off-Time,
V : 1.2V to 15V, V
= 34V, I = 20μA, I < 1μA,
Q SD
SW
IN
High Efficiency Step-Up DC/DC Converter
MS10 Package
LT1946/LT1946A
LT1961
1.5A (I ), 1.2MHz/2.7MHz High Efficiency Step-Up DC/DC
V : 2.6V to 16V, V
= 34V, I = 3.2mA, I < 1μA,
Q SD
SW
IN
Converter
MS8E Package
1.5A (I ), 1.25MHz High Efficiency Step-Up DC/DC Converter V : 3V to 25V, V
= 35V, I = 0.9mA, I < 6μA,
Q SD
SW
IN
OUT(MAX)
MS8E Package
LT3436
3A (I ), 800kHz, 34V Step-Up DC/DC Converter
V : 3V to 25V, V
= 34V, I = 0.9mA, I < 6μA,
Q SD
SW
IN
OUT(MAX)
TSSOP16E Package
LT3467
1.1A (I ), 1.3MHz High Efficiency Step-Up DC/DC Converter
V : 2.6V to 16V, V
= 40V, I = 1.2mA, I < 1μA,
OUT(MAX) Q SD
SW
IN
ThinSOT, 2mm × 3mm DFN Packages
LT3477
42V, 3A, 3.5MHz Boost, Buck-Boost, Buck LED Driver
V : 2.5V to 25V, V = 40V, Analog/PWM, I < 1μA,
IN
OUT(MAX)
SD
QFN, TSSOP20E Packages
V : 2.5V to 24V, V = 40V, Analog/PWM, I < 1μA,
OUT(MAX) SD
LT3479
3A Full-Featured DC/DC Converter with Soft-Start and Inrush
Current Protection
IN
DFN, TSSOP Packages
3580fc
LT 0508 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
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