LT1016CS8#PBF [Linear]
LT1016 - Ultra Fast Precision 10ns Comparator; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C;
| 型号： | LT1016CS8#PBF |
| 厂家： | 
Linear |
| 描述： | LT1016 - Ultra Fast Precision 10ns Comparator; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C 比较器 放大器 光电二极管 |
| 文件： | 总20页 (文件大小：1219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1016
UltraFast Precision
10ns Comparator
U
FEATURES
DESCRIPTIO
The LT®1016 is an UltraFast 10ns comparator that inter-
facesdirectlytoTTL/CMOSlogicwhileoperatingoffeither
±5V or single 5V supplies. Tight offset voltage specifica-
tions and high gain allow the LT1016 to be used in
precision applications. Matched complementary outputs
further extend the versatility of this comparator.
UltraFastTM (10ns typ)
■
■
Operates Off Single 5V Supply or ±5V
■
Complementary Output to TTL
■
Low Offset Voltage
No Minimum Input Slew Rate Requirement
No Power Supply Current Spiking
Output Latch Capability
■
■
■
A unique output stage provides active drive in both direc-
tions for maximum speed into TTL/CMOS logic or passive
loads, yet does not exhibit the large current spikes found
in conventional output stages. This allows the LT1016 to
remain stable with the outputs in the active region which,
greatlyreducestheproblemofoutput“glitching”whenthe
input signal is slow moving or is low level.
U
APPLICATIO S
■
High Speed A/D Converters
High Speed Sampling Circuits
Line Receivers
Extended Range V-to-F Converters
Fast Pulse Height/Width Discriminators
Zero-Crossing Detectors
Current Sense for Switching Regulators
High Speed Triggers
■
■
■
The LT1016 has a LATCH pin which will retain input data
at the outputs, when held high. Quiescent negative power
supply current is only 3mA. This allows the negative
supply pin to be driven from virtually any supply voltage
with a simple resistive divider. Device performance is not
affected by variations in negative supply voltage.
■
■
■
■
■
Crystal Oscillators
Linear Technology offers a wide range of comparators in
addition to the LT1016 that address different applications.
See the Related Parts section on the back page of the data
sheet.
, LTC and LT are registered trademarks of Linear Technology Corporation.
UltraFast is a trademark of Linear Technology Corporation.
U
TYPICAL APPLICATION
Response Time
10MHz to 25MHz Crystal Oscillator
5V
THRESHOLD
THRESHOLD
V
IN
10MHz TO 25MHz
100mV STEP
2k
(AT CUT)
5mV OVERDRIVE
22Ω
5V
820pF
+
V
+
–
Q
LT1016
2k
OUTPUT
V
OUT
Q
1V/DIV
GND
LATCH
–
V
0
0
20
TIME (ns)
20
2k
200pF
1016 TA1a
1016 TA2b
1
LT1016
W W U W
ABSOLUTE AXI U RATI GS
(Note 1)
Positive Supply Voltage (Note 5) ............................... 7V
Negative Supply Voltage ............................................ 7V
Differential Input Voltage (Note 7) ........................... ±5V
+IN, –IN and LATCH ENABLE Current (Note 7) .. ±10mA
Output Current (Continuous) (Note 7) ................ ±20mA
Operating Temperature Range
LT1016I ...............................................–40∞C to 85∞C
LT1016C.................................................. 0∞C to 70∞C
Storage Temperature Range ................. –65∞C to 150∞C
Lead Temperature (Soldering, 10 sec).................. 300∞C
U
W
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
TOP VIEW
+
+
V
1
2
3
4
Q OUT
Q OUT
GND
8
7
6
5
V
1
2
3
4
8
7
6
5
Q OUT
Q OUT
GND
LT1016CN8
LT1016IN8
LT1016CS8
LT1016IS8
+
–
+IN
+
–
+IN
–IN
–IN
–
–
V
LATCH
ENABLE
V
LATCH
ENABLE
S8 PART
MARKING
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 110∞C, qJA = 120∞C/W
TJMAX = 100∞C, qJA = 130∞C/W (N8)
1016
1016I
Consult LTC marketing for parts specified with wider operating temperature ranges.
2
LT1016
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25∞C. V+ = 5V, V– = 5V, VOUT (Q) = 1.4V, VLATCH = 0V, unless otherwise noted.
LT1016C/I
SYMBOL PARAMETER
Input Offset Voltage
CONDITIONS
MIN
TYP
MAX
UNITS
V
R £ 100W (Note 2)
S
1.0
±3
3.5
mV
mV
OS
●
●
DV
OS
Input Offset Voltage Drift
Input Offset Current
Input Bias Current
4
mV/∞C
DT
I
I
(Note 2)
(Note 3)
0.3
0.3
1.0
1.3
mA
mA
OS
●
●
5
10
13
mA
mA
B
Input Voltage Range
(Note 6)
Single 5V Supply
●
●
–3.75
1.25
3.5
3.5
V
V
CMRR
PSRR
Common Mode Rejection
Supply Voltage Rejection
–3.75V £ V £ 3.5V
●
●
80
60
96
75
dB
dB
CM
+
Positive Supply 4.6V £ V £ 5.4V
LT1016C
+
Positive Supply 4.6V £ V £ 5.4V
●
●
54
75
dB
LT1016I
–
Negative Supply 2V £ V £ 7V
80
100
dB
A
Small-Signal Voltage Gain
Output High Voltage
1V £ V
£ 2V
OUT
1400
3000
V/V
V
+
V
V ≥ 4.6V
I
I
=1mA
= 10mA
●
●
2.7
2.4
3.4
3.0
V
V
OH
OUT
OUT
V
Output Low Voltage
I
I
= 4mA
= 10mA
●
0.3
0.4
0.5
V
V
OL
SINK
SINK
+
I
I
Positive Supply Current
Negative Supply Current
LATCH Pin Hi Input Voltage
LATCH Pin Lo Input Voltage
LATCH Pin Current
●
●
●
●
●
25
3
35
5
mA
mA
V
–
V
V
I
2.0
IH
IL
0.8
V
V
= 0V
LATCH
500
mA
IL
t
Propagation Delay (Note 4)
DV = 100mV, OD = 5mV
10
9
14
16
ns
ns
PD
IN
●
●
DV = 100mV, OD = 20mV
IN
12
15
ns
ns
Dt
PD
Differential Propagation
Delay
(Note 4) DV = 100mV,
3
ns
IN
OD = 5mV
Latch Setup Time
2
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Dt limits shown can be guaranteed with this test if additional DC tests
PD
are performed to guarantee that all internal bias conditions are correct. For
low overdrive conditions V is added to overdrive. Differential
OS
Note 2: Input offset voltage is defined as the average of the two voltages
measured by forcing first one output, then the other to 1.4V. Input offset
current is defined in the same way.
propogation delay is defined as: Dt = t
– t
PDHL
PD
PDLH
Note 5: Electrical specifications apply only up to 5.4V.
Note 3: Input bias current (I ) is defined as the average of the two input
currents.
Note 6: Input voltage range is guaranteed in part by CMRR testing and in
part by design and characterization. See text for discussion of input
voltage range for supplies other than ±5V or 5V.
B
Note 4: t and Dt cannot be measured in automatic handling
PD
PD
equipment with low values of overdrive. The LT1016 is sample tested with
Note 7: This parameter is guaranteed to meet specified performance
a 1V step and 500mV overdrive. Correlation tests have shown that t and
through design and characterization. It has not been tested.
PD
3
LT1016
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Propagation Delay vs Input
Overdrive
Propagation Delay vs Load
Capacitance
Gain Characteristics
25
20
15
10
5
25
20
15
10
5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
T
= ±5V
V
T
OUT
V
= ± 5V
S
V
OUT
= ± 5V
S
J
S
= 25°C
= 25°C
I
= 0
J
T = 125°C
J
V
= 100mV
= 10pF
I
= 0
STEP
LOAD
C
= 100mV
STEP
OVERDRIVE = 5mV
T = 25°C
J
t
PDHL
t
PDLH
T = –55°C
J
0
0
0
10
20
30
40
50
–0.5
0
10
30
40
50
–2.5
–1.5
0.5
1.5
2.5
20
OVERDRIVE (mV)
DIFFERENTIAL INPUT VOLTAGE (mV)
OUTPUT LOAD CAPACITANCE (pF)
1016 G02
1016 G01
1016 G03
Propagation Delay vs Source
Resistance
Propagation Delay vs Supply
Voltage
Propagation Delay vs
Temperature
30
25
20
15
10
5
25
20
15
10
5
80
70
60
50
40
30
20
10
0
–
V
T
= ± 5V
V
= –5V
S
J
V
= ± 5V
S
= 25°C
T = 25°C
J
OVERDRIVE = 5mV
STEP SIZE = 100mV
OVERDRIVE = 20mV
EQUIVALENT INPUT
V
= 100mV
STEP
OVERDRIVE = 5mV
= 10pF
C
= 10pF
LOAD
CAPACITANCE IS ≈ 3.5pF
C
LOAD
C
= 10pF
LOAD
STEP SIZE = 800mV
400mV
FALLING EDGE t
200mV
PDHL
FALLING OUTPUT t
PDHL
100mV
RISING EDGE t
PDLH
RISING OUTPUT t
PDLH
0
0
50
100 125
–50 –25
0
25
75
2.5k
4.4
4.8
5.0
5.2
5.4
5.6
0
500
1k
1.5k
2k
3k
4.6
SOURCE RESISTANCE (Ω)
POSITIVE SUPPLY VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
1016 G06
1016 G05
1016 G04
Output Low Voltage (VOL) vs
Output Sink Current
Output High Voltage (VOH) vs
Output Source Current
Latch Set-Up Time vs
Temperature
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
6
4
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
V
I
= ± 5V
OUT
V
V
= ± 5V
IN
V
V
= ± 5V
IN
S
S
S
= 0V
= 30mV
= –30mV
T
= 125°C
J
2
T
= –55°C
J
T
= 25°C
J
0
T
= 25°C
J
T
= –55°C
J
–2
–4
–6
T
4
= 125°C
J
50
100 125
–50 –25
0
25
75
0
2
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
JUNCTION TEMPERATURE (°C)
OUTPUT SINK CURRENT (mA)
OUTPUT SOURCE CURRENT (mA)
1016 G07
1016 G08
1016 G09
4
LT1016
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Negative Supply Current vs
Temperature
Positive Supply Current vs
Positive Supply Voltage
Positive Supply Current vs
Switching Frequency
50
45
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
6
5
4
3
2
1
0
V– = 0V
T
= 125°C
= 25°C
= –55°C
V
I
= ± 5V
OUT
J
S
V
OUT
= 60mV
= 0
IN
T
T
J
I
= 0
J
T
= 25°C
J
T
= 125°C
J
V
V
OUT
= ± 5V
S
= ± 50mV
IN
T
= –55°C
J
I
= 0
0
0
1
10
SWITCHING FREQUENCY (MHz)
100
0
4
6
7
50
100 125
1
2
3
5
8
–50 –25
0
25
75
SUPPLY VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
1016 G12
1016 G11
1016 G10
Common Mode Rejection vs
Frequency
Positive Common Mode Limit vs
Temperature
Negative Common Mode Limit vs
Temperature
120
110
100
90
6
5
4
3
2
1
0
2
1
V
V
J
= ± 5V
IN
= 25°C
V
= ± 5V*
S
S
V
S
= SINGLE 5V SUPPLY
= 2V
P-P
T
0
*SEE APPLICATION INFORMATION
FOR COMMON MODE LIMIT WITH
VARYING SUPPLY VOLTAGE.
80
–1
–2
–3
–4
70
60
*SEE APPLICATION INFORMATION
FOR COMMON MODE LIMIT WITH
VARYING SUPPLY VOLTAGE.
50
V
S
= ± 5V*
40
10k
100k
1M
10M
50
100 125
–50 –25
0
25
75
50
100 125
–50 –25
0
25
75
FREQUENCY (Hz)
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
1016 G13
1016 G14
1016 G15
LATCH Pin Threshold vs
Temperature
LATCH Pin Current* vs
Temperature
2.6
2.2
1.8
1.4
1.0
0.6
0.2
300
250
200
150
100
50
V
= ± 5V
V
= ± 5V
S
S
V
= 0V
LATCH
OUTPUT LATCHED
OUTPUT UNAFFECTED
*CURRENT COMES OUT OF
LATCH PIN BELOW THRESHOLD
0
50
100 125
–50 –25
0
25
75
50
100 125
–50 –25
0
25
75
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
1016 G16
1016 G17
5
LT1016
W U U
U
APPLICATIO S I FOR ATIO
Input capacitance is typically 3.5pF. This is measured by
inserting a 1k resistor in series with the input and measur-
ing the resultant change in propagation delay.
Common Mode Considerations
The LT1016 is specified for a common mode range of
–3.75V to 3.5V with supply voltages of ±5V. A more
general consideration is that the common mode range is
1.25V above the negative supply and 1.5V below the
positive supply, independent of the actual supply voltage.
The criteria for common mode limit is that the output still
responds correctly to a small differential input signal.
Either input may be outside the common mode limit (up to
thesupplyvoltage)aslongastheremaininginputiswithin
the specified limit, and the output will still respond cor-
rectly. Thereisoneconsideration, however, forinputsthat
exceed the positive common mode limit. Propagation
delay will be increased by up to 10ns if the signal input is
morepositivethantheuppercommonmodelimitandthen
switches back to within the common mode range. This
effect is not seen for signals more negative than the lower
common mode limit.
LATCH Pin Dynamics
The LATCH pin is intended to retain input data (output
latched) when the LATCH pin goes high. This pin will float
to a high state when disconnected, so a flowthrough
condition requires that the LATCH pin be grounded. To
guarantee data retention, the input signal must be valid at
least 5ns before the latch goes high (setup time) and must
remain valid at least 3ns after the latch goes high (hold
time). When the latch goes low, new data will appear at the
output in approximately 8ns to 10ns. The LATCH pin is
designed to be driven with TTL or CMOS gates. It has no
built-in hysteresis.
Measuring Response Time
The LT1016 is able to respond quickly to fast low level
signals because it has a very high gain-bandwidth product
(ª50GHz), even at very high frequencies. To properly
measure the response of the LT1016 requires an input
signal source with very fast rise times and exceptionally
cleansettlingcharacteristics.Thislastrequirementcomes
about because the standard comparator test calls for an
input step size that is large compared to the overdrive
amplitude. Typical test conditions are 100mV step size
with only 5mV overdrive. This requires an input signal that
settles to within 1% (1mV) of final value in only a few
nanoseconds with no ringing or “long tailing.” Ordinary
high speed pulse generators are not capable of generating
such a signal, and in any case, no ordinary oscilloscope is
capable of displaying the waveform to check its fidelity.
Some means must be used to inherently generate a fast,
clean edge with known final value.
Input Impedance and Bias Current
Input bias current is measured with the output held at
1.4V. As with any simple NPN differential input stage, the
LT1016 bias current will go to zero on an input that is low
and double on an input that is high. If both inputs are less
than 0.8V above V–, both input bias currents will go to
zero. If either input exceeds the positive common mode
limit, input bias current will increase rapidly, approaching
several milliamperes at VIN = V+.
Differential input resistance at zero differential input
voltage is about 10kW, rapidly increasing as larger DC
differentialinputsignalsareapplied. Commonmodeinput
resistance is about 4MW with zero differential input
voltage. Withlargedifferentialinputsignals, thehighinput
will have an input resistance of about 2MW and the low
input greater than 20MW.
6
LT1016
W U U
APPLICATIO S I FOR ATIO
U
The circuit shown in Figure 1 is the best electronic means
ofgeneratingaknownfast,cleansteptotestcomparators.
It uses a very fast transistor in a common base configura-
tion. The transistor is switched “off” with a fast edge from
the generator and the collector voltage settles to exactly
0V in just a few nanoseconds. The most important feature
of this circuit is the lack of feedthrough from the generator
to the comparator input. This prevents overshoot on the
comparator input that would give a false fast reading on
comparator response time.
initslinearregion, afeaturenootherhighspeedcompara-
tor has. Additionally, output stage switching does not
appreciablychangepowersupplycurrent,furtherenhanc-
ing stability. These features make the application of the
50GHz gain-bandwidth LT1016 considerably easier than
other fast comparators. Unfortunately, laws of physics
dictate that the circuit environment the LT1016 works in
mustbeproperlyprepared.Theperformancelimitsofhigh
speed circuitry are often determined by parasitics such as
stray capacitance, ground impedance and layout. Some of
these considerations are present in digital systems where
designers are comfortable describing bit patterns and
memory access times in terms of nanoseconds. The
LT1016 can be used in such fast digital systems and
Figure 2 shows just how fast the device is. The simple test
circuit allows us to see that the LT1016’s (Trace B)
response to the pulse generator (Trace A) is as fast as a
TTL inverter (Trace C) even when the LT1016 has only
millivolts of input signal! Linear circuits operating with
this kind of speed make many engineers justifiably wary.
Nanosecond domain linear circuits are widely associated
with oscillations, mysterious shifts in circuit characteris-
tics, unintendedmodesofoperationandoutrightfailureto
function.
To adjust this circuit for exactly 5mV overdrive, V1 is
adjusted so that the LT1016 output under test settles to
1.4V (in the linear region). Then V1 is changed –5V to set
overdrive at 5mV.
The test circuit shown measures low to high transition on
the “+” input. For opposite polarity transitions on the
output, simply reverse the inputs of the LT1016.
High Speed Design Techniques
AsubstantialamountofdesignefforthasmadetheLT1016
relatively easy to use. It is much less prone to oscillation
and other vagaries than some slower comparators, even
with slow input signals. In particular, the LT1016 is stable
5V 0.01µF**
0V
–100mV
25Ω
Q
Q
10 SCOPE PROBE
IN
+
–
(C ≈ 10pF)
LT1016
L
130Ω
0.1µF
25Ω
10k
V1†
10 SCOPE PROBE
(C ≈ 10pF)
IN
2N3866
PULSE
IN
10Ω
–5V
0V
–3V
0.01µF
50Ω
400Ω
750Ω
–5V
* SEE TEXT FOR CIRCUIT EXPLANATION
** TOTAL LEAD LENGTH INCLUDING DEVICE PIN.
SOCKET AND CAPACITOR LEADS SHOULD BE
LESS THAN 0.5 IN. USE GROUND PLANE
1016 F01
†
(V + OVERDRIVE) • 1000
OS
Figure 1. Response Time Test Circuit
7
LT1016
W U U
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APPLICATIO S I FOR ATIO
Other common problems include different measurement
results using various pieces of test equipment, inability to
make measurement connections to the circuit without
inducing spurious responses and dissimilar operation
between two “identical” circuits. If the components used
in the circuit are good and the design is sound, all of the
above problems can usually be traced to failure to provide
a proper circuit “environment.” To learn how to do this
requires studying the causes of the aforementioned
difficulties.
devicesconnectedtoanunbypassedsupplycan“commu-
nicate” through the finite supply impedances, causing
erratic modes. Bypass capacitors furnish a simple way to
eliminate this problem by providing a local reservoir of
energy at the device. The bypass capacitor acts like an
electrical flywheel to keep supply impedance low at high
frequencies. The choice of what type of capacitors to use
for bypassing is a critical issue and should be approached
carefully. An unbypassed LT1016 is shown responding to
a pulse input in Figure 3. The power supply the LT1016
sees at its terminals has high impedance at high fre-
quency. This impedance forms a voltage divider with the
LT1016, allowing the supply to move as internal condi-
tions in the comparator change. This causes local feed-
back and oscillation occurs. Although the LT1016
responds to the input pulse, its output is a blur of 100MHz
oscillation. Always use bypass capacitors.
By far the most common error involves power supply
bypassing. Bypassingisnecessarytomaintainlowsupply
impedance. DC resistance and inductance in supply wires
and PC traces can quickly build up to unacceptable levels.
This allows the supply line to move as internal current
levels of the devices connected to it change. This will
almost always cause unruly operation. In addition, several
TEST CIRCUIT
7404
TRACE A
5V/DIV
PULSE
GENERATOR
1k
OUTPUTS
10Ω
+
TRACE B
5V/DIV
LT1016
–
TRACE C
5V/DIV
V
REF
10ns/DIV
1016 F02
Figure 2. LT1016 vs a TTL Gate
2V/DIV
100ns/DIV
1016 F03
Figure 3. Unbypassed LT1016 Response
8
LT1016
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APPLICATIO S I FOR ATIO
U
probleminhighspeedcircuitsandcanbequiteconfusing.
It is not due to suspension of natural law, but is traceable
to a grossly miscompensated or improperly selected
oscilloscope probe. Use probes that match your
oscilloscope’sinputcharacteristicsandcompensatethem
properly.Figure6showsanotherprobe-inducedproblem.
Here, the amplitude seems correct but the 10ns response
time LT1016 appears to have 50ns edges! In this case, the
probe used is too heavily compensated or slow for the
oscilloscope. Never use 1¥ or “straight” probes. Their
bandwidthis20MHzorlessandcapacitiveloadingishigh.
Check probe bandwidth to ensure it is adequate for
the measurement. Similarly, use an oscilloscope with
adequate bandwidth.
In Figure 4 the LT1016’s supplies are bypassed, but it still
oscillates. In this case, the bypass units are either too far
from the device or are lossy capacitors. Use capacitors
with good high frequency characteristics and mount them
as close as possible to the LT1016. An inch of wire
between the capacitor and the LT1016 can cause prob-
lems. If operation in the linear region is desired, the
LT1016 must be over a ground plate with good RF bypass
capacitors (≥0.01mF) having lead lengths less than 0.2
inches. Do not use sockets.
In Figure 5 the device is properly bypassed but a new
problem pops up. This photo shows both outputs of the
comparator. Trace A appears normal, but Trace B shows
an excursion of almost 8V—quite a trick for a device
running from a 5V supply. This is a commonly reported
2V/DIV
1016 F04
100ns/DIV
Figure 4. LT1016 Response with Poor Bypassing
TRACE A
2V/DIV
1V/DIV
TRACE B
2V/DIV
1016 F05
10ns/DIV
1016 F06
50ns/DIV
Figure 5. Improper Probe Compensation Causes
Seemingly Unexplainable Amplitude Error
Figure 6. Overcompensated or Slow Probes
Make Edges Look Too Slow
9
LT1016
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APPLICATIO S I FOR ATIO
In Figure 7 the probes are properly selected and applied power supplies. The inductance created by a long device
but the LT1016’s output rings and distorts badly. In this ground lead permits mixing of ground currents, causing
case, the probe ground lead is too long. For general undesired effects in the device. The solution here is
purpose work most probes come with ground leads about simple. KeeptheLT1016’sgroundpinconnectionasshort
six inches long. At low frequencies this is fine. At high (typically 1/4 inch) as possible and run it directly to a low
speed, the long ground lead looks inductive, causing the impedance ground. Do not use sockets.
ringing shown. High quality probes are always supplied
Figure 9 addresses the issue of the “low impedance
with some short ground straps to deal with this problem.
ground,” referred to previously. In this example, the
Some come with very short spring clips which fix directly
output is clean except for chattering around the edges.
to the probe tip to facilitate a low impedance ground
This photograph was generated by running the LT1016
connection. For fast work, the ground connection to the
without a “ground plane.” A ground plane is formed by
probe should not exceed one inch in length. Keep the
using a continuous conductive plane over the surface of
probe ground connection as short as possible.
the circuit board. The only breaks in this plane are for the
Figure 8 shows the LT1016’s output (Trace B) oscillating circuit’snecessarycurrentpaths.Thegroundplaneserves
near 40MHz as it responds to an input (Trace A). Note that two functions. Because it is flat (AC currents travel along
the input signal shows artifacts of the oscillation. This the surface of a conductor) and covers the entire area of
exampleiscausedbyimpropergroundingofthecompara- the board, it provides a way to access a low inductance
tor. In this case, the LT1016’s GND pin connection is groundfromanywhereontheboard.Also,itminimizesthe
one inch long. The ground lead of the LT1016 must be as effects of stray capacitance in the circuit by referring them
short as possible and connected directly to a low imped- to ground. This breaks up potential unintended and harm-
ance ground point. Any substantial impedance in the ful feedback paths. Always use a ground plane with the
LT1016’s ground path will generate effects like this. The LT1016 when input signal levels are low or slow moving.
reason for this is related to the necessity of bypassing the
1V/DIV
1016 F07
20ns/DIV
Figure 7. Typical Results Due to Poor Probe Grounding
TRACE A
1V/DIV
TRACE B
2V/DIV
2V/DIV
1016 F08
100ns/DIV
1016 F09
100ns/DIV
Figure 9. Transition Instabilities Due to No Ground Plane
Figure 8. Excessive LT1016 Ground Path
Resistance Causes Oscillation
10
LT1016
W U U
APPLICATIO S I FOR ATIO
U
“Fuzz” on the edges is the difficulty in Figure 10. This
condition appears similar to Figure 10, but the oscillation
is more stubborn and persists well after the output has
gone low. This condition is due to stray capacitive feed-
back from the outputs to the inputs. A 3kW input source
impedance and 3pF of stray feedback allowed this oscilla-
tion. The solution for this condition is not too difficult.
Keep source impedances as low as possible, preferably 1k
orless.Routeoutputandinputpinsandcomponentsaway
from each other.
source resistance and 10pF to ground gives a 20ns time
constant—significantly longer than the LT1016’s
response time. Keep source impedances low and mini-
mize stray input capacitance to ground.
Figure 12 shows another capacitance related problem.
Here the output does not oscillate, but the transitions are
discontinuous and relatively slow. The villain of this
situation is a large output load capacitance. This could be
caused by cable driving, excessive output lead length or
the input characteristics of the circuit being driven. In
most situations this is undesirable and may be eliminated
by buffering heavy capacitive loads. In a few circum-
stances it may not affect overall circuit operation and is
tolerable. Consider the comparator’s output load
characteristics and their potential effect on the circuit. If
necessary, buffer the load.
The opposite of stray-caused oscillations appears in
Figure 11. Here, the output response (Trace B) badly lags
the input (Trace A). This is due to some combination of
highsourceimpedanceandstraycapacitancetogroundat
the input. The resulting RC forces a lagged response at the
input and output delay occurs. An RC combination of 2k
2V/DIV
1016 F10
50ns/DIV
Figure 10. 3pF Stray Capacitive Feedback
with 3kW Source Can Cause Oscillation
TRACE A
2V/DIV
2V/DIV
TRACE B
2V/DIV
1016 F11
10ns/DIV
1016 F12
100ns/DIV
Figure 11. Stray 5pF Capacitance from
Input to Ground Causes Delay
Figure 12. Excessive Load Capacitance Forces Edge Distortion
11
LT1016
W U U
U
APPLICATIO S I FOR ATIO
Another output-caused fault is shown in Figure 13. The
output transitions are initially correct but end in a ringing
condition. The key to the solution here is the ringing. What
is happening is caused by an output lead that is too long.
The output lead looks like an unterminated transmission
line at high frequencies and reflections occur. This ac-
counts for the abrupt reversal of direction on the leading
edge and the ringing. If the comparator is driving TTL this
may be acceptable, but other loads may not tolerate it. In
this instance, the direction reversal on the leading edge
might cause trouble in a fast TTL load. Keep output lead
lengths short. If they get much longer than a few inches,
terminate with a resistor (typically 250W to 400W).
200ns-0.01% Sample-and-Hold Circuit
Figure 14’s circuit uses the LT1016’s high speed to
improve upon a standard circuit function. The 200ns
acquisition time is well beyond monolithic sample-and-
hold capabilities. Other specifications exceed the best
commercial unit’s performance. This circuit also gets
around many of the problems associated with standard
sample-and-holdapproaches,includingFETswitcherrors
and amplifier settling time. To achieve this, the LT1016’s
high speed is used in a circuit which completely abandons
traditional sample-and-hold methods.
Important specifications for this circuit include:
Acquisition Time
Common Mode Input Range
Droop
<200ns
±3V
1mV/ms
2mV
Hold Step
Hold Settling Time
Feedthrough Rejection
15ns
1V/DIV
>>100dB
When the sample-and-hold line goes low, a linear ramp
starts just below the input level and ramps upward. When
the ramp voltage reaches the input voltage, A1 shuts off
the ramp, latches itself off and sends out a signal indicat-
ing sampling is complete.
1016 F13
50ns/DIV
Figure 13. Lengthy, Unterminated Output Lines
Ring from Reflections
5V
390Ω
5.1k
470Ω
100Ω
1k
1N4148
100Ω
1k
DELAY
COMP
1N4148
Q2
Q1
2N5160
8pF
2N2907A
–
+
Q7
5.1k
1.5k
0.1µF
A1
2N5486
LT1016
NOW
1000pF
(POLYSTYRENE)
Q3
2N2369
SN7402
SN7402
LATCH
Q6
2N2222
220Ω
INPUT
±3V
Q5
2N2222
390Ω
820Ω
1N4148
1.5k
1.5k
SN7402
LT1009
2.5V
100Ω
300Ω
Q4
2N2907A
SAMPLE-HOLD
COMMAND (TTL)
–5V
1016 F14
–15V
OUTPUT
Figure 14. 200ns Sample-and-Hold
12
LT1016
W U U
APPLICATIO S I FOR ATIO
U
1.8ms, 12-Bit A/D Converter
Togetfasterconversiontime,theclockiscontrolledbythe
window comparator monitoring the DAC input summing
junction. Additionally, the DMOS FET clamps the DAC
output to ground at the beginning of each clock cycle,
shortening DAC settling time. After the fifth bit is con-
verted, the clock runs at maximum speed.
The LT1016’s high speed is used to implement a very fast
12-bit A/D converter in Figure 15. The circuit is a modified
form of the standard successive approximation approach
and is faster than most commercial SAR 12-bit units. In
thisarrangementthe2504successiveapproximationreg-
ister (SAR), A1 and C1 test each bit, beginning with the
MSB, and produce a digital word representing VIN’s value.
5V
2.5k
0.01µF
5V
–5V
–5V
150Ω 620Ω*
620Ω*
V
IN
0V TO 10V
2.5k**
1k
–
+
1k
C1
LT1016
1000pF
10V
LT1021
10V
5V
NC
Q3
10k** 10k
15V
20
–15V
17
14
15
–
13
GND
19
1k
+
+
–
V
R
V
R
I
V
V
O
0.01µF
16
18
I
Q1 Q2
–15V
COMP
AM6012
O
SD210
5V
150k
15k
PARALLEL
DIGITAL
DATA
5V
9
LSB
MSB
24
27k
–15V
OUTPUT
Q6
+
5V
V
6
11
AM2504
D
74121
Q
7
13
Q4
CLK
GND
12
E
S
CC
3
IN B
5
4
150k
1
14
3
Q5
1/4 74S00
STATUS
5V
5V
1k
–
NC
C3
LT1016
0.1µF 10Ω
+
1/4 74S00
1/4 74S08
1/4 74S08
D
Q
–5V
5V
1/2 74S74
CLK
–5V
1k
PRS
PRS
+
Q1 TO Q5 RCA CA3127 ARRAY
1N4148
C2
LT1016
1/2 74S74
RST
NC
–
HP5082-2810
1/6 74S04 1/6 74S04
CLOCK
*1% FILM RESISTOR
**PRECISION 0.01%; VISHAY S-102
0.1µF
10Ω
–5V
CONVERT
COMMAND
1016 F15
7.4MHz
Figure 15. 12-Bit 1.8ms SAR A-to-D
13
LT1016
U
TYPICAL APPLICATIO S
Voltage Controlled Pulse Width Generator
Single Supply Precision RC 1MHz Oscillator
5V
FULL-SCALE
≈6.2k*
LM385
1.23V
CALIBRATION
500Ω
2N3906
1k
5V
25Ω
2N3906
100pF
2k
100pF
1000pF
5V
2.7k
Q
–
+
LT1016
Q
LT1016
–5V
+
START
GND
LATCH
V
= 0V TO 2.5V
–
5V
IN
C
B
Q
EXT
Q
–
V
74121
A1
1k
10k
1%
1N914
5pF
2N3906
5V
74HC04
0µs TO 2.5µs
(MINIMUM
10k
470pF
WIDTH ≈ 0.05µs)
10k
1%
OUTPUTS
1%
8.2k
* SELECT OR TRIM FOR f = 1.00MHz
1016 AI02
1016 AI01
–5V
50MHz Fiber Optic Receiver with Adaptive Trigger
5V
3k
10k
–
–
0.005µF
22M
+
–
LT1097
LT1220
500pF
+
+
LT1223
330Ω
1k
22M
0.005µF
0.1µF
+
–
50Ω
OUTPUT
LT1016
= HP 5082-4204
NPN = 2N3904
PNP = 2N3906
3k
–5V
1016 AI03
14
LT1016
U
TYPICAL APPLICATIO S
1MHz to 10MHz Crystal
Oscillator
18ns Fuse with Voltage Programmable Trip Point
Q1
2N3866
28V
5V
2k
1MHz TO 10MHz
CRYSTAL
1k*
9k*
330Ω
2.4k
+
–
Q2
2N2369
–5V
10Ω
CARBON
A1
5V
LT1193
+
9k*
1k*
V
Q
+
900Ω
200Ω
FB
LT1016
2k
OUTPUT
–
33pF
300Ω
Q
CALIBRATE
GND
LATCH
+
–
A2
–
V
LT1016
1k
TRIP SET
0mA TO 250mA = 0V TO 2.5V
2k
L
* = 1% FILM RESISTOR
A1 AND A2 USE ±5V SUPPLIES
0.068µF
RESET (NORMALLY OPEN)
LOAD
1016 AI04
1016 AI05
U
APPE DIX A
About Level Shifts
The TTL output of the LT1016 will interface with many
circuitsdirectly.Manyapplications,however,requiresome
form of level shifting of the output swing. With LT1016
based circuits this is not trivial because it is desirable to
maintain very low delay in the level shifting stage. When
designing level shifters, keep in mind that the TTL output
of the LT1016 is a sink-source pair (Figure A1) with good
ability to drive capacitance (such as feedforward capaci-
tors).
transistor’s supplies. This 3ns delay stage is ideal for
driving FET switch gates. Q1, a gated current source,
switches the Baker-clamped output transistor, Q2. The
heavy feedforward capacitor from the LT1016 is the key to
lowdelay, providingQ2’sbasewithnearlyidealdrive. This
capacitor loads the LT1016’s output transition (Trace A,
FigureA4),butQ2’sswitchingisclean(TraceB,FigureA4)
with 3ns delay on the rise and fall of the pulse.
Figure A5 is similar to Figure A2 except that a sink
transistor has replaced the Schottky diode. The two emit-
ter-followers drive a power MOSFET which switches 1A at
15V. Most of the 7ns to 9ns delay in this stage occurs in
the MOSFET and the 2N2369.
Figure A2 shows a noninverting voltage gain stage with a
15V output. When the LT1016 switches, the base-emitter
voltages at the 2N2369 reverse, causing it to switch very
quickly. The 2N3866 emitter-follower gives a low imped-
ance output and the Schottky diode aids current sink
capability.
When designing level shifters, remember to use transis-
tors with fast switching times and high fTs. To get the kind
of results shown, switching times in the ns range and fTs
approaching 1GHz are required.
Figure A3 is a very versatile stage. It features a bipolar
swing that may be programmed by varying the output
15
LT1016
U
APPE DIX A
15V
+V
1k
2N2369
2N3866
+
–
HP5082-2810
OUTPUT = 0V TO
TYPICALLY 3V TO 4V
LT1016
OUTPUT
1k
1k
NONINVERTING
VOLTAGE GAIN
12pF
1016 FA01
LT1016 OUTPUT
t
t
= 4ns
= 5ns
RISE
FALL
1016 fFA02
Figure A1
Figure A2
5V
+
–
INPUT
LT1016
4.7k
430Ω
1N4148
5V
(TYP)
Q1
2N2907
1000pF
330Ω
HP5082-2810
OUTPUT TRANSISTOR SUPPLIES
(SHOWN IN HEAVY LINES)
CAN BE REFERENCED ANYWHERE
BETWEEN 15V AND –15V
5V
0.1µF
820Ω
OUTPUT
–10V
Q2
2N2369
820Ω
INVERTING VOLTAGE GAIN—BIPOLAR SWING
–10V
(TYP)
t
t
= 3ns
= 3ns
RISE
FALL
1016 FA03
Figure A3
15V
1k
TRACE A
2V/DIV
R
L
2N2369
2N3866
+
POWER FET
TRACE B
10V/DIV
(INVERTED)
LT1016
1k
2N5160
–
1k
12pF
NONINVERTING
VOLTAGE GAIN
t
t
= 7ns
= 9ns
RISE
FALL
1016 FA04
5ns/DIV
1016 FA05
Figure A4. Figure A3’s Waveforms
Figure A5
16
LT1016
W
W
SI PLIFIED SCHE ATIC
+
17
LT1016
U
PACKAGE DESCRIPTIO
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
8
7
6
5
0.255 ± 0.015*
(6.477 ± 0.381)
1
2
4
3
0.130 ± 0.005
0.300 – 0.325
0.045 – 0.065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
0.125
0.020
(0.508)
MIN
(3.175)
MIN
+0.035
0.325
–0.015
0.018 ± 0.003
(0.457 ± 0.076)
0.100
(2.54)
BSC
+0.889
8.255
(
)
–0.381
N8 1098
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
18
LT1016
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
5
8
6
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
SO8 1298
1
3
4
2
0.010 – 0.020
(0.254 – 0.508)
45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LT1016
W U U
U
APPLICATIO S I FOR ATIO
1Hz to 10MHz V-to-F Converter
A1’s 68pF feedback capacitor. The amplifier controls the
circuit’s output pulse generator, closing feedback loop
around the integrating amplifier. To maintain the sum-
ming node at zero, the pulse generator runs at a frequency
that permits enough charge pumping to offset the input
signal. Thus, the output frequency is linearly related to the
input voltage.
The LT1016 and the LT1122 FET input amplifier combine
to form a high speed V-to-F converter in Figure 16. A
variety of techniques is used to achieve a 1Hz to 10MHz
output. Overrange to 12MHz (VIN = 12V) is provided. This
circuit’sdynamicrangeis140dB,orsevendecades,which
is wider than any commercially available unit. The 10MHz
full-scale frequency is 10 times faster than monolithic
V-to-F’snowavailable. Thetheoryofoperationisbasedon
the identity Q = CV.
Totrimthiscircuit,apply6.000Vattheinputandadjustthe
2kW pot for 6.000MHz output. Next, excite the circuit with
a 10.000V input and trim the 20k resistor for 10.000MHz
output. Repeat these adjustments until both points are
fixed. Linearity of the circuit is 0.03%, with full-scale drift
of 50ppm/∞C. The LTC1050 chopper op amp servos the
integrator’snoninvertinginputandeliminatestheneedfor
Each time the circuit produces an output pulse, it feeds
back a fixed quantity of charge, Q, to a summing node, S.
The circuit’s input furnishes a comparison current at the
summing node. This difference current is integrated in
a zero trim. Residual zero point error is 0.05Hz/∞C.
OUTPUT
INPUT
0V TO 10V
1Hz TO 10MHz
5V REF
15V
15V
15pF
(POLYSTYRENE)
Q1
–15V
+
–
A4
LT1010
A3
LT1006
4.7µF
470Ω
Q2
15V
0.1µF
2k
5V
6.8Ω
6MHz
TRIM
68pF
1.2k
10k*
LM134
100k*
5V
–5V
–
+
8
100k*
A1
+
–
LT1122
A2
LT1016
LT1034-1.2V
LT1034-2.5V
100Ω
10k
–5V
150pF
2.2M*
Q3
5pF
1k
5V
Q4
0.02µF
–
36k
1k
10M
= 2N2369
= 74HC14
LTC1050
+
+
20k
10µF
10MHz
TRIM
* = 1% METAL FILM/10ppm/°C
BYPASS ALL ICs WITH 2.2µF ON
EACH SUPPLY DIRECTLY AT PINS
–5V
1016 F16
Figure 16. 1Hz to 10MHz V-to-F Converter. Linearity is Better Than 0.03% with 50ppm/∞C Drift
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sn1016 1016fcs LT/TP 0601 1.5K REV C • PRINTED IN USA
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
„ LINEAR TECHNOLOGY CORPORATION 1991
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