LT1112AMJ8 [Linear]
Dual/Quad Low Power Precision, Picoamp Input Op Amps; 双/四通道，低功耗精密，皮安输入运算放大器
| 型号： | LT1112AMJ8 |
| 厂家： | 
Linear |
| 描述： | Dual/Quad Low Power Precision, Picoamp Input Op Amps |
| 文件： | 总12页 (文件大小：370K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1112/LT1114
Dual/Quad Low Power
Precision, Picoamp Input Op Amps
U
DESCRIPTIO
EATURE
S8 Package – Standard Pinout
Offset Voltage – Prime Grade: 60µV Max
Offset Voltage – Low Cost Grade
(Including Surface Mount Dual/Quad): 75µV Max
Offset Voltage Drift: 0.5µV/°C Max
Input Bias Current: 250pA Max
S
F
■
■
■
TheLT1112dualandLT1114quadopampsachieveanew
standardincombininglowcostandoutstandingprecision
specifications.
The performance of the selected prime grades matches or
exceeds competitive devices. In the design of the LT1112/
LT1114 however, particular emphasis has been placed on
optimizing performance in the low cost plastic and SO
packages. For example, the 75µV maximum offset voltage
in these low cost packages is the lowest on any dual or
quad non-chopper op amp.
■
■
■
■
■
■
■
■
■
0.1Hz to 10Hz Noise: 0.3µVP-P, 2.2pAP-P
Supply Current per Amplifier: 400µA Max
CMRR: 120dB Min
Voltage Gain: 1 Million Min
Guaranteed Specs with ±1.0V Supplies
Guaranteed Matching Specifications
LT1114 in Narrow Surface Mount Package
The LT1112/LT1114 also provide a full set of matching
specifications, facilitating their use in such matching
dependent applications as two and three op amp instru-
mentation amplifiers.
O U
PPLICATI
A
S
Another set of specifications is furnished at ±1V supplies.
This, combined with the low 320µA supply current per
amplifier, allows the LT1112/LT1114 to be powered by
two nearly discharged AA cells.
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Picoampere/Microvolt Instrumentation
Two and Three Op Amp Instrumentation Amplifers
Thermocouple and Bridge Amplifiers
Low Frequency Active Filters
Photo Current Amplifiers
Battery-Powered Systems
Protected by U.S. Patents 4,575,685; 4,775,884 and 4,837,496
Distribution of Input Offset Voltage
(In All Packages)
Dual Output, Buffered Reference (On Single 3V Supply)
30
25
20
15
3V
TOTAL SUPPLY CURRENT = 700µA
V
S
T
A
= ±15V
= 25°C
2V REFERENCE: SOURCES 1.7mA, SINKS 5mA
R
X
15k
OPTIONAL R = 300Ω INCREASES SOURCE
X
CURRENT TO 5mA
0.765V REFERENCE: SOURCES 5mA,
SINKS 0.5mA
TEMPERATURE COEFFICIENT LIMITED
BY REFERENCE = 20ppm/°C
–
2
3
8
1
1/2 LT1112
+
2.000V
MINIMUM SUPPLY = 2.7V
75k
0.1%
10
5
LT1004-1.2
–
6
5
0
7
0.765V
1/2 LT1112
+
10
INPUT OFFSET VOLTAGE (µV)
50
70
–70 –50 –30 –10
30
4
LT1112/14 • TA02
46.4k
0.1%
LT1112/14 • TA01
1
LT1112/LT1114
W W W
U
ABSOLUTE AXI U RATI GS
Operating Temperature Range
Supply Voltage ..................................................... ±20V
Differential Input Current (Note 1) ..................... ±10mA
Input Voltage (Equal to Supply Voltage) ............... ±20V
Output Short-Circuit Duration......................... Indefinite
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................ 300°C
LT1112AM/LT1112M
LT1114AM/LT1114M ...................... –55°C to 125°C
LT1112AC/LT1112C/LT1112S8
LT1114AC/LT1114C/LT1114S .......... –40°C to 85°C
W
U
/O
PACKAGE RDER I FOR ATIO
TOP VIEW
TOP VIEW
ORDER PART
ORDER PART
+
+
OUT A
–IN A
+IN A
1
2
3
4
8
7
6
5
V
OUT A
–IN A
+IN A
1
2
3
4
8
7
6
5
V
NUMBER
NUMBER
OUT B
–IN B
+IN B
OUT B
–IN B
+IN B
A
A
LT1112AMJ8
LT1112MJ8
LT1112ACN8
LT1112CN8
LT1112S8
B
B
–
–
V
V
J8 PACKAGE
N8 PACKAGE
S8 PACKAGE
8-LEAD PLASTIC SO
PART MARKING
1112
8-LEAD CERAMIC DIP 8-LEAD PLASTIC DIP
T
JMAX = 160°C, θJA = 100°C/W (J8)
TJMAX = 140°C, θJA = 130°C/W (N8)
TJMAX = 140°C, θJA = 190°C/W
TOP VIEW
TOP VIEW
ORDER PART
NUMBER
ORDER PART
NUMBER
OUT A
–IN A
+IN A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
OUT D
–IN D
+IN D
OUT D
–IN D
+IN D
14
13
12
11
10
9
OUT A
–IN A
+IN A
A
B
D
C
A
B
D
C
LT1114S
LT1114AMJ
LT1114MJ
LT1114ACN
LT1114CN
–
+
–
+
V
V
V
V
+IN C
–IN C
OUT C
+IN B
–IN B
OUT B
NC
+IN C
–IN C
OUT C
NC
+IN B
–IN B
OUT B
8
J PACKAGE
N PACKAGE
14-LEAD CERAMIC DIP 14-LEAD PLASTIC DIP
S PACKAGE
16-LEAD PLASTIC SO (NARROW)
TJMAX = 140°C, θJA = 150°C/W
TJMAX = 160°C, θJA = 80°C/W (J)
TJMAX = 140°C, θJA = 110°C/W (N)
ELECTRICAL CHARACTERISTICS
VS = ±15V, VCM = 0V, TA = 25°C, unless otherwise noted.
LT1112M/C/S8
LT1114M/C/S
LT1112AM/AC
LT1114AM/AC
SYMBOL PARAMETER
CONDITIONS (Note 2)
MIN
TYP MAX MIN
TYP MAX
UNITS
V
OS
Input Offset Voltage
20
40
60
110
25
45
75
130
µV
µV
V = ±1.0V
S
∆V
∆Time
Long Term Input Offset
Voltage Stability
0.3
0.3
µV/Mo
OS
I
Input Offset Current
Input Bias Current
Input Noise Voltage
50
180
±250
0.9
60
75
230
330
pA
pA
OS
B
LT1114S
I
±70
0.3
±80
±100 ±450
±280
pA
pA
LT1114S
e
0.1Hz to 10Hz (Note 9)
0.3
0.9
µV
P-P
n
2
LT1112/LT1114
ELECTRICAL CHARACTERISTICS
VS = ±15V, VCM = 0V, TA = 25°C, unless otherwise noted.
LT1112M/C/S8
LT1114M/C/S
LT1112AM/AC
LT1114AM/AC
SYMBOL PARAMETER
Input Noise Voltage Density
CONDITIONS (Note 2)
MIN
TYP MAX MIN
TYP MAX
UNITS
nV/√Hz
nV/√Hz
f = 10Hz (Note 9)
16
14
28
18
16
14
28
18
O
f = 1000Hz (Note 9)
O
i
Input Noise Current
0.1Hz to 10Hz
2.2
2.2
pA
P-P
n
Input Noise Current Density
f = 10Hz
f = 1000Hz
O
0.030
0.008
0.030
0.008
pA/√Hz
pA/√Hz
O
V
Input Voltage Range
±13.5 ±14.3
±13.5 ±14.3
V
dB
dB
V
CM
CMRR
PSRR
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Minimum Supply Voltage
V
= ±13.5V
120
116
136
126
115
114
136
126
CM
V = ±1.0V to ±20V
S
(Note 4)
±1.0
±1.0
R
Input Resistance
Differential Mode
Common Mode
IN
(Note 3)
20
50
800
15
40
700
MΩ
GΩ
A
V
Large-Signal Voltage Gain
V = ±12V, R = 10kΩ
1000
800
5000
1500
800
600
5000
1300
V/mV
V/mV
VOL
OUT
O
L
V = ±10V, R = 2kΩ
O
L
Output Voltage Swing
R = 10kΩ
±13.0 ±14.0
±11.0 ±12.4
±13.0 ±14.0
±11.0 ±12.4
V
V
L
R = 2kΩ
L
SR
Slew Rate
0.16
450
0.30
750
0.16
450
0.30
750
V/µs
GBW
Gain-Bandwidth Product
Supply Current per Amplifier
f = 10kHz
kHz
O
I
350
320
400
370
350
320
450
420
µA
µA
S
V = ±1.0V
S
Channel Separation
Offset Voltage Match
f = 10Hz
150
35
150
40
dB
O
∆V
(Note 5)
100
450
130
µV
OS
+
∆I
Noninverting Bias Current Match
(Notes 5, 6)
100
100
120
500
680
pA
pA
B
LT1114S
∆CMRR
∆PSRR
Common-Mode Rejection Match
Power Supply Rejection Match
(Notes 5, 7)
(Notes 5, 7)
117
114
136
130
113
112
136
130
dB
dB
ELECTRICAL CHARACTERISTICS
VS = ±15V, –55°C ≤ TA ≤ 125°C, unless otherwise noted.
LT1112MJ8
LT1114MJ
LT1112AMJ8
LT1114AMJ
SYMBOL PARAMETER
Input Offset Voltage
CONDITIONS (Note 2)
V = ±1.2V
MIN
TYP MAX MIN
TYP MAX
UNITS
V
●
●
35
60
120
220
45
70
150
260
µV
µV
OS
S
∆V
Average Input Offset Voltage Drift (Note 8)
●
0.15
0.5
0.20
0.75
µV/°C
OS
∆Temp
I
I
Input Offset Current
Input Bias Current
Input Voltage Range
●
●
●
●
●
80
400
100
500
pA
pA
V
OS
B
±150 ±600
±13.5 ±14.1
±170 ±700
±13.5 ±14.1
V
CM
CMRR
PSRR
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain
V
= ±13.5V
116
112
130
124
111
110
130
124
dB
dB
CM
V = ±1.2V to ±20V
S
A
V = ±12V, R = 10kΩ
V = ±10V, R = 2kΩ
●
●
500
200
2500
600
400
170
2500
500
V/mV
V/mV
VOL
O
O
L
L
3
LT1112/LT1114
ELECTRICAL CHARACTERISTICS
VS = ±15V, –55°C ≤ TA ≤ 125°C, unless otherwise noted.
LT1112MJ8
LT1114MJ
LT1112AMJ8
LT1114AMJ
SYMBOL PARAMETER
CONDITIONS (Note 2)
MIN
TYP MAX MIN
TYP MAX
UNITS
V
V
Output Voltage Swing
R = 10kΩ
●
●
●
●
●
●
●
●
±13.0 ±13.85
±13.0 ±13.85
OUT
L
SR
Slew Rate
0.12
0.22
380
55
0.12
0.22
380
70
V/µs
µA
I
Supply Current per Amplifier
Offset Voltage Match
460
200
0.7
530
240
1.0
S
∆V
(Note 5)
µV
OS
Offset Voltage Match Drift
Noninverting Bias Current Match
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
(Notes 5, 8)
(Notes 5, 6)
(Notes 5, 7)
(Notes 5, 7)
0.2
0.3
µV/°C
pA
+
∆I
150
130
126
750
170
130
126
850
B
∆CMRR
∆PSRR
112
109
106
106
dB
dB
ELECTRICAL CHARACTERISTICS
VS = ±15V, 0°C ≤ TA ≤ 70°C, unless otherwise noted.
LT1112ACN8
LT1114ACN
LT1112N8/S8
LT1114CN/S
TYP MAX
SYMBOL PARAMETER
Input Offset Voltage
CONDITIONS (Note 2)
MIN
TYP MAX MIN
UNITS
V
LT1112N8
●
●
●
27
35
50
100
125
175
30
45
65
125
150
210
µV
µV
µV
OS
LT1112S8, LT1114N/S
V = ±1.2V
S
∆V
∆Temp
Average Input Offset Voltage Drift LT1112N8
●
●
0.15
0.3
0.5
1.1
0.2
0.4
0.75
1.3
µV/°C
µV/°C
OS
(Note 8)
LT1112S8, LT1114N/S
I
Input Offset Current
●
●
60
220
70
90
290
420
pA
pA
OS
B
LT1114S
LT1114S
I
Input Bias Current
●
●
±80
±300
±90
±115 ±550
±350
pA
pA
V
Input Voltage Range
●
●
●
±13.5 ±14.2
±13.5 ±14.2
V
dB
dB
CM
CMRR
PSRR
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain
V
= ±13.5V
118
114
133
125
113
112
133
125
CM
V = ±1.2V to ±20V
S
A
VOL
V = ±12V, R = 10kΩ
V = ±10V, R = 2kΩ
●
●
800
500
4000
1300
650
400
4000
1000
V/mV
V/mV
O
O
L
L
V
Output Voltage Swing
Slew Rate
R = 10kΩ
L
●
●
●
±13.0 ±13.9
±13.0 ±13.9
V
V/µs
µA
OUT
SR
0.14
0.27
370
0.14
0.27
370
I
Supply Current per Amplifier
440
500
S
∆V
OS
Offset Voltage Match
(Note 5)
LT1112N8
LT1112S8, LT1114N/S
●
●
45
55
170
220
55
70
210
270
µV
µV
Offset Voltage Match Drift
(Notes 5, 8)
LT1112N8
●
●
0.2
0.4
0.7
1.6
0.3
0.5
1.0
1.9
µV/°C
µV/°C
LT1112S8, LT1114N/S
+
∆I
Noninverting Bias Current Match
(Notes 5, 6)
●
●
120
530
135
160
620
880
pA
pA
B
LT1114S
∆CMRR
∆PSRR
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
(Notes 5, 7)
(Notes 5, 7)
●
●
114
110
134
128
109
108
134
128
dB
dB
4
LT1112/LT1114
ELECTRICAL CHARACTERISTICS
VS = ±15V, –40°C ≤ TA ≤ 85°C, (Note 10)
LT1112ACN8
LT1114ACN
LT1112N8/S8
LT1114CN/S
SYMBOL PARAMETER
Input Offset Voltage
CONDITIONS (Note 2)
MIN
TYP MAX MIN
TYP MAX
UNITS
V
LT1112N8
●
●
●
30
40
55
110
135
200
35
45
60
135
160
240
µV
µV
µV
OS
LT1112S8, LT1114N/S
V = ±1.2V
S
∆V
Average Input Offset Voltage Drift LT1112N8
LT1112S8, LT1114N/S
●
●
0.15
0.30
0.50
1.10
0.20
0.40
0.75
1.30
µV/°C
µV/°C
OS
∆Temp
I
Input Offset Current
●
●
70
330
85
400
600
pA
pA
OS
B
LT1114S
LT1114S
110
I
Input Bias Current
●
●
±110 ±500
±120 ±550
±150 ±800
pA
pA
V
Input Voltage Range
●
●
●
±13.5 ±14.1
±13.5 ±14.1
V
dB
dB
CM
CMRR
PSRR
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain
V
= ±13.5V
117
113
132
125
112
111
132
125
CM
V = ±1.2V to ±20V
S
A
V = ±12V, R = 10kΩ
●
●
700
400
3300
1100
600
300
3300
900
V/mV
V/mV
VOL
O
L
L
V = ±10V, R = 2kΩ
O
V
Output Voltage Swing
Slew Rate
R = 10kΩ
L
●
●
●
±13.0 ±13.85
±13.0 ±13.85
V
V/µs
µA
OUT
SR
0.13
0.24
370
0.13
0.24
370
I
Supply Current per Amplifier
450
510
S
∆V
Offset Voltage Match
(Note 5)
LT1112N8
●
●
50
60
180
230
60
70
225
270
µV
µV
OS
+
LT1112S8, LT1114N/S
Offset Voltage Match Drift
(Notes 5)
LT1112N8
LT1112S8, LT1114N/S
●
●
0.2
0.4
0.7
1.6
0.3
0.5
1.0
1.9
µV/°C
µV/°C
∆I
Noninverting Bias Current Match
(Notes 5, 6)
●
●
140
660
155
190
770
1300
pA
pA
B
LT1114S
∆CMRR
∆PSRR
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
(Notes 5, 7)
(Notes 5, 7)
●
●
113
110
133
127
109
107
133
127
dB
dB
The
●
range.
denotes specifications which apply over the operating temperature
Note 6: This parameter is the difference between two noninverting
input bias currents.
Note 1: Differential input voltages greater than 1V will cause excessive
current to flow through the input protection diodes unless limiting
resistance is used.
Note 2: Typical parameters are defined as the 60% yield of parameter
distributions of individual amplifiers; i.e., out of 100 LT1114s (or 100
LT1112s) typically 240 op amps (or 120) will be better than the indicated
specification.
Note 3: This parameter is guaranteed by design and is not tested.
Note 4: Offset voltage, supply current and power supply rejection ratio are
measured at the minimum supply voltage.
Note 5: Matching parameters are the difference between amplifiers A and
D and between B and C on the LT1114; between the two amplifiers on the
LT1112.
Note 7: ∆CMRR and ∆PSRR are defined as follows: (1) CMRR and
PSRR are measured in µV/V on the individual amplifiers. (2) The
difference is calculated between the matching sides in µV/V. (3) The
result is converted to dB.
Note 8: This parameter is not 100% tested.
Note 9: These parameters are not tested. More than 99% of the op
amps tested during product characterization have passed the
maximum limits. 100% passed at 1kHz.
Note 10: The LT1112/LT1114 are not tested and are not quality
assurance sampled at –40°C and at 85°C. These specifications are
guaranteed by design, correlation and/or inference from –55°C, 0°C,
25°C, 70°C and/or 125°C tests.
5
LT1112/LT1114
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Input Bias and Offset Current,
Noninverting Bias Current Match
vs Temperature
Input Bias Current Over
Common-Mode Range
Distribution of Input Bias Current
(In All Packages Except LT1114S)
150
100
50
30
20
10
0
200
100
0
V
T
= ±15V
= 25°C
INCM
V
T
= ±15V
= 25°C
S
A
R
S
A
+
= 800GΩ
∆I
B
I
OS
DEVICE WITH POSITIVE INPUT CURRENT
DEVICE WITH NEGATIVE INPUT CURRENT
I
(UNDERCANCELLED)
B
0
–50
–100
–150
–
I
(OVERCANCELLED)
B
–100
I
B
+
V
CM
V
= ±15V
S
–200
–75 –50 –25
0
25 50 75 100 125
–15
–5
0
5
10
15
–300
–100
0
100
200
300
–10
–200
TEMPERATURE (°C)
COMMON-MODE INPUT VOLTAGE (V)
INPUT BIAS CURRENT (pA)
LT1112/14 • TPC01
LT1112/14 • TPC02
LT1112/14 • TPC03
Drift with Temperature
LT1112N8/J8, LT1114J
Drift with Temperature
LT1112S8, LT1114N/S
Distribution of Offset Voltage at
VS = ±1.0V (In All Packages)
25
20
15
10
5
30
25
20
960 OP AMPS TESTED
240 LT1112S8
80 LT1114N
V = ±15V
S
850 OP AMPS TESTED
100 LT1112J8
165 LT1112N8
80 LT1114J
V = ±15V
S
T
= 25°C
A
40 LT1114S
15
10
5
20
15
10
5
0
0
0
–1.4
–0.6 –0.2 0.2
0.6 1.0 1.4
–1.0
0
0.2
–0.8 –0.6 –0.4 –0.2
0.4 0.6 0.8
–80 –60 –40 –20
0
20 40 60 80 100
OFFSET VOLTAGE DRIFT WITH TEMPERATURE (µV/°C)
INPUT OFFSET VOLTAGE (µV)
OFFSET VOLTAGE DRIFT WITH TEMPERATURE (µV/°C)
LT1112/14 • TPC05
LT1112/14 • TPC04
LT1112/14 • TPC06
Distribution of Offset Voltage
Match Drift (LT1112J8, LT1112N8,
LT1114J Packages)
Distribution of Offset Voltage
Match Drift (LT1112S8, LT1114N,
LT1114S Packages)
Distribution of Offset
Voltage Match
20
15
10
5
30
25
V
T
= ±15V
= 25°C
V
= ±15V
S
V = ±15V
S
364 PAIRS TESTED
S
A
342 PAIRS TESTED
25
20
15
10
5
20
15
10
5
0
0
0
0.4 0.6
OFFSET VOLTAGE MATCH DRIFT (µV/°C)
–0.8 –0.6 –0.4 –0.2
0
0.2
0.8
–1.6 –1.2 –0.8 –0.4
0
0.4 0.8 1.2 1.6
–100–80 –60 –40 –20
0
20 40 60 80 100
OFFSET VOLTAGE MATCH DRIFT (µV/°C)
∆V , OFFSET VOLTAGE MATCH (µV)
OS
LT1112/14 • TPC08
LT1112/14 • TPC09
LT1112/14 • TPC07
6
LT1112/LT1114
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Noise Spectrum
0.1Hz to 10Hz Noise
0.01Hz to 1Hz Noise
1000
100
10
V
= ±1V TO ±20V
= 25°C
S
A
V
T
= ±15V
= 25°C
V
T
= ±15V
= 25°C
S
A
S
A
T
CURRENT NOISE
VOLTAGE NOISE
1/f
CORNER
2.5Hz
1/f
CORNER
140Hz
1
1
10
100
1000
0
2
4
6
8
10
0
20
40
60
80
100
FREQUENCY (Hz)
TIME (SEC)
TIME (SEC)
LT1112/14 • TPC10
LT1112/14 • TPC11
LT1112/14 • TPC12
Long Term Stability of Three
Representative Units
Supply Current per Amplifier
vs Supply Voltage
Warm-Up Drift
6
4
3
2
1
0
600
500
400
300
200
V
T
= ±15V
= 25°C
V
T
= ±15V
= 25°C
S
A
S
A
2A
3A
2
2B
1A
3B
LT1112S8, LT1114N/S PACKAGES
0
T
A
= 125°C
LT1114J PACKAGE
–2
–4
–6
T
A
= 25°C
1B
LT1112J8, N8 PACKAGES
T
A
= –55°C
0
2
3
4
5
6
1
0
0.5
1.0
1.5
2.0
2.5
±10
±15
0
±20
±5
TIME (MONTHS)
TIME AFTER POWER ON (MINUTES)
SUPPLY VOLTAGE (V)
LT1112/14 • TPC14
LT1112/14 • TPC13
LT1112/14 • TPC15
Common-Mode Range and
Voltage Swing with Respect to
Supply Voltages
Minimum Supply Voltage vs Temp
Voltage Gain at Minimum Supply
Voltage
Output Voltage Swing
vs Load Current
+
+
±1.2
±1.1
±1.0
±0.9
V
V
V
L
= ±1V TO ±20V
S
+
+
+
+
+
–
–
–
–
V
V
V
V
V
V
V
V
V
– 0.2
– 0.4
– 0.6
– 0.8
– 1.0
+ 0.8
+ 0.6
+ 0.4
+ 0.2
I
< 100µA
+
V
V
– 1
– 2
V
T
= ±1V TO ±20V
= 25°C
L
S
A
SWING
+
MAX I AT ±1V = 1.3mA
AT ±1.5V = 3mA
+
–
–
CM RANGE
V
V
V
– 3
+ 3
+ 2
100
80
SWING
60
CM RANGE
40
–
V
+ 1
–
–
V
V
–50
0
25
50
75 100 125
125
–25
–75
–25
25
75
3
9
–9
–6
SINK
–3
0
6
SOURCE
TEMPERATURE (°C)
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
LT1112/14 • TPC16
LT1112/14 • TPC17
LT1112/14 • TPC18
7
LT1112/LT1114
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Voltage Gain
Gain, Phase Shift vs Frequency
Voltage Gain vs Frequency
–15
–10
–5
0
40
30
100
120
140
160
180
200
140
120
100
80
V
= ±15V
= 25°C
V
T
= ±15V
= 25°C
S
A
V
T
= ±15V
= 25°C
S
A
S
A
T
PHASE
20
R
L
= 10k
GAIN
60
10
R
L
= 2k
40
5
20
0
10
PHASE MARGIN = 70°C
0.1
0
–10
15
–20
–15
–5
0
5
10
15
0.01
1
10
–10
100 1k
10k 100k 1M 10M
0.01 0.1
1
10
OUTPUT VOLTAGE (V)
FREQUENCY (MHz)
FREQUENCY (Hz)
LT1112/14 • TPC21
LT1112/14 • TPC19
LT1112/14 • TPC20
Common-Mode Rejection
vs Frequency
Power Supply Rejection
vs Frequency
Channel Separation vs Frequency
160
140
120
100
80
140
120
100
80
V
= ±15V
= 25°C
V
= ±15V
= 25°C
V
= ±15V
= 25°C
S
A
S
A
S
A
T
T
T
NEGATIVE
SUPPLY
140
120
100
80
POSITIVE
SUPPLY
60
60
40
20
40
AMP 1 IN UNITY-GAIN
20V , R = 2k
P-P
AMP 2 IN GAIN = 1000
= 100Ω, R = 100k
L
20
R
S
F
0
1k
10 100
FREQUENCY (Hz)
100k 1M
10k
FREQUENCY (Hz)
1M
0.1
1
10k
1
10
100
1k
1M
1
10
100
1k
100k
10k 100k
FREQUENCY (Hz)
LT1112/14 • TPC23
LT1112/14 • TPC24
LT1112/14 • TPC22
Slew Rate, Gain-Bandwidth
Product and Phase Margin
vs Temperature
Closed-Loop Output Impedance
Capacitive Loading Handling
0.4
0.3
1000
100
10
120
100
80
60
40
20
0
V
T
= ±15V
= 25°C
V
T
= ±15V
= 25°C
S
A
S
A
SLEW
80
70
60
0.2
A
V
= 100
A = +1
V
φm
1
A
= +1
V
800
700
600
0.1
GBW
A
= 10
V
0.01
0.001
–50
0
25
50
75 100 125
1
100
1k
10k
100k 1M
0.001 0.01 0.1
CAPACITIVE LOAD (µF)
1
10
–25
10
0.00001 0.0001
TEMPERATURE (°C)
FREQUENCY (Hz)
LT1112/14 • TPC25
LT1112/14 • TPC26
LT1112/14 • TPC27
8
LT1112/LT1114
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Undistorted Output Voltage
vs Frequency
Small-Signal Transient Response
Large-Signal Transient Response
28
24
20
16
12
8
T
= 25°C
= 10k
A
L
R
V
= ±15V
S
V
= ±5V
S
4
50µs/DIV
2µs/DIV
0
AV = +1
A
V = +1
CL = 500pF
S = ±15V
1
10
100
1000
RF = 10k
FREQUENCY (kHz)
C
V
F = 100pF
S = ±15V
V
LT1112/14 • TPC30
O U
W
U
PPLICATI
A
S
I FOR ATIO
The LT1112 dual and LT1114 quad in the plastic and
ceramic DIP packages are pin compatible to and directly
replace such precision op amps as the OP-200, OP-297,
AD706 duals and OP-400, OP-497, AD704 quads with
improved price/performance.
the input is driven by a fast large-signal pulse (>1V), the
input protection diodes effectively short the output to the
input during slewing, and a current, limited only by the
output short-circuit protection, will flow through the
diodes.
The LT1112 in the S8 surface mount package has the
standard pin configuration, i.e., the same configuration as
the plastic and ceramic DIP packages.
The use of a feedback resistor is recommended because
thisresistorkeepsthecurrentbelowtheshort-circuitlimit,
resulting in faster recovery and settling of the output.
The LT1114 quad is offered in the narrow 16-pin surface
mount package. All competitors are in the wide 16-pin
package which occupies 1.8 times the area of the narrow
package. The wide package is also 1.8 times thicker than
the narrow package.
TheinputvoltageoftheLT1112/1114shouldneverexceed
the supply voltages by more than a diode drop. However,
theexamplebelowshowsthatastheinputvoltageexceeds
the common-mode range, the LT1112’s output clips
cleanly, without any glitches or phase reversal. The OP-
297 exhibits phase reversal. The photos also illustrate that
both the input and output ranges of the LT1112 are within
TheinputsoftheLT1112/1114areprotectedwithback-to-
back diodes. In the voltage follower configuration, when
Voltage Follower with Input Exceeding the Common-Mode Range (VS = ±5V)
INPUT: ±5.2V Sine Wave
LT1112 Output
OP-297 Output
9
LT1112/LT1114
O U
W
U
PPLICATI
A
S I FOR ATIO
800mV of the supplies. The effect of input and output
overdrive on the other amplifiers in the LT1112 or
LT1114 packages is negligible, as each amplifier is
biased independently.
Input offset current = 100pA
Input resistance = 800GΩ
Input noise = 0.42µVP-P
Three Op Amp Instrumentation Amplifier
Advantages of Matched Dual and Quad Op Amps
R4
100Ω
0.5%
R6
10k
–
IN
+
In many applications the performance of a system de-
pends on the matching between two operational amplifi-
ers rather than the individual characteristics of the two op
amps. Two or three op amp instrumentation amplifiers,
tracking voltage references and low drift active filters are
some of the circuits requiring matching between two op
amps.
0.5%
1/2 LT1112
OR
1/4 LT1114
–
R1
10k
1%
A
–
R3
2.1k
1%
LT1097 OR
1/4LT1114
R10
1M
OUTPUT
C1
33pF
+
B OR C
R8
200Ω
The well-known triple op amp configuration illustrates
these concepts. Output offset is a function of the differ-
ence between the offsets of the two halves of the LT1112.
This error cancellation principle holds for a considerable
number of input referred parameters in addition to offset
voltage and its drift with temperature. Input bias current
will be the average of the two noninverting input currents
(IB ). The difference between these two currents (∆IB ) is
the offset current of the instrumentation amplifier. Com-
mon-modeandpowersupplyrejectionswillbedependent
only on the match between the two amplifiers (assuming
perfect resistor matching).
R2
10k
1%
R5
100Ω
0.5%
GAIN = 1000
–
TRIM R8 FOR GAIN
TRIM R9 FOR DC
COMMON-MODE REJECTION
TRIM R10 FOR AC
COMMON-MODE REJECTION
1/2 LT1112
OR
R7
9.88k
0.5%
1/4 LT1114
+
+
D
IN
R9
200Ω
LT1112/14 • AI02
+
+
When the instrumentation amplifier is used with high
impedance sources, the LT1114 is recommended be-
cause its CMRR vs frequency performance is better than
theLT1112’s.Forexample,withtwomatched1MΩsource
resistors, CMRRat100Hzis100dBwiththeLT1114, 76dB
with the LT1112.
The concepts of common-mode and power supply rejec-
tion ratio match (∆CMRR and ∆PSRR) are best demon-
strated with a numerical example:
This difference is explained by the fact that capacitance
betweenadjacentpinsonanICpackageisabout0.25pF
(including package, socket and PC board trace capaci-
tances).
Assume CMRRA = +1µV/V or 120dB,
and CMRRB = +0.75µV/V or 122.5dB,
then ∆CMRR = 0.25µV/V or 132dB;
if CMRRB = –0.75µV/V which is still 122.5dB,
then ∆CMRR = 1.75µV/V or 115dB.
On the dual op amp package, positive input A is next to the
V– pin (AC ground), while positive input B has no AC
ground pin adjacent to it, resulting in a 0.25pF input
capacitance mismatch. At 100Hz, 0.25pF represents a
6.4 × 109 input impedance mismatch, which is only 76dB
higher than the 1MΩ source resistors.
Clearly the LT1112/LT1114, by specifying and guarantee-
ing all of these matching parameters, can significantly
improve the performance of matching-dependent
circuits.
On the quad package, all four inputs are adjacent to a
power supply terminal–therefore, there is no mismatch.
Typical performance of the instrumentation amplifier:
Input offset voltage = 35µV
Offset voltage drift = 0.3µV/°C
Input bias current = 80pA
10
LT1112/LT1114
U
O
TYPICAL APPLICATI
Dual Buffered ±0.617V Reference Powered by Two AA Batteries
+1.5V
R *
X
15k
*OPTIONAL
+
1/2 LT1112
+0.617V
–
20k
0.1%
LT1004-1.2
TOTAL SUPPLY CURRENT = 700µA
WORKS WITH BATTERIES DISCHARGED
TO ±1.3V
100pF
AT ±1.5V: MAXIMUM LOAD CURRENT = 800µA;
–
CAN BE INCREASED WITH OPTIONAL R , R ;
X
Y
AT R = R = 750Ω LOAD CURRENT = 2mA
X
Y
TEMPERATURE COEFFICIENT LIMITED BY
REFERENCE = 20ppm/°C
1/2 LT1112
+
R *
Y
20k
0.1%
*OPTIONAL
–1.5V
–0.617V
LT1112/14 • TA03
W
W
SCHE ATIC DIAGRA
(1/2 LT1112, 1/4 LT1114)
+
V
20µA
12pF
30k
30k
35µA
80µA
Q35 Q34
Q19
Q22
Q24
30pF
800Ω
1.5k
4k
Q33
Q21
Q6
Q27
Q5
Q25
Q29
S
Q8
Q4
28Ω
90Ω
Q7
3k
OUT
Q13
INVERTING
INPUT
Q11
Q23
2.5k
Q28
30Ω
S
S
Q20
S
Q1
Q2
–
Q26
Q3
50k
1.5k
Q12
J1
Q32
Q9
Q16
10k
Q17
NONINVERTING
INPUT
Q18
Q30
Q10
460Ω
460Ω
+
Q31
15µA
5µA
Q14
Q15
5µA
200Ω
200Ω
–
460Ω
V
Q1 TO Q4 ARE SUPERGAIN TRANSISTORS
LT1112/14 • SD01
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of circuits as described herein will not infringe on existing patent rights.
11
LT1112/LT1114
U
PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted.
0.405
(10.287)
0.005
(0.127)
MIN
0.200
(5.080)
MAX
MAX
0.290 – 0.320
(7.366 – 8.128)
6
5
4
8
7
0.015 – 0.060
(0.381 – 1.524)
J8 Package
8-Lead Ceramic DIP
0.025
(0.635)
RAD TYP
0.220 – 0.310
(5.588 – 7.874)
0.008 – 0.018
(0.203 – 0.460)
0° – 15°
1
2
3
0.055
(1.397)
MAX
0.038 – 0.068
(0.965 – 1.727)
0.385 ± 0.025
(9.779 ± 0.635)
0.125
3.175
MIN
0.100 ± 0.010
0.014 – 0.026
(2.540 ± 0.254)
(0.360 – 0.660)
0.400
(10.160)
MAX
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.320
(7.620 – 8.128)
0.045 – 0.065
(1.143 – 1.651)
8
1
7
6
5
4
N8 Package
8-Lead Plastic DIP
0.065
(1.651)
TYP
0.250 ± 0.010
(6.350 ± 0.254)
0.009 – 0.015
(0.229 – 0.381)
0.125
0.020
(0.508)
MIN
(3.175)
MIN
+0.025
–0.015
2
3
0.045 ± 0.015
(1.143 ± 0.381)
0.325
+0.635
8.255
(
)
–0.381
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
0.189 – 0.197
(4.801 – 5.004)
0.010 – 0.020
(0.254 – 0.508)
8
7
6
5
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
S8 Package
8-Lead Plastic SOIC
0.008 – 0.010
(0.203 – 0.254)
0.228 – 0.244
0.150 – 0.157
0.016 – 0.050
0.406 – 1.270
(5.791 – 6.197)
(3.810 – 3.988)
0.050
0.014 – 0.019
(0.355 – 0.483)
0°– 8° TYP
(1.270)
BSC
1
2
3
4
0.785
(19.939)
MAX
0.005
(0.127)
MIN
0.200
(5.080)
MAX
0.290 – 0.320
(7.366 – 8.128)
14
13
12
11
10
9
8
J Package
14-Lead Ceramic DIP
0.015 – 0.060
(0.381 – 1.524)
0.220 – 0.310
(5.588 – 7.874)
0.025
(0.635)
RAD TYP
0.008 – 0.018
(0.203 – 0.460)
0° – 15°
2
3
4
5
6
1
7
0.098
(2.489)
MAX
0.385 ± 0.025
(9.779 ± 0.635)
0.038 – 0.068
(0.965 – 1.727)
0.100 ± 0.010
(2.540 ± 0.254)
0.125
(3.175)
MIN
0.014 – 0.026
(0.360 – 0.660)
0.770
(19.558)
MAX
0.065
(1.651)
TYP
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
0.015
(0.380)
14
13
12
11
10
9
8
7
N Package
14-Lead Plastic DIP
MIN
0.130 ± 0.005
(3.302 ± 0.127)
0.260 ± 0.010
(6.604 ± 0.254)
0.009 – 0.015
(0.229 – 0.381)
+0.025
1
2
3
5
6
4
0.325
–0.015
0.075 ± 0.015
(1.905 ± 0.381)
0.018 ± 0.003
(0.457 ± 0.076)
0.125
(3.175)
MIN
+0.635
8.255
(
)
–0.381
0.100 ± 0.010
(2.540 ± 0.254)
0.386 – 0.394
(9.804 – 10.008)
0.010 – 0.020
(0.254 – 0.508)
16
15
14
13
12
11
10
9
× 45°
0.004 – 0.010
(0.101 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
S Package
16-Lead Plastic SOIC
0.008 – 0.010
(0.203 – 0.254)
0.150 – 0.157
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
0° – 8°
TYP
0.016 – 0.050
0.406 – 1.270
1
2
3
4
5
6
7
8
LT/GP 1292 10K REV 0
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
12
●
●
LINEAR TECHNOLOGY CORPORATION 1992
(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977
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