LT1122DC [Linear]
Fast Settling, JFET Input Operational Amplifier; 快速稳定， JFET输入运算放大器
| 型号： | LT1122DC |
| 厂家： | 
Linear |
| 描述： | Fast Settling, JFET Input Operational Amplifier |
| 文件： | 总8页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1122
Fast Settling, JFET Input
Operational Amplifier
U
EATURE
S
F
DESCRIPTIO
■
100% Tested Settling Time
to 1mV at Sum Node, 10V Step
Tested with Fixed Feedback Capacitor
Slew Rate
340ns Typ
540ns Max
The LT1122 JFET input operational amplifier combines
high speed and precision performance.
A unique poly-gate JFET process minimizes gate series
resistance and gate-to-drain capacitance, facilitating wide
bandwidth performance, without degrading JFET transis-
tor matching.
■
■
■
■
■
■
60V/µs Min
14MHz
Gain Bandwidth Product
Power Bandwidth (20Vp-p)
Unity Gain Stable; Phase Margin
Input Offset Voltage
Input Bias Current
Input Offset Current
Low Distortion
1.2 MHz
60°
600µV Max
75pA Max
600pA Max
40pA Max
150pA Max
It slews at 80V/µs and settles in 340ns. The LT1122 is
internally compensated to be unity gain stable, yet it has a
bandwidth of 14MHz at a supply current of only 7mA. Its
speed makes the LT1122 an ideal choice for fast settling
12-bit data conversion and acquisition systems.
25°C
70°C
25°C
70°C
■
■
The LT1122 offset voltage of 120µV, and voltage gain of
500,000 also support the 12-bit accurate applications.
O U
PPLICATI
S
A
The input bias current of 10pA and offset current of 4pA
combined with its speed allow the LT1122 to be used in
such applications as high speed sample and hold amplifi-
ers, peak detectors, and integrators.
■
■
■
■
■
■
■
■
Fast 12-Bit D/A Output Amplifiers
High Speed Buffers
Fast Sample and Hold Amplifiers
High Speed Integrators
Voltage to Frequency Converters
Active Filters
Log Amplifiers
Peak Detectors
U
O
TYPICAL APPLICATI
Large-Signal Response
12-Bit Voltage Output D/A Converter
+
C
f
2
–
+
V
6
OUT
0mA TO 2mA
OR 4mA
LT1122
0V TO 10V
3
12-BIT CURRENT OUTPUT D/A CONVERTER
C = 5pF TO 17pF
f
200ns/DIV
AV = –1
LT1122•TA01
(DEPENDING ON D/A CONVERTER USED)
1122 TA07
1
LT1122
W W W
U
ABSOLUTE AXI U RATI GS
Supply Voltage .................................................... ± 20V
Differential Input Voltage ...................................... ± 40V
Input Voltage ........................................................ ± 20V
Output Short Circuit Duration .......................... Indefinite
Lead Temperature (Soldering, 10 sec.)................. 300°C
Operating Temperature Range
LT1122AM/BM/CM/DM .................... – 55°C to 125°C
LT1122AC/BC/CC/DC/CS/DS .............. – 40°C to 85°C
Storage Temperature Range
All Devices....................................... – 65°C to 150°C
W
U
/O
PACKAGE RDER I FOR ATIO
ORDER PART
ORDER PART
TOP VIEW
TOP VIEW
NUMBER
V
SPEED BOOST/
OVERCOMP
V
V
SPEED BOOST/
OVERCOMP
V
NUMBER
OS
OS
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
TRIM
–IN
TRIM
–IN
+
+
LT1122AMJ8 LT1122CCJ8
LT1122BMJ8 LT1122DCJ8
LT1122CMJ8 LT1122ACN8
LT1122DMJ8 LT1122BCN8
LT1122ACJ8 LT1122CCN8
LT1122BCJ8 LT1122DCN8
LT1122CS8
LT1122DS8
LT1122
LT1122
+IN
OUT
+IN
OUT
–
–
V
V
TRIM
V
V
TRIM
OS
OS
PART MARKING
N8 PACKAGE
8-LEAD PLASTIC DIP 8-LEAD HERMETIC DIP
J8 PACKAGE
S8 PACKAGE
8-LEAD PLASTIC SOIC
1122C
1122D
TJMAX = 150°C, θJA = 130°C/W (N8)
JMAX = 175°C, θJA = 100°C/W (J8)
TJMAX = 150°C, θJA = 190°C/W
T
Consult factory for Industrial grade parts.
VS = ± 15V, TA = 25°C, VCM = 0V unless otherwise noted. (Note 1)
ELECTRICAL CHARACTERISTICS
LT1122CM/DM
LT1122AM/BM
LT1122AC/BC
LT1122CC/DC
LT1122CS/DS
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX
MIN
TYP MAX
UNITS
µV
V
Input Offset Voltage
Input Offset Current
Input Bias Current
120
600
130
900
OS
I
I
4
40
5
50
pA
OS
10
75
12
100
pA
B
Input Resistance
Differential
Common Mode
12
12
10
10
10
10
10
10
Ω
Ω
Ω
12
11
12
11
V
CM
V
CM
= – 10V to + 8V
= + 8V to + 11V
Input Capacitance
Slew Rate
4
4
pF
S
A = – 1
V
60
80
50
75
V/µs
R
Settling Time (Note 2)
+ 10V to 0V, – 10V to 0V
100% Tested: A and C Grades
to 1mV at Sum Node
B and D Grades to 1mV at Sum Node
All Grades to 0.5mV at Sum Node
340
350
450
540
350
360
470
590
ns
ns
ns
GBW
Gain Bandwidth Product
Power Bandwidth
14
1.2
13
1.1
MHz
MHz
V
OUT
= 20Vp-p
A
Large Signal Voltage Gain
V
OUT
V
OUT
= ± 10V, R = 2kΩ
180
130
500
250
150
110
450
220
V/mV
V/mV
VOL
L
= ± 10V, R = 600Ω
L
CMRR
PSRR
Common Mode Rejection Ratio
Input Voltage Range
V
= ± 10V
83
99
80
98
dB
V
CM
(Note 3)
= ± 10V to ± 18V
± 10.5 ± 11
86 103
± 10.5 ± 11
82 101
Power Supply Rejection Ratio
Input Noise Voltage
V
S
dB
0.1Hz to 10Hz
3.0
3.3
µV
P-P
Input Noise Voltage Density
f
f
= 100Hz
= 10kHz
25
14
27
15
nV/√Hz
nV/√Hz
O
O
Input Noise Current Density
f
= 100Hz, f = 10kHz
2
2
fA/√Hz
O
O
2
LT1122
ELECTRICAL CHARACTERISTICS
VS = ± 15V, TA = 25°C, VCM = 0V unless otherwise noted.
LT1122CM/DM
LT1122AM/BM
LT1122AC/BC
LT1122CC/DC
LT1122CS/DS
SYMBOL
PARAMETER
CONDITIONS
R = 2kΩ
MIN TYP MAX
MIN
± 12
TYP MAX
UNITS
V
OUT
Output Voltage Swing
± 12
± 12.5
± 12.5
V
V
L
R = 600Ω
L
± 11.5 ± 12
± 11.5 ± 12
I
S
Supply Current
7.5
10
7.8
11
mA
V
Minimum Supply voltage
Offset Adjustment Range
(Note 4)
± 5
± 4
± 5
+
R
POT
≥ 10k, Wiper to V
± 10
± 4
± 10
mV
VS = ± 15V, VCM = 0V, 0°C ≤ TA ≤ 70°C, unless otherwise noted. (Note 1)
LT1122CC/DC
LT1122CS/DS
LT1122AC/BC
SYMBOL
OS
PARAMETER
Input Offset Voltage
CONDITIONS
MIN TYP MAX
MIN
TYP MAX
UNITS
V
•
350 1400
400
2000
µV
Average Temperature Coefficient
of Input Offset Voltage
•
5
18
6
25
µV/°C
I
Input Offset Current
•
•
•
•
•
•
•
•
12
80
150
600
15
90
200
800
pA
pA
OS
I
B
Input Bias Current
A
Large Signal Voltage Gain
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Input Voltage Range
Output Voltage Swing
Slew Rate
V
V
V
= ± 10V, R ≥ 2kΩ
120
82
380
98
100
340
96
V/mV
dB
VOL
OUT
L
CMRR
PSRR
= ± 10V
78
80
CM
= ± 10V to ± 17V
84
101
± 10.8
99
dB
S
± 10
± 10
± 10.8
V
V
R = 2kΩ
± 11.5 ± 12.4
50 70
± 11.5 ± 12.4
40 65
V
OUT
L
S
A
= – 1
V
V/µs
R
VS = ± 15V, VCM = 0V, – 55°C ≤ TA ≤ 125°C, unless otherwise noted. (Note 1)
LT1122AM/BM
MIN TYP MAX
LT1122CM/DM
SYMBOL
PARAMETER
Input Offset Voltage
CONDITIONS
MIN TYP MAX
UNITS
µV
V
OS
•
•
650
6
2400
18
800
7
3400
25
Average Temperature Coefficient
of Input Offset Voltage
µV/°C
I
Input Offset Current
•
•
•
•
•
•
•
•
0.5
6
6
0.6
7
9
nA
nA
OS
I
B
Input Bias Current
25
35
A
Large Signal Voltage Gain
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Input Voltage Range
Output Voltage Swing
Slew Rate
V
V
V
= ± 10V, R ≥ 2kΩ
70
80
230
97
60
76
200
94
V/mV
dB
VOL
OUT
L
CMRR
PSRR
= ± 10V
CM
= ± 10V to ± 17V
83
100
± 10.5
78
98
dB
S
± 10
± 10
± 10.5
V
V
R = 2kΩ
± 11.3 ± 12.1
45 60
± 11.3 ± 12.1
35 55
V
OUT
L
S
A
= – 1
V
V/µs
R
The denotes the specifications which apply over the full operating
temperature range.
Note 3: Input voltage range functionality is assured by testing offset
voltage at the input voltage range limits to a maximum of 4mV (A, B
grades), to 5.7mV (C, D grades).
Note 4: Minimum supply voltage is tested by measuring offset voltage to
7mV maximum at ± 5V supplies.
Note 5: The LT1122 is not tested and not quality-assurance-sampled at
– 40°C and at 85°C. These specifications are guaranteed by design,
correlation and/or inference from – 55°C, 0°C, 25°C, 70°C and/or 125°C
tests.
•
Note 1: The LT1122 is measured in an automated tester in less than one
second after application of power. Depending on the package used, power
dissipation, heat sinking, and air flow conditions, the fully warmed up chip
temperature can be 10°C to 50°C higher than the ambient temperature.
Note 2: Settling time is 100% tested for A and C grades using the settling
time test circuit shown. This test is not included in quality assurance
sample testing.
3
LT1122
ELECTRICAL CHARACTERISTICS
VS = ± 15V, VCM = 0V, – 40°C ≤ TA ≤ 85°C, unless otherwise noted. (Note 5)
LT1122CC/DC
LT1122CS/DS
LT1122AC/BC
SYMBOL
PARAMETER
Input Offset Voltage
CONDITIONS
MIN TYP MAX
MIN TYP MAX
UNITS
µV
V
OS
•
•
450
1900
500
2700
Average Temperature Coefficient
of Input Offset Voltage
6
20
7
28
µV/°C
I
Input Offset Current
•
•
•
•
•
•
•
•
30
230
340
98
600
40
260
300
96
900
pA
pA
OS
I
B
Input Bias Current
2000
2700
A
Large Signal Voltage Gain
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Input Voltage Range
Output Voltage Swing
Slew Rate
V
V
V
= ± 10V, R ≥ 2kΩ
95
80
80
76
V/mV
dB
VOL
OUT
L
CMRR
PSRR
= ± 10V
CM
= ± 10V to ± 17V
83
100
± 10.6
78
98
dB
S
± 10
± 10
± 10.6
V
V
R = 2kΩ
± 11.3 ± 12.2
45 65
± 11.3 ± 12.2
35 60
V
OUT
L
S
A
= – 1
V
V/µs
R
Settling Time Test Fixture
DEVICE UNDER TEST
5pF
2k
1%
+10V
+15V
(REGULATED)
7
+15V
7
1
2k
1%
51
51
8
2
4
–
+
HA5002
6
2
LT1122
4
3
1
2
3
4
5
6
7
8
6
16
15
14
13
12
11
10
9
5
4
74LS00
GROUND ALL
OTHER INPUTS
–15V
5
–15V
5.1k*
1%
5.1k
1%
V
IN
(MEASURE INPUT
PULSE HERE)
1
LTC201A
3
TTL
IN
2
+15V
51
7
+15V
NO CONNECTION ON PINS
10, 11, 12, 14, AND 15
1
2
–10V
SUMMING
NODE
51
4
7
3
2
8
(REGULATED)
HA5002
5
+
1k
OUTPUT
6
+15V
LT1223
SETTLING
TIME OUTPUT
(20 TIMES SUM
NODE OUTPUT)
+
0.1µF
1µF TANT
–
4
–15V
79
–15V
1.5k
TYPICAL SUPPLY
BYPASSING FOR
EACH AMP/BUFFER
1N5712
1N5712
–15V
*THIS RESISTOR CAN BE ADJUSTED TO
NULL OUT ALL OFFSETS AT THE SETTLING
TIME OUTPUT. THE AUTOMATED TESTER
USES A SEPARATE AUTOZERO CIRCUIT.
0.1µF
1µF TANT
+
LT1122•TA02
4
LT1122
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Settling Time
(Input From –10V to 0V)
Settling Time
(Input From +10V to 0V)
Settling Time
(Input From 0V to +10V)
100ns/DIV
100ns/DIV
100ns/DIV
1122 G01
1122 G02
1122 G03
Settling Time
(Input From 0V to –10V)
Undistorted Output Swing vs
Frequency
Large Signal Response
30
25
20
15
10
5
V
A
= ±15V
= 25°C
S
T
200ns/DIV
AV = +1
100ns/DIV
1122 G04
1122 G05
0
100k
1M
10M
100M
FREQUENCY (Hz)
LT1122•TPC01
Common Mode Rejection vs
Frequency
Voltage Gain vs Frequency
Gain, Phase vs Frequency
120
100
120
100
80
80
V
A
= ±15V
= 25°C
S
100
120
20
10
V
A
= ±15V
= 25°C
S
T
T
80
60
60
140
160
180
40
20
0
40
20
0
V
A
C
= ±15V
= 25°C
= 15pF
S
T
0
200
L
–20
–40
–10
100k
FREQUENCY (Hz)
10M
100
1k
10k
1M
100M
1
10 100 1k 10k 100k
FREQUENCY (Hz)
100M
1M 10M
1M
100M
10M
FREQUENCY (Hz)
LT1122•TPC03
LT1122•TPC04
LT1122•TPC02
5
LT1122
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Distribution of Input Offset
Voltage
Input Bias and Offset Currents
Over Temperature
Bias and Offset Currents Over
The Common-Mode Range
120
100
100K
30K
10K
3K
800
600
V
T
= ±15V
= 25°C
3370 UNITS TESTED
IN ALL PACKAGES
S
A
V
CM
= ±15V
S
V
T
= ±15V
= 25°C
S
A
V
= 0V
(NOT WARMED UP)
(NOT-WARMED UP)
80
60
BIAS
CURRENT
1K
BIAS
CURRENT
300
100
30
400
40
20
0
OFFSET
CURRENT
OFFSET
CURRENT
200
0
10
3
1
10
COMMON-MODE INPUT VOLTAGE (V)
0
25
50
75
100
125
–15
–10
–5
0
5
15
–900
–500
–100 100
500
900
CHIP TEMPERATURE (°C)
INPUT OFFSET VOLTAGE (µV)
LT1122•TPC06
LT1122•TPC07
LT1122•TPC05
Warm-up Drift
Noise Spectrum
0.1Hz to 10Hz Noise
1000
100
10
250
200
150
100
50
V
A
= ±15V
= 25°C
S
V
A
= ±15V
S
SO PACKAGE
T
T
= 25°C
N PACKAGE
J PACKAGE
IN STILL AIR (SO PACKAGE
SOLDERED ONTO BOARD)
1
0
2
4
6
8
10
0
1
2
3
1
3
10
3k 10k
30 100 300 1k
FREQUENCY (Hz)
TIME (SECONDS)
TIME AFTER POWER ON (MINUTES)
LT1122•TPC10
LT1122•TPC08
LT1122•TPC09
Total Harmonic Distortion
+ Noise vs Frequency
Inverting Gain
Total Harmonic Distortion
+ Noise vs Frequency
Non-Inverting Gain
Intermodulation Distortion
(CCIF Method) vs Frequency
LT1122 and LF156*
0.1
0.1
0.01
0.1
0.01
T
V
Z
V
= 25°C
A
S
L
= ±15V
= 5k//15pF
= 7V RMS
LF156
O
0.01
0.001
A
= +50
V
A
A
= –50
V
V
V
T
A
V
Z
= ±15V
S
A
V
O
L
= 25°C
A
= +10
= +1
V
= –10
= 7V RMS
= 5k//15pF
= –10
= –1
0.001
0.0001
0.001
0.0001
A
V
T
V
Z
V
= 25°C
A
S
L
A
= ±15V
V
= 5k//15pF
= 7V RMS
LT1122
O
0.0001
3k
10k
FREQUENCY (Hz)
20k
20
100
1k
FREQUENCY (Hz)
10k 20k
20
100
1k
FREQUENCY (Hz)
10k 20k
*SEE LT1115 DATA SHEET FOR DEFINITION
OF CCIF TESTING
LT1122•TPC11
LT1122•TPC12
LT1122•TPC13
6
LT1122
O U
W
U
PPLICATI
A
S
I FOR ATIO
Settling Time Measurements
The power supply connections to the LT1122 must main-
tain a low impedance to ground over a bandwidth of
20MHz.Thisisespeciallyimportantwhendrivingasignifi-
cant resistive or capacitive load, since all current delivered
to the load comes from the power supplies. Multiple high
quality bypass capacitors are recommended for each
power supply line in any critical application. A 0.1µF
ceramic and a 1µF electrolytic capacitor, as shown, placed
as close as possible to the amplifier (with short lead
lengths to power supply common) will assure adequate
high frequency bypassing, in most applications.
Settling time test circuits shown on some competitive
devices’ data sheets require:
1. A “flat top” pulse generator. Unfortunately, flat top
pulse generators are not commercially available.
2. A variable feedback capacitor around the device under
test. This capacitor varies over a four to one range.
Presumably, as each op amp is measured for settling
time, the capacitor is fine tuned to optimize settling
time for that particular device.
+
V
3. A small inductor load to optimize settling.
+
1µF
0.1µF
7
The LT1122’s settling time is 100% tested in the test
circuit shown. No “flat top” pulse generator is required.
Thetestcircuitcanbereadilyconstructed, usingcommer-
cially available ICs. Of course, standard high frequency
board construction techniques should be followed. All
LT1122s are measured with a constant feedback capaci-
tor. No fine tuning is required.
2
3
–
+
6
LT1122
4
1µF
0.1µF
+
–
V
LT1122•TA03
Speed Boost/Overcompensation Terminal
When the feedback around the op amp is resistive (RF), a
pole will be created with RF, the source resistance and
capacitance (RS, CS), and the amplifier input capacitance
(CIN ≈ 4pF). In low closed loop gain configurations and
with RS and RF in the kilohm range, this pole can create
excess phase shift and even oscillation. A small capacitor
(CF) in parallel with RF eliminates this problem. With
RS (CS + CIN) = RFCF, the effect of the feedback pole is
completely removed.
Pin 8 of the LT1122 can be used to change the input stage
operating current of the device. Shorting pin 8 to the
positive supply (Pin 7) increases slew rate and bandwidth
by about 25%, but at the expense of a reduction in phase
margin by approximately 18 degrees. Unity gain capaci-
tive load handling decreases from typically 500pF to
100pF.
Conversely, connecting a 15k resistor from pin 8 to
ground pulls 1mA out of pin 8 (with V+ = 15V). This
reduces slew rate and bandwidth by 25%. Phase margin
and capacitive load handling improve; the latter typically
increasing to 800pF.
C
F
R
F
–
+
High Speed Operation
C
OUTPUT
IN
R
C
S
S
As with most high speed amplifiers, care should be taken
with supply decoupling, lead dress and component
placement.
LT1122•TA04
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of circuits as described herein will not infringe on existing patent rights.
7
LT1122
U
TYPICAL APPLICATIONS
Quartz Stabilized Oscillator With 9ppm Distortion
OUTPUT
–15V
4.7k
LT1004
2.5V
OUTPUT
AMPLITUDE
TRIM
10µF
4.7k
5k
47k
4kHz
J
CUT
+15V
–
+
–
4.7k
LT1122
LT1010
LT1006
+
DISTORTION
TRIM
430pF
MOUNT IN CLOSE
PROXIMITY
50k
560k
470Ω
+15V
2k
GROUND CRYSTAL CASE
–
+
1M
+15V
560k
100k
LT1122
= VACTEC VTL5C10 OR
CLAIREX CLM410
–15V
Q1
2N3904
1/4 LTC201
= 1N4148
LT1122•TA05
Wide-Band, Filtered, Full Wave Rectifier
200k
1%
1µF
200k
1%
50k
20k
1%
100k
1%
1k
–
20k
1%
E
DC
LT1122
OUT
–
+
V
IN
+
LT1122
OUTPUT DC = RMS VALUE OF INPUT
BANDWIDTH WITH 10Vp-p INPUT = 2MHz
LT1122•TA06
U
PACKAGE DESCRIPTION
Please see the 1994 Linear Databook Volume III for package descriptions.
8
相关型号：
LT1122DCN8#PBF
LT1122 - Fast Settling, JFET Input Operational Amplifier; Package: PDIP; Pins: 8; Temperature Range: 0°C to 70°C
Linear
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