LT1125CSW#PBF [Linear]
LT1125 - Quad Low Noise, High Speed Precision Op Amps; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C;
| 型号： | LT1125CSW#PBF |
| 厂家： | 
Linear |
| 描述： | LT1125 - Quad Low Noise, High Speed Precision Op Amps; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C 运算放大器 |
| 文件： | 总16页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1124/LT1125
Dual/Quad Low Noise,
High Speed Precision Op Amps
U
FEATURES
DESCRIPTIO
The LT®1124 dual and LT1125 quad are high performance
op amps that offer higher gain, slew rate and bandwidth
than the industry standard OP-27 and competing OP-270/
OP-470 op amps. In addition, the LT1124/LT1125 have
lower IB and IOS than the OP-27; lower VOS and noise
than the OP-270/OP-470.
■
100% Tested Low Voltage Noise: 2.7nV/√Hz Typ
4.2nV/√Hz Max
■
Slew Rate: 4.5V/µs Typ
■
Gain Bandwidth Product: 12.5MHz Typ
■
Offset Voltage, Prime Grade: 70µV Max
Low Grade: 100µV Max
■
High Voltage Gain: 5 Million Min
In the design, processing and testing of the device, par-
ticular attention has been paid to the optimization of the
entire distribution of several key parameters. Slew rate,
gain bandwidth and 1kHz noise are 100% tested for each
individual amplifier. Consequently, the specifications of
even the lowest cost grades (the LT1124C and the
LT1125C) have been spectacularly improved compared
■
Supply Current Per Amplifier: 2.75mA Max
■
Common Mode Rejection: 112dB Min
■
Power Supply Rejection: 116dB Min
■
Available in 8-Pin SO Package
U
APPLICATIO S
■
Two and Three Op Amp Instrumentation Amplifiers
Low Noise Signal Processing
Active Filters
Microvolt Accuracy Threshold Detection
Strain Gauge Amplifiers
Direct Coupled Audio Gain Stages
Tape Head Preamplifiers
to equivalent grades of competing amplifiers.
■
■
■
■
■
■
■
Power consumption of the LT1124 is one half of two
OP-27s. Low power and high performance in an 8-pin SO
packagemaketheLT1124afirstchoiceforsurfacemounted
systems and where board space is restricted.
For a decompensated version of these devices, with three
times higher slew rate and bandwidth, please see the
LT1126/LT1127 data sheet.
Infrared Detectors
, LTC and LT are registered trademarks of Linear Technology Corporation.
Protected by U.S. patents 4,775,884 and 4,837,496.
U
TYPICAL APPLICATIO
Instrumentation Amplifier with Shield Driver
Input Offset Voltage Distribution
3
+
(All Packages, LT1124 and LT1125)
1k
30k
1
1/4
LT1125
–
2
R
F
758 DUALS
200 QUADS
V
= ±15V
= 25°C
S
A
15V
4
3.4k
T
30
20
10
0
2316 UNITS
TESTED
5
6
GUARD
+
R
G
7
1/4
LT1125
100Ω
OUTPUT
30k
10
+
–
+
–
11
8
1/4
LT1125
R
G
INPUT
100Ω
9
–15V
–
GUARD
GAIN = 30 (1 + R /R ) ≈ 1000
F
G
POWER BW = 170kHz
SMALL-SIGNAL BW = 400kHz
R
F
13
12
NOISE = 3.8µV/√Hz AT OUTPUT
= 35µV
–
3.4k
V
OS
14
–100
–60
–20
20
60
100
1/4
LT1125
INPUT OFFSET VOLTAGE (µV)
1k
+
1124/25 TA02
1124/25 TA01
1
LT1124/LT1125
W W W
U
ABSOLUTE AXI U RATI GS (Note 1)
Supply Voltage ..................................................... ±22V
Input Voltages ......................... Equal to Supply Voltage
Output Short-Circuit Duration......................... Indefinite
Differential Input Current (Note 6) ..................... ±25mA
Lead Temperature (Soldering, 10 sec)................. 300°C
Storage Temperature Range ................ –65°C to 150°C
Operating Temperature Range
LT1124AC/LT1124C
LT1125AC/LT1125C (Note 10) .......... –40°C to 85°C
LT1124AI/LT1124I ............................ –40°C to 85°C
LT1124AM/LT1124M
LT1125AM/LT1125M ...................... –55°C to 125°C
W
U
/O
PACKAGE RDER I FOR ATIO
TOP VIEW
ORDER PART
ORDER PART
NUMBER
NUMBER
TOP VIEW
+IN A
1
2
3
4
8
7
6
5
–IN A
–
+
V
A
B
OUT A
OUT A
–IN A
+IN A
1
2
3
4
V
8
7
6
5
LT1124CS8
LT1124AIS8
LT1124IS8
LT1124CJ8
LT1124ACN8
LT1124CN8
LT1124AMJ8
LT1124MJ8
+
+IN B
–IN B
V
OUT B
–IN B
+IN B
A
OUT B
B
–
V
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 140°C, θJA = 190°C
S8 PART MARKING
J8 PACKAGE
N8 PACKAGE
8-LEAD CERDIP 8-LEAD PDIP
1124
1124AI
1124I
NOTE: THIS PIN CONFIGURATION DIFFERS FROM THE
8-PIN PDIP CONFIGURATION. INSTEAD, IT FOLLOWS
THE INDUSTRY STANDARD LT1013DS8 SO PACKAGE
PIN LOCATIONS
TJMAX = 160°C, θJA = 100°C (J8)
TJMAX = 140°C, θJA = 130°C (N8)
TOP VIEW
TOP VIEW
LT1125CS
LT1125CJ
LT1125ACN
LT1125CN
LT1125AMJ
LT1125MJ
OUT A
–IN A
+IN A
1
2
3
4
5
6
7
8
16 OUT D
15 –IN D
OUT A
–IN A
+IN A
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT D
–IN D
+IN D
A
B
D
C
A
B
D
C
14
13
12
11
10
9
+IN D
+
–
V
+
V
–
V
V
+IN B
–IN B
OUT B
NC
+IN C
–IN C
OUT C
NC
+IN B
–IN B
OUT B
+IN C
–IN C
OUT C
8
J PACKAGE
N PACKAGE
14-LEAD CERDIP 14-LEAD PDIP
SW PACKAGE
16-LEAD PLASTIC (WIDE) SO
TJMAX = 160°C, θJA = 80°C (J)
JMAX = 140°C, θJA = 110°C (N)
T
T
JMAX = 140°C, θJA = 130°C
ELECTRICAL CHARACTERISTICS TA = 25°C, VS = ±15V, unless otherwise noted.
LT1124AC/AI/AM
LT1124/C/I/M
LT1125AC/AM
LT1125/C/M
TYP
SYMBOL
PARAMETER
CONDITIONS (Note 2)
MIN
TYP
MAX
MIN
MAX
UNITS
V
Input Offset Voltage
LT1124
LT1125
20
25
70
90
25
30
100
140
µV
µV
OS
∆V
∆Time
Long Term Input Offset
Voltage Stability
0.3
0.3
µV/Mo
OS
I
Input Offset Current
LT1124
LT1125
5
6
15
20
6
7
20
30
nA
nA
OS
2
LT1124/LT1125
ELECTRICAL CHARACTERISTICS TA = 25°C, VS = ±15V, unless otherwise noted.
LT1124AC/AI/AM
LT1124C/I/M
LT1125C/M
LT1125AC/AM
SYMBOL
PARAMETER
CONDITIONS (Note 2)
MIN
TYP
±7
MAX
±20
200
MIN
TYP
MAX
UNITS
I
Input Bias Current
Input Noise Voltage
Input Noise Voltage Density
±8
±30
nA
B
e
n
0.1Hz to 10Hz (Notes 8, 9)
70
70
nV
P-P
f = 10Hz (Note 4)
O
3.0
2.7
5.5
4.2
3.0
2.7
5.5
4.2
nV/√Hz
nV/√Hz
f = 1000Hz (Note 3)
O
i
Input Noise Current Density
f = 10Hz
f = 1000Hz
O
1.3
0.3
1.3
0.3
pA/√Hz
pA/√Hz
n
O
V
Input Voltage Range
±12
112
116
±12.8
126
±12
106
110
±12.8
124
V
dB
dB
CM
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain
V
= ±12V
CM
V = ±4V to ±18V
S
126
124
A
VOL
R ≥ 10k, V = ±10V
OUT
R ≥ 2k, V
5
2
17
4
3.0
1.5
15
3
V/µV
V/µV
L
= ±10V
L
OUT
V
Maximum Output Voltage Swing R ≥ 2k
±13
3
±13.8
4.5
±12.5 ±13.8
V
V/µs
MHz
Ω
OUT
L
SR
Slew Rate
R ≥ 2k (Notes 3, 7)
L
2.7
8
4.5
12.5
75
GBW
Gain Bandwidth Product
Open-Loop Output Resistance
Supply Current per Amplifier
Channel Separation
f = 100kHz (Note 3)
9
12.5
75
O
Z
V
OUT
= 0, I
= 0
O
OUT
I
2.3
2.75
2.3
2.75
mA
dB
S
f ≤ 10Hz (Note 9)
= ±10V, R = 2k
134
150
130
150
V
OUT
L
The ● denotes the specifications which apply over the –55°C ≤ TA ≤ 125°C temperature range, VS = ±15V, unless otherwise noted.
LT1124AM
LT1125AM
LT1124M
LT1125M
TYP
SYMBOL
PARAMETER
CONDITIONS (Note 2)
MIN
TYP
MAX
MIN
MAX
UNITS
V
Input Offset Voltage
LT1124
LT1125
●
●
50
55
170
190
60
70
250
290
µV
µV
OS
∆V
∆Temp
Average Input Offset
Voltage Drift
(Note 5)
●
0.3
1.0
0.4
1.5
µV/°C
OS
I
Input Offset Current
LT1124
LT1125
●
●
18
18
45
55
20
20
60
70
nA
nA
OS
B
I
Input Bias Current
●
●
●
●
±18
±12
122
122
±55
±20
±12
120
120
±70
nA
V
V
Input Voltage Range
±11.3
106
±11.3
100
CM
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain
V
= ±11.3V
dB
dB
CM
V = ±4V to ±18V
S
110
104
A
R ≥ 10k, V = ±10V
OUT
●
●
3
1
10
3
2.0
0.7
10
2
V/µV
V/µV
VOL
L
R ≥ 2k, V
L
= ±10V
OUT
V
Maximum Output Voltage Swing R ≥ 2k
●
●
●
±12.5 ±13.6
±12
±13.6
3.8
V
V/µs
mA
OUT
L
SR
Slew Rate
R ≥ 2k (Notes 3, 7)
L
2.3
3.8
2.5
2
I
Supply Current per Amplifier
3.25
2.5
3.25
S
3
LT1124/LT1125
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the 0°C ≤ TA ≤ 70°C
temperature range, VS = ±15V, unless otherwise noted.
LT1124AC
LT1125AC
TYP
LT1124C
LT1125C
TYP
SYMBOL
PARAMETER
CONDITIONS (Note 2)
MIN
MAX
MIN
MAX
UNITS
V
Input Offset Voltage
LT1124
LT1125
●
●
35
40
120
140
45
50
170
210
µV
µV
OS
∆V
Average Input Offset
Voltage Drift
(Note 5)
●
0.3
1
0.4
1.5
µV/°C
OS
∆Temp
I
Input Offset Current
LT1124
LT1125
●
●
6
7
25
35
7
8
35
45
nA
nA
OS
I
Input Bias Current
●
●
●
●
±8
±35
±9
±45
nA
V
B
V
Input Voltage Range
±11.5 ±12.4
±11.5 ±12.4
CM
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain
V
= ±11.5V
109
112
125
125
102
107
122
122
dB
dB
CM
V = ±4V to ±18V
S
A
R ≥ 10k, V = ±10V
OUT
R ≥ 2k, V
●
●
4.0
1.5
15
3.5
2.5
1.0
14
2.5
V/µV
V/µV
VOL
L
L
= ±10V
OUT
V
Maximum Output Voltage Swing R ≥ 2k
●
●
●
±12.5 ±13.7
±12
±13.7
4
V
V/µs
mA
OUT
L
SR
Slew Rate
R ≥ 2k (Notes 3, 7)
L
2.6
4
2.4
I
Supply Current per Amplifier
2.4
3
2.4
3
S
The ● denotes the specifications which apply over the –40°C ≤ TA ≤ 85°C temperature range, VS = ±15V,
unless otherwise noted. (Note 10)
LT1124AC/AI
LT1125AC
LT1124C/I
LT1125C
TYP
SYMBOL
PARAMETER
CONDITIONS (Note 2)
MIN
TYP
MAX
MIN
MAX
UNITS
V
Input Offset Voltage
LT1124
LT1125
●
●
40
45
140
160
50
55
200
240
µV
µV
OS
∆V
Average Input Offset
Voltage Drift
(Note 5)
●
0.3
1
0.4
1.5
µV/°C
OS
∆Temp
I
Input Offset Current
LT1124
LT1125
●
●
15
15
40
50
17
17
55
65
nA
nA
OS
I
Input Bias Current
●
●
●
●
±15
±50
±17
±65
nA
V
B
V
Input Voltage Range
±11.4 ±12.2
±11.4 ±12.2
CM
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain
V
= ±11.4V
107
111
124
124
101
106
121
121
dB
dB
CM
V = ±4V to ±18V
S
A
R ≥ 10k, V = ±10V
OUT
R ≥ 2k, V
●
●
3.5
1.2
12
3.2
2.2
0.8
12
2.3
V/µV
V/µV
VOL
L
L
= ±10V
OUT
V
Maximum Output Voltage Swing R ≥ 2k
●
●
●
±12.5 ±13.6
±12
±13.6
3.9
V
V/µs
mA
OUT
L
SR
Slew Rate
R ≥ 2k (Notes 3, 7)
L
2.4
3.9
2.4
2.1
I
Supply Current per Amplifier
3.25
2.4
3.25
S
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 7: Slew rate is measured in A = –1; input signal is ±7.5V, output
measured at ±2.5V.
V
Note 2: Typical parameters are defined as the 60% yield of parameter
distributions of individual amplifiers; i.e., out of 100 LT1125s (or 100
LT1124s) typically 240 op amps (or 120) will be better than the indicated
specification.
Note 8: 0.1Hz to 10Hz noise can be inferred from the 10Hz noise voltage
density test. See the test circuit and frequency response curve for 0.1Hz to
10Hz tester in the Applications Information section of the LT1007 or
LT1028 data sheets.
Note 3: This parameter is 100% tested for each individual amplifier.
Note 4: This parameter is sample tested only.
Note 5: This parameter is not 100% tested.
Note 6: The inputs are protected by back-to-back diodes. Current limiting
resistors are not used in order to achieve low noise. If differential input
voltage exceeds ±1.4V, the input current should be limited to 25mA.
Note 9: This parameter is guaranteed but not tested.
Note 10: The LT1124C/LT1125C and LT1124AC/LT1125AC are guaranteed
to meet specified performance from 0°C to 70°C and are designed,
characterized and expected to meet these extended temperature limits, but
are not tested at –40°C and 85°C. The LT1124AI and LT1124I are
guaranteed to meet the extended temperature limits.
4
LT1124/LT1125
U W
TYPICAL PERFOR A CE CHARACTERISTICS
0.1Hz to 10Hz Voltage Noise
0.01Hz to 1Hz Voltage Noise
Voltage Noise vs Frequency
100
30
V
= ±15V
= 25°C
S
A
T
10
3
MAXIMUM
TYPICAL
1/f CORNER
2.3Hz
1
0.1
1.0
10
FREQUENCY (Hz)
100
1000
0
2
4
6
8
10
0
20
40
60
80
100
TIME (SECONDS)
TIME (SECONDS)
1124/25 G03
1124/25 G01
1124/25 G02
Input Bias or Offset Current
vs Temperature
Output Short-Circuit Current
vs Time
Current Noise vs Frequency
10.0
3.0
30
20
10
0
50
40
V
S
= ±15V
= 25°C
V = ±15V
S
V
S
= ±15V
T
A
25°C
–55°C
30
20
10
125°C
1.0
0.3
0
–10
–20
–30
MAXIMUM
TYPICAL
125°C
25°C
LT1124M/LT1125M
1/f CORNER
100Hz
LT1124AM/LT1125AM
–55°C
–40
–50
0.1
10
100
1k
10k
–75 –50 –25
0
25 50 75 100 125
0
1
2
3
4
TIME FROM OUTPUT SHORT TO GND (MINUTES)
FREQUENCY (Hz)
TEMPERATURE (°C)
1124 G04
1124/25 G05
LT1124 G06
Input Bias Current Over the
Common Mode Range
Common Mode Rejection Ratio
vs Frequency
Power Supply Rejection Ratio
vs Frequency
20
15
10
5
160
140
120
100
80
160
V
T
= ±15V
= 25°C
T
V
V
= 25°C
= ±15V
= ±10V
T
= 25°C
S
A
A
S
A
140
120
100
80
CM
DEVICE WITH POSITIVE
INPUT CURRENT
0
–PSRR
+PSRR
–5
60
60
DEVICE WITH NEGATIVE
INPUT CURRENT
40
–10
–15
–20
40
20
0
20
0
2
3
4
5
6
7
8
–15 –10
–5
0
5
10
15
1k
10k
100k
FREQUENCY (Hz)
1M
10M
1
10 10 10 10 10 10 10 10
FREQUENCY (Hz)
COMMON MODE INPUT VOLTAGE (V)
1124/25 G08
1124/25 G07
1124/25 G09
5
LT1124/LT1125
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Voltage Gain vs Frequency
Voltage Gain vs Temperature
Gain, Phase Shift vs Frequency
50
40
20
18
16
14
12
10
8
80
180
140
V
= ±15V
= 25°C
V
= ±15V
= 25°C
= 10pF
S
A
S
A
L
LT1124AM/LT1125AM
T
T
100
C
Ø
R = 10k
L
120
30
20
LT1124M/LT1125M
100
60
V
OUT
= ±15V
S
140
160
±
= 10V
V
GAIN
10
6
R = 2k
L
LT1124AM/LT1125AM
20
4
0
180
200
2
LT1124M/LT1125M
–10
0
–20
0.01
0.1
1
10
100
–75 –50 –25
0
25 50 75 100 125
1
100
10k
1M
100M
FREQUENCY (MHz)
TEMPERATURE (°C)
FREQUENCY (Hz)
1124/25 G12
1124/25 G11
1124/25 G10
Offset Voltage Drift with
Temperature of Representative
Units
Input Offset Voltage Drift
Distribution
Supply Current vs Supply Voltage
50
40
3
2
1
0
40
V = ±15V
S
V
S
= ±15V
200 N8
100 S8
96 J8
125°C
25°C
30
396 UNITS TESTED
30
20
20
10
–55°C
0
–10
–20
–30
–40
–50
10
0
–50 –25
0
25
50
75 100 125
0
±5
±10
±15
±20
–0.8
–0.4
0
0.4
0.8
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
1124/25 G14
1124/25 G15
1124/25 G13
Output Voltage Swing vs
Load Current
Small-Signal Transient Response
Large-Signal Transient Response
+
V
–0.8
–1.0
–1.2
–1.4
–1.6
V
S
= ±3V TO ±18V
125°C
50mV
0
10V
25°C
–55°C
0
–10V
1.2
1.0
0.8
0.6
0.4
–50mV
–55°C
125°C
25°C
1124/25 G16
1124/25 G17
AVCL = +1
AVCL = –1
VS = ±15V
VS = ±15V or ±5V
–
CL = 15pF
V
–10 –8 –6 –4 –2
0
2
4
6
8
10
I
I
SOURCE
SINK
OUTPUT CURRENT (mA)
1124/25 G18
6
LT1124/LT1125
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Common Mode Limit vs
Temperature
Channel Separation vs Frequency
Warm-Up Drift
+
V
180
160
140
10
8
–0.5
–1.0
V
= ±15V
= 25°C
S
A
LIMITED BY
THERMAL INTERACTION
T
–1.5
–2.0
–2.5
+
SO PACKAGE
V
= 3V TO 18V
120
100
80
V
= ±15V
S
L
6
R
= 2k
V
T
= 7V
OUT
P-P
= 25°C
A
N, J PACKAGES
4
2.5
2.0
–
V
= –3V TO –18V
60
40
20
0
LIMITED BY PIN
TO PIN CAPACITANCE
1.5
2
0
1.0
0.5
–
V
–60
–20
20
60
100
140
0
100
1k
10k 100k 1M
10M
0
1
2
3
4
5
TEMPERATURE (°C)
FREQUENCY (Hz)
TIME AFTER POWER ON (MINUTES)
1124/25 G19
1124/25 G20
1124/25 G21
Total Harmonic Distortion
and Noise vs Frequency for
Noninverting Gain
Total Harmonic Distortion
and Noise vs Frequency for
Inverting Gain
Total Harmonic Distortion
and Noise vs Frequency for
Competitive Devices
0.1
0.010
0.1
0.1
0.010
Z
V
A
= 2k/15pF
= 20Vp-p
= –10
Z
= 2k/15pF
Z
= 2k/15pF
L
O
V
L
O
V
L
O
V
V
A
= 20V
V
A
= 20Vp-p
P-P
= +1, +10, +100
= –1, –10, –100
MEASUREMENT BANDWIDTH
= 10Hz TO 80kHz
MEASUREMENT BANDWIDTH
= 10Hz TO 80kHz
MEASUREMENT BANDWIDTH
= 10Hz TO 80kHz
0.010
0.001
A
= +100
V
A
= –100
A
OP270
V
A
= +10
V
OP27
LT1124
= –10
V
0.001
0.001
A
= +1
V
A
= –1
V
0.0001
0.0001
0.0001
20
100
1k
FREQUENCY (Hz)
10k 20k
20
100
1k
FREQUENCY (Hz)
10k 20k
20
100
1k
FREQUENCY (Hz)
10k 20k
1124/25 G24
1124/25 G22
1124/25 G23
Total Harmonic Distortion and
Noise vs Output Amplitude for
Noninverting Gain
Total Harmonic Distortion and
Noise vs Output Amplitude for
Inverting Gain
Intermodulation Distortion
(CCIF Method)* vs Frequency
LT1124 and OP270
1
0.1
0.010
0.001
1
0.1
Z
f
= 2k/15pF
= 1kHz
Z = 2k/15pF
L
f (IM) = 1kHz
Z
f
= 2k/15pF
= 1kHz
L
L
O
O
A
= +1, +10, +100
f
V
A
= 13.5kHz
= 20Vp-p
= –10
A
= –1, –10, –100
V
O
O
V
V
MEASUREMENT BANDWIDTH
= 10Hz TO 22kHz
MEASUREMENT BANDWIDTH
= 10Hz TO 22kHz
MEASUREMENT BANDWIDTH
= 10Hz TO 80kHz
A
= +100
V
OP270
0.010
0.001
0.0001
0.010
0.001
0.0001
A
= –100
V
A
= +10
V
A
= –10
V
A
= –1
LT1124
A
= +1
1
V
V
0.0001
0.3
10
)
30
0.3
1
10
OUTPUT SWING (Vp-p)
30
3k
10k
20k
OUTPUT SWING (V
FREQUENCY (Hz)
P-P
1124/25 G25
1124/25 G26
1124/25 G27
*See LT1115 data sheet for definition of CCIF testing
7
LT1124/LT1125
O U
W
U
PPLICATI
A
S I FOR ATIO
The LT1124 may be inserted directly into OP-270 sockets.
The LT1125 plugs into OP-470 sockets. Of course, all
standard dual and quad bipolar op amps can also be
replaced by these devices.
(5µV/V). However, Table 1 can be used to estimate the
expected matching performance between the two sides of
the LT1124, and between amplifiers A and D, and between
amplifiers B and C of the LT1125.
Matching Specifications
Offset Voltage and Drift
In many applications the performance of a system de-
pends on the matching between two op amps, rather than
the individual characteristics of the two devices. The three
op amp instrumentation amplifier configuration shown in
thisdatasheetisanexample. Matchingcharacteristicsare
not 100% tested on the LT1124/LT1125.
Thermocouple effects, caused by temperature gradients
across dissimilar metals at the contacts to the input
terminals, can exceed the inherent drift of the amplifier
unless proper care is exercised. Air currents should be
minimized, package leads should be short, the two input
leadsshouldbeclosetogetherandmaintainedatthesame
temperature.
Some specifications are guaranteed by definition. For
example, 70µV maximum offset voltage implies that mis-
match cannot be more than 140µV. 112dB (= 2.5µV/V)
CMRR means that worst case CMRR match is 106dB
The circuit shown in Figure 1 to measure offset voltage is
also used as the burn-in configuration for the LT1124/
LT1125, with the supply voltages increased to ±16V.
50k*
15V
–
+
100Ω*
V
OUT
50k*
–15V
V
= 1000V
OS
OUT
*RESISTORS MUST HAVE LOW
THERMOELECTRIC POTENTIAL
1124/25 F01
Figure 1. Test Circuit for Offset Voltage
and Offset Voltage Drift with Temperature
Table 1. Expected Match
PARAMETER
LT1124AC/AM
LT1125AC/AM
LT1124C/M
LT1125C/M
50% YIELD
98% YIELD
110
50% YIELD
98% YIELD
130
UNITS
µV
V
Match, ∆V
LT1124
LT1125
20
30
30
50
0.5
7
OS
OS
150
180
µV
Temperature Coefficient Match
Average Noninverting I
0.35
6
1.0
1.5
µV/°C
nA
18
25
B
Match of Noninverting I
CMRR Match
7
22
8
30
nA
B
126
127
115
123
127
112
dB
PSRR Match
118
114
dB
8
LT1124/LT1125
O U
W
U
PPLICATI
A
S I FOR ATIO
High Speed Operation
During the fast feedthrough-like portion of the output, the
input protection diodes effectively short the output to the
input and a current, limited only by the output short circuit
protection, will be drawn by the signal generator. With RF
≥500Ω, the output is capable of handling the current
requirements (IL ≤ 20mA at 10V) and the amplifier stays
in its active mode and a smooth transition will occur.
When the feedback around the op amp is resistive (RF),
a pole will be created with RF, the source resistance and
capacitance (RS, CS), and the amplifier input capacitance
(CIN ≈2pF). In low closed loop gain configurations and
with RS and RF in the kilohm range, this pole can create
excessphaseshiftandevenoscillation. Asmallcapacitor
(CF) in parallel with RF eliminates this problem (see
Figure 2). With RS (CS + CIN) = RFCF, the effect of the
feedback pole is completely removed.
Noise Testing
Each individual amplifier is tested to 4.2nV/√Hz voltage
noise; i.e., for the LT1124 two tests, for the LT1125 four
tests are performed. Noise testing for competing multiple
op amps, if done at all, may be sample tested or tested
using the circuit shown in Figure 4.
C
F
R
F
e
n OUT = √(enA)2 + (enB)2 + (enC)2 + (enD)2
–
+
If the LT1125 were tested this way, the noise limit would
be √4 • (4.2nV/√Hz)2 = 8.4nV/√Hz. But is this an effective
screen? What if three of the four amplifiers are at a typical
2.7nV/√Hz, and the fourth one was contaminated and has
6.9nV/√Hz noise?
C
IN
OUTPUT
R
S
C
S
1124/25 F02
Figure 2. High Speed Operation
RMS Sum = √(2.7)2 + (2.7)2 + (2.7)2 + (6.9)2 = 8.33nV/√Hz
Unity Gain Buffer Applications
This passes an 8.4nV/√Hz spec, yet one of the amplifiers
is 64% over the LT1125 spec limit. Clearly, for proper
noise measurement, the op amps have to be tested
individually.
When RF ≤ 100Ω and the input is driven with a fast, large
signal pulse (>1V), the output waveform will look as
shown in Figure 3.
R
F
–
OUT
–
D
+
C
–
–
+
+
–
+
B
4.5V/µs
OUTPUT
+
A
1124/25 F03
1124/25 F04
Figure 3. Unity-Gain Buffer Applications
Figure 4. Competing Quad Op Amp Noise Test Method
9
LT1124/LT1125
W U
W
U
PERFOR A CE CO PARISO
Table 2 summarizes the performance of the LT1124/
LT1125 compared to the low cost grades of alternate
approaches.
but in most cases are superior. Normally dual and quad
performance is degraded when compared to singles, for
the LT1124/LT1125 this is not the case.
The comparison shows how the specs of the LT1124/
LT1125 not only stand up to the industry standard OP-27,
Table 2. Guaranteed Performance, VS = ±15V, TA = 25°C, Low Cost Devices
LT1124CN8
LT1125CN
PARAMETER/UNITS
OP-27 GP
OP-270 GP
OP-470 GP
UNITS
Voltage Noise, 1kHz
4.2
4.5
–
5.0
nV/√Hz
100% Tested
Sample Tested
No Limit
Sample Tested
Slew Rate
2.7
1.7
Not Tested
1.7
1.4
V/µs
100% Tested
Gain Bandwidth Product
8.0
5.0
Not Tested
–
–
MHz
100% Tested
No Limit
No Limit
Offset Voltage
Offset Current
LT1124
LT1125
100
140
100
–
250
–
–
µV
µV
1000
LT1124
LT1125
20
30
75
–
20
–
–
30
nA
nA
Bias Current
30
2.75
80
5.67
0.7
60
3.25
0.35
90
60
2.75
0.4
100
105
–
nA
mA
V/µV
dB
Supply Current/Amp
Voltage Gain, R = 2k
1.5
L
Common Mode Rejection Ratio
Power Supply Rejection Ratio
SO-8 Package
106
100
94
110
104
No
dB
Yes - LT1124
Yes
U
O
TYPICAL APPLICATI S
Gain 1000 Amplifier with 0.01% Accuracy, DC to 1Hz
Gain Error vs Frequency Closed-Loop Gain = 1000
1.0
20k
TRIM
340k
1%
15k
5%
TYPICAL
PRECISION
OP AMP
15V
6 (S0-8)
8 (N8)
365Ω
0.1
1%
2
–
1/2 LT1124
OUTPUT
7 (SO-8)
1 (N8)
3
LT1124/LT1125
0.01
+
4
RN60C FILM RESISTORS
–15V
INPUT
CLOSED-LOOP GAIN
GAIN ERROR =
THE HIGH GAIN AND WIDE BANDWIDTH OF THE LT1124/LT1125, IS USEFUL IN LOW
FREQUENCY HIGH CLOSED-LOOP GAIN AMPLIFIER APPLICATIONS. A TYPICAL
PRECISION OP AMP MAY HAVE AN OPEN-LOOP GAIN OF ONE MILLION WITH 500kHz
BANDWIDTH. AS THE GAIN ERROR PLOT SHOWS, THIS DEVICE IS CAPABLE OF 0.1%
AMPLIFYING ACCURACY UP TO 0.3Hz ONLY. EVEN INSTRUMENTATION RANGE
SIGNALS CAN VARY AT A FASTER RATE. THE LT1124/LT1125 “GAIN PRECISION —
OPEN-LOOP GAIN
0.001
0.1
1
10
100
FREQUENCY (Hz)
1124/25 TA04
BANDWIDTH PRODUCT” IS 75 TIMES HIGHER, AS SHOWN.
1124/25 TA03
10
LT1124/LT1125
W
W
SCHE ATIC DIAGRA
(1/2 LT1124, 1/4 LT1125)
+
V
360µA
570µA
100µA
Q7
Q28
200pF
21k
21k
3.6k
3.6k
35pF
Q27
Q18
20Ω
Q9
Q13
Q8
Q25
OUTPUT
Q26
Q17
Q10
900Ω
Q19
Q20
20Ω
–
V
NONINVERTING
INPUT (+)
Q2A
Q1A Q1B
400Ω
Q30
Q2B
67pF
20pF
+
V
Q3
INVERTING
INPUT (–)
Q29
+
V
Q22
Q11
Q23
6k
Q12 Q15
Q16
Q24
200µA
200µA
100µA
200Ω 6k
200Ω
50Ω
–
V
1124/25 SS
11
LT1124/LT1125
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
J8 Package
8-Lead CERDIP (Narrow 0.300, Hermetic)
(LTC DWG # 05-08-1110)
0.405
(10.287)
MAX
CORNER LEADS OPTION
(4 PLCS)
0.005
(0.127)
MIN
6
5
4
8
7
2
0.023 – 0.045
(0.584 – 1.143)
HALF LEAD
OPTION
0.025
(0.635)
RAD TYP
0.220 – 0.310
(5.588 – 7.874)
0.045 – 0.068
(1.143 – 1.727)
FULL LEAD
OPTION
1
3
0.200
0.300 BSC
(5.080)
MAX
(0.762 BSC)
0.015 – 0.060
(0.381 – 1.524)
0.008 – 0.018
(0.203 – 0.457)
0° – 15°
0.045 – 0.068
(1.143 – 1.727)
0.125
3.175
MIN
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
0.100 ± 0.010
0.014 – 0.026
J8 1197
(2.540 ± 0.254)
(0.360 – 0.660)
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
8
7
6
5
4
0.255 ± 0.015*
(6.477 ± 0.381)
1
2
3
0.130 ± 0.005
0.300 – 0.325
0.045 – 0.065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
0.125
0.020
(0.508)
MIN
(3.175)
MIN
+0.035
0.325
–0.015
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
+0.889
8.255
(
)
N8 1197
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
12
LT1124/LT1125
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
5
8
6
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.053 – 0.069
3
4
2
0.010 – 0.020
(0.254 – 0.508)
× 45°
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 0996
13
LT1124/LT1125
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
J Package
14-Lead CERDIP (Narrow 0.300, Hermetic)
(LTC DWG # 05-08-1110)
0.785
(19.939)
MAX
0.005
(0.127)
MIN
14
13
12
11
10
9
8
0.220 – 0.310
0.025
(5.588 – 7.874)
(0.635)
RAD TYP
2
3
4
5
6
1
7
0.200
(5.080)
MAX
0.300 BSC
(0.762 BSC)
0.015 – 0.060
(0.381 – 1.524)
0.008 – 0.018
(0.203 – 0.457)
0° – 15°
0.045 – 0.068
0.100 ± 0.010
0.125
(1.143 – 1.727)
(2.540 ± 0.254)
(3.175)
MIN
0.014 – 0.026
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
(0.360 – 0.660)
J14 1197
N Package
14-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.770*
(19.558)
MAX
14
13
12
11
10
9
8
7
0.255 ± 0.015*
(6.477 ± 0.381)
1
2
3
5
6
4
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.020
(0.508)
MIN
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.035
0.325
0.005
(0.125)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
–0.015
0.125
(3.175)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
+0.889
8.255
(
)
–0.381
N14 1197
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
14
LT1124/LT1125
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
SW Package
16-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.398 – 0.413*
(10.109 – 10.490)
15 14 12
10
11
9
16
13
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
2
3
5
7
8
1
4
6
0.291 – 0.299**
(7.391 – 7.595)
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
0.010 – 0.029
(0.254 – 0.737)
× 45°
0° – 8° TYP
0.050
(1.270)
TYP
0.004 – 0.012
(0.102 – 0.305)
0.009 – 0.013
NOTE 1
(0.229 – 0.330)
0.014 – 0.019
0.016 – 0.050
(0.356 – 0.482)
TYP
(0.406 – 1.270)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
S16 (WIDE) 0396
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LT1124/LT1125
U
TYPICAL APPLICATION
Strain Gauge Signal Conditioner with Bridge Excitation
15V
5k
1k
3
THE LT1124/LT1125 IS CAPABLE OF PROVIDING EXCITATION CURRENT DIRECTLY
+
2.5V
TO BIAS THE 350Ω BRIDGE AT 5V WITH ONLY 5V ACROSS THE BRIDGE (AS OPPOSED
TO THE USUAL 10V) TOTAL POWER DISSIPATION AND BRIDGE WARM-UP DRIFT IS
REDUCED. THE BRIDGE OUTPUT SIGNAL IS HALVED, BUT THE LT1124/LT1125 CAN
AMPLIFY THE REDUCED SIGNAL ACCURATELY.
1
1/4
LT1125
–
LT1009
2
–15V
REFERENCE
OUTPUT
350Ω
BRIDGE
15V
5
6
4
+
–
7
1/4
LT1125
0V TO 10V
OUTPUT
301k*
10k
ZERO
TRIM
13
–15V
1µF
301k*
15V
1/4
13
12
–
50k
14
499Ω*
GAIN
TRIM
LT1125
+
1k
*RN60C FILM RESISTORS
1124/25 TA05
–15V
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1007
Single Low Noise, Precision Op Amp
Single Low Noise, Precision Op Amps
Dual/Quad Precision Picoamp Input
Dual Low Noise JFET Op Amp
Decompensated LT1124/LT1125
Dual Low Noise JFET Op Amp
Single LT1113
2.5nV/√Hz 1kHz Voltage Noise
0.85nV/√Hz Voltage Noise
LT1028/LT1128
LT1112/LT1114
LT1113
250pA Max I
B
4.5nV/√Hz Voltage Noise, 10fA/√Hz Current Noise
11V/µs Slew Rate
LT1126/LT1127
LT1169
6nV/√Hz Voltage Noise, 1fA/√Hz Current Noise, 10pA Max I
4.2nV/√Hz Voltage Noise, 10fA/√Hz Current Noise
6nV/√Hz Voltage Noise, 1fA/√Hz Current Noise, 10pA Max I
B
LT1792
LT1793
Single LT1169
B
11245fas, sn11245 LT/TP 0699 REV A 2K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1992
16 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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