LT1166CN8 [Linear]
Power Output Stage Automatic Bias System; 功率输出级自动偏置系统型号: | LT1166CN8 |
厂家: | Linear |
描述: | Power Output Stage Automatic Bias System |
文件: | 总16页 (文件大小:458K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LT1166
Power Output Stage
Automatic Bias System
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FEATURES
DESCRIPTION
The LT®1166 is a bias generating system for controlling
class AB output current in high powered amplifiers. When
connected with external transistors, the circuit becomes a
unity-gain voltage follower. The LT1166 is ideally suited
for driving power MOSFET devices because it eliminates
all quiescent current adjustments and critical transistor
matching. Multiple outputstages using theLT1166 canbe
paralleled to obtain higher output current.
■
Set Class AB Bias Currents
■
Eliminates Adjustments
■
Eliminates Thermal Runaway of IQ
■
Corrects for Device Mismatch
■
Simplifies Heat Sinking
■
Programmable Current Limit
■
May Be Paralleled for Higher Current
■
Small SO-8 or PDIP Package
Thermal runaway of the quiescent point is eliminated
because the bias system senses the current in each power
transistor by using a small external sense resistor. A high
speed regulator loop controls the amount of drive applied
to each power device. TheLT1166canbebiasedfromapair
ofresistorsorcurrentsourcesandbecauseitoperatesonthe
drive voltage to the output transistors, it operates on any
supply voltage.
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APPLICATIONS
■
Biasing Power MOSFETs
High Voltage Amplifiers
Shaker Table Amplifiers
Audio Power Amplifiers
■
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATION
Unity Gain Buffer Amp Driving 1Ω Load
R1
15V
MPS2907
+
100Ω
47Ω
220µF
R2
2N2907
100Ω
IRF530
1
I
= 15mA
TOP
300pF
INPUT
0V
V
TOP
5.6k
8
7
+
SENSE
1k
+
I
LIM
+
–
R
SENSE
1µF
0.33Ω
4.3k
3
2
V
OUT
V
V
V
LT1166
OUT
IN
IN
R
1Ω
SENSE
1µF
0.33Ω
1k
6
5
–
I
LIM
OUTPUT
0V
–
SENSE
V
BOTTOM
R3
100Ω
4
I
= 15mA
BOTTOM
IRF9530
1166 • TA01
300pF
–15V
2N2222
220µF
+
R4
100Ω
47Ω
1166 • F01
MPS2222
Figure 1. Unity Gain Buffer with Current Limit
1
LT1166
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ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
Supply Current (Pin 1 or Pin 4) ............................ 75mA
Differential Voltage (Pin 2 to Pin 3) ......................... ±6V
Output Short-Circuit Duration (Note 1).........Continuous
Specified Temperature Range (Note 2)........ 0°C to 70°C
Operating Temperature Range ................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Junction Temperature (Note 3)............................ 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
TOP VIEW
NUMBER
+
V
1
2
3
4
SENSE
+
8
7
6
5
TOP
+1
V
I
LT1166CN8
LT1166CS8
IN
LIM
–
V
I
OUT
LIM
–
V
SENSE
BOTTOM
S8 PART MARKING
1166
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 100°C/ W (N8)
TJMAX = 150°C, θJA = 150°C/ W (S8)
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
Pin 1 = 2V, Pin 4 = –2V, Operating current 15mA and RIN = 20k, unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
50
2
15
20
MAX
250
10
UNITS
mV
µA
MΩ
mV
mV
V
Output Offset Voltage
Input Bias Current
Input Resistance
Operating Current 15mA to 50mA
Operating Current 15mA to 50mA (Note 4)
Operating Current 15mA to 50mA (Note 5)
Measure Pin 8 to Pin 3, No Load
Measure Pin 5 to Pin 3, No Load
Operating Current = 50mA (Notes 6, 9)
Operating Voltage = ±2V
●
●
●
2
14
–14
±2
±4
V
V
(Top)
(Bottom)
26
AB
AB
–20
–26
±10
±50
Voltage Compliance
Current Compliance
Transconductance
●
●
mA
(Note 7)
gm
gm
gm
gm
Pin 1 = 2V, Pin 4 = – 2V
Pin 1 = 2V, Pin 4 = –2V
Pin 1 = 10V, Pin 4 = –10V
Pin 1 = 10V, Pin 4 = –10V
●
●
●
●
0.08
0.08
0.09
0.09
0.100
0.100
0.125
0.125
0.13
0.13
0.16
0.16
mho
mho
mho
mho
CC2
EE2
CC10
EE10
PSRR
PSRR
(Note 8)
(Note 8)
19
19
dB
dB
CC
EE
Current Limit Voltage
Operating Current 15mA to 50mA
Pin 7 Voltage to Pin 3
Pin 6 Voltage to Pin 3
●
●
1.0
–1.0
1.3
–1.3
1.5
–1.5
V
V
The
●
denotes specifications which apply over the full operating
Note 5: The input resistance is typically 15MΩ when the loop is closed.
When the loop is open (current limit) the input resistance drops to 200Ω
referred to Pin 3.
temperature range.
Note 1: External power devices may require heat sinking.
Note 6: Maximum T can be exceeded with 50mA operating current and
simultaneous 10V and –10V (20V total).
Note 7: Apply ±200mV to Pin 2 and measure current change in Pin 1
and 4. Pin 3 is grounded.
J
Note 2: Commercial grade parts are designed to operate over the
temperature range of –40°C to 85°C but are neither tested nor guaranteed
beyond 0°C to 70°C. Industrial grade parts specified and tested over
–40°C and 85°C are available on special request, consult factory.
PSRR = gm
Note 8:
– gm
Note 3: T calculated from the ambient temperature T and the power
CC
CC2
CC10
J
A
dissipation P according to the following formulas:
D
gm
CC2
LT1166CN8: T = T + (P • 100°C/W)
J
A
D
PSRR = gm – gm
EE EE2
EE10
LT1166CS8: T = T + (P • 150°C/W)
J
A
D
gm
EE2
Note 4: I
= I
BOTTOM
TOP
Note 9: For Linear Operation, Pin 1 must not be less than 2V or more than
10V from Pin 3. Similarly, Pin 4 must not be less than 2V or more than
10V from Pin 3.
2
LT1166
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TYPICAL PERFORMANCE CHARACTERISTICS
Output Offset Voltage vs
Temperature
Input Bias Current vs
Current Source Mismatch
Output Offset Voltage vs
Current Source Mismatch
60
55
50
45
40
35
30
150
100
50
800
600
R
= ∞
L
I
= I = 50mA
TOP BOTTOM
I
= I
= 15mA
TOP BOTTOM
R
= 4.3k
IN
R
IN
= 20k
400
I
= I
= 50mA
TOP BOTTOM
200
0
0
R
= 2k
IN
I
= I
= 4mA
TOP BOTTOM
–200
–400
–600
–800
–50
–100
–150
2.5 5.0
50
TEMPERATURE (°C)
100 125
–10 –7.5 –5.0 –2.5
0
7.5 10
0
–50 –25
0
25
75
–1.0 –0.75 –0.5 –0.25
0.25 0.5 0.75 1.0
MISMATCH (mA)
LT1166 • TPC02
CURRENT SOURCE MISMATCH (%)
I
AND I
BOTTOM
TOP
LT1166 • TPC01
LT1166 • TPC03
Input Bias Current vs
Temperature
Open-Loop Voltage Gain vs
Frequency
Output Voltage vs Input Voltage
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
10
8
30
25
R
C
= 4.3k
R
=
∞
R
=
L
∞
IN
1
L
= C = 500pF
2
I
= I
= 15mA
= 4.3k
TOP BOTTOM
R
L
= 10Ω
R
R
=10Ω
6
IN
L
20
SEE FIGURE 8
4
15
2
10
R
= R
= 1k
BOTTOM
TOP
0
5
–2
–4
–6
–8
–10
0
V
= ±15V
S
–5
–10
–15
–20
I
= I
= 12mA
TOP BOTTOM
R
I
= 4.3k
= I
IN
= 12mA
0.1
TOP BOTTOM
C
= C = 500pF
2
1
SEE FIGURE 8
–50
0
25
50
75 100 125
–10 –8 –6 –4
0
2
4
6
8
10
–25
–2
0.001
0.01
1
10
TEMPERATURE (°C)
INPUT VOLTAGE (V)
FREQUENCY (MHz)
LT1166 • TPC05
LT1166 • TPC06
LT1166 • TPC04
Closed-Loop Voltage Gain vs
Frequency
Voltage Across Sense Resistors
vs Temperature
Current Limit Pin Voltage vs
Temperature
24
22
20
18
16
1.25
1.20
2
1
V
= ±1.5V
IN
R
= ∞
L
+
SENSE
0
PIN 7 TO PIN 3
R
L
=10Ω
–1
–2
–3
–4
–5
–6
–7
–8
1.15
–16
–18
–20
–22
–24
–1.15
–1.20
–1.25
V
= ±15V
S
IN
R
I
= 4.3k
= I
= 12mA
PIN 6 TO PIN 3
TOP BOTTOM
C
= C = 500pF
2
–
1
SENSE
SEE FIGURE 8
–50
0
25
50
75 100 125
125
0.001
0.01
0.1
1
10
–25
–50
0
25
50
75 100
–25
FREQUENCY (MHz)
TEMPERATURE (°C)
TEMPERATURE (°C)
LT1166 • TPC07
LT1166 • TPC08
LT1166 • TPC09
3
LT1166
TYPICAL PERFORMANCE CHARACTERISTICS
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Total Harmonic Distortion vs
Frequency
Sense Pin Voltage Referenced to
Input Transconductance vs
Supply Voltage
V
OUT vs Load Current
10
1
1000
100
10
0.120
0.110
0.100
0.090
0.080
R
O
= 10Ω
L
25°C
V
V
TOP
P
= 1W
BOTTOM
SEE FIGURE 8
125°C
–55°C
gm
CC
V
R
R
= ±200mV
IN
L
IN
= 0
= 0
–0.080
–0.090
–0.100
–0.110
–0.120
0.1
0.01
125°C
–55°C
gm
EE
25°C
R
= 100Ω
SENSE
1
10
8
6
4
2
0
2
4
6
8
10
0
1
2
3
4
5
6
7
8
9
10
0.01
0.1
1
10
100
SINKING
SOURCING
SUPPLY VOLTAGE (V)
FREQUENCY (kHz)
LT1166 • TPC12
LT1166 • TPC10
LT1166 • TPC11
LOAD CURRENT (mA)
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PIN FUNCTIONS
VTOP (Pin 1): Pin 1 establishes the top side drive voltage
fortheoutputtransistors. Operatingsupplycurrententers
Pin 1 and a portion biases internal circuitry; Pin 1 current
should be greater than 4mA. Pin 1 voltage is internally
clamped to 12V with respect to VOUT and the pin current
should be limited to 75mA maximum.
SENSE– (Pin 5): The Sense– pin voltage is established
by the current control loop and it controls the output
quiescent current in the bottom side power device. Limit
the maximum differential voltage between Pin 5 and Pin 3
to ±6V during fault conditions.
–
ILIM (Pin 6): The negative side current limit, limits the
VIN (Pin 2): Pin 2 is the input to a unity gain buffer which
drives VOUT (Pin 3). During a fault condition (short circuit)
the input impedance drops to 200Ω and the input current
must be limited to 5mA or VIN to VOUT limited to less than
±6V.
voltage at VBOTTOM to VOUT during a negative fault condi-
tion. The maximum reverse voltage on Pin 6 with respect
to VOUT is 6V.
+
ILIM (Pin 7): The positive side current limit, limits the
voltage at VTOP to VOUT during a positive fault condition.
The maximum reverse voltage on Pin 7 with respect to
VOUT is –6V.
SENSE+ (Pin 8): The Sense+ pin voltage is established by
the current control loop and it controls the output quies-
cent current in the top side power device. Limit the
maximum differential voltage between Pin 8 and Pin 3 to
±6V during fault conditions.
VOUT (Pin 3): Pin 3 of the LT1166 is the output of a voltage
control loop that maintains the output voltage at the input
voltage.
VBOTTOM (Pin 4): Pin 4 establishes the bottom side drive
voltage for the output transistors. Operating supply cur-
rent exits this pin; Pin 4 current should be greater than
4mA. Pin 4 voltage is internally clamped to –12V with
respect to VOUT and the pin current should be limited to
75mA maximum.
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LT1166
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APPLICATIONS INFORMATION
Overvoltage Protection
internal op amps. The feedback of the op amps force the
same voltage on the (–) inputs and these voltages then
appear on the sense resistors in series with the power
devices. The product of the two currents in the power
devices is constant, as one increases the other decreases.
The excellent logging nature of Q9 and Q10 allows this
relation to hold over many decades in current.
The supplies VTOP (Pin 1) and VBOTTOM (Pin 4) have clamp
diodes that turn on when they exceed ±12V. These diodes
act as ESD protection and serve to protect the LT1166
when used with large power MOS devices that produce
high VGS voltage. Current into Pin 1 or Pin 4 should be
limited to ±75mA maximum.
The total current in Q7 and Q8 is actually the sum of IREF
and a small error current from the shunt regulator. During
high output current conditions the error current from the
regulator decreases. Current conducted by the regulator
also decreases allowing VT or VB to increase by an amount
needed to drive the power devices.
Multiplier Operation
Figure 2 shows the current multiplier circuit internal to the
LT1166 and how it works in conjunction with power
output transistors. The supply voltages VT (top) and VB
(bottom) of the LT1166 are set by the required “on”
voltage of the power devices. A reference current IREF sets
a constant VBE7 and VBE8. This voltage is across emitter
base of Q9 and Q10 which are 1/10 the emitter area of Q7
and Q8. The expression for this current multiplier is:
Driving the Input Stage
Figure 3 shows the input transconductance stage of the
LT1166 that provides a way to drive VT and VB. When a
positive voltage VIN is applied to RIN, a small input current
flows into R2 and the emitter of Q2. This effect causes VO
to follow VIN within the gain error of the amplifier. The
input current is then mirrored by Q3/Q4 and current
supplied to Q4’s collector is sourced by power device M1.
The signal current in Q4’s emitter is absorbed by external
resistor RB and this causes VB to rise by the same amount
VBE7 + VBE8 = VBE9 + VBE10
or in terms of current:
(IC9)(IC10) = (IREF)2/100 = Constant
The product of IC9 and IC10 is constant. These currents are
mirrored and set the voltage on the (+) inputs of a pair of
+
V
+
V
R
T
R
T
1k
1k
V
TOP
V
1
M
1
TOP
1
M
1
Q5
× 1
Q6
× 32
I
REF
–
+
C
I
EXT1
REF
10
8
3
5
SHUNT
REGULATOR
Q1
Q2
+
–
V
AB
AB
1Ω
1Ω
Q11
Q12
R1
R2
Q9
× 1
Q7
R
IN
1k
1k
× 10
2
3
V
O
V
O
Q10
× 1
Q8
× 10
V
IN
1Ω
V
1Ω
+
–
Q3
× 1
Q4
× 32
4
M
2
V
BOTTOM
R
B
C
EXT2
4
M
2
1k
–
V
V
BOTTOM
R
B
1166 • F03
1k
–
V
1166 • F02
Figure 3. Input Stage Driving Gates
Figure 2. Constant Product Generator
5
LT1166
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APPLICATIONS INFORMATION
as VIN. Similarly for VT, when positive voltage is applied to
RIN, current that was flowing in R1 and Q1 is now supplied
through RIN. This effect reduces the current in mirror Q5/
Q6.Thereducedcurrenthastheeffectofreducingthedrop
on RT, and VT rises to make VO track VIN.
Driving Capacitive Loads
Ideally, amplifiers have enough phase margin that they
don’t oscillate but just slow down with capacitive loads.
Practically, amplifiers that drive significant power require
some isolation from heavy capacitive loads to prevent
oscillation. This isolation is normally an inductor in series
with the output of the amplifier. A 1µH inductor in parallel
with a 10Ω resistor is sufficient for many applications.
The open-loop voltage gain VO/(VIN – VPIN2) can be
increased by replacing RT and RB with current sources.
The effect of this is to increase the voltage gain VOUT/ VIN
from approximately 0.8 to 1 (see Typical Performance
Characteristics curves). The use of current sources in-
stead of resistors greatly increases loop gain and this
compensates for the nonlinearity of the output stage
resulting in much lower distortion.
Setting Output AB Bias Current
Setting the output AB quiescent current requires no ad-
justments. The internal op amps force VAB = ±20mV
between each Sense (Pins 5 and 8) to the Output (Pin 3).
At quiescent levels the output current is set by:
Frequency Compensation and Stability
IAB = 20mV/RSENSE
The input transconductance is setby theinputresistorRIN
and the 32:1 current mirrors Q3/Q4 and Q5/Q6. The
resistors R1 and R2 are small compared to the value of
RIN. Current in RIN appears 32 times larger in Q4 or Q6,
which drive external compensation capacitors CEXT1 and
CEXT2. These two input signal paths appear in parallel to
give an input transconductance of:
The LT1166 does not require a heat sink or mounting on
the heat sink for thermal tracking. The temperature coef-
ficient of VAB is approximately 0.3%/°C and is set by the
junction temperature of the LT1166 and not the tempera-
ture of the power transistors.
Output Offset Voltage and Input Bias Current
gm = 16/RIN
The output offset voltage is a function of the value of RIN
and the mismatch between external current sources ITOP
and IBOTTOM (see the Typical Performance Characteristics
curves). Any error in ITOP and IBOTTOM match is reduced
by the 32:1 input current mirror, but is multiplied by the
input resistor RIN.
The gain bandwidth is:
16
IN EXT
GBW =
2π(R )(C
)
Depending on the speed of the output devices, typical
values are RIN = 4.3k and CEXT1 = CEXT2 = 500pF giving a
–3dB bandwidth of 1.2MHz (see Typical Performance
Characteristics curves).
Current Limit
The voltage to activate the current limit is ±1.3V. The
simplest way to protect the output transistors is to con-
nect the Current Limit pins 6 and 7 to the Sense pins 5 and
8. A current limit of 1.3A can be set by using 1Ω sense
resistors. To keep the current limit circuit from oscillating
in hard limit, it is necessary to add an RC (1k and 1µF)
between the Sense pin and the ILIM as shown in Figure 1.
To prevent instability it is important to provide good
supply bypassing as shown in Figure 1. Large supply
bypass capacitors (220µF) and short power leads can
eliminate instabilities at these high current levels. The
100Ω resistors (R2 and R3) in series with the gates of the
output devices stop oscillations in the 100MHz region as do
the 100Ω resistors R1 and R4 in Figure 1.
The sense resistors can be tapped up or down to increase
or decrease the current limit without changing AB bias
current in the power transistors. Figure 4 demonstrates
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LT1166
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APPLICATIONS INFORMATION
how tapping the sense resistors gives twice the limit
current or one half the limit current.
devices. Foldback limit simply makes the output current
dependent on output voltage. This scheme puts dissipa-
tion limits on the output devices. The larger the voltage
across the power device, the lower the available output
current. This is represented in Figure 6, Output Voltage vs
Output Current for the circuit of Figure 5.
Foldback current limit can be added to the normal or
“square” current limit by including two resistors (30k
typical) from the power supplies to the ILIM pins as shown
in Figure 5. With square current limit the maximum output
current is independent of the voltage across the power
+
V
200
160
+
SQUARE I
LIM
120
80
1
V
TOP
8
7
3
6
5
+
+
SENSE
+
FOLDBACK I
FOLDBACK I
LIM
40
0.5Ω
0.5Ω
0
I
(2)(I
)
LIM
LIM
–
–40
–80
–120
–160
–200
LIM
R
IN
2
V
OUT
V
V
V
I
LT1166
IN
IN
OUT
–
SQUARE I
LIM
1Ω
1Ω
–
(1/2)(I
)
LIM
LIM
–10 –8 –6 –4 –2
0
2
4
6
8
10
OUTPUT VOLTAGE (V)
–
SENSE
BOTTOM
LT1166 • F06
V
4
Figure 6. Output Current vs Output Voltage
–
V
1166 • F04
Figure 4. Tapping Current Limit Resistors
Driving the Shunt Regulator
15V
20mA
100Ω
It is possible to current drive the shunt regulator directly
without driving the input transconductance stage. This
hastheadvantageofhigherspeedandeliminatestheneed
to compensate the gm stage. With Pin 2 floating, the
LT1166 can be placed inside a feedback loop and
driven through the biasing current sources. The input
transconductance stage remains biased but has no effect
on circuit operation. The RL in Figure 7 is used to modu-
late the op amp supply current with input signal. This op
amp functions as a V-to-I with the supply leads acting as
current source outputs. The load resistor and the positive
input of the op amp are connected to the output of the
LT1166 for feedback to set AV = 1V/V. The capacitor CF
eliminates output VOS due to mismatch between ITOP and
IBOTTOM, and it also forms a pole at DC and a zero at
1/RFCF. The zero frequency is selected to give a –1V/V
gain in the op amp before the phase of the MOSFETs
degenerate the stability of the loop.
30k
IRFR024
1
+
330pF
V
TOP
8
7
3
6
5
+
+
SENSE
1k
I
LIM
10Ω
1µF
5.1k
2
V
OUT
mA
V
V
LT1166
IN
OUT
–
1µF
10Ω
1k
I
LIM
–
SENSE
V
BOTTOM
4
100Ω
IRFR9024
–15V
30k
20mA
330pF
1166 • F05
Figure 5. Unity Gain Buffer Amp with Foldback Current Limit
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LT1166
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APPLICATIONS INFORMATION
APPLICATION CIRCUITS
the output stage. The simplest way to do this is to use
Darlingtondriversandseriesdiodes. Therearenothermal
trackingcircuitsoradjustmentsnecessaryandtheLT1166
does not need to be mounted on the heat sink with the
power devices. RTOP and RBOTTOM can be used to replace
ITOP and IBOTTOM; see Typical Characteristics curves.
Bipolar Buffer
Similar to the unity gain buffer in Figure 1, the LT1166 can
be used to bias bipolar transistors as shown in Figure 8.
The minimum operating voltage for the LT1166 is ±2V, so
it is necessary to bias the part with adequate voltage from
15V
+
47Ω
220µF
100Ω
2N2907
R
TOP
2N2907
I
=
TOP
15mA
100Ω
2N2222
500pF
+
1
V
V
TOP
I
IN4001
T
8
7
3
6
5
5.6k
+
+
SENSE
M1
TIP29
1Ω
1
I
LIM
V
TOP
8
7
3
6
5
+
+
150Ω
150Ω
SENSE
C
F
4.7k
2
R
–
+
F
V
OUT
V
IN
V
IN
V
I
LT1166
OUT
10Ω
I
1Ω
LIM
R
IN
–
1Ω
1Ω
V
IN
LIM
2
V
OUT
V
IN
V
LT1166
OUT
–
TIP30
–
SENSE
BOTTOM
V
IN4001
2N2907
I
LIM
4
100Ω
R
L
–
I
=
BOT
SENSE
BOTTOM
500pF
15mA
V
4
2N2222
R
BOTTOM
M2
100Ω
2N2222
I
B
220µF
+
47Ω
–
V
1166 • F08
–15V
1166 • F07
Figure 7. Current Source Drive
Figure 8. Bipolar Buffer Amp
8
LT1166
U
W U U
APPLICATIONS INFORMATION
Adding Voltage Gain
The circuit in Figure 9 adds voltage gain to the circuit in
Figure 1. At low frequency the LT1166 is in the feedback
loop of the LT1360 so the gain error and the VOS are
reduced and the closed-loop gain is 10V/V.
15V
+
110Ω
LT1004-2.5
440µF
MPS2907
5.1k
15mA
100Ω
IRF530
300pF
1
V
T
8
+
SENSE
0.1µF
1k
7
+
I
LIM
3
2
0.33Ω
0.33Ω
V
+
–
1µF
LT1166
IN
7
4
39k
3
2
6
V
V
V
OUT
LT1360
OUT
IN
1k
1Ω
1µF
6
5
–
I
LIM
1k
–
SENSE
C
V
F
BOT
0.1µF
500pF
4
100Ω
15mA
IRF9530
5.1k
MPS2222
300pF
LT1004
2.5
110Ω
–15V
909Ω
1166 • F09
440µF
+
100Ω
500pF
Figure 9. Power Op Amp AV = 10
INPUT
INPUT
0V
0V
0V
0V
OUTPUT
OUTPUT
1166 • F10
1166 • F11
Figure 10. Power Amp Driving 1Ω Load
Figure 11. Power Amp at 6A Current Limit
9
LT1166
U
W U U
APPLICATIONS INFORMATION
1A Adjustable Voltage Reference
common mode voltage to its output. The following appli-
cations utilize amplifiers operating in suspended-supply
operation (Figure 13). See “Linear Technology Magazine”
Volume IV Number 2 for a discussion of suspended
supplies. The gain setting resistors used in suspended-
supplyoperationmustbetighttoleranceorthegainwillbe
wrong. For example: with 1% resistors the gain can be as
far off as 75%, but with 0.1% resistors that error is cut to
less than 5%. Using the values shown in Figure 13, the
formula for computing the gain is:
ThecircuitinFigure12usestheLT1166inafeedbackloop
with the LT1431 to make a voltage reference with an
“attitude.” This 5V reference can drive ±1A and maintain
0.4% tolerance at the output. If other output voltages are
desired, external resistors can be used instead of the
LT1431’s internal 5k resistors.
HIGH VOLTAGE APPLICATION CIRCUITS
In order to use op amps in high voltage applications it is
necessary to use techniques that confine the amplifier’s
R8(R9 + R10)
(R8 • R9) – (R7 • R10)
A =
V
= –11.22
12V
100Ω
100Ω
12V
IRF530
1
V
TOP
8
+
SENSE
1k
7
3
6
5
12V
1k
+
I
LIM
1Ω
1Ω
1µF
2k
2
5V
V
IN
V
LT1166
OUT
OUT
4
7
8
3
1
+
1µF
220µF
+
R
R
TOP
REF
V
COL
MID
–
I
LIM
1k
5k
+
–
–
SENSE
BOTTOM
V
5k
2.5V
4
100Ω
IRF9530
LT1431
GND
FORCE
100Ω
–
GND/SENSE
5
6
1166 • F12
Figure 12. ±1A, 5V Voltage Reference
R8
1k
R7
10k
–
IN
OUT
+
R10
1k
R9
9.1k
1166 • F13
Figure 13. Op Amp in Suspended-Supply Operation
10
LT1166
U
W U U
APPLICATIONS INFORMATION
Parallel Operation
resistors, the FET RON resistance at 10A, and some
sagging of the power supply, the circuit of Figure 14
actuallydelivers350WRMSinto8Ω.Performancephotos
and a THD vs frequency plot are included in Figure 15
through 18. Frequency compensation is provided by the
2k input resistor, 180µH inductor and the 1nF compensa-
tion capacitors. The common node in the auxiliary power
supplies is connected to amplifier output to generate the
floating ±15V supplies.
Parallel operation is an effective way to get more output
power by connecting multiple power drivers. All that is
required is a small ballast resistor to ensure current
sharing between the drivers and an isolation inductor to
keep the drivers apart at high frequency. In Figure 14 one
power slice can deliver ±6A at 100VPK, or 300W RMS into
16Ω. The addition of another slice boosts the power
output to 600W RMS into 8Ω and the addition of two or
more drivers theoretically raises the power output to
1200W RMS into 4Ω. Due to IR loss across the sense
POWER SLICE
15V
R1
100Ω
+
10µF
FB
100V
2N3906
R2
100Ω
IRF230
R15
390Ω
1nF
1
V
TOP
SENSE
8
+
R9*
9.1k
R10*
1k
LT1004-2.5
12.5V
R5
1k
7
+
I
LIM
3
2
7
R3
0.22Ω
C1
R
IN
+
LT1166
V
1µF
2k
3
C4
0.1µF
2
6
R14
1k
V
LT1360
4
OUT
IN
180µH
C2
1µF
R4
0.22Ω
R17
0.22Ω
R6
1k
–
6
5
–
–
I
LIM
R7*
10k
R8*
1k
V
IN
L1**
0.4µH
SENSE
BOTTOM
4
–12.5V
V
R11
100Ω
R16
390Ω
IRF9240
1nF
FB
–100V
LT1004-2.5
2N3904
+
R13
200Ω
10µF
R12
100Ω
–15V
C3
3300pF
POWER SLICE
+
7815
15V
~
C7
C5
+
+
1000µF
220µF
35V
25V
L3***
1.5µH
DIODE
BRIDGE
110V
AC
1Ω
C8
C6
+
+
1000µF
220µF
35V
25V
10A
FAST-BLOW
7915
–
–15V
~
1166 • F14
V
OUT
AUXILARY SUPPLIES
* 0.1% RESISTORS
** 4 TURNS T37-52 (MICROMETALS)
*** 6 TURNS T80-52 (MICROMETALS)
Figure 14. 350W Shaker Table Amplifier
11
LT1166
U
W U U
APPLICATIONS INFORMATION
1166 • F15
1166 • F17
Figure 17. 2kHz Square-Wave, CL = 1µF
Figure 15. 0.3% THD at 10kHz, PO = 350W, RL = 8Ω
1.0
P
= 350W
= 8Ω
O
L
R
0.1
0.01
100
10k
10
1k
100k
FREQUENCY (Hz)
LT1166 • F18
1166 • F16
Figure 16. Clipping at 1kHz, RL = 8Ω
Figure 18. THD vs Frequency
100W Audio Power Amplifier
The function of U3 is to drive the gates of M1 and M2. This
amplifier’s real output is not point C as it appears, but
rather the Power Supply pins. Current through R6 is used
to modulate the supply current and thus provide drive to
VTOP and VBOTTOM. Because the output impedance of U3
(through its supply pins) is very high, it is not able to drive
the capacitive inputs of M1 and M2 with the combination
of speed and accuracy needed to have very low distortion
at 20kHz. The purposes of U2 are to drive the gate
capacitance of M1 and M2 through its low output imped-
ance and to reduce the nonlinearty of the M1 and M2
transconductance. R24, C4 set a frequency above which
U2 no longer looks after U3 and U4, but just looks after
itself as its gain goes through unity. R1/R2 and C2/C3 are
compensation components for the CMRR feedthough.
Curves showing the performance of the amplifier are
shown in Figures 20 through 22.
The details of a low distortion audio amplifier are shown in
Figure 19. The LT1360, designated U1, was chosen for its
goodCMRRandisoperatedinsuspended-supplymodeat
a closed-loop gain of –26.5V/V. The ±15V supplies of U1
are effectively bootstrapped by the output at point D and
are generated as shown in Figure 14. A 3VP-P signal at VIN
will cause an 80VPP output at point A. Resistors 7 to 10 set
the gain of –26.5V/V of U1, while C1 compensates for the
additional pole generated by the CMRR of U1. The rest of
the circuit (point A to point D) is an ultralow distortion
unity-gain buffer.
The main component in the unity-gain buffer is U4
(LT1166). This controller performs two important func-
tions, first it modifies the DC voltage between the gates of
M1 and M2 by keeping the product of the voltage across
R20 and R21 constant. Its secondary role is to perform
current limit, protecting M1 and M2 during short circuit.
12
LT1166
U
W U U
APPLICATIONS INFORMATION
13
LT1166
U
W U U
APPLICATIONS INFORMATION
1166 • F20
1166 • F21
RL = 8Ω
f = 8kHz
RL = 8Ω
f = 20kHz
Figure 20. Square Wave Response Into 8Ω
Figure 21. 100W 20kHz Sine Wave and Its Distortion
0.1
R
= 8Ω
L
POWER OUT = 100W
0.01
0.001
10
100
1k
FREQUENCY (Hz)
10k
100k
LT1166 • F21
Figure 22. THD vs Frequency
14
LT1166
W
W
SI PLIFIED SCHEMATIC
V
1
8
TOP
Q5
× 1
Q6
× 32
I
REF
–
+
+
SENSE
+
V
AB
I
REF
10
SHUNT
REGULATOR
Q1
+
7
3
6
I
LIM
R1
Q9
× 1
Q7
200Ω
Q11
Q12
1k
1k
× 10
V
IN
2
V
OUT
R2
200Ω
Q10
× 1
Q8
× 10
–
I
LIM
Q2
–
V
AB
+
–
–
5
4
SENSE
Q3
× 1
Q4
× 32
V
BOTTOM
1166 • SS
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
8
7
6
5
4
0.255 ± 0.015*
(6.477 ± 0.381)
1
2
3
0.130 ± 0.005
0.300 – 0.325
0.045 – 0.065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
0.125
(3.175)
MIN
0.005
(0.127)
MIN
0.015
+0.025
–0.015
(0.380)
MIN
0.325
+0.635
8.255
(
)
–0.381
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
N8 0695
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LT1166
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
5
8
6
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
3
4
2
0.010 – 0.020
(0.254 – 0.508)
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
SO8 0695
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1010
Fast ±150mA Power Buffer
Ideal for Boosting Op Amp Output Current
LT1105
Off-Line Switching Regulator
250mA/60MHz Current Feedback Amplifier
1A/40MHz Current Feedback Amplifier
10A High Efficiency Switching Regulator
50MHz, 800V/µs Op Amp
Generate High Power Supplies
LT1206
C-LoadTM Op Amp with Shutdown and 900V/µs Slew Rate
C-Load Op Amp with Shutdown and 700V/µs Slew Rate
Use as Battery Boost Converter
LT1210
LT1270A
LT1360
±15V, Ideal for Driving Capacitive Loads
±15V, Very High Speed, C-Load
LT1363
70MHz, 800V/µs Op Amp
C-Load is a registered trademark of Linear Technology
LT/GP 1195 6K • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977
LINEAR TECHNOLOGY CORPORATION 1995
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