LT1169 [Linear]
Dual Low Noise, Picoampere Bias Current, JFET Input Op Amp; 双路低噪声， Picoampere偏置电流， JFET输入运算放大器
| 型号： | LT1169 |
| 厂家： | 
Linear |
| 描述： | Dual Low Noise, Picoampere Bias Current, JFET Input Op Amp |
| 文件： | 总12页 (文件大小：336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1169
Dual Low Noise,
Picoampere Bias Current,
JFET Input Op Amp
U
DESCRIPTIO
EATURE
S
F
■
Input Bias Current, Warmed Up: 20pA Max
100% Tested Low Voltage Noise: 8nV/√Hz Max
S8 and N8 Package Standard Pinout
Very Low Input Capacitance: 1.5pF
Voltage Gain: 1.2 Million Min
TheLT1169achievesanew standardofexcellencein noise
performance for a dual JFET op amp. For the first time low
voltage noise (6nV/√Hz) is simultaneously offered with
extremely low current noise (1fA/√Hz), providing the low-
est total noise for high impedance transducer applications.
Unlike most JFET op amps, the very low input bias current
(5pA Typ) is maintained over the entire common mode
range which results in an extremely high input resistance
(1013Ω). When combined with a very low input capaci-
tance (1.5pF) an extremely high input impedance results,
making the LT1169 the first choice for amplifying low level
signals from high impedance transducers. The low input
capacitancealsoassureshighgainlinearitywhenbuffering
AC signals from high impedance transducers.
■
■
■
■
■
■
■
■
■
Offset Voltage: 2mV Max
Input Resistance: 1013Ω
Gain-Bandwidth Product: 5.3MHz Typ
Guaranteed Specifications with ±5V Supplies
Guaranteed Matching Specifications
O U
PPLICATI
A
S
■
■
■
■
Photocurrent Amplifiers
Hydrophone Amplifiers
High Sensitivity Piezoelectric Accelerometers
Low Voltage and Current Noise Instrumentation
Amplifier Front Ends
Two and Three Op Amp Instrumentation Amplifiers
Active Filters
TheLT1169isunconditionallystableforgainsof1ormore,
even with 1000pF capacitive loads. Other key features are
0.6mV VOS and a voltage gain over 4 million. Each indi-
vidual amplifier is 100% tested for voltage noise, slew rate
(4.2V/µs), and gain-bandwidth product (5.3MHz).
■
■
The LT1169 is offered in the S8 and N8 packages.
A full set of matching specifications are provided for
precision instrumentation amplifier front ends. Specifica-
tions at ±5V supply operation are also provided. For an
evenlowervoltagenoisepleaseseetheLT1113datasheet.
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
O
TYPICAL APPLICATI
Low Noise Light Sensor with DC Servo
1kHz Output Voltage Noise
Density vs Source Resistance
C1
2pF
10k
–
R1
–
2
V
N
1M
1k
100
10
+
1
1/2 LT1169
C2
V
OUT
R
SOURCE
+
3
0.022µF
D2
1N914
C
D
+V
8
R2
100k
–
6
D1
1N914
R3
1k
V
N
7
SOURCE
2N3904
1/2 LT1169
T
= 25°C
= ±15V
A
S
RESISTANCE
ONLY
+
5
V
HAMAMATSU
R5
10k 1k
R4
1
100
4
–V
S1336-5BK
1k 10k 100k 1M 10M
1G
100M
(908) 231-0960
R2C2 > C1R1
SOURCE RESISTANCE (Ω)
C
V
= PARASITIC PHOTODIODE CAPACITANCE
D
2
2
V
=
√
(V
OP AMP
)
+ 4kTR + 2qI R
= 100mV/µWATT FOR 200nm WAVE LENGTH
N
S
B
S
V–
OUT
LT1169 • TA01
330mV/µWATT FOR 633nm WAVE LENGTH
LT1169 • TA02
1
LT1169
W W W
U
/O
ABSOLUTE AXI U RATI GS
PACKAGE RDER I FOR ATIO
Supply Voltage
TOP VIEW
ORDER PART
–55°C to 105°C ............................................... ±20V
105°C to 125°C ............................................... ±16V
Differential Input Voltage ...................................... ±40V
Input Voltage (Equal to Supply Voltage)............... ±20V
Output Short-Circuit Duration......................... Indefinite
Operating Temperature Range............... –40°C to 85°C
Storage Temperature Range................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................ 300°C
+
NUMBER
OUT A
–IN A
+IN A
1
2
3
4
V
8
7
6
5
OUT B
–IN B
+IN B
A
LT1169CN8
LT1169CS8
B
–
V
S8 PACKAGE
8-LEAD PLASTIC SO
N8 PACKAGE
8-LEAD PDIP
S8 PART MARKING
1169
TJMAX = 150°C, θJA = 80°C/W (N8)
JMAX = 160°C, θJA = 190°C/W (S8)
T
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS VS = ±15V, VCM = 0V, TA = 25°C, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS (Note 1)
MIN
TYP
MAX
UNITS
V
Input Offset Voltage
0.60
0.65
2.0
2.2
mV
mV
OS
V = ±5V
S
I
I
Input Offset Current
Input Bias Current
Warmed Up (Note 2)
T = 25°C (Note 5)
J
2.5
0.7
15
4
pA
pA
OS
Warmed Up (Note 2)
T = 25°C (Note 5)
J
4.0
1.5
20
5
pA
pA
B
e
Input Noise Voltage
0.1Hz to 10Hz
2.4
µV
P-P
n
Input Noise Voltage Density
f = 10Hz
f = 1000Hz
O
17
6
nV/√Hz
nV/√Hz
O
8
i
Input Noise Current Density
f = 10Hz, f = 1kHz (Note 3)
1
fA/√Hz
n
O
O
R
Input Resistance
Differential Mode
Common Mode
IN
14
10
Ω
Ω
13
V
CM
= –10V to 13V
10
C
V
Input Capacitance
1.5
2.0
pF
pF
IN
V = ±5V
S
Input Voltage Range (Note 4)
13.0
–10.5
13.5
–11.0
V
V
CM
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain
V
= –10V to 13V
82
83
95
98
dB
dB
CM
V = ±4.5V to ± 20V
S
A
V = ±12V, R = 10k
V = ±10V, R = 1k
1000
500
4500
3000
V/mV
V/mV
VOL
O
L
O
L
V
Output Voltage Swing
R = 10k
R = 1k
L
±13.0
±12.0
±13.8
±13.0
V
V
OUT
L
SR
Slew Rate
R ≥ 2k (Note 6)
2.4
3.3
4.2
5.3
V/µs
MHz
dB
L
GBW
Gain-Bandwidth Product
Channel Separation
Supply Current per Amplifier
f = 100kHz
O
f = 10Hz, V = ±10V, R = 1k
126
O
O
L
I
5.3
5.3
6.50
6.45
mA
mA
S
V = ±5V
S
∆V
Offset Voltage Match
0.8
3
3.5
20
mV
pA
dB
dB
OS
+
∆I
Noninverting Bias Current Match
Common Mode Rejection Match
Power Supply Rejection Match
Warmed Up (Note 2)
(Note 8)
B
∆CMRR
∆PSRR
78
80
94
95
(Note 8)
2
LT1169
ELECTRICAL CHARACTERISTICS VS = ±15V, VCM = 0V, 0°C ≤ TA ≤ 70°C, (Note 9), unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS (Note 1)
MIN
TYP
MAX
UNITS
V
Input Offset Voltage
●
●
0.7
0.8
3.2
3.4
mV
mV
OS
V = ± 5V
S
∆V
Average Input Offset Voltage Drift
(Note 5)
●
20
50
µV/°C
OS
∆Temp
I
I
Input Offset Current
●
●
10
50
pA
pA
OS
B
Input Bias Current
180
400
V
Input Voltage Range
●
●
12.9
–10.0
13.4
–10.8
V
V
CM
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain
V
= –10V to 12.9V
●
●
79
81
94
97
dB
dB
CM
V = ±4.5V to ±20V
S
A
V = ±12V, R = 10k
V = ±10V, R = 1k
●
●
800
400
3400
2400
V/mV
V/mV
VOL
O
L
O
L
V
Output Voltage Swing
R = 10k
R = 1k
L
●
●
±12.5
±11.5
±13.5
±12.7
V
V
OUT
L
SR
Slew Rate
R ≥ 2k (Note 6)
●
●
1.9
3
4
V/µs
L
GBW
Gain-Bandwidth Product
Supply Current per Amplifier
f = 100kHz
O
4.2
MHz
I
●
●
5.3
5.3
6.55
6.50
mA
mA
S
V = ±5V
S
∆V
Offset Voltage Match
●
●
●
●
1.5
5.5
93
5
mV
pA
dB
dB
OS
+
∆I
Noninverting Bias Current Match
Common Mode Rejection Match
Power Supply Rejection Match
50
B
∆CMRR
∆PSRR
(Note 8)
(Note 8)
74
77
93
VS = ±15V, VCM = 0V, –40°C ≤ TA ≤ 85°C, (Note 7), unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS (Note 1)
MIN
TYP
MAX
UNITS
V
Input Offset Voltage
●
●
0.8
0.9
3.8
4.0
mV
mV
OS
V = ±5V
S
∆V
Average Input Offset Voltage Drift
●
20
50
µV/°C
OS
∆Temp
I
I
Input Offset Current
●
●
30
200
pA
pA
OS
B
Input Bias Current
320
1200
V
Input Voltage Range
●
●
12.6
–10.0
13.0
–10.5
V
V
CM
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain
V
= –10V to 12.6V
●
●
78
79
93
96
dB
dB
CM
V = ±4.5V to ±20V
S
A
V = ±12V, R = 10k
V = ±10V, R = 1k
●
●
750
300
3000
2000
V/mV
V/mV
VOL
O
L
O
L
V
Output Voltage Swing
R = 10k
R = 1k
L
●
●
±12.5
±11.3
±12.5
±12.0
V
V
OUT
L
SR
Slew Rate
R ≥ 2k
●
●
1.8
2.7
3.8
4
V/µs
L
GBW
Gain-Bandwidth Product
Supply Current per Amplifier
f = 100kHz
O
MHz
I
●
●
5.30
5.25
6.55
6.50
mA
mA
S
V = ±5V
S
3
LT1169
V = ±15V, VCM = 0V, –40°C ≤ TA ≤ 85°C, (Note 7), unless otherwise noted.
ELECTRICAL CHARACTERISTICS
S
SYMBOL
PARAMETER
CONDITIONS (Note 1)
MIN
TYP
1.8
10
MAX
6
UNITS
mV
pA
∆V
Offset Voltage Match
●
●
●
●
OS
+
∆I
Noninverting Bias Current Match
Common Mode Rejection Match
Power Supply Rejection Match
180
B
∆CMRR
∆PSRR
(Note 8)
(Note 8)
73
75
93
dB
92
dB
Note 6: Slew rate is measured in A = –1; input signal is ±7.5V, output
The
● denotes specifications which apply over the full operating
V
measured at ±2.5V.
temperature range.
Note 7: The LT1169 is designed, characterized and expected to meet these
extended temperature limits, but is not tested at –40°C and 85°C.
Guaranteed I grade parts are available; consult factory.
Note 1: Typical parameters are defined as the 60% yield of parameter
distributions of individual amplifiers, i.e., out of 100 LT1169s (200 op
amps) typically 120 op amps will be better than the indicated specification.
Note 8: ∆CMRR and ∆PSRR are defined as follows:
(1) CMRR and PSRR are measured in µV/V on the individual
amplifiers.
(2) The difference is calculated between the matching sides in µV/V.
(3) The result is converted to dB.
Note 9: The LT1169 is measured in an automated tester in less than one
second after application of power. Depending on the package used, power
dissipation, heat sinking, and air flow conditions, the fully warmed-up chip
temperature can be 10°C to 50°C higher than the ambient temperature.
Note 2: I and I readings are extrapolated to a warmed-up temperature
from 25°C measurements and 45°C characterization data.
B
OS
Note 3: Current noise is calculated from the formula:
1/2
i = (2qI )
n
B
–19
where q = 1.6 × 10
coulomb. The noise of source resistors up to 200M
swamps the contribution of current noise.
Note 4: Input voltage range functionality is assured by testing offset
voltage at the input voltage range limits to a maximum of 2.8mV.
Note 5: This parameter is not 100% tested.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
1kHz Input Noise Voltage
Distribution
0.1Hz to 10Hz Voltage Noise
Voltage Noise vs Frequency
100
10
1
50
40
30
20
10
0
T
A
= 25°C
= ±15V
T
= 25°C
= ±15V
A
S
V
S
V
510 OP AMPS TESTED
TYPICAL
1/f CORNER
60Hz
4.2 4.6 5.0 5.4 5.8 6.2 6.6 7.0 7.4 7.8 8.2
INPUT VOLTAGE NOISE (nV/√Hz)
LT1169 • TPC02
1
10
100
1k
10k
0
2
4
6
8
10
FREQUENCY (Hz)
TIME (SEC)
LT1169 • TPC03
LT1169 • TPC01
4
LT1169
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Input Bias and Offset Currents
vs Chip Temperature
Input Bias and Offset Currents
Over the Common Mode Range
Voltage Noise vs Chip Temperature
30n
10n
10
9
10
8
V
S
= ±15V
V
V
= ±15V
CM
T
= 25°C
V = ±15V
S
S
A
= –10 TO 13V
3n
1n
6
4
2
8
BIAS
CURRENT
7
BIAS CURRENT
OFFSET CURRENT
300p
100p
6
0
30p
10p
3p
–2
5
OFFSET
CURRENT
–4
–6
4
3
1p
–8
2
0.3p
–10
50 75
TEMPERATURE (°C)
25
75
TEMPERATURE (°C)
–75 –50 –25
0
25
100 125
0
50
100
125
–15
–10
0
5
10
15
–5
COMMON MODE RANGE (V)
LT1169 • TPC04
LT1169 • TPC05*
LT1169 • TPC06
Common Mode Limit
vs Temperature
Power Supply Rejection Ratio
vs Frequency
Common Mode Rejection Ratio
vs Frequency
+
120
100
80
60
40
20
0
V
0
–0.5
–1.0
–1.5
120
100
80
60
40
20
0
T
= 25°C
A
T
= 25°C
= ±15V
A
S
V
+
+PSRR
V
= 5V TO 20V
–2.0
–PSRR
3.0
2.5
2.0
–
V
= –5V TO –20V
1.5
–
V
+1.0
–60
–20
20
60
100
140
1k
10k
100k
1M
10M
10
1k
10k 100k
1M
10M
100
FREQUENCY (Hz)
FREQUENCY (Hz)
TEMPERATURE (°C)
LT1169 • TPC08
LT1169 • TPC07
LT1169 • TPC09
Gain and Phase Shift
vs Frequency
Voltage Gain vs Frequency
Voltage Gain vs Chip Temperature
10
9
8
7
6
5
4
3
2
1
0
180
140
100
60
50
40
30
20
10
0
60
T
V
C
= 25°C
= ±15V
= 10pF
T
= 25°C
= ±15V
A
S
L
A
S
V
S
V
O
V
O
= ±15V
V
= ±10V, R = 1k
L
80
= ±12V, R = 10k
L
100
120
140
160
R
L
=10k
PHASE
R
L
= 1k
GAIN
20
–10
180
100
–20
0.01
1
100
10k
1M
100M
125
100
0.1
1
10
–75
50
CHIP TEMPERATURE (°C)
–50 –25
0
25
75
FREQUENCY (MHz)
FREQUENCY (Hz)
LT1169 • TPC10
LT1169 • TPC12
LT1169 • TPC11
5
LT1169
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Small-Signal Transient Response
Large-Signal Transient Response
Supply Current vs Supply Voltage
6
5
4
25°C
–55°C
125°C
LT1169 • TPC14
LT1169 • TPC13
AV = 1
2µs/DIV
AV = 1
5µs/DIV
C
L = 10pF
C
L = 10pF
VS = ±15V, ±5V
VS = ±15V
±10
±15
0
±20
±5
SUPPLY VOLTAGE (V)
LT1169 • TPC15
Output Voltage Swing
vs Load Current
Slew Rate and Gain-Bandwidth
Product vs Temperature
Capacitive Load Handling
+
V
–0.8
–1.0
–1.2
–1.4
–1.6
1.4
50
40
30
20
10
0
6
5
4
3
2
1
0
12
10
8
125°C
V
= ±15V
= 25°C
≥ 10k
25°C
S
A
L
O
V
T
R
V
A
–55°C
SLEW RATE
= 100mV
P-P
= +10, R = 10k, C = 20pF
F
F
GAIN-BANDWIDTH
V
= ±5V TO ±20V
S
6
1.2
4
1.0
A
= 1
V
–55°C
25°C
0.8
2
0.6
A
= 10
V
125°C
–2
–
V
+0.4
0
0
2
4
8
50 75
TEMPERATURE (°C)
–10 –8
6
I
10
0.1
1
100
1000 10000
–75 –50 –25
0
25
100 125
–6 –4
10
I
SINK
SOURCE
OUTPUT CURRENT (mA)
CAPACITIVE LOAD (pF)
LT1169 • TPC16
LT1169 • TPC17
LT1169 • TPC18
Distribution of Offset Voltage Drift
with Temperature
Warm-Up Drift
Channel Separation vs Frequency
50
40
30
20
10
0
1000
800
600
400
140
120
100
80
V
= ±15V
T
= 25°C
= ±15V
S
A
S
188 OP AMPS
V
N8 PACKAGE
LIMITED BY
THERMAL
INTERACTION
LIMITED BY
PIN-TO-PIN
CAPACITANCE
60
40
T
= 25°C
= ±15V
= 1k
A
S
L
O
200
0
V
20
R
V
= 10V
P-P
0
0
2
3
4
5
6
–50
–10
10 20
1
–40 –30 –20
0
30
100k
FREQUENCY (Hz)
10M
10
100
1k
10k
1M
TIME AFTER POWER ON (MIN)
OFFSET VOLTAGE DRIFT WITH TEMPERATURE (µV/°C)
LT1169 • TPC20
LT1169 • TPC19
LT1169 • TPC21
6
LT1169
U W
TYPICAL PERFOR A CE CHARACTERISTICS
THD and Noise vs
Frequency for Noninverting Gain
THD and Noise vs
Frequency for Inverting Gain
1
0.1
1
0.1
Z
= 2k 15pF
P-P
= 1, 10, 100
Z
= 2k 15pF
L
O
V
L
O
V
V
A
= 20V
V
A
= 20V
P-P
= –1, –10, –100
MEASUREMENT BANDWIDTH
= 10Hz TO 80kHz
MEASUREMENT BANDWIDTH
= 10Hz TO 80kHz
A
= –100
V
A
= 100
V
0.01
0.01
A
= –10
V
A
= 10
V
A
= 1
V
0.001
0.0001
0.001
0.0001
A
= –1
V
NOISE FLOOR
NOISE FLOOR
20
100
1k
FREQUENCY (Hz)
10k 20k
20
100
1k
FREQUENCY (Hz)
10k 20k
LT1169 • TPC22
LT1169 • TPC23
THD and Noise vs Output
Amplitude for Inverting Gain
THD and Noise vs Output
Amplitude for Noninverting Gain
CCIF IMD Test (Equal Amplitude
Tones at 13kHz, 14kHz)*
1
0.1
1
0.1
1
0.1
T
A
= 25°C
= ±15V
= 2k
Z
O
A
= 2k 15pF
= 1kHz
= –1, –10, –100
Z
= 2k 15pF
= 1kHz
O
L
L
V
S
f
f
R
L
A
= 1, 10, 100
V
V
MEASUREMENT BANDWIDTH
= 10Hz TO 22kHz
MEASUREMENT BANDWIDTH
= 10Hz TO 22kHz
A
= 100
A
= ±10
V
V
A
= –100
V
0.01
0.01
0.01
A
= –10
V
A
= 10
V
A
= 1
V
0.001
0.0001
0.001
0.0001
0.001
0.0001
A
= –1
1
V
NOISE FLOOR
10
NOISE FLOOR
10
0.3
30
0.3
1
30
0.02
0.1
1
10
30
OUTPUT SWING (V
)
P-P
OUTPUT SWING (V )
OUTPUT SWING (V
)
P-P
P-P
LT1169 • TPC24
LT1169 • TPC25
LT1169 • TPC26
*SEE LT1115 DATA SHEET FOR DEFINITION OF
CCIF TESTING
W
U
O U
I FOR ATIO
S
PPLICATI
A
The extremely high input impedance (1013Ω) assures that
the input bias current is almost constant over the entire
common mode range. Figure 1 shows how the LT1169
standsuptothecompetition.Unlikethecompetition,asthe
input voltage is swept across the entire common mode
range the input bias current of the LT1169 hardly changes.
As a result the current noise does not degrade. This makes
the LT1169 the best choice in applications where an
amplifier has to buffer signals from a high impedance
transducer.
LT1169 vs the Competition
Withimprovednoiseperformance, theLT1169dualinthe
plastic DIP directly replaces such JFET op amps as the
OPA2111, OPA2604, OP215, and the AD822. The combi-
nation of low current and voltage noise of the LT1169
allows it to surpass most dual and single JFET op amps.
The LT1169 can replace many of the lowest noise bipolar
amps that are used in amplifying low level signals from
high impedance transducers. The best bipolar op amps
will eventually lose out to the LT1169 when transducer
impedance increases due to higher current noise.
7
LT1169
W
U
O U
I FOR ATIO
S
PPLICATI
A
100
thetotalnoise. ThismeanstheLT1169issuperiortomost
dualJFETopamps. Onlythelowestnoisebipolaropamps
have the advantage at low source resistances. As the
source resistance increases from 5k to 50k, the LT1169
will match the best bipolar op amps for noise perfor-
mance, since the thermal noise of the transducer (4kTR)
begins to dominate the total noise. A further increase in
source resistance, above 50k, is where the op amp’s
current noise component (2qIBR2) will eventually domi-
nate the total noise. At these high source resistances, the
LT1169 will out perform the lowest noise bipolar op amps
due to the inherently low current noise of FET input op
amps. Clearly, the LT1169 will extend the range of high
impedance transducers that can be used for high signal-
to-noiseratios.ThismakestheLT1169thebestchoicefor
high impedance, capacitive transducers.
CURRENT NOISE = √2qI
B
80
60
40
20
OP215
LT1169
0
–20
AD822
–40
–60
–80
–100
–15
–10
0
5
10
15
–5
COMMON MODE RANGE (V)
LT1169 • F01
Figure 1. Comparison of LT1169, OP215, and AD822
Input Bias Current vs Common Mode Range
Amplifying Signals from High Impedance Transducers
The low voltage and current noise offered by the LT1169
makes it useful in a wide range of applications, especially
where high impedance, capacitive transducers are used
such as hydrophones, precision accelerometers, and
photodiodes. The total output noise in such a system is
thegaintimestheRMSsumoftheopamp’sinputreferred
voltagenoise, thethermalnoiseofthetransducer, andthe
op amp’s input bias current noise times the transducer
impedance. Figure 2 shows total input voltage noise
versus source resistance. In a low source resistance
(<5k) application the op amp voltage noise will dominate
Optimization Techniques for Charge Amplifiers
The high input impedance JFET front end makes the
LT1169 suitable in applications where very high charge
sensitivity is required. Figure 3 illustrates the LT1169 in its
inverting and noninverting modes of operation. A charge
amplifier is shown in the inverting mode example; the gain
depends on the principal of charge conservation at the
input of the LT1169. The charge across the transducer
capacitance CS is transferred to the feedback capacitor CF
resultinginachangeinvoltagedV, whichisequaltodQ/CF.
The gain therefore is 1 + CF/CS. For unity-gain, the CF
should equal the transducer capacitance plus the input
capacitance of the LT1169 and RF should equal RS.
10k
C
LT1124*
S
–
+
R
LT1169*
S
1k
100
10
Inthenoninvertingmodeexample,thetransducercurrent
is converted to a change in voltage by the transducer
capacitance, CS. This voltage is then buffered by the
LT1169 with a gain of 1 + R1/R2. A DC path is provided by
RS, which is either the transducer impedance or an
external resistor. Since RS is usually several orders of
magnitude greater than the parallel combination of R1
andR2,RB isaddedtobalancetheDCoffsetcausedbythe
noninverting input bias current and RS. The input bias
currents, although small at room temperature, can create
significant errors over increasing temperature, especially
with transducer resistances of up to 1000MΩ or more.
The optimum value for RB is determined by equating the
thermal noise (4kTRS) to the current noise (2qIB) times
V
O
R
C
S
S
†
LT1124
LT1169
†
LT1169
LT1124
RESISTOR NOISE ONLY
1
100 1k 10k 100k 1M 10M 100M 1G
SOURCE RESISTANCE (Ω)
LT1169 • F02
SOURCE RESISTANCE = 2R = R
S
* PLUS RESISTOR
†
PLUS RESISTOR
2
1000pF CAPACITOR
2
V = A √V
+ 4kTR + 2qI R
B
n
V
n (OP AMP)
Figure 2. Comparison of LT1169 and LT1124 Total Output
1kHz Voltage Noise vs Source Resistance
2
RS . Solving for RS results in RB = RS = 2VT/IB. A parallel
8
LT1169
W
U
O U
S
I FOR ATIO
PPLICATI
A
R
R2
F
C
B
C
F
R
B
–
+
–
+
R
C
S
OUTPUT
R1
OUTPUT
S
C
= C
C
S
R
S
B
B
F
F
TRANSDUCER
R
= R
R
C
S
C
R
R
C
S
S
B
B
S
dQ
dt
dV
dt
= R
S
Q = C
V;
= I = C
R
B
C
B
> R1 OR R2
TRANSDUCER
LT1169 • F03
Figure 3. Inverting and Noninverting Gain Configurations
LT1169 Output
Input: ±5.2 Sine Wave
OPA2111 Output
LT1169 • F04a
LT1169 • F04b
LT1169 • F04c
Figure 4. Voltage Follower with Input Exceeding the Common Mode Range (VS = ±5V)
capacitor CB, is used to cancel the phase shift caused by
the op amp input capacitance and RB.
amps. Two or three op amp instrumentation amplifiers,
tracking voltage references and low drift active filters
are some of the circuits requiring matching between two
op amps.
Reduced Power Supply Operation
To take full advantage of a wide input common-mode
range, the LT1169 was designed to eliminate phase rever-
sal. Referring to the photographs in Figure 4, the LT1169
is shown operating in the follower mode (AV = 1) at ±5V
supplies with the input swinging ±5.2V. The output of the
LT1169 clips cleanly and recovers with no phase reversal,
unlike the competition as shown by the last photograph.
This has the benefit of preventing lockup in servo systems
and minimizing distortion components. The effect of input
and output overdrive on one amplifier has no effect on the
other, as each amplifier is biased independently.
The well-known triple op amp configuration in Figure 5
illustrates these concepts. Output offset is a function of the
differencebetweenthetwohalvesoftheLT1169.Thiserror
cancellation principle holds for a considerable
number of input referred parameters in addition to
offset voltage and bias current. Input bias current will
+
be the average of the two noninverting input currents (IB +).
The difference between these two currents (∆IB )
is the offset current of the instrumentation amplifier. Com-
mon-mode and power supply rejections will be
dependent only on the match between the two amplifiers
(assuming perfect resistor matching).
Advantages of Matched Dual Op Amps
The concepts of common mode and power supply
rejection ratio match (∆CMRR and ∆PSRR) are best dem-
onstrated with a numerical example:
In many applications the performance of a system
depends on the matching between two operational ampli-
fiersratherthantheindividualcharacteristicsofthetwoop
9
LT1169
W
U
O U
S
I FOR ATIO
PPLICATI
A
15V
Input offset current = 3pA
Input resistance = 1013Ω
Input noise = 3.4µVP-P
3
8
R6
R4
1k
IN–
+
1/2
10k
1
LT1169
IC1
2
C1
30pF
–
R1
1k
4
High Speed Operation
–15V
R2
The low noise performance of the LT1169 was achieved by
enlarging the input JFET differential pair to maximize the
firststagegain.EnlargingtheJFETgeometryalsoincreases
the parasitic gate capacitance, which if left unchecked, can
result in increased overshoot and ringing. When the feed-
back around the op amp is resistive (RF), a pole will be
created with RF, the source resistance and capacitance
(RS,CS), and the amplifier input capacitance (CIN = 1.5pF).
In closed-loop gain configurations with RS and RF in the
MΩrange(Figure6),thispolecancreateexcessphaseshift
and even oscillation. A small capacitor (CF) in parallel with
RF eliminates this problem. With RS(CS + CIN) = RFCF, the
effect of the feedback pole is completely removed.
–
2
200Ω
1/2
1
OUTPUT
LT1169
IC2
R3
1k
–
6
3 +
R5
1k
C
L
1/2
LT1169
7
5 + IC1
R7
+
IN
10k
GAIN = 100
BANDWIDTH = 330kHz
INPUT REFERRED NOISE = 8.7nV/√Hz AT 1kHz
WIDEBAND NOISE DC TO 330kHz = 5.3µV
RMS
C
L
≤ 0.01µF
LT1169 • F05
Figure 5. Three Op Amp Instrumentation Amplifier
Assume CMRRA = 50µV/V or 86dB,
and CMRRB = 39µV/V or 88dB,
then ∆CMRR = 11µV/V or 99dB;
if CMRRB = –39µV/V which is still 88dB,
then ∆CMRR = 89µV/V or 81dB
C
F
R
F
–
+
By specifying and guaranteeing all of these matching
parameters, the LT1169 can significantly improve the
performance of matching-dependent circuits.
C
OUTPUT
IN
R
C
S
S
LT1169 • F06
Typical performance of the instrumentation amplifier:
Figure 6
Input offset voltage = 0.8mV
Input bias current = 4pA
U
TYPICAL APPLICATIONS N
Unity-Gain Buffer with Extended Load Capacitance
Drive Capability
Light Balance Detection Circuit
R2
1k
R1
1M
C1
I
I
1
2
C1
3pF TO 5pF
PD
PD
1
–
R1
33Ω
–
V
1/2 LT1169
OUT
+
V
OUT
1/2 LT1169
C
V
IN
L
+
2
LT1169 • TA03
C1 = C ≤ 0.1µF
L
LT1169 • TA04
OUTPUT SHORT CIRCUIT CURRENT ( 30mA) WILL LIMIT THE RATE
V
= 1M × (I – I )
1 2
2
OUT
1,
AT WHICH THE VOLTAGE CAN CHANGE ACROSS LARGE CAPACITORS
dV
PD PD = HAMAMATSU S1336-5BK
WHEN EQUAL LIGHT ENTERS PHOTODIODES, V
< 3mV.
OUT
(I = C
)
dt
10
LT1169
U
TYPICAL APPLICATIONS N
Low Noise Hydrophone Amplifier with DC Servo
Accelerometer Amplifier with DC Servo
C1
1250pF
5V TO 15V
8
R3
3.9k
R1*
R1
100M
R2
18k
100M
–
2
3
1
C2
2µF
1/2
R3
2k
OUTPUT
LT1169
+
C2
0.47µF
C1*
R2
4
R4
200Ω
20M
–5V TO –15V
–
6
5
R4
7
1M
R8
–
+
6
5
R5
20M
C
T
1/2 LT1169
R6
100k
100M
+
HYDRO-
PHONE
7
1/2
LT1169
R5
1M
5V TO 15V
8
ACCELEROMETER
B & K MODEL 4381
OR EQUIVALENT
(800) 442-1030
C3
2µF
R7
1M
–
2
3
1
1/2 LT1169
OUTPUT
R4C2 = R5C3 > R1 (1 + R2/R3) C1
OUTPUT = 0.8mV/pC* = 8.0mV/g**
DC OUTPUT ≤ 1.9mV
+
DC OUTPUT ≤ 2.5mV FOR T < 70°C
A
4
OUTPUT VOLTAGE NOISE = 128nV/√Hz AT 1kHz (GAIN = 20)
C1 ≈ C ≈ 100pF TO 5000pF; R4C2 > R8C ; *OPTIONAL
LT1169 • TA05
T
T
–5V TO –15V OUTPUT NOISE = 8nV/√Hz AT 1kHz
*PICOCOULOMBS
**g = EARTH’S GRAVITATIONAL CONSTANT
LT1169 • TA07
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
0.130 ± 0.005
0.300 – 0.325
0.045 – 0.065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
8
1
7
6
5
4
0.065
(1.651)
TYP
0.255 ± 0.015*
(6.477 ± 0.381)
0.009 – 0.015
(0.229 – 0.381)
0.125
0.020
(0.508)
MIN
(3.175)
MIN
+0.035
–0.015
2
3
0.325
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
+0.889
8.255
(
)
(0.457 ± 0.076)
N8 1197
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
0.010 – 0.020
(0.254 – 0.508)
7
5
8
6
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
SO8 0996
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
2
3
4
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresenta-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LT1169
TYPICAL APPLICATIONS N
U
10Hz Fourth Order Chebyshev Lowpass Filter (0.01dB Ripple)
R2
237k
R5
15V
8
C1
R1
R3
249k
154k
33nF
237k
–
2
3
R4
154k
R6
249k
C3
V
IN
10nF
–
1
6
5
1/2 LT1169
C2
100nF
7
+
C4
330nF
V
1/2 LT1169
OUT
4
+
–15V
LT1169 • TA08
TYPICAL OFFSET ≈ 0.8mV
1% TOLERANCES
FOR V = 10V , V
= –121dB AT f > 330Hz
= – 6dB AT f = 16.3Hz
IN
P-P OUT
LOWER RESISTOR VALUES WILL RESULT IN LOWER THERMAL NOISE AND LARGER CAPACITORS
Paralleling Amplifiers to Reduce Voltage Noise
3
+
1.6k
1.6k
1.6k
A1
1
1
7
1/2 LT1169
2
–
91Ω
91Ω
3k
10k
3
2
15V
8
+
–
A2
6
5
1/2 LT1169
7
OUTPUT
1/2 LT1169
–
+
3k
4
15V
8
–15V
5
6
+
An
1/2 LT1169
–
4
1. ASSUME VOLTAGE NOISE OF LT1169 AND 5Ω1 SOURCE RESISTOR = 6.1nV/√Hz
2. GAIN WITH n LT1169s IN PARALLEL = n× 200
3. OUTPUT NOISE =√n × 200 × 6.1nV/√Hz
–15V
91Ω
3k
OUTPUT NOISE 6.1
4. INPUT REFERRED NOISE =
=
nV/√Hz
× 2n00
n
√
5. NOISE CURRENT AT INPUT INCREASES n TIMES
6. IF n = 5, GAIN = 1000, BANDWIDTH = 110kHz, RMS NOISE, DC TO 1MHz =
√
2.1µV
√5
= 1.0µV
LT1169 • TA06
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1113
LT1462
LT1464
Lowest Noise Dual JFET Op Amp
Micro Power Dual JFET Op Amp
Low Power Dual JFET Op Amp
4.5nV/√Hz Voltage Noise
3.0pA I , 45µA I
B SUPPLY
3.0pA (Max) Input Bias Current
1169fa LT/TP 0198 REV A 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1994
Linear Technology Corporation
●
1630McCarthyBlvd.,Milpitas, CA95035-7417 (408)432-1900
12
●
●
FAX: (408) 434-0507 TELEX: 499-3977 www.linear-tech.com
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