LT1186FCS [Linear]
DAC Programmable CCFL Switching Regulator(Bits-to-NitsTM); DAC可编程CCFL开关稳压器（比特至NitsTM ）
| 型号： | LT1186FCS |
| 厂家： | 
Linear |
| 描述： | DAC Programmable CCFL Switching Regulator(Bits-to-NitsTM) |
| 文件： | 总16页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1186F
DAC Programmable
CCFL Switching Regulator
(Bits-to-NitsTM)
facemodesincludingstandardSPImodeandpulsemode.
On power-up, the DAC counter resets to half-scale and the
DACconfigurestoSPIorpulsemodedependingonthe CS
signal level. In SPI mode, the system microprocessor
serially transfers the present 8-bit data and reads back the
previous8-bitdata. Inpulsemode, theuppersixbitsofthe
DAC configure as increment-only (1-wire interface) or
increment/decrement(2-wireinterface)operationdepend-
ing on the DIN signal level.
FEATURES
■
Wide Battery Input Range: 4.5V to 30V
■
Grounded Lamp or Floating Lamp Configurations
■
Open Lamp Protection
Precision 50µA Full-Scale DAC Programming Current
Standard SPI Mode or Pulse Mode
DAC Setting Is Retained in Shutdown
■
■
■
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APPLICATIONS
TheLT1186Fcontrolcircuitryoperatesfromalogicsupply
voltage of 3.3V or 5V. The IC also has a battery supply
voltage pin that operates from 4.5V to 30V. The LT1186F
draws 6mA typical quiescent current. An active low shut-
down pin reduces total supply current to 35µA for standby
operation and the DAC retains its last setting. A 200kHz
switchingfrequencyminimizesmagneticcomponentsize.
Current mode switching techniques with cycle-by-cycle
limiting gives high reliability and simple loop frequency
compensation. The LT1186F is available in a 16-pin nar-
row SO package.
■
Notebook and Palmtop Computers
■
Portable Instruments
■
Retail Terminals
U
DESCRIPTION
The LT®1186F is a fixed frequency, current mode, switch-
ing regulator that provides the control function for Cold
Cathode Fluorescent Lighting (CCFL). The IC includes an
efficient high current switch, an oscillator, output drive
logic, control circuitry and a micropower 8-bit 50µA full-
scale current output DAC. The DAC provides simple “bits-
to-lamp current control” and communicates in two inter-
, LTC and LT are registered trademarks of Linear Technology Corporation.
Bits-to-Nits is a trademark of Linear Technology Corporation. 1 Nit = 1 Candela/meter2
U
TYPICAL APPLICATION
90% Efficient Floating CCFL with 1-Wire (Increment Only) Pulse Mode Control of Lamp Current
UP TO 6mA
LAMP
CCFL BACKLIGHT APPLICATION CIRCUITS
D1
L1 = COILTRONICS CTX210605
L2 = COILTRONICS CTX100-4
*DO NOT SUBSTITUTE COMPONENTS
COILTRONICS (407) 241-7876
CONTAINED IN THIS DATA SHEET ARE COVERED
BAT85
C2
27pF
3kV
BY U.S. PATENT NUMBER 5408162
AND OTHER PATENTS PENDING
10
6
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C5
1000pF
CCFL
L1
CCFL V
SW
PGND
3
2
1
5
4
BAT
I
BULB
BAT
CCFL
8V TO 28V
+
C3B
+
C3A
R2
220k
2.2µF
2.2µF
DIO
35V
C7, 1µF
35V
LT1186F
R1
750Ω
CCFL V
AGND
SHDN
ROYER
C
C1*
0.068µF
V
IN
V
3.3V
CC
+
OR 5V
C4
2.2µF
R3
100k
SHUTDOWN
FROM MPU
I
OUT
Q2*
Q1*
CLK
CS
D
OUT
D
IN
L2
100µH
D1
1N5818
ALUMINUM ELECTROLYTIC IS RECOMMENDED FOR C3A AND C3B.
LT1186F • TA01
MAKE 3CB ESR ≥ 0.5Ω TO PREVENT DAMAGE TO THE LT1186F HIGH-SIDE
SENSE RESISTOR DUE TO SURGE CURRENTS AT TURN-ON
C1 MUST BE A LOW LOSS CAPACITOR, C1 = WIMA MKP-20
Q1, Q2 = ZETEX ZTX849 OR ROHM 2SC5001
0µA TO 50µA I
CCFL
CURRENT GIVES
0mA TO 6mA LAMP CURRENT
FOR A TYPICAL DISPLAY.
FOR ADDITIONAL CCFL/LCD CONTRAST APPLICATION CIRCUITS,
REFER TO THE LT1182/83/84/84F DATA SHEET
1
LT1186F
U
W U
W W U W
PACKAGE/ORDER INFORMATION
ABSOLUTE MAXIMUM RATINGS
VCC ........................................................................... 7V
BAT, Royer, BULB .................................................. 30V
CCFL VSW ............................................................... 60V
Shutdown ................................................................. 6V
TOP VIEW
ORDER PART
CCFL PGND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CCFL V
BULB
BAT
SW
NUMBER
I
CCFL
DIO
LT1186FCS
LT1186FIS
I
CCFL Input Current .............................................. 10mA
CCFL V
C
ROYER
DIO Input Current (Peak, <100ms).................... 100mA
Digital Inputs ................................ –0.3V to VCC + 0.3V
Digital Outputs.............................. –0.3V to VCC + 0.3V
DAC Output Voltage ....................... –20V to VCC + 0.3V
Junction Temperature (Note 1)........................... 100°C
Operating Ambient Temperature Range
AGND
SHDN
CLK
V
CC
I
OUT
D
D
OUT
IN
CS
S PACKAGE
16-LEAD PLASTIC SO
TJMAX = 100°C, θJA = 100°C/W
LT1186FC ............................................ 0°C to 100°C
LT1186FI .......................................... – 40°C to 100°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................ 300°C
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
TA = 25°C, VCC = SHUTDOWN = DIN = CS = 3.3V, BAT = Royer = BULB = 12V, ICCFL = CCFL VSW = Open, DOUT = Three-State, DIO = IOUT
= CLK = GND, CCFL VC = 0.5V, unless otherwise specified.
xSYMBOL PARAMETER
CONDITIONS
3V ≤ V ≤ 6.5V, 1/2 Full-Scale DAC Output Current
MIN
TYP
6
MAX
9.5
70
UNITS
mA
µA
I
I
Supply Current
●
Q
CC
SHUTDOWN Supply Current
SHUTDOWN Input Bias Current
SHUTDOWN Threshold Voltage
Switching Frequency
SHUTDOWN = 0V, CCFL V Open (Note 2)
35
5
SHDN
C
SHUTDOWN = 0V, CCFL V = Open
10
µA
C
●
●
●
0.45
0.85
1.2
V
f
Measured at CCFL V , I = 50mA,
175
160
200
200
225
240
kHz
kHz
SW SW
I
= 100µA, CCFL V = Open
CCFL
C
DC(MAX) Maximum Switch Duty Cycle
Measured at CCFL V
80
75
85
85
%
%
SW
SW
BV
Switch Breakdown Voltage
Switch Leakage Current
Measured at CCFL V
60
70
V
V
V
= 12V, Measured at CCFL V
= 30V, Measured at CCFL V
20
40
µA
µA
SW
SW
SW
SW
I
Summing Voltage
3V ≤ V ≤ 6.5V
0.425
0.385
0.465 0.505
0.465 0.555
V
V
CCFL
CC
●
●
∆I
Summing Voltage for
I
= 0µA to 100µA
CCFL
5
15
mV
CCFL
∆Input Programming Current
CCFL V Offset Sink Current
CCFL V = 1.5V, Positive Current Measured into Pin
–5
5
15
µA
C
C
∆CCFL V Source Current for
I
= 25µA, 50µA, 75µA, 100µA,
CCFL
4.70
4.95
5.20
µA/µA
C
∆I
Programming Current
CCFL V = 1.5V
T < 0°C
J
CCFL
C
●
●
●
●
●
4.60
94
4.95
99
5.20
104
0.3
µA/µA
CCFL V to DIO Current Servo Ratio
DIO = 5mA out of Pin, Measure I(V ) at CCFL V = 1.5V
µA/mA
C
C
C
CCFL V Low Clamp Voltage
V
– V = BULB Protect Servo Voltage
BULB
0.1
V
V
V
C
BAT
CCFL V High Clamp Voltage
I
= 100µA
1.7
0.6
2.1
2.4
C
CCFL
CCFL V Switching Threshold
CCFL V DC = 0%
0.95
1.3
C
SW
2
LT1186F
ELECTRICAL CHARACTERISTICS
TA = 25°C, VCC = SHUTDOWN = DIN = CS = 3.3V, BAT = Royer = BULB = 12V, ICCFL = CCFL VSW = Open, DOUT = Three-State, DIO = IOUT
= CLK = GND, CCFL VC = 0.5V, unless otherwise specified.
SYMBOL PARAMETER
CCFL High-Side Sense Servo Current
CONDITIONS
= 100µA, I(V ) = 0µA at CCFL V = 1.5V
T < 0°C
J
MIN
TYP
MAX
UNIT
I
●
●
0.93
0.91
1.00
1.00
1.07
1.07
A
A
CCFL
C
C
CCFL High-Side Sense Servo Current BAT = 5V to 30V, I
= 100µA,
0.1
0.16
%/V
CCFL
Line Regulation
I(V ) = 0µA at CCFL V = 1.5V
C C
CCFL High-Side Sense Supply Current Current Measured into BAT and Royer Pins
●
●
50
100
7.0
150
7.5
µA
BULB Protect Servo Voltage
I
= 100µA, I(V ) = 0µA at CCFL V = 1.5V,
6.5
V
CCFL
C
C
Servo Voltage Measured between BAT and BULB Pins
BULB Input Bias Current
CCFL Switch Current Limit
I
= 100µA, I(V ) = 0µA at CCFL V = 1.5V
5
9
µA
CCFL
C
C
I
Duty Cycle = 50%
Duty Cycle = 75% (Note 3)
●
●
1.25
0.9
1.9
1.6
3.0
2.6
A
A
LIM
V
CCFL Switch On Resistance
CCFL I = 1A
●
0.6
20
1.0
30
Ω
SAT
SW
∆I
∆I
Supply Current Increase During
CCFL Switch On Time
CCFL I = 1A
mA/A
Q
SW
SW
DAC Resolution
8
Bits
DAC Full-Scale Current
V(I ) = 0.465V, Measured in SPI Mode
OUT
48.5
47.0
50
50
51.5
53.0
µA
µA
●
DAC Zero Scale Current
DAC Differential Nonlinearity
DAC Supply Voltage Rejection
Logic Input Current
V(I ) = 0.465V, Measured in SPI Mode
200
±2.0
4
nA
LSB
LSB
µA
OUT
●
●
●
3V ≤ V ≤ 6.5V, I
= Full Scale, V(I ) = 0.465V
2
CC
OUT
OUT
0V ≤ V ≤ V
±1
IN
CC
V
V
V
V
High Level Input Voltage
V
V
= 3.3V
= 5V
●
●
1.9
2
V
V
IH
CC
CC
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Three-State Output Leakage
V
V
= 3.3V
= 5V
●
●
0.45
0.80
V
V
IL
CC
CC
V
V
= 3.3V, I = 400µA
= 5V, I = 400µA
●
●
2.1
2.4
V
V
OH
OL
CC
CC
O
O
V
V
= 3.3V, I = 1mA
= 5V, I = 2mA
●
●
0.4
0.4
V
V
CC
CC
O
O
I
V
= V
CC
●
±5
µA
OZ
CS
SERIAL INTERFACE (Notes 4, 5)
f
t
t
t
t
t
t
t
t
t
t
t
Clock Frequency
●
●
●
●
●
●
●
●
●
●
●
●
2
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
CKS
CSS
DV
Setup Time, CLK↓ Before CS↓
Setup Time, CS↓ Before CLK↑
150
400
150
150
150
150
200
250
150
CS↓ to D
Valid
See Test Circuits
See Test Circuits
OUT
Data in Setup Time Before CLK↑
Data in Hold Time After CLK↑
DS
DH
CLK↓ to D
Valid
DO
OUT
CLK High Time
CLK Low Time
CLK↓ Before CS↑
CKHI
CKLO
CSH
DZ
CS↑ to D
In Hi-Z
See Test Circuits
400
400
OUT
CS↑ Before CLK↑
CKH
3
LT1186F
ELECTRICAL CHARACTERISTICS
TA = 25°C, VCC = SHUTDOWN = DIN = CS = 3.3V, BAT = Royer = BULB = 12V, ICCFL = CCFL VSW = Open, DOUT = Three-State, DIO = IOUT
= CLK = GND, CCFL VC = 0.5V, unless otherwise specified.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
SERIAL INTERFACE (Notes 4, 5)
t
t
CS Low Time
CS High Time
f
= 2MHz
CLK
●
●
4550
400
ns
ns
CSLO
CSHI
The
● denotes specifications which apply over the specified operating
Note 3: For duty cycles (DC) between 50% and 80%, minimum
temperature range.
guaranteed switch current is given by I = 1.4(1.393 – DC) for the
LIM
LT1186F due to internal slope compensation circuitry.
Note 1: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formula:
Note 4: Timings for all input signals are measured at 0.8V for a High-to-
D
Low transition and 2.0V for a Low-to-High transition.
LT1186FCS: T = T + (P )(100°C/W)
J
A
D
Note 5: Timings are guaranteed but not tested.
Note 2: Does not include switch leakage.
W
U
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current
vs Temperature
Shutdown Current
vs Temperature
Shutdown Input Bias Current
vs Temperature
10
9
8
7
6
5
4
3
2
1
0
100
90
8O
70
60
50
40
30
20
10
0
6
5
4
3
2
1
0
V
= 5V
= 3V
CC
V
= 5V
= 3V
CC
V
CC
V
CC
–50 –25
0
25 50 75 100
125
150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
–75
TEMPERATURE (°C)
TEMPERATURE (°C)
LT1186F • G01
LT1186F • G02
LT1186F • G03
Shutdown Threshold Voltage
vs Temperature
Maximum Duty Cycle
vs Temperature
Frequency vs Temperature
240
230
220
210
200
190
180
170
160
1.2
1.1
95
93
91
89
1.0
0.9
0.8
0.7
0.6
87
85
83
81
79
77
75
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
50 75 100 125 150 175
0
25
–75 –50 –25
0
75 100 125 150
175
25 50
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
LT1186F • G04
LT1186F • G05
LT1186F • G06
4
LT1186F
W
U
TYPICAL PERFORMANCE CHARACTERISTICS
ICCFL Summing Voltage
vs Temperature
ICCFL Summing Voltage
Load Regulation
VC Sink Offset Current
vs Temperature
10
0.53
0.52
0.51
0.50
0.49
0.48
0.47
0.46
0.45
0.44
0.43
0.42
0.41
0.40
0.39
0.38
5
4
3
2
1
9
8
7
6
5
CCFL V = 1.5V
C
T = –55°C
T = 25°C
0
CCFL V = 1.0V
C
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
4
3
2
T = 125°C
1
0
–1
–2
–3
CCFL V = 0.5V
C
–75 –50 –25
0
25 50 75 100 125 150 175
0
20 40 60 80 100 120 140 160 180 200
PROGRAMMING CURRENT (µA)
–75 – 50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
I
TEMPERATURE (°C)
CCFL
LT1186F • G09
LT1186F • G07
LT1186F • G08
∆CCFL VC Source Current for
∆ICCFL Programming Current
vs Temperature
Positive DIO Voltage
vs Temperature
Negative DIO Voltage
vs Temperature
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
5.10
1.2
5.05
5.00
4.95
4.90
4.85
4.80
1.0
0.8
0.6
0.4
0.2
0
I(DIO) = 10mA
I(DIO) = 5mA
I(DIO) = 1mA
I(DIO) = 10mA
I(DIO) = 1mA
I
= 100µA
CCFL
I(DIO) = 5mA
I
= 50µA
CCFL
I
= 10µA
CCFL
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
LT1186F • G10
LT1186F • G11
LT1186F • G12
VC to DIO Current Servo
Ratio vs Temperature
VC Low Clamp Voltage
vs Temperature
VC High Clamp Voltage
vs Temperature
103
102
101
100
99
0.30
0.25
0.20
0.15
0.10
0.05
0
2.4
2.3
I(DIO) = 10mA
I(DIO) = 1mA
2.2
2.1
2.0
1.9
1.8
I(DIO) = 5mA
98
97
96
95
1.7
–75 – 50–25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75
0
50 75 100 125 150 175
– 50 –25
25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
LT1186F • G13
LT1186F • G14
LT1186F • G15
5
LT1186F
TYPICAL PERFORMANCE CHARACTERISTICS
W
U
VC Switching Threshold
vs Temperature
BULB Protect Servo Voltage
vs Temperature
BULB Input Bias Current
vs Temperature
7.5
7.4
7.3
7.2
10
8
1.3
1.2
1.1
I
= 100µA
CCFL
6
7.1
7.0
1.0
0.9
0.8
0.7
6.9
6.8
6.7
6.6
6.5
4
2
0
I
= 50µA
CCFL
I
= 10µA
CCFL
0.6
–75 – 50 –25
0
25 50 75 100 125 150 175
–50
–75
–25
0
25 50
75 100
125 150 175
–75
0
50 75 100 125 150 175
– 50 –25
25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
LT1186F • G17
LT1186F • G18
LT1186F • G16
High-Side Sense Supply Current
vs Temperature
High-Side Sense Null
High-Side Sense Null Current Line
Regulation vs Temperature
Current vs Temperature
0.160
0.140
0.120
0.100
0.080
0.060
0.040
0.020
0.000
150
140
130
120
1.060
1.040
1.020
1.000
0.980
0.960
0.940
110
100
90
80
70
60
50
0
–75 –50 –25
0
25 50 75 100 125 150 175
–75 – 50–25
0
25
50 75 100 125
150 175
–75 –50 –25
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
LT1186F • G20
LT1186F • G21
LT1186F • G19
VSW Sat Voltage
vs Switch Current
VSW Current Limit vs Duty Cycle
Forced Beta vs ISW on VSW
110
100
90
80
70
60
50
40
30
20
10
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.5
2.0
T = 0°C
T = 25°C
T = 25°C
T = 125°C
T = –5°C
1.5
T = 125°C
MINIMUM
1.0
0.5
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0
0.3
0.6
0.9
1.2
1.5
0
10 20 30 40 50 60 70 80 90
DUTY CYCLE (%)
CCFL I (A)
SW
SWITCH CURRENT (A)
LT1186F • G24
LT1186F • G22
LT1186F • G23
6
LT1186F
W
U
TYPICAL PERFORMANCE CHARACTERISTICS
DAC IOUT vs Temperature
DAC IOUT vs Supply Voltage
DAC IOUT vs IOUT Bias Voltage
52
51
50
49
48
53
52
51
50
49
48
47
46
45
53
52
51
50
49
48
47
46
45
V
OUT
= 0V
V
J
= 0V
T
= 25°C
OUT
T = 25°C
J
V
CC
= 5V
V
CC
= 5V
V
CC
= 3.3V
V
CC
= 3.3V
75
5
–50
–25
0
25
50
100
4
–20 –15
–10
–5
0
10
0
2
6
8
TEMPERATURE (°C)
OUTPUT BIAS VOLTAGE (V)
SUPPLY VOLTAGE (V)
LT1186F • G25
LT1186F • G27
LT1186F • G26
U
U
U
PIN FUNCTIONS
current provided by the lamp-current programmer circuit.
A single capacitor on the CCFL VC pin provides both stable
loop compensation and an averaging function to the half-
wave-rectified sinusoidal lamp current. Therefore, input
programming current relates to one-half of average lamp
current. This scheme reduces the number of loop com-
pensation components and permits faster loop transient
response in comparison to previously published circuits.
If a floating lamp configuration is used, ground the DIO
pin.
CCFL PGND (Pin 1): This pin is the emitter of an internal
NPN power switch. CCFL switch current flows through
this pin and permits internal, switch-current sensing. The
regulator provides a separate analog ground and power
ground to isolate high current ground paths from low
current signal paths. Linear Technology recommends the
use of star-ground layout techniques.
ICCFL (Pin2):ThispinistheinputtotheCCFLlampcurrent
programming circuit. This pin internally regulates to
465mV. The pin accepts a DC input current signal of 0µA
to 50µA full scale from the DAC. This input signal is
convertedtoa0µAto250µAsourcecurrentattheCCFLVC
pin. As input programming current increases, the regu-
lated lamp current increases. For a typical 6mA lamp, the
range of input programming current is about 0µA to 50µA.
CCFL VC (Pin 4): This pin is the output of the lamp current
programmer circuit and the input of the current compara-
tor for the CCFL regulator. Its uses include frequency
compensation,lamp-currentaveragingforgrounded-lamp
circuits and current limiting. The voltage on the CCFL VC
pin determines the current trip level for switch turn-off.
During normal operation this pin sits at a voltage between
0.95V (zero switch current) and 2.0V (maximum switch
current) with respect to analog ground (AGND). This pin
has a high impedance output and permits external voltage
clamping to adjust current limit. A single capacitor to
ground provides stable loop compensation. This simpli-
fied loop compensation method permits the CCFL regula-
tor to exhibit single-pole transient response behavior and
virtually eliminates transformer output overshoot.
DIO (Pin 3): This pin is the common connection between
the cathode and anode of two internal diodes. The remain-
ing terminals of the two diodes connect to ground. In a
grounded-lamp configuration, DIO connects to the low
voltage side of the lamp. Bidirectional lamp current flows
in the DIO pin and thus the diodes conduct alternately on
half cycles. Lamp current is controlled by monitoring one-
half of the average lamp current. The diode conducting on
negativehalfcycleshasone-tenthofitscurrentdivertedto
the CCFL VC pin. This current nulls against the source
7
LT1186F
U
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PIN FUNCTIONS
AGND (Pin 5): This is the low current analog ground. It is
the negative sense terminal for the internal 1.24V refer-
ence and the ICCFL summing voltage in the LT1186F.
Connect low current signal paths that terminate to ground
and frequency compensation components that terminate
to ground directly to this pin for best regulation and
performance.
DOUT (Pin 10): This pin is the digital output for the DAC. In
SPI mode, DOUT is in three-state until CS falls low. The
DOUT pin then serially transfers the previous 8-bit data on
every falling edge of the clock. When CS rises high again,
DOUT returns to a three-state condition. In pulse mode,
DOUT is always three-stated.
IOUT (Pin 11): This pin is the analog current output for the
DAC and provides an output current of 50 ±3µA over
temperature. This pin can be biased from –20V to 2V for
a 3.3V VCC supply voltage or from –20V to 2.5V for a 5V
VCCsupplyvoltage.However,thispinistiedtotheICCFL pin
and provides the programming current which sets operat-
ing lamp current. The IOUT pin has very little bias voltage
change when it is tied to the ICCFL pin as ICCFL is regulated.
TheprogrammingcurrentissourcedfromtheIOUT pinand
sunk by the ICCFL pin.
SHDN (Pin 6): Pulling this pin low causes complete
regulator shutdown with quiescent current typically re-
duced to 35µA. If the pin is not used, use a pull-up resistor
to force a logic high level (maximum of 6V) or tie directly
to VCC. In a shutdown condition, the DAC retains its last
output current setting and returns to this level when the
logic-low signal at the shutdown pin is removed.
CLK (Pin 7): This pin is the shift clock for the DAC. This
clock synchronizes the serial data and is a Schmitt
trigger input. In standard SPI mode, the clock shifts data
into DIN and out of DOUT on the rising and falling edges
of the clock respectively. In pulse mode, the rising edge
oftheclockeitherincrementsordecrementsthecounter.
This action depends on the choice of a 1-wire interface
(increment only) or a 2-wire interface (increment/decre-
ment).
VCC (Pin 12): This is the supply pin for the LT1186F. The
IC accepts an input voltage range of 3V minimum to 6.5V
maximum with little change in quiescent current (zero
switch current). An internal, low-dropout regulator pro-
vides a 2.4V supply for most of the internal circuitry.
Supply current increases as switch current increases at a
rate approximately 1/50 of switch current. This corre-
sponds to a forced Beta of 50 for the power switch. The IC
incorporates undervoltage lockout by sensing regulator
dropout and locking out switching for input voltages
below 2.5V. Hysteresis is not used to maximize the useful
range of input voltage. The typical input voltage is a 3.3V
or 5V logic supply.
CS (Pin 8): This pin is the chip select input for the DAC. In
SPI mode, a logic low on the CS pin enables the DAC to
receive and transfer 8-bit serial data. After the serial input
data is shifted in, a rising edge of CS transfers the data into
the counter, the DAC assumes the new IOUT value and the
DOUT pin returns to the high impedance state. On power
up,alogichighplacestheDACintopulsemode.PullingCS
low after this places the DAC into SPI mode until VCC
resets.
ROYER (Pin 13): This pin connects to the center-tapped
primary of the Royer converter and is used with the BAT
pin in a floating-lamp configuration where lamp current is
controlled by sensing Royer primary-side converter cur-
rent. This pin is the inverting terminal of a high-side
current sense amplifier. The typical quiescent current is
50µA into the pin. If the CCFL regulator is not used in a
floating-lamp configuration, tie the Royer and BAT pins
together.
DIN or UP/DN (Pin 9): This pin is the digital input for the
DAC. In SPI mode, the 8-bit serial data is shifted into the
DIN input on each rising edge of the clock signal. In pulse
mode, on power up, a logic high at DIN transfers the pin
function from DIN to UP/DN, puts the counter into incre-
ment-only mode and the pin function shifts to up or down
increment control of DAC output current. If UP/DN re-
ceives a logic-low signal, the counter configures to incre-
ment/decrement mode until VCC resets.
8
LT1186F
U
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PIN FUNCTIONS
BAT (Pin 14): This pin connects to the battery or AC wall
adapter voltage from which the CCFL Royer converter
operates. This voltage is typically higher than the VCC
supplyvoltagebutcanequalVCCifVCC isa5Vlogicsupply.
The BAT voltage must be at least 2.1V greater than the
internal 2.4V regulator or 4.5V. This pin provides biasing
for the lamp-current programming block, is used with the
Royer pin for floating-lamp configurations and connects
to one input for the open-lamp protection circuitry. For
floating-lamp configurations, this pin is the noninverting
terminal of a high-side current sense amplifier. The typical
quiescent current is 50µA into the pin. The BAT and Royer
pins monitor the primary-side Royer converter current
through an internal 0.1Ω topside current sense resistor. A
0A to1A primary-side, center tap converter current is
translatedtoaninputsignalrangeof0mVto100mVforthe
current sense amplifier. This input range translates to a
0µA to 500µA sink current at the CCFL VC pin that nulls
against the source current provided by the programmer
circuit. The BAT pin also connects to the topside of the
internalclampbetweentheBATandBULBpinsthatisused
for open-lamp protection.
conditions and limits the maximum secondary output
under start-up conditions or open-lamp conditions. This
eases transformer voltage rating requirements. Set the
voltage limit to ensure lamp start-up with worst-case,
lamp start voltages and cold temperature, system operat-
ing conditions. The BULB pin connects to the junction of
an external divider network. The divider network connects
from the center tap of the Royer transformer or the actual
battery supply voltage to the topside of the current source
“tail inductor.” A capacitor across the top of the divider
network filters switching ripple and sets a time constant
that determines how quickly the clamp activates. When
the comparator activates, sink current is generated to pull
the CCFL VC pin down. This action transfers the entire
regulator loop from current mode operation into voltage
mode operation.
CCFL VSW (Pin 16): This pin is the collector of the internal
NPN power switch for the CCFL regulator. The power
switch provides a minimum of 1.25A. Maximum switch
current is a function of duty cycle as internal slope com-
pensation ensures stability with duty cycles greater than
50%. Using a driver loop to automatically adapt base drive
current to the minimum required to keep the switch in a
quasi-saturationstateyieldsfastswitchingtimesandhigh
efficiency operation. The ratio of switch current to driver
current is about 50:1.
BULB (Pin 15): This pin connects to the low side of a 7V
threshold comparator between the BAT and BULB pins.
This circuit sets the maximum voltage level across the
primary side of the Royer converter under all operating
TEST CIRCUITS
Voltage Waveforms for tDZ, tDV
Voltage Waveforms for tDO
Load Circuit for tDO
1.4V
2.0V
CLK
CS
0.8V
0.8V
3k
t
DO
D
OUT
2.4V
D
90%
10%
OUT
2.4V
0.4V
100pF
D
OUT
WAVEFORM 1
(SEE NOTE 1)
0.4V
t
LT1186F • TC03
DZ
t
LT1186F • TC01
DV
D
OUT
WAVEFORM 2
(SEE NOTE 2)
Load Circuit for tDZ, tDV
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL
CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS
DISABLED BY CS
3k
5V t WAVEFORM 2, t
DZ DV
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL
CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS
DISABLED BY CS
D
OUT
t
WAVEFORM 1
LT1186F • TC04
DZ
100pF
LT1186F • TC02
9
LT1186F
W
BLOCK DIAGRAM
LT1186F DAC Programmable CCFL Switching Regulator
V
BAT
14
ROYER
13
CC
12
UNDER-
VOLTAGE
LOCKOUT
THERMAL
SHUTDOWN
2.4V
REGULATOR
6
SHUTDOWN
SHUTDOWN
CCFL
SW
V
16
200kHz
OSC
Q1
DRIVE
LOGIC
COMP
R4
0.1Ω
ANTI-
SAT
+
–
D2
6V
g
m
R3
1k
+
R1
0.125Ω
CURRENT
AMP
Q5
1×
Q6
2×
Q11
–
Q3
2×
+
CCFL
GAIN = 4.4
Q4
5×
Q8
1×
Q7
9×
–
Q10
2×
Q9
3×
V1
0.465V
D1
3
15
BULB
4
2
5
1
I
AGND
DIO
CCFL
CCFL
PGND
CCFL
V
C
LATCH
AND
LOGIC
VOLTAGE
REFERENCE
SHDN
POWER-ON
RESET
UP ONLY/
UP/DN
LATCH
AND
LOGIC
8-BIT
CURRENT
DAC
SHDN
I
11
OUT
50µA
FULL SCALE
MODE SELECT
0 = PULSE
1 = SPI
8
CLK
CLK
7
9
8
8-BIT COUNTER/REGISTER
9-BIT SHIFT REGISTER
UP/DN
8
D
IN
CONTROL
LOGIC
8
CS
CLK
D
Q9
10
OUT
DO(LSB)
LT1186F • BD
10
LT1186F
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APPLICATIONS INFORMATION
Introduction
to the lamp and reduce the parasitic loss from stray lamp-
to-frame capacitance, extending illumination range.
Current generation portable computers and instruments
use backlit Liquid Crystal Displays (LCDs). Cold Cathode
Fluorescent Lamps (CCFLs) provide the highest available
efficiency in back lighting the display. Providing the most
light out for the least amount of input power is the most
important goal. These lamps require high voltage AC to
operate, mandating an efficient high voltage DC/AC con-
verter. The lamps operate from DC, but migration effects
damage the lamp and shorten its lifetime. Lamp drive
should contain zero DC component. In addition to good
efficiency, the converter should deliver the lamp drive in
the form of a sine wave. This minimizes EMI and RF
emissions. Such emissions can interfere with other de-
vices and can also degrade overall operating efficiency.
Sinusoidal CCFL drive maximizes current-to-light conver-
sion in the lamp. The circuit should also permit lamp
intensity control from zero to full brightness with no
hysteresis or “pop-on.”
Block Diagram Operation
The LT1186F is a fixed frequency, current mode switching
regulator. A fixed frequency, current mode switcher con-
trols switch duty cycle directly by switch current rather
than by output voltage. Referring to the block diagram for
the LT1186F, the switch turns ON at the start of each
oscillator cycle. The switch turns OFF when switch current
reaches a predetermined level. The control of output lamp
current is obtained by using the output of a unique
programming block to set current trip level. The current
mode switching technique has several advantages. First,
it provides excellent rejection of input voltage variations.
Second, it reduces the 90° phase shift at mid-frequencies
intheenergystorageinductor. Thissimplifiesclosed-loop
frequency compensation under widely varying input volt-
age or output load conditions. Finally, it allows simple
pulse-by-pulsecurrentlimitingtoprovidemaximumswitch
protection under output overload or short-circuit condi-
tions.
The small size and battery-powered operation associated
with LCD equipped apparatus dictate low component
count and high efficiency for these circuits. Size con-
straintsplaceseverelimitationsoncircuitarchitectureand
longbatterylifeisapriority. Laptopandhandheldportable
computers offer an excellent example. The CCFL and its
power supply are responsible for almost 50% of the
battery drain. Additionally, all components, including PC
board and hardware, usually must fit within the LCD
enclosure with a height restriction of 5mm to 10mm.
The LT1186F incorporates a low dropout internal regula-
tor that provides a 2.4V supply for most of the internal
circuitry. This low dropout design allows input voltage to
vary from 3V to 6.5V with little change in quiescent
current. Anactivelowshutdownpintypicallyreducestotal
supply current to 35µA by shutting off the 2.4V regulator
and locks out switching action for standby operation. The
ICincorporatesundervoltagelockoutbysensingregulator
dropout and locking out switching below about 2.5V. The
regulator also provides thermal shutdown protection that
locks out switching in the presence of excessive junction
temperatures.
The CCFL regulator drives an inductor that acts as a
switched-modecurrentsourceforacurrent-drivenRoyer-
class converter with efficiencies as high as 90%. The
control loop forces the CCFL PWM to modulate the aver-
age inductor current to maintain constant current in the
lamp. The constant current value, and thus lamp intensity,
is programmable. This drive technique provides a wide
range of intensity control. A unique lamp-current pro-
gramming block permits either grounded lamp or floating
lampconfigurations.Groundedlampcircuitsdirectlysense
one-half of average lamp current. Floating lamp circuits
directly sense the Royer’s primary-side converter current.
Floating-lampcircuitsprovidesymmetricdifferentialdrive
A200kHzoscillatoristhebasicclockforallinternaltiming.
The oscillator turns on the output switch via its own logic
and driver circuitry. Adaptive anti-sat circuitry detects the
onset of saturation in the power switch and adjusts base
drive current instantaneously to limit switch saturation.
This minimizes driver dissipation and provides rapid turn-
off of the switch. The CCFL power switch is guaranteed to
provide a minimum of 1.25A in the LT1186F. The anti-sat
11
LT1186F
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APPLICATIONS INFORMATION
circuitryprovidesaratioofswitchcurrenttodrivercurrent
of about 50:1.
POWER ON
V
CC
8-Bit Current Output DAC
CS ALWAYS HIGH
The8-bitcurrentoutputDACisguaranteedmonotonicand
is digitally adjustable by the 8-bit counter in 256 equal
steps. Onpowerup, thecounterresetsto80HandtheDAC
assumes its mid-range value. The current output IOUT
drives the ICCFL pin and sets control current for the lamp
current programming block. The DAC has its own 1.24V
bandgap reference and a voltage to current converter that
is trimmed at wafer sort to provide the precision full-scale
current reference. Over temperature, the current output of
the DAC is 50µA ±6%.
D
ALWAYS HIGH
IN
LT1186F • F01c
Figure 1c. Pulse Mode Setup (Increment Only)
POWER ON
V
CC
CS ALWAYS HIGH
UP/DN
Digital Interface
UP/DN EVER GOES LOW
LT1186F • F01d
On power-up, a logic high at CS configures the DAC into
pulse mode. If CS is ever pulled low, the chip configures
into SPI mode until VCC resets. On power-up in pulse
mode, a logic high at DIN puts the counter into increment-
only mode. If UP/DN (DIN) is ever pulled low, the counter
configures into increment/decrement mode until VCC re-
sets. These modes are illustrated in Figure 1.
Figure 1d. Pulse Mode Setup (Increment/Decrement)
Standard SPI Mode
Refer to the serial interface operating sequence in Figure
2. A falling edge at CS initiates the data transfer. After the
falling CS is recognized, DOUT comes out of three-state.
Theclock(CLK)synchronizesthedatatransfer.Eachinput
bitshiftsintoDIN beginningwiththeMSBontherisingCLK
edge and each previous data bit shifts out of DOUT begin-
ning with the MSB on the falling CLK edge. After the 8-bit
serial input data is shifted in, a rising edge at CS transfers
the data into the counter, the DAC assumes the new value
IOUT =(8-bitserialinputdata)(50µA)/255andtheDOUT pin
returns to a high impedance state.
SINGLE DAC
CS STAYS
HIGH
CS EVER
GOES LOW
SPI MODE
PULSE MODE
D
(UP/DN)
IN
D
STAYS
IN
EVER GOES
LOW
HIGH
INCREMENT/
DECREMENT
INCREMENT-
ONLY
1-Wire Interface (Pulse Mode)
LT1186F • F01a
In increment-only pulse mode, each rising edge of CLK
increments the upper six bits of the counter by one count.
When incremented beyond 11111100B, the counter rolls
over and sets the DAC to the minimum value 00000000B.
Therefore, a single pulse applied to CLK increases the
upper 6-bit counter by one-step, and 63 pulse applied to
CLK decreases the counter by one-step. The last two LSBs
are always zero in this mode. IOUT = (B7B6B5B4B3B2B1B0)
(50µA)/255. The upper 6-bit counter = B7B6B5B4B3B2 and
B1 = B0 = 0. To configure the LT1186F into increment-only
mode, tie CS and DIN to VCC.
Figure 1a. Tree Diagram (LT1186F DAC Operating Modes)
POWER ON
V
CC
CS
CS EVER GOES LOW
LT1186F • F01b
Figure 1b. SPI Mode Setup
12
LT1186F
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APPLICATIONS INFORMATION
t
t
CSLO
CSHI
CS
t
CKS
t
t
CSH
CKHI
CLK
t
CKH
t
t
t
t
CKLO
CSS
DS
DH
D
IN
D6
D5
D4
D3
D2
D1
D0
D7
DV
t
t
t
DO
DZ
Hi-Z
Hi-Z
D
D7′
D6′
D5′
D4′
D3′
D2′
D1′
D0′
D7
OUT
LT1186F • F02
Figure 2. SPI Interface Timing Specification
2-Wire Interface (Pulse Mode)
frequency compensation. This compensation scheme
meant that the loop had to be fairly slow and that output
overshoot with start-up or overload conditions had to be
carefully evaluated in terms of transformer stress and
breakdown voltage requirements.
In increment/decrement pulse mode, a logic high at UP/
DN programs the counter into increment mode and each
rising edge of CLK increments the upper six bits of the
counter by one. The counter stops incrementing at
11111100B. A logic low at UP/DN programs the counter
into decrement mode and each rising edge of CLK decre-
mentstheuppersixbitsofthecounterbyone. Thecounter
stops decrementing at 00000000B. The last two LSBs are
always zero in this mode. IOUT = (B7B6B5B4B3B2B1B0)
(50µA)/255. The upper 6-bit counter = B7B6B5B4B3B2 and
B1 = B0 = 0. To configure the LT1186F into increment/
decrement mode, tie CS to VCC and pulse the UP/DN pin
once on power-up.
The LT1186F eliminates the error amplifier concept en-
tirely and replaces it with a lamp current programming
block. This block provides an easy-to-use interface to
program lamp current. The programmer circuit also re-
duces the number of time constants in the control loop by
combining the error signal conversion scheme and fre-
quency compensation into a single capacitor. The control
loop thus exhibits the response of a single pole system,
allows for faster loop transient response and virtually
eliminates overshoot under start-up or overload condi-
tions.
Simplified Lamp Current Programming
A programming block in the LT1186F controls lamp
current, permitting either grounded lamp or floating lamp
configurations. Grounded configurations control lamp
current by directly controlling one-half of actual lamp
current and converting it to a feedback signal to close a
control loop. Floating configurations control lamp current
by directly controlling the Royer’s primary-side converter
currentandgeneratingafeedbacksignaltocloseacontrol
loop.
Lamp current is programmed at the input of the program-
mer block, the ICCFL pin. This pin is the input of a shunt
regulator and accepts a DC input current signal of 0µA to
50µAfromtheDAC. Thisinputsignalisconvertedtoa0µA
to 250µA source current at the CCFL VC pin. The program-
mer circuit is simply a current-to-current converter with a
gain of five. The typical input current programming range
for 0mA to 6mA lamp current is 0µA to 50µA.
The ICCFL pin is sensitive to capacitive loading and will
oscillate with capacitance greater than 10pF. For example,
loading the ICCFL pin with a 1× or 10× scope probe causes
oscillation and erratic CCFL regulator operation because
of the probe’s respective input capacitance. A current
meter in series with the ICCFL pin will also produce oscil-
Previous backlighting solutions have used a traditional
erroramplifierinthecontrollooptoregulatelampcurrent.
ThisapproachconvertedanRMScurrentintoaDCvoltage
for the input of the error amplifier. This approach used
several time constants in order to provide stable loop
13
LT1186F
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APPLICATIONS INFORMATION
lation due to its shunt capacitance. Use a decoupling
resistor of several kilohms between the ICCFL pin and the
IOUT pin if excessive trace stray capacitance exists. Nor-
mally, this resistor is not required.
The transfer function between lamp current and input
programmingcurrentmustbeempiricallydeterminedand
is dependent on the particular lamp/display housing com-
bination used. The lamp and display housing are a distrib-
uted loss structure due to parasitic lamp-to-frame capaci-
tance. This means that the current flowing at the high-
voltage side of the lamp is higher than what is flowing at
the DIO pin side of the lamp. The input programming
current is set to control lamp current at the high-voltage
side of the lamp, even though the feedback signal is the
lamp current at the bottom of the lamp. This ensures that
the lamp is not overdriven which can degrade the lamp’s
operating lifetime. Therefore, the full scale current of the
DAC does not necessarily correspond to the current re-
quired to set maximum lamp current.
In some applications, the maximum programming current
required at the ICCFL pin for a maximum lamp current will be
less than the full-scale output current of the DAC, which is
50µA. The system designer can either limit the maximum
programmingcurrentthroughsoftwarebuiltintothesystem,
oruseacurrentsplitterwhichshuntsapercentageofthefull-
scale current from the ICCFL pin. A splitter circuit is illustrated
in Figure 3. A divider string is used from a reference voltage
to set up a voltage level equal to the ICCFL summing voltage,
or 465mV. The main current flowing in the divider string
should be chosen to swamp out the effects of the shunted
current into the divider string.
Floating Lamp Configuration
I
FULL-SCALE
V(I
)
CCFL
I = 50µA
OUT
In a floating lamp configuration, the lamp is fully floating
with no galvanic connection to ground. This allows the
transformer to provide symmetric differential drive to the
lamp. Balanced drive eliminates the field imbalance asso-
ciated with parasitic lamp-to-frame capacitance and re-
duces“thermometering”(unevenlampintensityalongthe
lamp length) at low lamp currents.
R1
XI
50µA
465mV
0 < X < 1
SELECT V1 WITHIN THE DAC I
COMPLIANCE RANGE
(EX. V1 = 2V FOR V = 3.3V OR 5V)
CHOOSE I1 >> (1 – X)I
OUT
V1
V
REF
I
CC
I1
R3
R2
R1 = (V1 – 0.465)/(X)(50µA)
V(I
)
CCFL
R2 = (V1 – 0.465)/(1 – X)(50µA)
(1 – X)I
R4
R3 = (V
– 0.465)/I1
REF
R4 = 0.465R3/[(1 – X) 50µAR3
+ (V – 0.465)]
REF
LT1186F • F03
Figure 3
Carefully evaluate display designs in relation to the physi-
cal layout of the lamp, its leads and the construction of the
display housing. Parasitic capacitance from any high
voltage point to DC or AC ground creates paths for
unwanted current flow. This parasitic current flow de-
grades electrical efficiency and losses up to 25% have
been observed in practice. As an example, at a Royer
operating frequency of 60kHz, 1pF of stray capacitance
represents an impedance of 2.65MΩ. With an operating
lamp voltage of 400V and an operating lamp current of
6mA, the parasitic current is 150µA. This additional cur-
rent must be supplied by the transformer secondary.
Layout techniques that increase parasitic capacitance
include long high voltage lamp leads, reflective metal foil
around the lamp and displays supplied in metal enclo-
sures. Losses for a good display are under 5%, whereas,
losses for a bad display range from 5% to 25%. Lossy
displays are the primary reason to use a floating lamp
configuration. Providing symmetric, differential drive to
the lamp reduces the total parasitic loss by one-half.
Grounded Lamp Configuration
In a grounded lamp configuration, the low voltage side of
the lamp connects directly to the LT1186F DIO pin. This
pin is the common connection between the cathode and
anode of two internal diodes. In previous grounded lamp
solutions, these diodes were discrete units and are now
integrated onto the IC, saving cost and board space.
Bidirectional lamp current flows in the DIO pin and thus,
the diodes conduct alternately on half cycles. Lamp cur-
rent is controlled by monitoring one-half of the average
lamp current. The diode conducting on negative half
cycles has one-tenth of its current diverted to the CCFL pin
and nulls against the source current provided by the lamp
current programmer circuit. The compensation capacitor
ontheCCFLVC pinprovidesstableloopcompensationand
an averaging function to the rectified sinusoidal lamp
current. Therefore, input programming current relates to
one-half of average lamp current.
14
LT1186F
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APPLICATIONS INFORMATION
Maintaining closed-loop control of lamp current in a
floating lamp configuration necessitates deriving a feed-
back signal from the primary side of the Royer trans-
former. Previous solutions have used an external preci-
sion shunt and high-side sense amplifier configuration.
This approach has been integrated onto the LT1186F for
simplicity of design and ease of use. An internal 0.1Ω
resistor monitors the Royer converter current and con-
nects between the input terminals of a high-side sense
amplifier. A 0 – 1 Amp Royer primary-side, center-tap
current is translated to a 0µA to 500µA sink current at the
CCFL VC pin to null against the source current provided by
the lamp current programmer circuit. The compensation
capacitor on the CCFL VC pin provides stable loop com-
pensation and an averaging function to the error sink
current. Therefore, input programming current is related
to average Royer converter current. Floating lamp circuits
operate similarly to grounded lamp circuits except for the
derivation of the feedback signal.
grounded lamp circuits do not make use of the high-side
sense resistor.
Input Capacitor Type
Caution must be used in selecting the input capacitor type
for switching regulators. Aluminum electrolytics are elec-
tricallyruggedandthelowestcost, butarephysicallylarge
to meet required ripple current ratings, and size con-
straints (especially height) may preclude their use. Ce-
ramic capacitors are now available in larger values and
their high ripple current and voltage rating make them
ideal for input bypassing. Cost is fairly high and footprint
can be large.
Solid tantalum capacitors would be a good choice except
for a history of occasional failure when subjected to large
current surges during start-up. The input bypass capaci-
tor of regulators can see these high surges when a battery
or high capacitance source is connected. Some manufac-
turers have developed tantalum capacitor lines specially
tested for surge capability (AVX TPS series for instance),
but even these units may fail if the input voltage surge
approaches the capacitor’s maximum voltage rating. AVX
recommendsderatingthecapacitorvoltageby2:1forhigh
surge applications.
The transfer function between lamp current and input
programmingcurrentmustbeempiricallydeterminedand
is dependent upon a myriad of factors including lamp
characteristics, display construction, transformer turns
ratio and the tuning of the Royer oscillator. Once again,
lamp current will be slightly higher at one end of the lamp
and input programming current should be set for this
higher level to ensure that the lamp is not overdriven.
Applications Support
Linear Technology invests an enormous amount of time,
resources and technical expertise in understanding, de-
signing and evaluating backlight/LCD contrast solutions
for system designers. The design of an efficient and
compact LCD backlight system is a study of compromise
in a transduced electronic system. Every aspect of the
design is interrelated and any design change requires
complete re-evaluation for all other critical design param-
eters. Linear Technology has engineered one of the most
complete test and evaluation setups for backlight designs
and understands the issues and tradeoffs in achieving a
compact, efficient and economical customer solution.
Linear Technology welcomes the opportunity to discuss,
design, evaluate and optimize any backlight/LCD contrast
system with a customer. For further information on back-
light/LCD contrast designs, consult the References.
Theinternal0.1Ωhigh-sidesenseresistorontheLT1186F
is rated for a maximum DC current of 1A. This resistor can
be damaged by extremely high surge currents at start-up.
The Royer converter typically uses a few microfarads of
bypass capacitance at the center tap of the transformer.
This capacitor charges up when the system is first pow-
eredbythebatterypackoranACwalladapter. Theamount
of current delivered at start-up can be very large if the total
impedance in this path is small and the voltage source has
high current capability. Linear Technology recommends
the use of an aluminum electrolytic for the transformer
center-tap bypass capacitor with an ESR greater than or
equal to 0.5Ω. This lowers the peak surge currents to an
acceptable level. In general, the wire and trace inductance
in this path also help reduce the di/dt of the surge current.
This issue only exists with floating lamp circuits as
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LT1186F
U
W U U
APPLICATIONS INFORMATION
References
1. Williams, Jim. August 1992. Illumination Circuitry for
Liquid Crystal Displays. Linear Technology Corporation,
Application Note 49.
4. Williams, Jim. April 1995. A Precision Wideband Cur-
rent Probe for LCD Backlight Measurement. Linear Tech-
nology Corporation, Design Note 101.
2. Williams, Jim. August 1993. Techniques for 92% Effi-
cient LCD Illumination. Linear Technology Corporation,
Application Note 55.
5. LT1182/LT1183/LT1184/LT1184F Data Sheet. CCFL/
LCD Contrast Switching Regulators. April 1995. Linear
Technology Corporation.
3. Bonte, Anthony. March 1995. LT1182 Floating CCFL
with Dual Polarity Contrast. Linear Technology Corpora-
tion, Design Note 99.
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
0.010 – 0.020
(0.254 – 0.508)
16
15
14
13
12
11
10
9
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0° – 8° TYP
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
0.016 – 0.050
0.406 – 1.270
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
2
3
4
5
6
7
8
S16 0695
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1107
Micropower DC/DC Converter for LCD Contrast Control
1A, 63kHz, Hysteretic
1.25A, 100kHz
LT1172
Current Mode Switching Regulator for CCFL or LCD Contrast Control
Micropower DC/DC Converter for LCD Contrast Control
LT1173
1A, 24kHz, Hysteretic
LT1182
Dual Current Mode Switching Regulator for CCFL and LCD Contrast Control 1.25A, 0.625A, 200kHz
Dual Current Mode Switching Regulator for CCFL and LCD Contrast Control 1.25A, 0.625A, 200kHz
LT1183
LT1184
Current Mode Switching Regulator for CCFL Control
1.25A, 200kHz
1.25A, 200kHz
1.5A, 500kHz
LT1184F
LT1372
Current Mode Switching Regulator for CCFL Control
Current Mode Switching Regulator for CCFL or LCD Contrast Contol
LT/GP 1096 7K REV A • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1995
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
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(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977
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