LT1424CS8-9#PBF [Linear]
LT1424-9 - Isolated Flyback Switching Regulator with 9V Output; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C;
| 型号： | LT1424CS8-9#PBF |
| 厂家： | 
Linear |
| 描述： | LT1424-9 - Isolated Flyback Switching Regulator with 9V Output; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C 开关 光电二极管 |
| 文件： | 总16页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1424-9
Isolated Flyback
Switching Regulator
with 9V Output
U
FEATURES
DESCRIPTIO
The LT®1424-9 is a monolithic high power switching
regulator specifically designed for the isolated flyback
topology. No “third winding” or optoisolator is required;
the integrated circuit senses the isolated output voltage
directly from the primary side flyback waveform. A high
current, high efficiency switch is included on the die along
with all oscillator, control and protection circuitry.
■
No Transformer “Third Winding” or Optoisolator
Required
■
Application Circuit Meets PCMCIA Type II
Height Requirement
■
Fixed, Application Specific 9V Output Voltage
■
Regulation Maintained Well into Discontinuous
Mode (Light Load)
■
Load Compensation Provides Excellent
The LT1424-9 operates with input supply voltages from
3V to 20V and draws only 7mA quiescent current. It can
deliver up to 200mA at 9V with no external power devices.
By utilizing current mode switching techniques, it pro-
vides excellent AC and DC line regulation.
Load Regulation
■
Available in 8-Pin PDIP and SO Packages
■
Operating Frequency: 285kHz
U
APPLICATIO S
TheLT1424-9hasanumberoffeaturesnotfoundonother
switching regulator ICs. Its unique control circuitry can
maintain regulation well into discontinuous mode. Load
compensation circuitry allows for improved load regula-
tion. An externally activated shutdown mode reduces total
supply current to 20µA typical for standby operation.
■
Ethernet Isolated 5V to –9V Converter
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
–9V PCMCIA Type II Isolated LAN Supply
(2.41mm Maximum Component Height)
C6
220pF
ISOLATION
BARRIER
R2
75Ω
5V
MBRS130LT3
C1
10µF
25V
R1
D1
C2
10µF
25V
OUT
0.1µF
75Ω
1N5248
C5
220pF
COM
1
3
LT1424-9
C3
C4
10µF
25V
1.8k
2
1
3
4
8
7
6
5
10µF
T1
D2
MBR0540T4
V
R
CCOMP
C
25V
SHDN
SYNC
SGND
V
IN
2
4
100k
1000pF
–9V
200mA
V
47pF
SW
1424 TA01
1:1
C1, C2, C3, C4: MARCON THCS50E1E106Z CERAMIC
PGND
0.1µF
INPUT
COM
CAPACITOR, SIZE 1812. (847) 696-2000
T1: COILTRONICS CTX02-13483
sn14249 14249fs
1
LT1424-9
W W U W
U
W U
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Note 1)
ORDER PART
Supply Voltage ........................................................ 20V
Switch Voltage......................................................... 35V
SHDN, SYNC Pin Voltage........................................... 7V
Operating Junction Temperature Range
Commercial .......................................... 0°C to 125°C
Industrial ......................................... –40°C to 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
TOP VIEW
NUMBER
1
2
3
4
8
7
6
5
SHDN
R
CCOMP
LT1424CN8-9
LT1424CS8-9
LT1424IN8-9
LT1424IS8-9
V
V
V
C
IN
SYNC
SGND
SW
PGND
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
S8 PART MARKING
TJMAX = 145°C, θJA = 130°C/ W (N)
JMAX = 145°C, θJA = 110°C/ W (S)
14249
1424I9
T
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSW Open, VC = 1.4V, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply
V
Minimum Input Voltage
Supply Current
●
●
●
●
2.8
7.0
15
3.1
9.5
40
V
mA
µA
V
IN(MIN)
I
CC
Shutdown Mode Supply Current
Shutdown Mode Threshold
0.3
0.9
1.3
Feedback Amplifier
V
Reference Voltage
Measured at V Pin (Note 2)
9.00
8.90
9.15
9.15
9.30
9.40
V
V
REF
SW
●
●
●
g
Feedback Amplifier Transconductance
Feedback Amplifier Source or Sink Current
Feedback Amplifier Clamp Voltage
Reference Voltage/Current Line Regulation
Voltage Gain
∆I = ±10µA (Note 2)
C
400
30
1000
50
1600
80
µmho
µA
m
I
, I
SOURCE SINK
V
1.9
V
CL
5V ≤ V ≤ 18V
●
0.01
500
0.04
%/V
V/V
IN
(Note 3)
Output Switch
BV
Output Switch Breakdown Voltage
Output Switch ON Voltage
Switch Current Limit
I = 5mA
●
●
35
50
V
V
C
V(V
)
SW
I
= 1A
SW
0.55
0.85
I
Duty Cycle = 50%, 0°C ≤ T ≤ 125°C
Duty Cycle = 50%, –40°C ≤ T ≤ 125°C
Duty Cycle = 80%
●
●
1.35
1.20
1.6
1.6
1.3
1.95
1.95
A
A
A
LIM
J
J
Current Amplifier
Control Pin Threshold
Duty Cycle = Minimum
0.95
0.85
1.2
1.2
1.3
1.4
V
V
●
Control Voltage to Switch Transconductance
2
A/V
sn14249 14249fs
2
LT1424-9
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSW Open, VC = 1.4V, unless otherwise specified.
SYMBOL
Timing
f
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Switching Frequency
260
240
285
285
300
320
kHz
kHz
●
●
t
t
t
Minimum Switch ON Time
Flyback Enable Delay Time
Minimum Flyback Enable Time
Maximum Switch Duty Cycle
170
200
150
180
90
260
ns
ns
ns
%
ON
ED
EN
85
Load Compensation
∆V /∆I
1.5
1.5
40
Ω
REF
SW
SYNC Function
Minimum SYNC Amplitude
Synchronization Range
●
●
2.2
V
kHz
kΩ
330
450
SYNC Pin Input Resistance
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 3: Feedback amplifier transconductance is R referred.
REF
Note 4: Voltage gain is R referred.
REF
Note 2: V is a parameter which is measured at the V pin. It differs
REF
SW
from the output voltage because it accounts for output diode drop,
transformer leakage inductance, etc. Nominal output voltage is 9V in the
intended application circuit.
sn14249 14249fs
3
LT1424-9
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Switch Saturation Voltage
vs Switch Current
Switch Current Limit
vs Duty Cycle
Minimum Input Voltage
vs Temperature
1.2
1.0
0.8
0.6
0.4
0.2
0
2.0
1.5
1.0
0.5
0
3.1
3.0
2.9
2.8
2.7
2.6
2.5
2.4
T
= 25°C
A
125°C
25°C
–55°C
0.8
SWITCH CURRENT (A)
1.2 1.4
–50 –25
0
25
50
75
100 125
0
0.2
0.4 0.6
1.0
0
10
30 40 50 60 70 80 90 100
DUTY CYCLE (%)
20
TEMPERATURE (°C)
1424-9 G01
1424-9 G02
1424-9 G03
Reference Voltage
vs Temperature
Feedback Amplifier Output
Current vs Flyback Voltage
VC Pin Threshold and High Clamp
Voltage vs Temperature
9.30
9.25
9.20
9.15
60
40
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
25°C
125°C
–55°C
V
C
HIGH CLAMP
20
0
–20
–40
–60
–80
9.10
9.05
9.00
V
C
THRESHOLD
50
TEMPERATURE (°C)
100 125
7.5 8.0
8.5 9.0 9.5 10.0 10.5 11.0
FLYBACK VOLTAGE (V)
1424-9 G05
–50 –25
0
25
50
75
100 125
–50 –25
0
25
75
TEMPERATURE (°C)
1424-9 G04
1424-9 G06
Switching Frequency
vs Temperature
Minimum Synchronization
Voltage vs Temperature
SHDN Pin Input Current
vs Voltage
300
295
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
1
0
T
= 25°C
A
290
285
280
275
270
–1
–2
–3
–4
265
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
1
3
–50 –25
0
25
75
–50
25
75
0
2
4
5
–25
0
SHDN PIN VOLTAGE (V)
1424-9 G07
1424-9 G08
1424-9 G09
sn14249 14249fs
4
LT1424-9
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Minimum Switch On Time
vs Temperature
Flyback Enable Delay Time
vs Temperature
Minimum Flyback Enable Time
vs Temperature
275
250
250
225
200
175
150
125
275
250
225
200
175
150
125
225
200
175
150
125
100
75
100
100
50
100 125
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
75
–50 –25
0
25
75
TEMPERATURE (°C)
1424-9 G10
1424-9 G11
1424-9 G12
U
U
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PIN FUNCTIONS
PGND (Pin 5): Power Ground. This pin is the emitter of the
powerswitchdeviceandhaslargecurrentsflowingthrough
it. It should be connected directly to a good quality ground
plane.
SHDN (Pin 1): Shutdown. This pin is used to turn off the
regulator and reduce VIN input current to a few tens of
microamperes. The SHDN pin can be left floating when
unused.
VSW (Pin 6): This is the collector node of the output switch
and has large currents flowing through it. Keep the traces
to the switching components as short as possible to
minimize electromagnetic radiation and voltage spikes.
VC (Pin 2): Control Voltage. This pin is the output of the
feedback amplifier and the input of the current compara-
tor.Frequencycompensationoftheoverallloopiseffected
by placing a capacitor between this node and ground.
VIN (Pin 7): Supply Voltage. Bypass input supply pin with
10µF or more. The part goes into undervoltage lockout
when VIN drops below 2.8V. Undervoltage lockout stops
switching and pulls the VC pin low.
SYNC (Pin 3): Pin to synchronize internal oscillator to
external frequency reference. It is directly logic compat-
ible and can be driven with any signal between 10% and
90% duty cycle. If unused, this pin should be tied to
ground.
RCCOMP (Pin 8): Pin for the External Filter Capacitor for
Load Compensation Function. A common 0.1µF
ceramic capacitor will suffice.
SGND (Pin 4): Signal Ground. This pin is a clean ground.
The internal reference and feedback amplifier are referred
to it. Keep the ground path connection to the VC compen-
sation capacitor free of large ground currents.
sn14249 14249fs
5
LT1424-9
W
BLOCK DIAGRAM
V
IN
2.6V
SHDN
SYNC
REGULATOR
V
SW
FLYBACK
ERROR
AMPLIFIER
285kHz
OSCILLATOR
LOGIC
COMP
DRIVER
R
CCOMP
LOAD
COMPENSATION
SGND
V
C
+
CURRENT
AMPLIFIER
R
SENSE
GND IS OMITTED FOR CLARITY
PGND
–
1424BD
W
W
FLYBACK ERROR A PLIFIER DIAGRA
D1
V
IN
T1
+
•
+
ISOLATED
C1
V
OUT
V
SW
•
–
V
IN
Q4
R
FB
I
M
I
FXD
D2
V
C
Q1
ENABLE
V
BG
C
EXT
Q2 Q3
I
R
REF
I
M
1424 EA
sn14249 14249fs
6
LT1424-9
WU
W
TI I G DIAGRA
V
SW
VOLTAGE
COLLAPSE
DETECT
V
FLBK
0.80×
FLBK
V
V
IN
GND
SWITCH
STATE
OFF
ON
OFF
ON
MINIMUM t
ON
ENABLE DELAY
DISABLED
MINIMUM ENABLE TIME
FLYBACK AMP
STATE
ENABLED
DISABLED
1424 TD
sn14249 14249fs
7
LT1424-9
U
OPERATION
The LT1424-9 is a current mode switching regulator IC
that has been designed specifically for the isolated fly-
back topology. The special problem normally encoun-
tered in such circuits is that information relating to the
output voltage on the isolated secondary side of the
transformer must be communicated to the primary side
inordertomaintainregulation. Historically, thishasbeen
done with optoisolators or extra transformer windings.
Optoisolator circuits waste output power and the extra
components they require increase the cost and physical
volume of the power supply. Optoisolators can also
exhibit trouble due to limited dynamic response (tempo-
ral), nonlinearity, unit-to-unit variation and aging over
life. Circuits employing extra transformer windings also
exhibit deficiencies. The extra winding adds to the
transformer’s physical size and cost. Dynamic response
is often mediocre. There is usually no method for main-
taining load regulation versus load.
information from the flyback pulse. Due to space con-
straints, this discussion will not reiterate the basics of
current mode switcher/controllers and isolated flyback
converters. A good source of information on these topics
is LTC’s Application Note 19.
ERROR AMPLIFIER—PSEUDO DC THEORY
Please refer to the simplified diagram of the Flyback Error
Amplifier. Operation is as follows: when output switch Q4
turns off, its collector voltage rises above the VIN rail. The
amplitudeofthisflybackpulse, i.e., thedifferencebetween
it and VIN, is given as:
V
+ V + (I )(ESR)
F
OUT
SEC
SP
V
=
FLBK
N
V = D1 forward voltage
F
SEC
I
= Transformer secondary current
ESR = Total impedance of secondary circuit
The LT1424-9 derives its information about the isolated
output voltage by examining the primary side flyback
pulsewaveform. Inthismannernooptoisolatornorextra
transformer winding is required. This IC is a quantum
improvement over previous approaches because: target
output voltage is directly resistor programmable, regula-
tion is maintained well into discontinuous mode and
optional load compensation is available.
N
= Transformer effective secondary-to-primary
turns ratio
SP
The flyback voltage is then converted to a current by the
action of RFB and Q1. Nearly all of this current flows
through resistor RREF to form a ground-referred voltage.
Thisisthencomparedtotheinternalbandgapreferenceby
the differential transistor pair Q2/Q3. The collector current
from Q2 is mirrored around and subtracted from fixed
current source IFXD at the VC pin. An external capacitor
integrates this net current to provide the control voltage to
set the current mode trip point.
The Block Diagram shows an overall view of the system.
Many of the blocks are similar to those found in tradi-
tional designs including: internal bias regulator, oscilla-
tor, logic, current amplifier and comparator, driver and
output switch. The novel sections include a special
flyback error amplifier and a load compensation mecha-
nism. Also, due to the special dynamic requirements of
flyback control, the logic system contains additional
functionality not found in conventional designs.
The relatively high gain in the overall loop will then cause
the voltage at the RREF resistor to be nearly equal to the
bandgap reference VBG. The relationship between VFLBK
and VBG may then be expressed as:
TheRREF, RRFB andROCOMP resistorsintheBlockDiagram
are application-specific thin-film resistors internal to the
LT1424-9. The capacitor connected to the RCCOMP pin is
external.
V
R
V
FLBK
BG
α
=
or,
R
FB
REF
R
1
FB
V
= V
FLBK
BG
)
)
)
)
α
R
REF
The LT1424-9 operates much the same as traditional
current mode switchers, the major difference being a
different type of error amplifier which derives its feedback
α = Ratio of Q1 I to I
C
E
V
= Internal bandgap reference
BG
sn14249 14249fs
8
LT1424-9
U
OPERATION
Combination with the previous VFLBK expression yields an
expression for VOUT, in terms of the internal reference,
programming resistors, transformer turns ratio and diode
forward voltage drop:
resents the output voltage. This is partly due to rise time
ontheVSW node, butmoreimportantlyduetotransformer
leakage inductance. The latter causes a voltage spike on
the primary side not directly related to output voltage.
(Some time is also required for internal settling of the
feedback amplifier circuitry.)
N
α
R
SP
FB
V
= V
– V – I
(ESR)
OUT
BG
F
SEC
)
)
)
)
R
REF
Inordertomaintainimmunitytothesephenomena, afixed
delay is introduced between the switch turn-off command
and the enabling of the feedback amplifier. This is termed
“enable delay”. In certain cases where the leakage spike is
not sufficiently settled by the end of the enable delay
period, regulation error may result. See Applications
Information section for further details.
Additionally, it includes the effect of nonzero secondary
output impedance. See Load Compensation for details.
ThepracticalaspectsofapplyingthisequationforVOUT are
found in the Applications Information section.
So far, this has been a pseudo-DC treatment of flyback
error amplifier operation. But the flyback signal is a pulse,
not a DC level. Provision must be made to enable the
flyback amplifier only when the flyback pulse is present.
Thisisaccomplishedbythedashedlineconnectionstothe
block labeled “ENABLE”. Timing signals are then required
to enable and disable the flyback amplifier.
Collapse Detect
Once the feedback amplifier is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, that compares the flyback
voltage (RREF referred) to a fixed reference, nominally
80% of VBG. When the flyback waveform drops below this
level, the feedback amplifier is disabled. This action
accommodatesbothcontinuousanddiscontinuousmode
operation.
ERROR AMPLIFIER—DYNAMIC THEORY
There are several timing signals that are required for
proper LT1424-9 operation. Please refer to the Timing
Diagram.
Minimum Enable Time
Minimum Output Switch ON Time
The feedback amplifier, once enabled, stays enabled for a
fixed minimum time period termed “minimum enable
time”. This prevents lock-up, especially when the output
voltage is abnormally low, e.g., during start-up. The mini-
mum enable time period ensures that the VC node is able
to “pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. The “minimum enable time” often determines
thelowloadlevelatwhichoutputvoltageregulationislost.
See Applications Information section for details.
TheLT1424-9effectsoutputvoltageregulationviaflyback
pulse action. If the output switch is not turned on at all,
there will be no flyback pulse, and output voltage informa-
tion is no longer available. This would cause irregular loop
response and start-up/latchup problems. The solution
chosen is to require the output switch to be on for an
absolute minimum time per each oscillator cycle. This in
turn establishes a minimum load requirement to maintain
regulation. See Applications Information section for fur-
ther details.
Effects of Variable Enable Period
Enable Delay
It should now be clear that the flyback amplifier is enabled
only during a portion of the cycle time. This can vary from
thefixed“minimumenabletime”describedtoamaximum
of roughly the OFF switch time minus the enable delay
When the output switch shuts off, the flyback pulse
appears. However, it takes a finite time until the trans-
formerprimarysidevoltagewaveformapproximatelyrep-
sn14249 14249fs
9
LT1424-9
U
OPERATION
time. Certain parameters of flyback amp behavior will then
be directly affected by the variable enable period. These
include effective transconductance and VC node slew rate.
tracted from the RFB node. As output loading increases,
averageswitchcurrentincreasestomaintainroughoutput
voltage regulation. This causes an increase in ROCOMP
resistor current subtracted from the RFB node, through
which feedback loop action causes a corresponding
increase in target output voltage.
LOAD COMPENSATION THEORY
TheLT1424-9usestheflybackpulsetoobtaininformation
about the isolated output voltage. A potential error source
is caused by transformer secondary current flow through
the real life nonzero impedances of the output rectifier,
transformer secondary and output capacitor. This has
beenrepresentedpreviouslybytheexpression(ISEC)(ESR).
However,itisgenerallymoreusefultoconvertthisexpres-
sion to an effective output impedance. Because the sec-
ondarycurrentonlyflowsduringtheoffportionoftheduty
cycle, the effective output impedance equals the lumped
secondary impedance times the inverse of the OFF duty
cycle. That is,
Assuming a relatively fixed power supply efficiency, Eff
Power Out = (Eff)(Power In)
(VOUT)(IOUT) = (Eff)(VIN)(IIN)
Average primary side current may be expressed in terms
of output current as follows:
V
OUT
I =
I
OUT
IN
)
)
(V )(Eff)
IN
combining the efficiency and voltage terms in a single
variable,
1
I = K1(I ) where,
IN
OUT
R
R
= ESR
where,
OUT
)
)
DC OFF
V
OUT
K1 =
= Effective supply output impedance
ESR = Lumped secondary impedance
DC OFF = OFF duty cycle
)
)
OUT
(V )(Eff)
IN
Switch current is converted to voltage by a sense resistor
and amplified by the current sense amplifier with associ-
ated gain G. This voltage is then impressed across the
external ROCOMP resistor to form a current that is
subtracted from the RFB node. So the effective change in
VOUT target is:
Expressing this in terms of the ON duty cycle, remember-
ing DC OFF = 1 – DC,
1
R
= ESR
OUT
)
)
1 – DC
(R
)
)(G)
SENSE
R
∆V
= K1(∆I
)
R
FB
OUT
OUT
)
DC = ON duty cycle
OCOMP
In less critical applications, or if output load current
remains relatively constant, this output impedance error
may be judged acceptable and the external RFB resistor
value adjusted to compensate for nominal expected error.
In more demanding applications, output impedance error
may be minimized by the use of the load compensation
function.
Expressing the product of RSENSE and G as the data sheet
value of ∆VRCCOMP/∆ISW
,
∆V
R
FB
R
OCOMP
RCCOMP
R
= K1
and,
OUT
)
)
)
)
∆I
SW
Toimplementtheloadcompensationfunction,avoltageis
developed that is proportional to average output switch
current.Thisvoltageisthenimpressedacrosstheexternal
ROCOMP resistor and the resulting current is then sub-
R
∆V
FB
RCCOMP
R
= K1
where,
OCOMP
)
)
)
)
R
∆I
OUT
SW
K1 = Dimensionless variable related to VIN, VOUT and
efficiency as above
sn14249 14249fs
10
LT1424-9
U
OPERATION
∆V
∆I
∆V
R
FB
∆V
OUT
RCCOMP
RCCOMP
= K1
= Data sheet value for R
pin
CCOMP
)
)
)
R
)
)
)
∆I
∆I
OUT
SW
OCOMP
SW
action vs switch current
Nominal output impedance cancellation is obtained by
equating this expression with ROUT
RFB = External “feedback” resistor value
ROUT = Uncompensated output impedance
.
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APPLICATIONS INFORMATION
Internal Voltage Reference
The LT1424-X is an application-specific 8-pin part which
implements an isolated flyback switcher/controller. Three
on-chip thin-film resistors are used to “program” the part
for a specific application including mainly desired output
voltage,transformerturnsratioandsecondarycircuitESR
behavior. As of Initial Release, the LT1424-9 is available
which implements the “–9V PCMCIA II Isolated LAN
Supply” as described in the Typical Application section.
The internal bandgap voltage reference is, of course,
imperfect. Its error, both at 25°C and over temperature is
already included in the specifications for Reference
Voltage.
Schottky Diode Drop
The LT1424-9 senses the output voltage from the trans-
formerprimarysideduringtheflybackportionofthecycle.
This sensed voltage therefore includes the forward drop,
VF, of the rectifier (usually a Schottky diode). Lot-to-lot
andambienttemperaturevariationswillshowupasoutput
voltage shift/drift.
Potential users with a high volume requirement for other
applications are advised as follows: general experimenta-
tion/breadboarding may be done with the LT1425. This is
a general purpose 16-pin part whose functionality is
similar to the LT1424-X, with the exception that the three
application resistors are external user-supplied compo-
nents. Application information relating to the proper
selection of these resistor values is contained within the
LT1425 data sheet. Once technical feasibility is demon-
strated,thepotentialusermaydiscussthepossibilityofan
additional LT1424-X version with the factory.
Secondary Leakage Inductance
Leakage inductance on the transformer secondary
reduces the effective primary-to-secondary turns ratio
(NP/NS) from its ideal value. This increases the output
voltage target by a similar percentage and has been
nominally taken into account in the design of the
LT1424-9. To the extent that secondary leakage induc-
tance varies from part-to-part, the output voltage will be
affected.
OUTPUT VOLTAGE ERROR SOURCES
Conventional nonisolated switching power supply ICs
typically have only two substantial sources of output
voltage error— the internal or external resistor divider
network that connects to VOUT and the internal IC refer-
ence. The LT1424-9, which senses the output voltage in
both a dynamic and an isolated manner, exhibits addi-
tional potential error sources to contend with. Some of
these errors are proportional to output voltage, others are
fixedinanabsolutemillivoltsense.Hereisalistofpossible
error sources and their effective contribution:
Output Impedance Error
The LT1424-9 contains a load compensation function to
provide a nominal, first-order cancellation of the effects
of secondary circuit ESR. Unit-to-unit variation plus
some inherent nonlinearity in the cancellation results in
some residual VOUT variation with load.
sn14249 14249fs
11
LT1424-9
U
W U U
APPLICATIONS INFORMATION
MINIMUM LOAD CONSIDERATIONS
suggest operation down to 2mA to 3mA before significant
output voltage rise is observed. Nevertheless, this situa-
tion is addressed in the application by the use of a fixed
1.8k load resistor, which preloads the supply with a
nominal 5mA.
The LT1424-9 generally provides better low load perfor-
mance than previous generation switcher/controllers
utilizingindirectoutputvoltagesensingtechniques. Spe-
cifically, it contains circuitry to detect flyback pulse
“collapse,” thereby supporting operation well into dis-
continuous mode. In general, there are two possible
constraints to ultimate low load operation, minimum
switch ON time which sets a minimum level of delivered
power, and minimum flyback enable time, which deals
with the ability of the feedback system to derive valid
output voltage information from the flyback pulse. In the
application for which the LT1424-9 is designed, the
minimum flyback enable time is more restrictive.
MAXIMUM LOAD/SHORT-CIRCUIT CONSIDERATIONS
The LT1424-9 is a current mode controller. It uses the VC
node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
this peak current is reached. The internal clamp on the VC
node, nominally 1.9V, then acts as an output switch peak
current limit. This action becomes the switch current limit
specification. The maximum available output power is
then determined by the switch current limit, which is
somewhat duty cycle dependent due to internal slope
compensation action.
The LT1424-9 derives its output voltage information from
the flyback pulse. If the internal minimum enable time
pulse extends beyond the flyback pulse, loss of regulation
will occur. The onset of this condition can be determined
by setting the width of the flyback pulse equal to the sum
of the flyback enable delay, tED, plus the minimum enable
time, tEN. Minimum power delivered to the load is then:
Short-circuit conditions are handled by the same mecha-
nism. The output switch turns on, peak current is quickly
reached and the switch is turned off. Because the output
switchisonlyonforasmallfractionoftheavailableperiod,
internal power dissipation is controlled. (The LT1424-9
contains an internal overtemperature shutdown circuit,
that disables switch action, just in case.)
1
f
2
[V
• (t + t )]
EN ED
Min Power =
OUT
)
)
)
)
2 L
SEC
= (V )(I
)
OUT OUT
THERMAL CONSIDERATIONS
Which yields a minimum output constraint:
Care should be taken to ensure that the worst-case input
voltage and load current conditions do not cause exces-
sive die temperatures. The packages are rated at 110°C/W
for SO-8 and 130°C/W for N8.
f(V
L
)
1
OUT
SEC
2
I
=
(t + t ) , where
ED EN
OUT(MIN)
)
)
)
)
2
f = Switching frequency (nominally 285kHz)
Average supply current (including driver current) is:
L
V
= Transformer secondary side inductance
= Output voltage
SEC
I
35
OUT
SW
I = 7mA + DC
where,
IN
)
)
t
t
= Enable delay time
= Minimum enable time
ED
EN
I
= Switch current
SW
DC = On switch duty cycle
Switch power dissipation is given by:
PSW = (ISW)2(RSW)(DC)
In reality, the previously derived expression is a conserva-
tive one, as it assumes perfectly “square” waveforms,
which is not the case at light load. Furthermore, the
equation was set up to yield just theonset of control error.
In other words, while the equation suggests a minimum
load current of perhaps 7mA, laboratory observations
RSW = Output switch ON resistance
sn14249 14249fs
12
LT1424-9
U
W U U
APPLICATIONS INFORMATION
Total power dissipation of the die is the sum of supply
current times supply voltage plus switch power:
PCB LAYOUT CONSIDERATIONS
For maximum efficiency, switch rise and fall times are
made as short as practical. To prevent radiation and high
frequency resonance problems, proper layout of the com-
ponents connected to the IC is essential, especially the
power paths (primary and secondary). B field (magnetic)
radiationisminimizedbykeepingoutputdiode, switchpin
and output bypass capacitor leads as short as possible. E
field radiation is kept low by minimizing the length and
area of all traces connected to the switch pin. A ground
plane should always be used under the switcher circuitry
to prevent interplane coupling.
PD(TOTAL) = (IIN • VIN) + PSW
FREQUENCY COMPENSATION
Loop frequency compensation is performed by connect-
ing a capacitor from the output of the error amplifier (VC
pin) to ground. An additional series resistor, often
required in traditional current mode switcher controllers
is usually not required; and can even prove detrimental.
The phase margin improvement traditionally offered by
this extra resistor will usually be already accomplished by
the nonzero secondary circuit impedance, which adds a
“zero” to the loop response.
The high speed switching current paths are shown sche-
matically in Figure 1. Minimum lead length in these paths
are essential to ensure clean switching and minimal EMI.
The path containing the input capacitor, transformer pri-
mary, output switch, the path containing the transformer
secondary, output diode and output capacitor are the only
ones containing nanosecond rise and fall times. Keep
these paths as short as possible.
In further contrast to traditional current mode switchers,
VC pin ripple is generally not an issue with the LT1424-9.
The dynamic nature of the clamped feedback amplifier
forms an effective track/hold type response, whereby the
VC voltage changes during the flyback pulse, but is then
“held” during the subsequent “switch ON” portion of the
next cycle. This action naturally holds the VC voltage
stable during the current comparator sense action (cur-
rent mode switching).
V
OUT
•
HIGH
FREQUENCY
CIRCULATING
PATH
ISOLATED
LOAD
HIGH
FREQUENCY
CIRCULATING
PATH
V
IN
•
F
1424 F01
Figure 1
sn14249 14249fs
13
LT1424-9
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
8
7
6
5
4
0.255 ± 0.015*
(6.477 ± 0.381)
1
2
3
0.130 ± 0.005
0.300 – 0.325
0.045 – 0.065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
0.125
0.020
(0.508)
MIN
(3.175)
MIN
+0.035
0.325
–0.015
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
+0.889
8.255
(
)
N8 1197
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
sn14249 14249fs
14
LT1424-9
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
5
8
6
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.053 – 0.069
3
4
2
0.010 – 0.020
(0.254 – 0.508)
× 45°
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 0996
sn14249 14249fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LT1424-9
U
TYPICAL APPLICATION
–9V PCMCIA Type II Isolated LAN Supply
C6
220pF
ISOLATION
BARRIER
R2
75Ω
5V
MBRS130LT3
C1
10µF
25V
R1
75Ω
C2
10µF
25V
D1
OUT
0.1µF
1N5248
COM
1
C5
220pF
3
LT1424-9
C3
C4
10µF
25V
1.8k
2
1
3
4
8
7
6
5
10µF
T1
D2
MBR0540T4
V
R
CCOMP
C
25V
SHDN
SYNC
SGND
V
IN
2
4
100k
1000pF
–9V
200mA
V
47pF
SW
1424 TA01
1:1
C1, C2, C3, C4: MARCON THCS50E1E106Z CERAMIC
PGND
0.1µF
INPUT
COM
CAPACITOR, SIZE 1812. (847) 696-2000
T1: COILTRONICS CTX02-13483
Transformer T1
LPRI
RATIO
ISOLATION
(L × W × H)
IOUT
EFFICIENCY
COILTRONICS
CTX02-13483
27µH
1:1
500VAC
14 × 14 × 2.2mm
200mA
70%
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1105
Off-Line Switching Regulator
Isolated Digital Data Transceivers
5A/3A/1.25A Flyback Regulators
6A/3A Flyback Regulators
Built-In Isolated Regulation Without Optoisolator
Up to 200kbps Data Rate, UL Listed
Isolated Flyback Mode for Higher Currents
Uses Small Magnetics
LTC®1145/46
LT1170/71/72
LT1370/71
LT1372/77
LT1424-5
500kHz/1MHz Boost/Flyback Regulators
Isolated Flyback Switching Regulator
Isolated Flyback Switching Regulator
Uses Ultrasmall Magnetics
Same as LT1424-9 But with 5V Output
General Purpose with External Application Resistors
LT1425
sn14249 14249fs
LT/TP 0599 4K • PRINTED IN USA
Linear Technology Corporation
●
1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900
16
●
●
FAX: (408) 434-0507 TELEX: 499-3977 www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 1998
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