LT1468CS8-2#PBF [Linear]
LT1468-2 - 200MHz, 30V/µs 16-Bit Accurate AV ≥ 2 Op Amp; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C;
| 型号： | LT1468CS8-2#PBF |
| 厂家： | 
Linear |
| 描述： | LT1468-2 - 200MHz, 30V/µs 16-Bit Accurate AV ≥ 2 Op Amp; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C 放大器 光电二极管 |
| 文件： | 总14页 (文件大小：255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1468-2
200MHz, 30V/µs
16-Bit Accurate
A ≥ 2 Op Amp
V
FeaTures
DescripTion
TheLT®1468-2isaprecisionhighspeedoperationalampli-
fier with 16-bit accuracy, decompensated to be stable in a
gain of 2 or greater. The combination of precision and AC
performancemakestheLT1468-2theoptimumchoicefor
highaccuracyapplicationssuchasDACcurrent-to-voltage
conversion and ADC buffers. The initial accuracy and drift
characteristics of the input offset voltage and inverting
input bias current are tailored for inverting applications.
n
Stable in Gain A ≥ 2 (A = –1)
V
V
n
n
n
n
n
n
n
n
n
n
n
n
n
n
200MHz Gain Bandwidth Product
30V/μs Slew Rate
Settling Time: 800ns (10V Step, 150µV)
Specified at 5V and 15V Supplies
Low Distortion, –96.±dB for 100kHz, 105
Maximum Input Offset 5oltage: 7±µ5
P-P
Maximum Input Offset 5oltage Drift: 2µ5/°C
Maximum (–) Input Bias Current: 10nA
Minimum DC Gain: 10005/m5
The 200MHz gain bandwidth ensures high open-loop gain
at frequency for reducing distortion. In noninverting ap-
plications such as an ADC buffer, the low distortion and
DC accuracy allow full 16-bit AC and DC performance.
The high slew rate of the LT1468-2 improves large-signal
performance in applications such as active filters and
instrumentation amplifiers compared to other precision
op amps.
Minimum Output Swing into 2k: ±12.85
Input Noise 5oltage: ±n5/√Hz
Input Noise Current: 0.6pA/√Hz
Total Input Noise Optimized for 1k < R < 20k
S
Available in an 8-Lead Plastic SO Package
and 8-Lead DFN Package
The LT1468-2 is specified on power supply voltages of
±±5 and ±1±5 and from –40°C to 8±°C. For a unity-gain
stableopampwithsameDCperformance, seetheLT1468
data sheet.
applicaTions
n
16-Bit DAC Current-to-5oltage Converter
n
Precision Instrumentation
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
n
ADC Buffer
Low Distortion Active Filters
High Accuracy Data Acquisition Systems
Technology Corporation. All other trademarks are the property of their respective owners.
n
n
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Photodiode Amplifiers
Typical applicaTion
16-Bit DAC I-to-V Converter
Large Signal Transient, AV = –1
V
A
= 1ꢀV
S
V
F
F
10V
= –1
20pF
R
= R = 2k
G
C
= 22pF
16
6k
DAC
–
INPUTS
2k
2V/DIV
0V
V
LT1468-2
OUT
LTC®1597
+
50pF
OPTIONAL NOISE FILTER
OFFSET: V + I (6kΩ) < 1LSB
OS
B
SETTLING TIME TO 150µV = 1.6µs
SETTLING LIMITED BY 6k AND 20pF TO COMPENSATE DAC OUTPUT CAPACITANCE
200ns/DIV
14682 TA01
14682 TA02
14682fb
1
LT1468-2
(Note 1)
absoluTe MaxiMuM raTings
+
–
Total Supply 5oltage (5 to 5 ).................................365
Maximum Input Current (Note 2)...........................10mA
Output Short-Circuit Duration (Note 3) ............ Indefinite
Operating Temperature Range ................. –40°C to 8±°C
Specified Temperature Range (Note 4) .... –40°C to 8±°C
Junction Temperature ........................................... 1±0°C
Storage Temperature Range................... –6±°C to 1±0°C
Lead Temperature (Soldering, 10 sec)
for S8 Only........................................................ 300°C
pin conFiguraTion
TOP VIEW
TOP VIEW
NULL
–IN
1
2
3
4
8
7
6
5
DNC*
NULL
–IN
1
2
3
4
8
7
6
5
DNC*
–
+
–
+
+
+
V
V
+IN
V
+IN
OUT
OUT
–
–
V
NULL
V
NULL
S8 PACKAGE
DD PACKAGE
8-LEAD PLASTIC SO
8-LEAD (3mm × 3mm) PLASTIC DFN
*DO NOT CONNECT
T
JMAX
= 1±0°C, θ = 43°C/W
JA
EXPOSED PAD IS INTERNALLY CONNECTED TO 5
T
= 1±0°C, θ = 190°C/W
JA
–
JMAX
orDer inForMaTion
LEAD FREE FINISH
LT1468CS8-2#PBF
LT1468IS8-2#PBF
LT1468ACDD-2#PBF
LT1468AIDD-2#PBF
LT1468CDD-2#PBF
LT1468IDD-2#PBF
TAPE AND REEL
PART MARKING* PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
LT1468CS8-2#TRPBF
LT1468IS8-2#TRPBF
LT1468ACDD-2#TRPBF
LT1468AIDD-2#TRPBF
LT1468CDD-2#TRPBF
LT1468IDD-2#TRPBF
14682
14682
LDSY
LDSY
LDSY
LDSY
8-Lead Plastic Small Outline
8-Lead Plastic Small Outline
0°C to 70°C
–40°C to 8±°C
0°C to 70°C
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
–40°C to 8±°C
0°C to 70°C
–40°C to 8±°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating
elecTrical characTerisTics
temperature range, otherwise specifications are at TA = 25°C. VCM = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
V
MIN
TYP
MAX
UNITS
SUPPLY
5
OS
Input Offset 5oltage
S8 Package
±1±5
±±5
30
±0
7±
17±
µ5
µ5
LT1468A, DD Package
LT1468, DD Package
±1±5
±±5
30
±0
7±
µ5
µ5
17±
±1±5
±±5
100
1±0
200
300
µ5
µ5
I
Input Offset Current
±±5 to ±1±5
13
±0
nA
OS
14682fb
2
LT1468-2
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCM = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
V
MIN
TYP
3
MAX
±10
±40
UNITS
nA
SUPPLY
–
I
B
I
B
Inverting Input Bias Current
Noninverting Input Bias Current
Input Noise 5oltage
Input Noise 5oltage
Input Noise 5oltage
Input Resistance
±±5 to ±1±5
±±5 to ±1±5
±±5 to ±1±5
±±5 to ±1±5
±±5 to ±1±5
+
–10
0.3
±
nA
0.1Hz to 10Hz
f = 10kHz
µ5
P-P
e
n
n5/√Hz
pA/√Hz
i
f = 10kHz
0.6
n
R
5
= ±12.±5
±1±5
±1±5
100
±0
240
1±0
MΩ
kΩ
IN
CM
Differential
C
IN
Input Capacitance
±1±5
4
pF
Input 5oltage Range +
±1±5
±±5
12.±
2.±
13.±
3.±
5
5
Input 5oltage Range –
±1±5
±±5
–14.3
–4.3
–12.±
–2.±
5
5
CMRR
PSRR
Common Mode Rejection Ratio
5
5
= ±12.±5
= ±2.±5
±1±5
±±5
96
96
110
112
dB
dB
CM
CM
Power Supply Rejection Ratio
Large-Signal 5oltage Gain
5 = ±4.±5 to ±1±5
S
100
112
dB
A
5OL
5
OUT
5
OUT
5
OUT
5
OUT
= ±12.±5, R = 10k
±1±5
±1±5
±±5
1000
±00
1000
±00
9000
±000
6000
3000
5/m5
5/m5
5/m5
5/m5
L
L
= ±12.±5, R = 2k
= ±2.±5, R = 10k
L
L
= ±2.±5, R = 2k
±±5
5
OUT
Output Swing
R = 10k
±1±5
±1±5
±±5
±±5
±13.0
±12.8
±3.0
±13.6
±13.±
±3.6
5
5
5
5
L
R = 2k
L
R = 10k
L
R = 2k
±2.8
±3.±
L
I
I
Output Current
5
5
= ±12.±5
= ±2.±5
±1±5
±±5
±1±
±1±
±22
±22
mA
mA
OUT
OUT
OUT
Short-Circuit Current
Slew Rate
5
OUT
= 05, 5 = ±0.25
±1±5
±2±
±40
mA
SC
IN
SR
R = 2k (Note ±)
±1±5
±±5
20
1±
30
22
5/µs
5/µs
L
Full-Power Bandwidth
Gain Bandwidth
Settling Time
105 Peak, (Note 6)
35 Peak, (Note 6)
±1±5
±±5
47±
kHz
kHz
1160
GBW
f = 100kHz, R = 2k
±1±5
±±5
140
130
200
190
MHz
MHz
L
t
s
105 Step, 0.01%, A = –1
±1±5
±1±5
±±5
6±0
800
±±0
ns
ns
ns
5
5
105 Step, 1±0µ5, A = –1
±5 Step, 0.01%, A = –1
5
R
Output Resistance
Supply Current
A = –1, f = 100kHz
5
±1±5
0.02
Ω
O
I
±1±5
±±5
3.9
3.6
±.2
±.0
mA
mA
S
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
0°C ≤ TA ≤ 70°C, VCM = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
V
MIN
TYP
MAX
UNITS
SUPPLY
5
OS
Input Offset 5oltage
S8 Package
±1±5
±±5
●
●
1±0
2±0
µ5
µ5
LT1468A, DD Package
LT1468, DD Package
±1±5
±±5
●
●
1±0
2±0
µ5
µ5
±1±5
±±5
●
●
300
400
µ5
µ5
14682fb
3
LT1468-2
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. 0°C ≤ TA ≤ 70°C, VCM = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
V
MIN
TYP
MAX
2.0
UNITS
µ5/°C
nA
SUPPLY
Input 5 Drift
(Note 7)
●
●
0.7
±±5 to ±1±5
±±5 to ±1±5
±±5 to ±1±5
±±5 to ±1±5
±±5 to ±1±5
±±5 to ±1±5
OS
I
Input Offset Current
6±
OS
Input Offset Current Drift
Inverting Input Bias Current
Negative Input Current Drift
Noninverting Input Bias Current
Common Mode Rejection Ratio
60
40
pA/°C
nA
–
I
●
●
±1±
±±0
B
pA/°C
nA
+
I
B
CMRR
5
CM
5
CM
= ±12.±5
= ±2.±5
±1±5
±±5
●
●
94
94
dB
dB
PSRR
Power Supply Rejection Ratio
Large-Signal 5oltage Gain
5 = ±4.±5 to ±1±5
●
98
dB
S
A
5
5
OUT
5
OUT
5
OUT
5
OUT
= ±12.±5, R = 10k
±1±5
±1±5
±±5
●
●
●
●
±00
2±0
±00
2±0
5/m5
5/m5
5/m5
5/m5
5OL
OUT
L
= ±12.±5, R = 2k
L
= ±2.±5, R = 10k
L
= ±2.±5, R = 2k
±±5
L
Output Swing
Output Current
R = 10k
±1±5
±1±5
±±5
●
●
●
●
±12.9
±12.7
±2.9
5
5
5
5
L
R = 2k
L
R = 10k
L
R = 2k
±±5
±2.7
L
I
I
5
OUT
5
OUT
= ±12.±5
= ±2.±5
±1±5
±±5
●
●
±12.±
±12.±
mA
mA
OUT
SC
Short-Circuit Current
Slew Rate
5
OUT
= 05, 5 = ±0.25
±1±5
●
±17
mA
IN
SR
R = 2k (Note ±)
L
±1±5
±±5
●
●
18
13
5/µs
5/µs
GBW
Gain Bandwidth
Supply Current
f = 100kHz, R = 2k
±1±5
±±5
●
●
130
120
200
190
MHz
MHz
L
I
±1±5
±±5
●
●
6.±
6.3
mA
mA
S
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
–40°C ≤ TA ≤ 85°C, VCM = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
V
MIN
TYP
MAX
UNITS
SUPPLY
5
Input Offset 5oltage
S8 Package
±1±5
±±5
●
●
230
330
µ5
µ5
OS
LT1468A, DD Package
LT1468, DD Package
(Note 7)
±1±5
±±5
●
●
230
330
µ5
µ5
±1±5
±±5
●
●
400
±00
µ5
µ5
Input 5 Drift
●
●
0.7
120
80
2.±
80
µ5/°C
nA
±±5 to ±1±5
±±5 to ±1±5
±±5 to ±1±5
±±5 to ±1±5
±±5 to ±1±5
±±5 to ±1±5
OS
I
I
Input Offset Current
OS
Input Offset Current Drift
Inverting Input Bias Current
Negative Input Current Drift
Noninverting Input Bias Current
Common Mode Rejection Ratio
pA/°C
nA
–
●
●
±30
±60
B
pA/°C
nA
+
I
B
CMRR
5
CM
5
CM
= ±12.±5
= ±2.±5
±1±5
±±5
●
●
92
92
dB
dB
PSRR
Power Supply Rejection Ratio
5 = ±4.±5 to ±1±5
S
●
96
dB
14682fb
4
LT1468-2
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. –40°C ≤ TA ≤ 85°C, VCM = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
V
MIN
TYP
MAX
UNITS
SUPPLY
A
Large-Signal 5oltage Gain
5
5
5
5
= ±125, R = 10k
±1±5
±1±5
±±5
●
●
●
●
300
1±0
300
1±0
5/m5
5/m5
5/m5
5/m5
5OL
OUT
OUT
OUT
OUT
L
= ±105, R = 2k
L
= ±2.±5, R = 10k
L
= ±2.±5, R = 2k
±±5
L
5
Output Swing
Output Current
R = 10k
±1±5
±1±5
±±5
●
●
●
●
±12.8
±12.6
±2.8
5
5
5
5
OUT
L
R = 2k
L
R = 10k
L
R = 2k
±±5
±2.6
L
I
I
5
5
= ±12.±5
= ±2.±5
±1±5
±±5
●
●
±7
±7
mA
mA
OUT
SC
OUT
OUT
Short-Circuit Current
Slew Rate
5
= 05, 5 = ±0.25
±1±5
●
±12
mA
OUT
IN
SR
R = 2k (Note ±)
L
±1±5
±±5
●
●
1±
11
5/µs
5/µs
GBW
Gain Bandwidth
Supply Current
f = 100kHz, R = 2k
±1±5
±±5
●
●
110
100
200
190
MHz
MHz
L
I
±1±5
±±5
●
●
7.0
6.8
mA
mA
S
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: The LT1468C-2 is guaranteed to meet specified performance from
0°C to 70°C and is designed, characterized and expected to meet these
extended temperature limits, but is not tested at –40°C and at 8±°C. The
LT1468I-2 is guaranteed to meet the extended temperature limits.
Note 2: The inputs are protected by back-to-back diodes and two 100Ω
series resistors. If the differential input voltage exceeds 0.75, the input
current should be limited to 10mA. Input voltages outside the supplies will
be clamped by ESD protection devices and input currents should also be
limited to 10mA.
Note 5: Slew rate is measured between ±85 on the output with ±125 input
for ±1±5 supplies and ±25 on the output with ±35 input for ±±5 supplies.
Note 6: Full power bandwidth is calculated from the slew rate
measurement: FPBW = SR/2π5
P
Note 7: This parameter is not 100% tested.
Note 3: A heat sink may be required to keep the junction temperature
below absolute maximum when the output is shorted indefinitely.
Typical perForMance characTerisTics
Supply Current vs Supply Voltage
and Temperature
Input Common Mode Range
vs Supply Voltage
Input Bias Current
vs Input Common Mode Voltage
+
7
6
80
60
V
T
= 25°C
OS
A
V
T
=
15V
S
A
–0.5
–1.0
–1.5
–2.0
ΔV < 100µV
= 25°C
40
125°C
5
4
20
–
I
B
0
+
25°C
I
B
2.0
1.5
1.0
0.5
–20
–40
–60
–80
3
2
1
–55°C
–
V
0
5
10
15
20
0
3
9
12
15
18
–10
–5
5
6
–15
10
15
0
SUPPLY VOLTAGE ( Vꢀ
SUPPLY VOLTAGE ( Vꢀ
INPUT COMMON MODE VOLTAGE (V)
14682 G01
14682 G02
14682 G03
14682fb
5
LT1468-2
Typical perForMance characTerisTics
Input Bias Current
vs Temperature
Input Noise Spectral Density
0.1Hz to 10Hz Voltage Noise
1000
100
10
1
30
20
V
S
= 1ꢀV
V
=
15V
V
= 15V
S
A
S
T
= 25°C
A
= 101
= 100k FOR i
V
R
S
n
i
10
n
–
+
I
I
B
0
–10
–20
–30
–40
e
n
10
1
0.1
B
0.01
1
10
100
1k
10k
100k
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
TIME (1s/DIV)
FREQUENCY (Hz)
14682 G06
14682 G05
14682 G04
Open-Loop Gain
vs Resistive Load
Open-Loop Gain
vs Temperature
Warm-Up Drift vs Time
160
150
5
0
140
135
130
125
120
115
110
R
L
= 2k
T
= 25°C
A
V
S
= 15V
V
=
=
15V
5V
S
S0-8 5V
–5
V
S
=
5V
140
130
120
110
100
–10
–15
–20
–25
–30
–35
–40
V
S
S0-8 15V
90
50
100 125
–50 –25
0
25
75
10
100
1k
10k
0
20
40
60
80 100 120 140
LOAD RESISTANCE (Ω)
TEMPERATURE (°C)
TIME AFTER POWER UP (s)
14682 G09
14682 G08
14682 G07
Output Voltage Swing
vs Supply Voltage
Output Voltage Swing
vs Load Current
Output Short-Circuit Current
vs Temperature
+
+
V –0.5
–1.0
60
55
50
45
40
35
30
25
20
15
10
V
R
L
= 2k
V
S
= 15V
V
V
=
IN
15V
0ꢀ2V
85°C
S
25°C
–1
–2
–3
–4
4
=
R
L
= 10k
–40°C
–1.5
SOURCE
–2.0
SINK
–2.5
2.5
2.0
1.5
40°C
85°C
3
2
R
L
= 2k
25°C
1
R
L
= 10k
1.0
–
T
= 25°C
A
–
V
V
0.5
–20
0
10 15
–50
0
25
50
75 100 125
–15 –10 –5
5
20
–25
0
5
10
15
20
SUPPLY VOLTAGE ( Vꢀ
OUTPUT CURRENT (mA)
TEMPERATURE (°C)
14682 G11
14682 G12
14682 G10
14682fb
6
LT1468-2
Typical perForMance characTerisTics
Open-Loop Gain and Phase
vs Frequency
Gain vs Frequency, A = –1
Output Impedance vs Frequency
V
70
60
50
40
30
20
10
0
100
80
100
10
6
5
T
= 25°C
= –1
G
V
T
=
15V
A
V
F
F
S
A
C
= 100pF
A
L
= 25°C
R = R = 2k
4
PHASE
C = 6.8pF
60
C
= 47pF
= 22pF
L
3
R
= 500Ω
L
A
V
= 100
40
2
C
L
1
GAIN
1
A = 10
V
20
0
0.1
0
NO C
–1
–2
–3
–4
–5
L
T
= 25°C
= –1
G
A
V
= –1
1M
A
V
F
F
–20
–40
–60
A
0.01
0.001
R = R = 5.1k
C = 5pF
R
= 2k
L
–10
10k
100k
1M
10M
100M
100k
1M
10M
100M
10k
100k
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
14682 G14
14682 G13
14682 G15
Undistorted Output Swing
vs Frequency, V = 15V
Undistorted Output Swing
vs Frequency, V = 5V
Settling Time vs Output Step
S
S
30
25
20
15
10
5
10
9
8
7
6
5
4
3
2
1
0
10
8
V
=
15V
S
A
F
150µV
T
= 25°C
R = R = 2.5k
G
6
A
= –1
V
R
= 5k
L
0.01%
C = 8pF
4
F
V
0.1%
A
= –1
2
A
= –1
V
0
–2
–4
–6
–8
–10
0.1%
V
=
15V
V
=
5V
S
A
L
S
A
L
T
= 25°C
= 2k
T
= 25°C
= 2k
R
R
150µV
0.01%
THD<1%
THD<1%
0
1
10
100
1000
1
10
100
1000 2000
0
100 200 300 400 500 600 700 800 9001000
FREQUENCY (kHz)
FREQUENCY (kHz)
SETTLING TIME (ns)
14682 G16
14682 G17
14682 G18
Settling Time vs Output Step
Small-Signal Transient, A = –1
Large-Signal Transient, A = –1
V
V
10
8
V
=
15V
V
A
=
1ꢀV
S
S
V
F
10V
= –1
R = R = 2k
= 22pF
0.01%
G
6
C
2V/DIV
L
4
2
20mV/DIV
0
V
=
15V
S
A
–2
–4
–6
–8
–10
0V
T
= 25°C
R = R = 1k
F
G
0.01%
R
= 5k INTO DIODES
L
C = 22pF
F
A
= 2
50ns/DIV
200ns/DIV
V
14682 G20
14682 G21
R
= 511Ω/30pF
L
0
100 200 300 400 500 600 700 800 9001000
SETTLING TIME (ns)
14682 G19
14682fb
7
LT1468-2
applicaTions inForMaTion
TheLT1468-2maybeinserteddirectlyintomanyoperational
amplifier applications improving both DC and AC perfor-
mance, provided that the nulling circuitry is removed. The
suggested nulling circuit for the LT1468-2 is shown below.
and minimize leakage (i.e., 1.±GΩ of leakage between an
input and a 1±5 supply will generate 10nA—equal to the
–
maximum I specification.)
B
Board leakage can be minimized by encircling the input
circuitry with a guard ring operated at a potential close
to that of the inputs. For inverting configurations tie the
ring to ground, in noninverting connections tie the ring
to the inverting input (note the input capacitance will
increase which may require a compensating capacitor as
discussed below.)
Offset Nulling
+
V
3
0.1µF
0.1µF
2.2µF
2.2µF
+
7
4
6
LT1468-2
2
–
5
1
100k
Microvolt level error voltages can also be generated in
the external circuitry. Thermocouple effects caused by
temperature gradients across dissimilar metals at the
contacts to the inputs can exceed the inherent drift of
the amplifier. Air currents over device leads should be
minimized, package leads should be short, and the two
input leads should be as close together as possible and
maintained at the same temperature.
–
14682 AI01
V
Gain of 2 Stable
The LT1468-2 is a decompensated version of the LT1468.
The precision DC performance is identical, but the internal
compensation capacitors have been reduced to a point
where the op amp needs a gain of 2 or greater in order
to be stable.
Make no connection to Pin 8. This pin is used for factory
trim of the inverting input current.
In general, for applications where the gain around the op
amp is ≥ 2, the decompensated version should be used,
because it will give the best AC performance. In applica-
tions where the gain is < 2, the unity-gain stable version
should be used.
The parallel combination of the feedback resistor and gain
settingresistorontheinvertinginputcancombinewiththe
input capacitance to form a pole that can cause peaking
or even oscillations. A feedback capacitor of the value:
The appropriate way to define the ‘gain’ is as the inverse
of the feedback ratio from output to differential input,
including all relevant parasitics. Moreover, as with all
feedback loops, the stability of the loop depends on the
value of that feedback ratio at frequencies where the total
loop-gain would cross unity. Therefore, it is possible to
have circuits in which the gain at DC is lower than the gain
at high frequency, and these circuits can be stable even
with a non unity-gain stable op amp. An example is many
current-output DAC buffer applications.
C = (R )(C /R )
F
G
IN
F
maybeusedtocanceltheinputpoleandoptimizedynamic
performance. For applications where the DC noise gain is
one, and a large feedback resistor is used, C should be
less than or equal to one half of C . An example would
be a DAC I-to-5 converter as shown on the front page of
this data sheet where the DAC can have many tens of pF
of output capacitance.
F
IN
Nulling Input Capacitance
Layout and Passive Components
R
F
C
The LT1468 requires attention to detail in board layout
in order to maximize DC and AC performance. For best
AC results (for example fast settling time) use a ground
plane,shortleadlengths,andRF-qualitybypasscapacitors
(0.01µF to 0.1µF) in parallel with low ESR bypass capaci-
tors(1µFto10µFtantalum). ForbestDCperformance, use
“star” grounding techniques, equalize input trace lengths
F
R
G
–
C
LT1468-2
V
OUT
IN
+
V
IN
14682 AI02
14682fb
8
LT1468-2
applicaTions inForMaTion
Input Considerations
The input bias currents vary with common mode voltage
as shown in the Typical Performance Characteristics. The
cancellation circuitry was not designed to track this com-
mon mode voltage because the settling time would have
been adversely affected.
Each input of the LT1468-2 is protected with a 100Ω
series resistor and back-to-back diodes across the bases
of the input devices. If the inputs can be pulled apart, the
input current should be limited to less than 10mA with
an external series resistor. Each input also has two ESD
clamp diodes—one to each supply. If an input is driven
abovethesupply,limitthecurrentwithanexternalresistor
to less than 10mA.
The LT1468 inputs can be driven to the negative supply
and to within 0.±5 of the positive supply without phase
reversal. As the input moves closer than 0.±5 to the posi-
tive supply, the output reverses phase.
The LT1468-2 employs bias current cancellation at the
inputs. The inverting input current is trimmed at zero
common mode voltage to minimize errors in inverting
applications such as I-to-5 converters. The noninverting
input current is not trimmed and has a wider variation
and therefore a larger maximum value. As the input offset
current can be greater than either input current, the use
of balanced source resistance is NOT recommended as it
actually degrades DC accuracy and also increases noise.
Total Input Noise
ThecurveofTotalNoisevsUnmatchedSourceResistance
in the Typical Performance Characteristics shows that
with source resistance below 1k, the voltage noise of the
amplifierdominates. Inthe1kto20kregiontheincreasein
noise is due to the source resistance. Above 20k the input
current noise component is larger than the resistor noise.
Input Stage Protection
R1
100Ω
R2
100Ω
Q1
Q2
+IN
–IN
14682 AI03
14682fb
9
LT1468-2
siMpliFieD scheMaTic
+
V
I1
I2
I5
Q10
Q11
Q8
Q9
OUT
+IN
Q1
Q2
–IN Q5
Q3
Q6
Q7
Q4
C
BIAS
I3
I4
I6
–
V
14682 SS
14682fb
10
LT1468-2
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 0±-08-1610 Rev G)
.189 – .197
(4.801 – 5.004)
.045 ±.005
NOTE 3
.050 BSC
7
5
8
6
.245
MIN
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
1
3
4
2
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
(0.254 – 0.508)
× 45°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
NOTE:
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
SO8 REV G 0212
14682fb
11
LT1468-2
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 0±-08-1698 Rev C)
0.70 ±0.05
3.5 ±0.05
2.10 ±0.05 (2 SIDES)
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50
BSC
2.38 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.125
0.40 ±0.10
TYP
5
8
3.00 ±0.10
(4 SIDES)
1.65 ±0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD8) DFN 0509 REV C
4
1
0.25 ±0.05
0.75 ±0.05
0.200 REF
0.50 BSC
2.38 ±0.10
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
14682fb
12
LT1468-2
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
10/09 Change to Both Packages in Pin Configuration.
2
B
11/12 Updated S8 and DD packages in the Package Description section.
11-12
14682fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
13
LT1468-2
Typical applicaTion
16-Bit ADC Buffer
22pF
1k
1k
–
16 BITS
200Ω
LT1468-2
LTC1605
CAP
1000pF
+
V
IN
14682 TA04
33.2k
2.2µF
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
LT1167
Precision Instrumentation Amplifier
Single Resistor Gain Set, 0.04% Max Gain Error, 10ppm Max Gain
Nonlinearity
LT1468
Single 200MHz, 305/µs, 16-Bit Accurate A ≥ 2 Op Amp
7±µ5 5
7±µ5 5
7±µ5 5
7±µ5 5
5
OS(MAX)
OS(MAX)
OS(MAX)
OS(MAX)
LT1468-2
LT1469
Single 90MHz, 225/µs, 16-Bit Accurate Op Amp
Dual 200MHz, 305/µs, 16-Bit Accurate A ≥ 2 Op Amp
5
LT1469-2
Dual 90MHz, 225/µs, 16-Bit Accurate Op Amp
LTC1±9±/
LTC1±96
16-Bit Serial Multiplying I
DACs
±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade
OUT
LTC1±97
LTC1604
LTC160±
16-Bit Parallel Multiplying I
DAC
±1LSB Max INL/DNL, Low Glitch, On-Chip Bipolar Resistors
±2.±5 Input, SINAD = 90dB, THD = –100dB
OUT
16-Bit, 333ksps Sampling ADC
Single ±5, 16-Bit, 100ksps Sampling ADC
Low Power, ±105 Inputs, Parallel/Byte Interface
14682fb
LT 1112 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 9±03±-7417
14
●
●
LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0±07 www.linear.com
相关型号：
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LT1468 - 90MHz, 22V/us 16-Bit Accurate Operational Amplifier; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
Linear
LT1468IDD-2#PBF
LT1468-2 - 200MHz, 30V/µs 16-Bit Accurate AV ≥ 2 Op Amp; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
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