LT1469CS8 [Linear]
Dual 90MHz, 22V/us 16-Bit Accurate Operational Amplifier; 双90MHz的， 22V / us的16位的高精度运算放大器
| 型号： | LT1469CS8 |
| 厂家： | 
Linear |
| 描述： | Dual 90MHz, 22V/us 16-Bit Accurate Operational Amplifier |
| 文件： | 总12页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Final Electrical Specifications
LT1469
Dual 90MHz, 22V/µs
16-Bit Accurate Operational Amplifier
February 2000
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DESCRIPTIO
FEATURES
The LT®1469 is a dual, precision high speed operational
amplifierwith16-bitaccuracyand900nssettlingto150µV
for 10V signals. This unique blend of precision and AC
performance makes the LT1469 the optimum choice for
high accuracy applications such as DAC current-to-volt-
age conversion and ADC buffers. The initial accuracy and
drift characteristics of the input offset voltage and invert-
ing input bias current are tailored for inverting applica-
tions.
■
90MHz Gain Bandwidth, f = 100kHz
Maximum Input Offset Voltage: 125µV
Settling Time: 900ns (AV = –1, 150µV, 10V Step)
22V/µs Slew Rate
Low Distortion: –96.5dB for 100kHz, 10VP-P
Maximum Input Offset Voltage Drift: 3µV/°C
Maximum Inverting Input Bias Current: 10nA
Minimum DC Gain: 300V/mV
Minimum Output Swing into 2k: ±12.8V
Unity-Gain Stable
Input Noise Voltage: 5nV/√Hz
Input Noise Current: 0.6pA/√Hz
■
■
■
■
■
■
■
■
■
■
■
■
■
The 90MHz gain bandwidth ensures high open-loop gain
atfrequencyforreducingdistortion. Innoninvertingappli-
cations such as an ADC buffer, the low distortion and DC
accuracy allow full 16-bit AC and DC performance.
Total Input Noise Optimized for 1kΩ < RS < 20kΩ
Specified at ±5V and ±15V Supplies
The 22V/µs slew rate of the LT1469 improves large signal
performance compared to other precision op amps in
applications such as active filters and instrumentation
amplifiers.
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APPLICATIO S
■
Precision Instrumentation
■
The LT1469 is manufactured on Linear Technology’s
complementary bipolar process and is available in 8-pin
PDIP and SO packages. A single version,the LT1468, is
also available.
High Accuracy Data Acquisition Systems
■
16-Bit DAC Current-to-Voltage Converter
■
ADC Buffer
■
Low Distortion Active Filters
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
Photodiode Amplifiers
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TYPICAL APPLICATIO
16-Bit Accurate Single Ended to Differential ADC Buffer
+
200Ω
1/2 LT1469
–
300pF
V
IN
+IN
10pF
2k
16 BITS
2k
LTC1604
333ksps
–IN
300pF
200Ω
1469 TA01
–
1/2 LT1469
+
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
1
LT1469
W W
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W
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ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
ORDER PART
Total Supply Voltage (V+ to V–) .............................. 36V
Input Current (Note 2) ........................................ ±10mA
Output Short-Circuit Duration (Note 3)............ Indefinite
Operating Temperature Range (Note 4) .. –40°C to 85°C
Specified Temperature Range (Note 5)... –40°C to 85°C
Maximum Junction Temperature .......................... 150°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
+
NUMBER
OUT A
–IN A
+IN A
1
2
3
4
8
7
6
5
V
OUT B
–IN B
+IN B
A
LT1469CS8
LT1469IS8
LT1469CN8
LT1469IN8
B
–
V
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 130°C/W (N8)
JMAX = 150°C, θJA = 190°C/W (S8)
S8 PART MARKING
T
1469
1469I
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
TA = 25°C, VCM = 0V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
V
MIN
TYP
MAX
UNITS
SUPPLY
V
Input Offset Voltage
±15V
±5V
30
50
125
200
µV
µV
OS
I
Input Offset Current
±5V to ±15V
±5V to ±15V
±5V to ±15V
±5V to ±15V
±5V to ±15V
13
3
±50
±10
±40
nA
nA
OS
I –
Inverting Input Bias Current
Noninverting Input Bias Current
Input Noise Voltage Density
Input Noise Current Density
Input Resistance
B
I +
–10
5
nA
B
e
f = 10kHz
f = 10kHz
nV/√Hz
pA/√Hz
n
i
0.6
n
R
V
= ±12.5V
CM
±15V
±15V
100
50
240
150
MΩ
kΩ
IN
Differential
C
V
Input Capacitance
±15V
4
pF
IN
Input Voltage Range (Positive)
±15V
±5V
12.5
2.5
13.5
3.5
V
V
CM
Input Voltage Range (Negative)
Common Mode Rejection Ratio
±15V
±5V
–14.3
–4.3
–12.5
–2.5
V
V
CMRR
PSRR
V
V
= ±12.5V
= ±2.5V
±15V
±5V
96
96
110
112
dB
dB
CM
CM
Minimum Supply Voltage
Power Supply Rejection Ratio
Large-Signal Voltage Gain
Guaranteed by PSRR
V = ±4.5V to ±15V
±2.5
±4.5
V
100
112
dB
S
A
V
V
V
V
= ±12.5V, R = 10k
±15V
±15V
±5V
300
300
200
200
9000
5000
6000
3000
V/mV
V/mV
V/mV
V/mV
VOL
OUT
OUT
OUT
OUT
L
= ±12.5V, R = 2k
L
= ±2.5V, R = 10k
L
= ±2.5V, R = 2k
±5V
L
V
Maximum Output Swing
R = 10k, 1mV Overdrive
±15V
±15V
±5V
±13
±12.8
±3
±13.6
±13.5
±3.6
V
V
V
V
OUT
L
R = 2k, 1mV Overdrive
L
R = 10k, 1mV Overdrive
L
R = 2k, 1mV Overdrive
L
±5V
±2.8
±3.5
I
I
Maximum Output Current
V
V
= ±12.5V, 1mV Overdrive
= ±2.5V, 1mV Overdrive
±15V
±5V
±15
±15
±22
±22
mA
mA
OUT
SC
OUT
OUT
Output Short-Circuit Current
V
= 0V, 0.2V Overdrive (Note 3)
±15V
±25
±40
mA
OUT
2
LT1469
ELECTRICAL CHARACTERISTICS
TA = 25°C, VCM = 0V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
V
MIN
TYP
MAX
UNITS
SUPPLY
±15V
±5V
SR
Slew Rate
A = –10, R = 2k (Note 6)
15
11
22
17
V/µs
V/µs
V
L
FPBW
GBW
Full-Power Bandwidth
Gain Bandwidth Product
Rise Time, Fall Time
Overshoot
10V Peak, (Note 7)
3V Peak, (Note 7)
±15V
±5V
350
900
kHz
kHz
f = 100kHz, R = 2k
±15V
±5V
60
55
90
88
MHz
MHz
L
t , t
r
A = 1, 10% to 90%, 0.1V
V
±15V
±5V
11
12
ns
ns
f
OS
A = 1, 0.1V
V
±15V
±5V
30
35
%
%
t
t
Propagation Delay
Settling Time
A = 1, 50% V to 50% V , 0.1V
±15V
±5V
9
10
ns
ns
PD
S
V
IN
OUT
10V Step, 0.01%, A = –1
±15V
±15V
±5V
760
900
770
ns
ns
ns
V
10V Step, 150µV, A = –1
V
5V Step, 0.01%, A = –1
V
THD
Total Harmonic Distortion
Output Resistance
A = 1, 10V , 100kHz
±15V
±15V
–96.5
0.02
dB
V
P-P
R
OUT
A = 1, f = 100kHz
V
Ω
Channel Separation
V
V
= ±12.5V, R = 2k
±15V
±5V
100
100
120
120
dB
dB
OUT
OUT
L
= ±2.5V, R = 2k
L
I
Supply Current
Per Amplifier
±15V
±5V
4.1
3.8
5.2
5
mA
mA
S
∆V
OS
Input Offset Voltage Match
±15V
±5V
225
350
µV
µV
∆I –
Inverting Input Bias Current Match
±5V to ±15V
±5V to ±15V
±18
±78
nA
nA
B
∆I +
B
Noninverting Input Bias Current Match
∆CMRR Common Mode Rejection Match
V
V
= ±12.5V (Note 9)
= ±2.5V (Note 9)
±15V
±5V
93
93
dB
dB
CM
CM
∆PSRR Power Supply Rejection Match
V = ±4.5V to ±15V (Note 9)
S
97
dB
The ● denotes the specifications which apply over the temperature range 0°C ≤ TA ≤ 70°C, VCM = 0V unless otherwise noted.
SYMBOL PARAMETER
Input Offset Voltage
CONDITIONS
V
MIN
TYP
MAX
UNITS
SUPPLY
V
±15V
±5V
●
●
350
350
µV
µV
OS
∆V /∆T Input Offset Voltage Drift
(Note 8)
(Note 8)
(Note 8)
±5V to ±15V
±5V to ±15V
±5V to ±15V
±5V to ±15V
±5V to ±15V
±5V to ±15V
●
●
●
●
●
●
1
3
µV/°C
nA
OS
I
Input Offset Current
±80
OS
OS
∆I /∆T Input Offset Current Drift
60
40
pA/°C
nA
I –
B
Inverting Input Bias Current
±20
±60
∆I –/∆T Inverting Input Bias Current Drift
B
pA/°C
nA
I +
Noninverting Input Bias Current
Input Voltage Range (Positive)
B
V
±15V
±5V
●
●
12.5
2.5
V
V
CM
Input Voltage Range (Negative)
Common Mode Rejection Ratio
±15V
±5V
●
●
–12.5
–2.5
V
V
CMRR
V
V
= ±12.5V
= ±2.5V
±15V
±5V
●
●
94
94
dB
dB
CM
CM
3
LT1469
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the temperature range
0°C ≤ TA ≤ 70°C, VCM = 0V unless otherwise noted.
SYMBOL PARAMETER
Minimum Supply Voltage
CONDITIONS
V
MIN
TYP
MAX
UNITS
V
SUPPLY
Guaranteed by PSRR
●
●
±4.5
PSRR
Power Supply Rejection Ratio
Large-Signal Voltage Gain
V = ±4.5V to ±15V
S
95
dB
A
V
V
V
V
V
= ±12.5V, R = 10k
= ±12.5V, R = 2k
= ±2.5V, R = 10k
= ±2.5V, R = 2k
±15V
±15V
±5V
●
●
●
●
100
100
100
100
V/mV
V/mV
V/mV
V/mV
VOL
OUT
OUT
OUT
OUT
L
L
L
±5V
L
Maximum Output Swing
Maximum Output Current
R = 10k, 1mV Overdrive
±15V
±15V
±5V
●
●
●
●
±12.9
±12.7
±2.9
V
V
V
V
OUT
L
R = 2k, 1mV Overdrive
L
R = 10k, 1mV Overdrive
L
R = 2k, 1mV Overdrive
L
±5V
±2.7
I
I
V
V
= ±12.5V, 1mV Overdrive
= ±2.5V, 1mV Overdrive
±15V
±5V
●
●
±12.5
±12.5
mA
mA
OUT
SC
OUT
OUT
Output Short-Circuit Current
Slew Rate
V
= 0V, 0.2V Overdrive (Note 3)
±15V
●
±17
mA
OUT
SR
A = –10, R = 2k (Note 6)
±15V
±5V
●
●
13
9
V/µs
V/µs
V
L
GBW
Gain Bandwidth Product
Channel Separation
f = 100kHz, R = 2k
±15V
±5V
●
●
55
50
MHz
MHz
L
V
V
= ±12.5V, R = 2k
±15V
±5V
●
●
98
98
dB
dB
OUT
OUT
L
= ±2.5V, R = 2k
L
I
Supply Current
Per Amplifier
±15V
±5V
●
●
6.5
6.3
mA
mA
S
∆V
OS
Input Offset Voltage Match
±15V
±5V
●
●
600
600
µV
µV
∆I –
Inverting Input Bias Current Match
±5V to ±15V
±5V to ±15V
●
●
±38
nA
nA
B
∆I +
B
Noninverting Input Bias Current Match
±118
∆CMRR Common Mode Rejection Match
V
V
= ±12.5V (Note 9)
= ±2.5V (Note 9)
±15V
±5V
●
●
91
91
dB
dB
CM
CM
∆PSRR Power Supply Rejection Match
V = ±4.5V to ±15V (Note 9)
S
●
92
dB
The ● denotes the specifications which apply over the temperature range –40°C ≤ TA ≤ 85°C, VCM = 0V unless otherwise noted.
(Note 5)
SYMBOL PARAMETER
Input Offset Voltage
CONDITIONS
V
MIN
TYP
MAX
UNITS
SUPPLY
V
±15V
±5V
●
●
500
500
µV
µV
OS
∆V /∆T Input Offset Voltage Drift
(Note 8)
(Note 8)
(Note 8)
±5V to ±15V
±5V to ±15V
±5V to ±15V
±5V to ±15V
±5V to ±15V
±5V to ±15V
●
●
●
●
●
●
1
4
µV/°C
nA
OS
I
Input Offset Current
±120
OS
OS
∆I /∆T Input Offset Current Drift
120
80
pA/°C
nA
I –
B
Inverting Input Bias Current
±40
±80
∆I –/∆T Inverting Input Bias Current Drift
B
pA/°C
nA
I +
Noninverting Input Bias Current
Input Voltage Range (Positive)
B
V
±15V
±5V
●
●
12.5
2.5
V
V
CM
Input Voltage Range (Negative)
±15V
±5V
●
●
–12.5
–2.5
V
V
4
LT1469
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the temperature range
–40°C ≤ TA ≤ 85°C, VCM = 0V unless otherwise noted. (Note 5)
SYMBOL PARAMETER CONDITIONS
V
MIN
TYP
MAX
UNITS
SUPPLY
±15V
±5V
CMRR
Common Mode Rejection Ratio
V
V
= ±12.5V
= ±2.5V
●
●
92
92
dB
dB
CM
CM
Minimum Supply Voltage
Power Supply Rejection Ratio
Large-Signal Voltage Gain
Guaranteed by PSRR
V = ±4.5V to ±15V
●
●
±4.5
V
PSRR
93
dB
S
A
V
V
V
V
V
= ±12,5V, R = 10k
±15V
±15V
±5V
●
●
●
●
75
75
75
75
V/mV
V/mV
V/mV
V/mV
VOL
OUT
OUT
OUT
OUT
OUT
L
= ±12.5V, R = 2k
L
= ±2.5V, R = 10k
L
= ±2.5V, R = 2k
±5V
L
Maximum Output Swing
Maximum Output Current
R = 10k, 1mV Overdrive
±15V
±15V
±5V
●
●
●
●
±12.8
±12.6
±2.8
V
V
V
V
L
R = 2k, 1mV Overdrive
L
R = 10k, 1mV Overdrive
L
R = 2k, 1mV Overdrive
L
±5V
±2.6
I
I
V
V
= ±12.5V, 1mV Overdrive
= ±2.5V, 1mV Overdrive
±15V
±5V
●
●
±7
±7
mA
mA
OUT
SC
OUT
OUT
Output Short-Circuit Current
Slew Rate
V
= 0V, 0.2V Overdrive (Note 3)
±15V
●
±12
mA
OUT
SR
A = –10, R = 2k (Note 6)
±15V
±5V
●
●
9
6
V/µs
V/µs
V
L
GBW
Gain Bandwidth Product
Channel Separation
f = 100kHz, R = 2k
±15V
±5V
●
●
45
40
MHz
MHz
L
V
V
= ±12.5V, R = 2k
±15V
±5V
●
●
96
96
dB
dB
OUT
OUT
L
= ±2.5V, R = 2k
L
I
Supply Current
Per Amplifier
±15V
±5V
●
●
7
6.8
mA
mA
S
∆V
OS
Input Offset Voltage Match
±15V
±5V
●
●
800
800
µV
µV
∆I –
Inverting Input Bias Current Match
±5V to ±15V
±5V to ±15V
●
●
±78
nA
nA
B
∆I +
B
Noninverting Input Bias Current Match
±158
∆CMRR Common Mode Rejection Match
V
V
= ±12.5V (Note 9)
= ±2.5V (Note 9)
±15V
±5V
●
●
89
89
dB
dB
CM
CM
∆PSRR Power Supply Rejection Match
V = ±4.5V to ±15V (Note 9)
S
●
90
dB
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The inputs are protected by back-to-back diodes and two 100Ω
series resistors. If the differential input voltage exceeds 0.7V, the input
current should be limited to less than 10mA. Input voltages outside the
supplies will be clamped by ESD protection devices and input currents
should also be limited to less than 10mA.
performance from –40°C to 85°C but is not tested or QA sampled at these
temperatures. The LT1469I is guaranteed to meet specified performance
from –40°C to 85°C.
Note 6: Slew rate is measured between ±8V on the output with ±12V
swing for ±15V supplies and ±2V on the output with ±3V swing for ±5V
supplies.
Note 7: Full-power bandwidth is calculated from the slew rate.
Note 3: A heat sink may be required to keep the junction temperature
FPBW = SR/2πV .
P
below absolute maximum when the output is shorted indefinitely.
Note 8: This parameter is not 100% tested.
Note 4: The LT1469C and LT1469I are guaranteed functional over the
operating temperature range of –40°C to 85°C.
Note 5: The LT1469C is guaranteed to meet specified performance from
0°C to 70°C and is designed, characterized and expected to meet specified
Note 9: ∆CMRR and ∆PSRR are defined as follows: 1) CMRR and PSRR
are measured in µV/V on each amplifier; 2) the difference between the two
sides is calculated in µV/V; 3) the result is converted to dB.
5
LT1469
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APPLICATIO S I FOR ATIO
Layout and Passive Components
Microvolt level error voltages can also be generated in the
external circuitry. Thermocouple effects caused by tem-
perature gradients across dissimilar metals at the con-
tacts to the inputs can exceed the inherent drift of the
amplifier. Air currents over device leads should be mini-
mized, package leads should be short and the two input
leads should be as close together as possible and main-
tained at the same temperature.
The LT1469 requires attention to detail in board layout in
order to maximize DC and AC performance. For best AC
results (for example, fast settling time) use a ground
plane, short lead lengths and RF quality bypass capacitors
(0.01µF to 0.1µF) in parallel with low ESR bypass capaci-
tors(1µFto10µFtantalum). ForbestDCperformance, use
“star” grounding techniques, equalize input trace lengths
and minimize leakage (i.e., 1.5GΩ of leakage between an
input and a 15V supply will generate 10nA—equal to the
maximum IB– specification).
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input can combine with
the input capacitance to form a pole which can cause
peakingorevenoscillations.Forfeedbackresistorsgreater
than 2k, a feedback capacitor of value CF > RG • CIN/RF
should be used to cancel the input pole and optimize
dynamic performance. For applications where the DC
noise gain is one, and a large feedback resistor is used, CF
should be greater than or equal to CIN. An example would
beaDACI-to-Vconverterasshownonthebackpageofthe
data sheet where the DAC can have many tens of picofar-
ads of output capacitance. Another example would be a
gainof–1with5kresistors;a5pFto10pFcapacitorshould
be added across the feedback resistor.
Board leakage can be minimized by encircling the input
circuitry with a guard ring operated at a potential close to
that of the inputs: for inverting configurations tie the ring
to ground, in noninverting connections tie the ring to the
inverting input (note the input capacitance will increase
whichmayrequireacompensatingcapacitorasdiscussed
below).
C
F
R
F
R
G
–
C
IN
1/2 LT1469
V
OUT
V
IN
+
1469 F01
Figure 1. Nulling Input Capacitance
6
LT1469
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APPLICATIO S I FOR ATIO
Input Considerations
The input bias currents vary with common mode voltage.
The cancellation circuitry was not designed to track this
common mode voltage because the settling time would
have been adversely affected.
Each input of the LT1469 is protected with a 100Ω series
resistor and back-to-back diodes across the bases of the
input devices. If large differential input voltages are antici-
pated, limit the input current to less than 10mA with an
external series resistor. Each input also has two ESD
clamp diodes—one to each supply. If an input is driven
beyond the supply, limit the current with an external
resistor to less than 10mA.
The LT1469 inputs can be driven to the negative supply
and to within 0.5V of the positive supply without phase
reversal. As the input moves closer than 0.5V to the
positive supply, the output reverses phase.
Total Input Noise
The LT1469 employs bias current cancellation at the
inputs. The inverting input current is trimmed at zero
common mode voltage to minimize errors in inverting
applications such as I-to-V converters. The noninverting
input current is not trimmed and has a wider variation and
therefore a larger maximum value. As the input offset
current can be greater than either input current, the use of
balanced source resistance is NOT recommended as it
actually degrades DC accuracy and also increases noise.
The total input noise of the LT1469 is optimized for a
source resistance between 1k and 20k. Within this range,
the total input noise is dominated by the noise of the
source resistance itself. When the source resistance is
below 1k, voltage noise of the amplifier dominates. When
the source resistance is above 20k, the input noise current
is the dominant contributor.
R1
100Ω
R1
100Ω
Q1
Q2
+IN
–IN
1469 F02
Figure 2. Input Stage Protection
7
LT1469
U
W
U U
APPLICATIO S I FOR ATIO
Capacitive Loading
The settling of the DAC I-to-V converter on the back page
was measured using the exact methods of AN74. The
optimum nulling of the DAC output capacitance requires
20pF across the 6k feedback resistor. The theoretical limit
for 16-bit settling is 11.1 times this RC time constant or
1.33µs.Theactualsettlingtimeis1.7µsattheoutputofthe
LT1469. The LT1469 is the fastest Linear Technology
amplifier in this application.
TheLT1469drivescapacitiveloadsofupto100pFinunity-
gain and 300pF in a gain of –1. When there is a need to
drive a larger capacitive load, a small series resistor
should be inserted between the output and the load. In
addition, a capacitor should be added between the output
and the inverting input as shown in Figure 3.
Settling Time
The RC output noise filter adds a slight settling time delay
of 100ns but reduces the noise bandwidth to 1.6MHz
which increases the output resolution for 16-bit accuracy.
The LT1469 is a single stage amplifier with an optimal
thermal layout that leads to outstanding settling perfor-
mance. Measuring settling, even at the 12-bit level is very
challenging, and at the 16-bit level requires a great deal of
subtletyandexpertise. Fortunately, therearetwoexcellent
Linear Technology reference sources for settling mea-
surements—Application Notes 47 and 74. Appendix B of
AN47 is a vital primer on 12-bit settling measurements
andAN74extendsthestate-of-the-artwhileconcentrating
on settling time with a 16-bit current output DAC input.
R
F
R
R
F
≥ (1 + R /R )/(2π • C • 5MHz)
F G L
O
F
≥ 10R
O
C = (2R /R )C
O
F
L
C
R
F
G
–
R
O
1/2 LT1469
V
OUT
C
L
V
IN
+
1469 F03
Figure 3. Driving Capacitive Loads
8
LT1469
W
W
SI PLIFIED SCHE ATIC
+
V
I1
I2
I5
Q10
Q11
Q8
Q9
OUT
+IN
Q1
Q2
–IN Q5
Q3
Q6
Q7
Q4
C
BIAS
I3
I4
I6
–
V
1469 SS
9
LT1469
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
8
7
6
5
4
0.255 ± 0.015*
(6.477 ± 0.381)
1
2
3
0.130 ± 0.005
0.300 – 0.325
0.045 – 0.065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
0.125
0.020
(0.508)
MIN
(3.175)
MIN
+0.035
0.325
–0.015
0.018 ± 0.003
(0.457 ± 0.076)
0.100
(2.54)
BSC
+0.889
8.255
(
)
N8 1098
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
10
LT1469
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
5
8
6
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
3
4
2
0.010 – 0.020
(0.254 – 0.508)
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 1298
11
LT1469
U
TYPICAL APPLICATIO
16-Bit DAC I-to-V Converter and Reference Inverter for Bipolar Output Swing (VOUT = –10V to 10V)
REF
+
1/2 LT1469
–
15pF
20pF
16 BITS
DAC INPUTS
LTC1597
–
2k
1/2 LT1469
V
OUT
50pF
+
1469 TA03
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
Single Resistor Gain Set, 0.04% Max Gain Error, 10ppm Max Gain Nonlinearity
LT1167
Precision Instrumentation Amplifier
Single 90MHz, 22V/µs, 16-Bit Accurate Op Amp
LT1468
75µV Max V , Single Version of LT1469
OS
LTC1595/LTC1596
LTC1597
16-Bit Serial Multiplying I
DAC
±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade
±1LSB Max INL/DNL, Low Glitch, On-Chip Bipolar Resistors
±2.5V Input, SINAD = 90dB, THD = –100dB
OUT
16-Bit Parallel Multiplying I
DAC
OUT
LT1604
16-Bit, 333ksps Sampling ADC
Single 5V, 16-Bit, 100ksps Sampling ADC
LTC1605
Low Power, ±10V Inputs, Parallel/Byte Interface
1469i LT/TP 0200 4K • PRINTED IN USA
12 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 2000
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