LT1577CS-3.3/ADJ#TR [Linear]
LT1577 - Ultrafast Transient Response, Low Dropout Regulators Adjustable and Fixed; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C;
| 型号： | LT1577CS-3.3/ADJ#TR |
| 厂家： | 
Linear |
| 描述： | LT1577 - Ultrafast Transient Response, Low Dropout Regulators Adjustable and Fixed; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C 线性稳压器IC 调节器 电源电路 光电二极管 输出元件 |
| 文件： | 总20页 (文件大小：372K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1575/LT1577
Ultrafast Transient Response,
Low Dropout Regulators
Adjustable and Fixed
U
DESCRIPTION
FEATURES
UltraFastTM Transient Response Eliminates
The LT®1575/LT1577 are single/dual controller ICs that
drive low cost external N-channel MOSFETs as source
followers to produce ultrafast transient response, low
dropout voltage regulators.
■
Tantalum and Electrolytic Output Capacitors
■
FET RDS(ON) Defines Dropout Voltage
■
1% Reference/Output Voltage Tolerance Over
Temperature
Typical Load Regulation: 1mV
The LT1575/LT1577 achieve unprecedented transient-
load performance by eliminating expensive tantalum or
bulk electrolytic output capacitors in the most demanding
modern microprocessor applications. Precision-trimmed
adjustable and fixed output voltage versions accommo-
date any required microprocessor power supply voltage.
Selection of the N-channel MOSFET RDS(ON) allows very
low dropout voltages to be achieved.
■
■
High Side Sense Current Limit
■
Multifunction ShUutdown Pin with Latchoff
APPLICATIONS
Pentium® Processor Supplies
■
PowerPCTM Supplies
■
■
5V to 3.XXV or 3.3V to 2.XXV Microprocessor Supplies
GTL Termination
Low Voltage Logic Supplies
Unique protection features include a high side current
limit amplifier that activates a fault protection timer
circuit. A multifunction Shutdown pin provides either
current limit time-out with latchoff, overvoltage protec-
tion, thermal shutdown or a combination of these func-
tions. TheLT1575isavailablein8-pinSOorPDIPandthe
LT1577 is available in 16-pin narrow body SO.
■
■
LT1575CN8/LT1575CS8
LT1575CN8-1.5/LT1575CS8-1.5
LT1575CN8-2.8/LT1575CS8-2.8
LT1575CN8-3.3/LT1575CS8-3.3
LT1575CN8-3.5/LT1575CS8-3.5
LT1575CN8-5/LT1575CS8-5
LT1577CS-ADJ/ADJ
Adjustable
1.5V Fixed
2.8V Fixed
3.3V Fixed
3.5V Fixed
5V Fixed
Adjustable, Adjustable
3.3V Fixed, Adjustable
3.3V Fixed, 2.8V Fixed
, LTC and LT are registered trademarks of Linear Technology Corporation.
UltraFast is a trademark of Linear Technology Corporation.
Pentium is a registered trademark of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
LT1577CS-3.3/ADJ
LT1577CS-3.3/2.8
Consult factory for additional output voltage combinations available
in the LT1577.
U
TYPICAL APPLICATION
Transient Response for
0.2A to 5A Output Load Step
Ultrafast Transient Response 5V to 3.3V Low Dropout Regulator
(For Schematic Including Current Limit, See Typical Applications)
LT1575-3.3
12V
1
2
3
4
8
7
6
5
SHDN
IPOS
INEG
5V
50mV/DIV
2A/DIV
+
FOR T < 45°C:
*
C5
220µF
C2
1µF
V
IN
C6 = 24 × 1µF Y5V
CERAMIC SURFACE
MOUNT CAPACITORS.
Q1
IRFZ24
GND
OUT
GATE
COMP
R2
5Ω
V
3.3V
5A
FOR T > 45°C:
OUT
C6 = 24 × 1µF X7R
CERAMIC SURFACE
MOUNT CAPACITORS.
PLACE C6 IN THE
MICROPROCESSOR
SOCKET CAVITY
R1
7.5k
C4
C6*
24µF
C3
10pF
1000pF
GND
1575/77 TA02
100µs/DIV
1575/77 TA01
1
LT1575/LT1577
W W W
U
ABSOLUTE AXI U RATI GS
(Note 1)
Junction Temperature (Note 2)................ 0°C to 100°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
VIN, IPOS, INEG ...................................................... 22V
SHDN....................................................................... VIN
Operating Ambient Temperature Range ..... 0°C to 70°C
W
U
/O
PACKAGE RDER I FOR ATIO
TOP VIEW
TOP VIEW
SHDN
1
2
3
4
IPOS
INEG
GATE
COMP
8
7
6
5
SHDN
IPOS
INEG
GATE
COMP
1
2
3
4
8
7
6
5
TOP VIEW
V
V
IN
IN
GND
FB
GND
OUT
SHDN1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IPOS1
INEG1
GATE1
COMP1
IPOS2
INEG2
GATE2
COMP2
V
IN1
GND1
FB1
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
8-LEAD PLASTIC SO
TJMAX = 100°C, θJA = 100°C/ W (N8)
JMAX = 100°C, θJA = 130°C/ W (S8)
TJMAX = 100°C, θJA = 100°C/ W (N8)
JMAX = 100°C, θJA = 130°C/ W (S8)
SHDN2
T
T
V
IN2
GND2
FB2
ORDER PART NUMBER
ORDER PART NUMBER
LT1575CN8
LT1575CS8
LT1575CN8-1.5
LT1575CS8-3.3
LT1575CN8-3.5
LT1575CS8-3.5
LT1575CN8-5
LT1575CS8-5
S PACKAGE
16-LEAD PLASTIC NARROW SO
LT1575CS8-1.5
LT1575CN8-2.8
LT1575CS8-2.8
LT1575CN8-3.3
TJMAX = 100°C, θJA = 100°C/ W
S8 PART MARKING
1575
S8 PART MARKING
ORDER PART NUMBER
LT1577CS-ADJ/ADJ
157535
15755
157515
157528
157533
TOP VIEW
TOP VIEW
SHDN1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
IPOS1
SHDN1
1
2
3
4
5
6
7
8
IPOS1
INEG1
GATE1
COMP1
IPOS2
INEG2
GATE2
COMP2
V
INEG1
GATE1
COMP1
IPOS2
INEG2
GATE2
COMP2
V
IN1
IN1
GND1
OUT-3.3
SHDN2
GND1
OUT-3.3
SHDN2
V
V
IN2
IN2
GND2
FB
GND2
OUT-2.8
S PACKAGE
16-LEAD PLASTIC NARROW SO
S PACKAGE
16-LEAD PLASTIC NARROW SO
TJMAX = 100°C, θJA = 100°C/ W
TJMAX = 100°C, θJA = 100°C/ W
ORDER PART NUMBER
LT1577CS-3.3/2.8
ORDER PART NUMBER
LT1577CS-3.3/ADJ
Consult factory for Industrial and Military grade parts.
2
LT1575/LT1577
ELECTRICAL CHARACTERISTICS
TA = 25°C, VIN = 12V, GATE = 6V, IPOS = INEG = 5V, SHDN = 0.75V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Supply Current
●
●
●
●
●
●
5
12
19
mA
Q
V
LT1575 Reference Voltage
–0.6
–1.0
1.210
1.210
0.6
1.0
%
%
FB
V
LT1575-1.5 Output Voltage
LT1575-2.8 Output Voltage
LT1575-3.3 Output Voltage
LT1575-3.5 Output Voltage
LT1575-5 Output Voltage
–0.6
–1.0
1.500
1.500
0.6
1.0
%
%
OUT
–0.6
–1.0
2.800
2.800
0.6
1.0
%
%
–0.6
–1.0
3.300
3.300
0.6
1.0
%
%
–0.6
–1.0
3.500
3.500
0.6
1.0
%
%
–0.6
–1.0
5.000
5.000
0.6
1.0
%
%
●
●
●
●
●
●
●
●
●
●
●
●
●
Line Regulation
10V ≤ V ≤ 20V
0.01
–0.6
1.0
84
0.03
–4.0
1.5
%/V
µA
mA
dB
dB
dB
dB
dB
dB
V
IN
I
I
FB Input Bias Current
FB = V
FB
FB
OUT
OUT Divider Current
OUT = V
0.5
69
67
60
60
60
56
OUT
A
LT1575 Large-Signal Voltage Gain
LT1575-1.5 Large-Signal Voltage Gain
LT1575-2.8 Large-Signal Voltage Gain
LT1575-3.3 Large-Signal Voltage Gain
LT1575-3.5 Large-Signal Voltage Gain
LT1575-5 Large-Signal Voltage Gain
GATE Output Swing Low (Note 3)
GATE Output Swing High
V
V
V
V
V
V
= 3V to 10V
= 3V to 10V
= 3V to 10V
= 3V to 10V
= 3V to 10V
= 3V to 10V
= 0mA
VOL
GATE
GATE
GATE
GATE
GATE
GATE
GATE
GATE
82
76
75
74
71
V
V
I
I
2.5
3.0
1.0
OL
= 0mA
V
– 1.6
V
– 1
IN
V
OH
IN
IPOS + INEG Supply Current
Current Limit Threshold Voltage
3V ≤ IPOS ≤ 20V
0.3
0.625
mA
42
37
50
50
58
63
mV
mV
●
●
Current Limit Threshold Voltage
Line Regulation
3V ≤ IPOS ≤ 20V
–0.20
–0.50
%/V
SHDN Sink Current
Current Flows Into Pin
Current Flows Out of Pin
●
●
●
●
●
●
2.5
–8
5.0
–15
0.1
8.0
–23
0.25
2.20
1.240
150
µA
µA
V
SHDN Source Current
SHDN Low Clamp Voltage
SHDN High Clamp Voltage
SHDN Threshold Voltage
SHDN Threshold Hysteresis
1.50
1.18
50
1.85
1.21
100
V
V
mV
The
●
denotes specifications which apply over the full operating
Because the LT1577 consists of two regulators in the package, the total
LT1577 power dissipation must be used for its junction temperature
temperature range.
calculation. The total LT1577 P = P (Regulator 1) + P (Regulator 2).
D
D
D
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 3: The V
of the external MOSFET must be greater than
GS(th)
3V – V
.
OUT
Note 2: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formulas:
D
LT1575CN8: T = T + (P • 100°CW)
J
A
D
LT1575CS8: T = T + (P • 130°CW)
J
A
D
LT1577CS: T = T + (P • 100°CW)
J
A
D
3
LT1575/LT1577
W
U
TYPICAL PERFORMANCE CHARACTERISTICS
Adjustable LT1575 VREF
vs Temperature
FB Input Bias Current
vs Temperature
Quiescent Current vs Temperature
19
18
17
16
15
14
13
12
11
10
9
4.0
3.5
1.222
1.220
1.218
1.216
3.0
2.5
V
IN
V
IN
= 12V
= 20V
1.214
1.212
2.0
1.5
1.210
1.208
V
IN
= 8V
1.206
1.204
V
IN
= 20V
1.0
0.5
8
7
6
1.202
1.200
V
IN
V
IN
= 12V
= 8V
5
0
1.198
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1575/77 G03
1575/77 G01
1575/77 G02
LT1575-2.8 VOUT vs Temperature
LT1575-3.3 VOUT vs Temperature
LT1575-1.5 VOUT vs Temperature
2.828
2.824
2.800
2.816
2.812
2.808
2.804
2.800
2.796
2.792
2.788
2.784
2.780
2.776
2.772
3.333
3.327
3.321
3.315
3.309
3.303
3.297
3.291
3.285
3.279
3.273
3.267
1.515
1.512
1.509
1.506
1.503
1.500
1.497
1.494
1.491
1.488
1.485
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
50
100 125 150 175
75
25
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1575/77 G04
1575/77 G06
1575/77 G05
OUT Divider Current
vs Temperature
LT1575-5 VOUT vs Temperature
LT1575-3.5 VOUT vs Temperature
3.535
3.530
3.525
3.520
3.515
3.510
3.505
3.500
3.495
3.490
3.485
3.480
3.475
3.470
3.465
5.050
5.040
5.030
5.020
5.010
5.000
4.990
4.980
4.970
4.960
4.950
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
–75 –50 –25
0
25 50 75
100 125
150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1575/77 G08
1575/77 G09
1575/77 G07
4
LT1575/LT1577
W
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TYPICAL PERFORMANCE CHARACTERISTICS
Error Amplifier Large-Signal
Voltage Gain vs Temperature
VREF/VOUT Line Regulation
vs Temperature
Gain and Phase vs Frequency
200
150
100
50
0.030
0.025
120
115
110
105
100
95
0.020
0.015
PHASE
90
GAIN
0.010
0.005
0
85
80
75
70
0
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
75 100 125 150 175
1k
10k
100k
1M
10M
100M
25 50
TEMPERATURE (°C)
FREQUENCY (Hz)
TEMPERATURE (°C)
1575/77 G12
1575/77 G10
1575/77 G11
Gate Output Swing Low
vs Temperature
Gate Output Swing High
vs Temperature
IPOS + INEG Supply Current
vs Temperature
3.00
2.75
3.0
2.5
1000
900
I
= 50mA
LOAD
2.50
2.25
IPOS = INEG = 5V
IPOS = INEG = 12V
IPOS = INEG = 20V
800
NO LOAD
2.0
1.5
700
600
500
400
I
= 50mA
LOAD
2.00
1.75
IPOS = INEG = 3V
1.0
0.5
0
1.50
1.25
NO LOAD
1.00
300
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75
0
50 75 100 125 150 175
–50 –25
25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1575/77 G13
1575/77 G14
1575/77 G15
Current Limit Threshold Voltage
Line Regulation vs Temperature
Current Limit Threshold Voltage
vs Temperature
0
65
60
–0.1
–0.2
–0.3
–0.4
–0.5
IPOS = 5V
IPOS = 3V
55
50
IPOS = 20V
45
40
35
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
1575/77 G17
1575/77 G16
5
LT1575/LT1577
TYPICAL PERFORMANCE CHARACTERISTICS
W
U
SHDN Low Clamp Voltage
vs Temperature
SHDN Sink Current
vs Temperature
SHDN Source Current
vs Temperature
–10
–11
–12
–13
–14
–15
–16
–17
–18
–19
–20
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
0.25
0.20
0.15
0.10
0.05
0
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1575/77 G18
1575/77 G19
1575/77 G20
SHDN High Clamp Voltage
vs Temperature
SHDN Hysteresis vs Temperature
2.1
2.0
150
140
130
120
110
100
90
1.9
1.8
1.7
1.6
1.5
80
70
60
50
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
1575/77 G21
1575/77 G22
6
LT1575/LT1577
U
U
U
PIN FUNCTIONS
SHDN (Pin 1): This is a multifunction shutdown pin that
provides GATE drive latchoff capability. A 15µA current
source, that turns on when current limit is activated,
charges a capacitor placed in series with SHDN to GND
and performs a current limit time-out function. The pin is
also the input to a comparator referenced to VREF (1.21V).
WhenthepinpullsaboveVREF, thecomparatorlatchesthe
gate drive to the external MOSFET off. The comparator
typically has 100mV of hysteresis and the Shutdown pin
can be pulled low to reset the latchoff function. This pin
provides overvoltage protection or thermal shutdown
protection when driven from various resistor divider
schemes.
sation. The transconductance of the error amplifier is 15
millimhos and open-loop voltage gain is typically 84dB.
Frequency compensation is generally performed with a
series RC network to ground.
GATE (Pin 6): This is the output of the error amplifier that
drives N-channel MOSFETs with up to 5000pF of “effec-
tive” gate capacitance. The typical open-loop output
impedance is 2Ω. When using low input capacitance
MOSFETs (<1500pF), a small gate resistor of 2Ω to 10Ω
dampens high frequency ringing created by an LC reso-
nance that is created by the MOSFET gate’s lead induc-
tance and input capacitance. The GATE pin delivers up to
50mA for a few hundred nanoseconds when slewing the
gateoftheN-channelMOSFETinresponsetooutputload
current transients.
VIN (Pin 2): This is the input supply for the IC that powers
the majority of internal circuitry and provides sufficient
gatedrivecompliancefortheexternalN-channelMOSFET.
Thetypicalsupplyvoltageis12Vwith12.5mAofquiescent
current. The maximum operating VIN is 20V and the
minimum operating VIN is set by VOUT + VGS of the
MOSFET at max. IOUT + 1.6V (worst-case VIN to GATE
output swing).
INEG (Pin 7): This is the negative sense terminal of the
current limit amplifier. A small sense resistor is connected
in series with the drain of the external MOSFET and is
connected between the IPOS and INEG pins. A 50mV
threshold voltage in conjunction with the sense resistor
value sets the current limit level. The current sense resis-
tor can be a low value shunt or can be made from a piece
of PC board trace. If the current limit amplifier is not used,
tie the INEG pin to IPOS to defeat current limit. An
alternative is to ground the INEG pin. This action disables
the current limit amplifier and additional internal circuitry
activates the timer circuit on the SHDN pin if the GATE pin
swings to the VIN rail. This option provides the user with
a “sense-less” current limit function.
GND (Pin 3): Analog Ground. This pin is also the negative
sense terminal for the internal 1.21V reference. Connect
external feedback divider networks that terminate to GND
and frequency compensation components that terminate
to GND directly to this pin for best regulation and perfor-
mance.
FB (Pin 4): This is the inverting input of the error amplifier
for the adjustable voltage LT1575. The noninverting input
is tied to the internal 1.21V reference. Input bias current
forthispinistypically0.6µAflowingoutofthepin.Thispin
is normally tied to a resistor divider network to set output
voltage. Tie the top of the external resistor divider directly
to the output voltage for best regulation performance.
IPOS (Pin 8): This is the positive sense terminal of the
current limit amplifier. Tie this pin directly to the main
input voltage from which the output voltage is regulated.
The typical input voltage is a 5V logic supply. This pin is
also the input to a comparator on the fixed voltage ver-
sions that monitors the input/output differential voltage of
theexternalMOSFET.Ifthisdifferentialvoltageislessthan
0.5V,thentheSHDNtimerisnotallowedtostartevenifthe
GATE is at the VIN rail. This allows the regulator to start up
normallyastheinputvoltageisrampingup,evenwithvery
slow ramp rates.
OUT (Pin 4): This is the inverting input of the error
amplifier for the fixed voltage LT1575. The fixed voltage
parts contain a precision resistor divider network to set
output voltage. The typical resistor divider current is 1mA
into the pin. Tie this pin directly to the output voltage for
best regulation performance.
COMP (Pin 5):This is the high impedance gain node of the
erroramplifierandisusedforexternalfrequencycompen-
7
LT1575/LT1577
W
BLOCK DIAGRAM
LT1575 Adjustable Voltage
V
TH1
50mV
IPOS
INEG
I1
+
–
15µA
I
AMP
LIM
OR1
SW1
NORMALLY
OPEN
D1
D2
SHDN
+
COMP1
R2
5k
–
+
Q6
–
I2
5µA
COMP2
COMP3
100mV
HYSTERESIS
OR2
SW2
NORMALLY
CLOSED
+
–
V
IN
V
TH2
1V
1.21V
START-UP
V
REF
GND
FB
+
GATE
ERROR AMP
–
COMP
I3
100µA
Q4
Q5
Q1
Q2
Q3
R1
50k
1575/77 BD1
8
LT1575/LT1577
W
BLOCK DIAGRAM
LT1575 Fixed Voltage
IPOS
I1
+
15µA
V
TH1
I
AMP
LIM
INEG
OR1
SW1
50mV
NORMALLY
OPEN
–
D1
D2
SHDN
–
+
+
V
TH3
COMP4
COMP2
COMP3
COMP1
500mV
R2
5k
Q6
–
100mV
HYSTERESIS
I2
5µA
–
+
OR2
SW2
NORMALLY
CLOSED
+
–
V
IN
V
TH2
1V
1.21V
START-UP
V
REF
Q7
GND
OUT
+
GATE
ERROR AMP
–
R3*
COMP
I3
100µA
Q4
Q5
Q1
Q2
Q3
R4*
R1
50k
*V
= (1 + R3/R4)V
REF
1575/77 BD2
OUT
9
LT1575/LT1577
U
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APPLICATIONS INFORMATION
Introduction
nificant cost as all additional bulk capacitance is removed.
The additional savings of insertion cost, purchasing/in-
ventory cost and board space are readily apparent.
The current generation of microprocessors place strin-
gent demands on the power supply that powers the
processor core. These microprocessors cycle load cur-
rent from near zero to amps in tens of nanoseconds.
Output voltage tolerances as low as ±100mV include
transient response as part of the specification. Some
microprocessorsrequireonlyasingleoutputvoltagefrom
which the core and I/O circuitry operate. Other higher
performance processors require a separate power supply
voltage for the processor core and the I/O circuitry. These
requirements mandate the need for very accurate, very
high speed regulator circuits.
Precision-trimmed adjustable and fixed output voltage
versions accommodate any required microprocessor
power supply voltage. Proper selection of the N-channel
MOSFET RDS(ON) allows user-settable dropout voltage
performance. The only output capacitors required are the
high frequency ceramic decoupling capacitors. This regu-
lator design provides ample bandwidth and responds to
transient load changes in a few hundred nanoseconds
versus regulators that respond in many microseconds.
The ceramic capacitor network generally consists of 10 to
24 1uF capacitors for individual microprocessor require-
ments. The LT1575/LT1577 family also incorporates cur-
rent limitingfor no additional system cost, provides on/off
control and overvoltage protection or thermal shutdown
with simple external components.
Previously employed solutions included monolithic
3-terminallinearregulators,PNPtransistorsdrivenbylow
cost control circuits and simple buck converter switching
regulators. The 3-terminal regulator achieves a high level
of integration, the PNP driven regulator achieves very low
dropoutperformanceandtheswitchingregulatorachieves
high electrical efficiency.
Therefore, the unique design of these new ICs combines
the benefits of low dropout voltage, high functional inte-
gration, precision performance and ultrafast transient
response, as well as providing significant cost savings on
the output capacitance needed in fast load transient appli-
cations. As lower input/output differential voltage applica-
tions become increasingly prevalent, an LT1575-based
solutionachievescomparableefficiencyperformancewith
a switching regulator at an appreciable cost savings.
However, the common trait manifested by these solutions
is that transient response is measured in many microsec-
onds. This fact translates to a regulator output decoupling
capacitor scheme that requires several hundred microfar-
ads of very low ESR bulk capacitance using multiple
capacitors surrounding the CPU. This required bulk ca-
pacitance is in addition to the ceramic decoupling capaci-
tor network that handles the transient load response
during the first few hundred nanoseconds as well as
providing microprocessor clock frequency noise immu-
nity. The combined cost of all capacitors is a significant
percentage of the total power supply cost.
The new LT1575/LT1577 family of low dropout regulator
controller ICs step to the next level of performance re-
quired by system designers for the latest generation
motherboards and microprocessors. The simple versatil-
ity and benefits derived from these circuits allow the
power supply needs of today’s high performance micro-
processors to be met with ease.
The LT1575/LT1577 family of single/dual controller ICs
are unique, easy to use devices that drive external
N-channelMOSFETsassourcefollowersandpermitauser
to realize an extremely low dropout, ultrafast transient
response regulator. These circuits achieve superior regu-
lator bandwidth and transient load performance by com-
pletely eliminating expensive tantalum or bulk electrolytic
capacitors in the most modern and demanding micropro-
cessor applications. For example, a 200MHz Pentium
processor can operate with only the recommended 24 1µF
ceramic capacitors. Users benefit directly by saving sig-
Block Diagram Operation
The primary block diagram elements consist of a simple
feedback control loop and the secondary block diagram
elements consist of multiple protection functions. Exam-
ining the block diagram for the LT1575, a start-up circuit
provides controlled start-up for the IC, including the
precision-trimmed bandgap reference, and establishes all
internal current and voltage biasing.
10
LT1575/LT1577
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APPLICATIONS INFORMATION
Reference voltage accuracy for the adjustable version and
output voltage accuracy for the fixed voltage versions are
specified as ±0.6% at room temperature and as ±1% over
the full operating temperature range. This places the
LT1575/LT1577familyamongaselectgroupofregulators
with a very tightly specified output voltage tolerance. The
accurate 1.21V reference is tied to the noninverting input
of the main error amplifier in the feedback control loop.
Because the MOSFET pass transistor is connected as a
source follower, the power path gain is much more pre-
dictable than designs that employ a discrete PNP transis-
tor as the pass device. This is due to the significant
production variations encountered with PNP Beta.
MOSFETsarealsoveryhighspeeddeviceswhichenhance
the ability to produce a stable wide bandwidth control
loop. An additional advantage of the follower topology is
inherently good line rejection. Input supply disturbances
donotpropagatethroughtotheoutput. Thefeedbackloop
for a regulator circuit is completed by providing an error
signal to the FB pin in the adjustable voltage version and
the OUT pin in the fixed voltage version. In both cases, a
resistor divider network senses the output voltage and
sets the regulated DC bias point. In general, the LT1575
regulator feedback loop permits a loop crossover fre-
quency on the order of 1MHz while maintaining good
phase and gain margins. This unity-gain frequency is a
factor of 20 to 30 times the bandwidth of currently
implementedregulatorsolutionsformicroprocessorpower
supplies. This significant performance benefit is what
permits the elimination of all bulk output capacitance.
Theerroramplifierconsistsofasinglehighgaingm stage
with a transconductance equal to 15 millimhos. The
inverting terminal is brought out as the FB pin in the
adjustable voltage version and as the OUT pin in fixed
voltage versions. The gm stage provides differential-to-
single ended conversion at the COMP pin. The output
impedance of the gm stage is about 1MΩ and thus, 84dB
of typical DC error amplifier open-loop gain is realized
along with a typical 75MHz uncompensated unity-gain
crossover frequency. Note that the overall feedback
loop’s DC gain decreases from the gain provided by the
error amplifier by the attenuation factor in the resistor
divider network which sets the DC output voltage. These
attenuation factors are already built into the Open-Loop
Voltage Gain specifications for the LT1575 fixed voltage
versions in the Electrical Characteristics table to simplify
user calculations. External access to the high impedance
gain node of the error amplifier permits typical loop
compensation to be accomplished with a series RC
network to ground.
Several other unique features are included in the design
that increase its functionality and robustness. These func-
tions comprise the remainder of the block diagram.
A high side sense, current limit amplifier provides active
current limiting for the regulator. The current limit ampli-
fier uses an external low value shunt resistor connected in
series with the external MOSFET’s drain. This resistor can
be a discrete shunt resistor or can be manufactured from
a Kelvin-sensed section of “free” PC board trace. All load
currentflowsthroughtheMOSFETdrainandthus,through
the sense resistor. The advantage of using high side
current sensing in this topology is that the MOSFET’s gain
and the main feedback loop’s gain remain unaffected. The
sense resistor develops a voltage equal to IOUT(RSENSE).
The current limit amplifier’s 50mV threshold voltage is a
goodcompromisebetweenpowerdissipationinthesense
resistor, dropout voltage impact and noise immunity.
Current limit activates when the sense resistor voltage
equals the 50mV threshold.
A high speed, high current output stage buffers the COMP
node and drives up to 5000pF of “effective” MOSFET gate
capacitance with almost no change in load transient per-
formance. The output stage delivers up to 50mA peak
when slewing the MOSFET gate in response to load
current transients. The typical output impedance of the
GATE pin is typically 2Ω. This pushes the pole due to the
error amplifier output impedance and the MOSFET input
capacitance well beyond the loop crossover frequency. If
the capacitance of the MOSFET used is less than 1500pF,
it may be necessary to add a small value series gate
resistor of 2Ω to 10Ω. This gate resistor helps damp the
LC resonance created by the MOSFET gate’s lead induc-
tance and input capacitance. In addition, the pole formed
by this resistance and the MOSFET input capacitance can
be fine tuned.
Two events occur when current limit activates: the first is
that the current limit amplifier drives Q2 in the block
11
LT1575/LT1577
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APPLICATIONS INFORMATION
diagram and clamps the positive swing of the COMP node
in the main error amplifier to a voltage that provides an
output load current of 50mV/RSENSE. This action contin-
ues as long as the output current overload persists. The
second event is that a timer circuit activates at the SHDN
pin.Thispinisnormallyheldlowbya5µAactivepull-down
that limits to ≈ 100mV above ground. When current limit
activates, the 5µA pull-down turns off and a 15µA pull-up
current source turns on. Placing a capacitor in series with
the SHDN pin to ground generates a programmable time
ramp voltage.
provide thermal shutdown with the use of a thermistor in
the divider network. Diode-ORing these functions to-
gether is simple to accomplish and provides multiple
functionality for one pin.
If the current limit amplifier is not used, two choices
present themselves. The simplest choice is to tie the INEG
pin directly to the IPOS pin. This action defeats current
limit and provides the simplest, no frills circuit. An appli-
cation in which the current limit amplifier is not used is
where an extremely low dropout voltage must be achieved
and the 50mV threshold voltage cannot be tolerated.
The SHDN pin is also the positive input of COMP1. The
negativeinputistiedtotheinternal1.21Vreference. When
the SHDN pin ramps above VREF, the comparator drives
Q4 and Q5. This action pulls the COMP and GATE pins low
and latches the external MOSFET drive off. This condition
reduces the MOSFET power dissipation to zero. The time
period until the latched-off condition occurs is typically
equaltoCSHUT(1.11V)/15µA. Forexample, a1µFcapacitor
on the SHDN pin yields a 74ms ramp time. In short, this
unique circuit block performs a current limit time-out
function that latches off the regulator drive after a pre-
defined time period. The time-out period selected is a
function of system requirements including start-up and
safe operating area. The SHDN pin is internally clamped to
typically 1.85V by Q6 and R2. The comparator tied to the
SHDN pin has 100mV of typical hysteresis to provide
noise immunity. The hysteresis is especially useful when
using the SHDN pin for thermal shutdown.
However, a second available choice permits a user to
provide short-circuit protection with no external sensing.
This technique is activated by grounding the INEG pin.
This action disables the current limit amplifier because
Schottky diode D1 clamps the amplifier’s output and
prevents Q2 from pulling down the COMP node. In addi-
tion, Schottky diode D2 turns off pull-down transistor Q1.
Q1isnormallyonandholdsinternalcomparatorCOMP3’s
output low. This comparator circuit, now enabled, moni-
torstheGATEpinanddetectssaturationatthepositiverail.
When a saturated condition is detected, COMP3 activates
the shutdown timer. Once the time-out period occurs, the
output is shut down and latched off. The operation of
resetting the latch remains the same. Note that this tech-
nique does not limit the FET current during the time-out
period. The output current is only limited by the input
powersupplyandtheinput/outputimpedance. Settingthe
timer to a short period in this mode of operation keeps the
external MOSFET within its SOA (safe operating area)
boundaryandkeepstheMOSFET’stemperatureriseunder
control.
Restoring normal operation after the load current fault is
cleared is accomplished in two ways. One option is to
recycle the nominal 12V LT1575 supply voltage as long as
an external bleed path for the Shutdown pin capacitor is
provided. The second option is to provide an active reset
circuit that pulls the SHDN pin below VREF. Pulling the
SHDN pin below VREF turns off the 15µA pull-up current
source and reactivates the 5µA pull-down. If the SHDN pin
is held below VREF during a fault condition, the regulator
continues to operate in current limit into a short. This
action requires being able to sink 15µA from the SHDN pin
at less than 1V. The 5µA pull-down current source and the
15µA pull-up current source are designed low enough in
value so that an external resistor divider network can drive
the SHDN pin to provide overvoltage protection or to
Unique circuit design incorporated into the LT1575 allevi-
ates all concerns about power supply sequencing. The
issue of power supply sequencing is an important topic as
the typical LT1575 application has inputs from two sepa-
rate power supply voltages. If the typical 12V VIN supply
voltage is slow in ramping up, insufficient MOSFET gate
drive is present and therefore, the output voltage does
not come up. If the VIN supply voltage is present, but the
typical 5V supply voltage tied to the IPOS pin has not
started yet, then the feedback loop wants to drive the
GATE pin to the positive VIN rail. This would result in a
12
LT1575/LT1577
U
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APPLICATIONS INFORMATION
very large current spike as soon as the 5V supply started
torampup.However,undervoltagelockoutcircuitCOMP2,
whichmonitorstheIPOSsupplyvoltage,holdsQ3onand
pulls the COMP pin low until the IPOS voltage increases
to greater than the internal 1.21 reference voltage. The
undervoltage lockout circuit then smoothly releases the
COMP pin and allows the output voltage to come up in
dropout from the input supply voltage. An additional
benefit derived from the speed of the LT1575 feedback
loop is that turn-on overshoot is virtually nonexistent in
a properly compensated system.
cessors dictate that precision resistors must be used with
currently available adjustable voltage regulators to meet
the initial set point tolerance. The LT1575 fixed voltage
versions incorporate the precision resistor divider into the
IC and still maintain a 1% output voltage tolerance over
temperature. Thus, the LT1575 fixed voltage versions
completely eliminate the requirement for precision resis-
tors and this results in additional system cost savings.
Applications Support
Linear Technology invests an enormous amount of time,
resources and technical expertise in understanding, de-
signing and evaluating microprocessor power supply so-
lutions for system designers. As processor speeds and
powerincrease, thepowersupplychallengespresentedto
the motherboard designer increase as well. Application
Note 69, “Using the LT1575 Linear Regulator Controller,”
has been written and serves as an extremely useful guide
for this new family of ICs. This Application Note covers
topics including PC board layout for the LT1575/LT1577
family, MOSFET selection criteria, external component
selection (capacitors) and loop compensation. Linear
Technology welcomes the opportunity to discuss, design,
evaluate and optimize a microprocessor power supply
solution with a customer. For additional information,
consult the factory.
An additional circuit feature is built-in to the LT1575 fixed
voltage versions. When the regulator circuit starts up, it
must charge up the output capacitors. The output voltage
typicallytrackstheinputvoltagesupplyasitrampsupwith
the difference in input/output voltage defined by the drop-
outvoltage. Untilthefeedbackloopcomesintoregulation,
the circuit operation results in the GATE pin being at the
positive VIN rail, which starts the timer at the SHDN pin if
the current limit amplifier is disabled. However, internal
comparator COMP4 monitors the input/output voltage
differential. This comparator does not permit the shut-
down timer to start until the differential voltage is greater
than 500mV. This permits normal start-up to occur.
One final benefit is derived in using an LT1575 fixed
voltage version. Today’s highest performance micropro-
U
TYPICAL APPLICATIONS N
UltraFast Transient Response 5V to 3.5V Low Dropout Regulator
with Current Limit and Timer Latchoff
LT1575-3.5
12V
1
2
3
4
8
7
6
5
5V
SHDN
IPOS
INEG
C1
1µF
R3*
0.007Ω
Q2
VN2222L
RESET
C2
1µF
V
IN
+
GND
OUT
GATE
COMP
C5
R2
5Ω
220µF
Q1
IRFZ24
V
*R3 IS MADE FROM
“FREE” PC BOARD
TRACE
OUT
3.5V
5A
**C6 = 24 × 1µF X7R
CERAMIC SURFACE
MOUNT CAPACITORS.
PLACE C6 IN THE
MICROPROCESSOR
SOCKET CAVITY
R1
C6**
24µF
C3
10pF
7.5k
C4
1000pF
GND
1575/77 TA11
13
LT1575/LT1577
U
TYPICAL APPLICATIONS N
Setting Output Voltage with the Adjustable LT1575
Using “Sense-Less” Current Limit
V
R3
10Ω
OUT
SHDN IPOS
V
CC
R2
C1
10µF
C
T
FB
INEG
GATE
R1
Q1
V
= 1.21V(1 + R2/R1)
OUT
V
OUT
1575 TA04
1575 TA03
Setting Current Limit
Setting Current Limit with Foldback Limiting
IPOS
V
IPOS
INEG
V
CC
CC
R5
R
*
R4
SENSE
10Ω
INEG
GATE
D1
Q2
1N4148
D2
1N4148
Q3
GATE
V
OUT
R6
1.2k
*I
= 50mV/R
LIM
SENSE
V
OUT
R
= DISCRETE SHUNT RESISTOR OR
= KELVIN-SENSED PC BOARD TRACE
SENSE
SENSE
1575 TA06
R
ACTIVATING CURRENT LIMIT ALSO ACTIVATES
THE SHDN PIN TIMER
1575 TA05
Shutdown Time-Out with Reset
Basic Thermal Shutdown
SHDN
5V
RESET
0V TO 5V
Q1
VN2222L
RT1
10k
R1
100k
C1*
NTC
RT1 = DALE NTHS-1206N02
THERMALLY MOUNT RT1
IN CLOSE PROXIMITY
TO THE EXTERNAL
SHDN
*C1 = 15µA(t)/1.11V
t = SHUTDOWN LATCHOFF TIME
R4
549Ω
1575 TA07
N-CHANNEL MOSFET
1575 TA08
Shutdown Time-Out with Reset
Overvoltage Protection
R2
100k
V
SHDN
C2*
OUT
RESET
0V TO 5V
Q2
2N3904
R6
R3
100k
SHDN
R5
*C2 = 15µA(t)/1.11V
t = SHUTDOWN LATCH-OFF TIME
1575 TA10
1575 TA09
V
V
= 1.21(R6/R5) + 5µA(R6)
= 1.11(R6/R5) – 15µA(R6)
OUT(uth)
OUT(lth)
14
LT1575/LT1577
U
TYPICAL APPLICATIONS N
Pentium® II Processor GTL+ Power Supply
V
TT
1.5V
V
IN
3.3V
12V
+
C1
220µF
6.3V
R4
R6
75Ω
R8
100Ω
R10
R11
R9
100Ω
75Ω
100Ω 100Ω
V
REF
V
REF
R7
LT1575-1.5
C6
0.1µF
C7
0.1µF
1
2
3
4
8
R5
150Ω
R1
0.005Ω
RESET
SHDN
IPOS
INEG
150Ω
7
6
5
V
IN
C2
0.22µF
C3
1µF
R2
3.9Ω
GND
OUT
GATE
COMP
RX
TX
RX
TX
Q1
IRFZ24
Q3
Q5
Q2
Q4
C8 TO C23
1µF
CERAMIC
0805
CASE
R3
C4
10pF
4.99k
C5
1000pF
RX
TX
RX
TX
•
•
•
NOTE: LTC RECOMMENDS CENTRALLY
LOCATING THE LT1575-1.5 OUTPUT
TO MINIMIZE V DISTRIBUTION
TT
142 TOTAL SIGNAL LINES
DROPS AND USING SEPARATE V
REF
1575/77 TA12
GENERATORS AT EACH BUS END
Generating 12V Gate Drive from a 5V Power Supply
D1
1N5818
LT1262
L1
33µH
1
2
3
4
8
7
6
5
–
+
–
+
C1
C1
C2
C2
SHDN
GND
V
12V
25mA
C1
0.22µF
CC
C4
4.75V TO 5.5V
+
4.7µF
2
12V
V
OUT
SW
C2
25mA
C3
0.22µF
+
C5
LT1109CZ-12
V
V
CC
+
4.7µF
3
100µF
V
CC
OUT
10V
4.75V TO 5.5V
+
C6
GND
1
10µF
25V
D2
BAT85
V
CC
4.75V TO 5.5V
C9
0.22µF
D3
BAT85
D4
BAT85
D5
BAT85
74HC14
12V
25mA
+
C7
R1
2k
×5
100µF
10V
D6
BAT85
C11
0.22µF
C12
0.22µF
C8
390pF
C10
0.22µF
1575/77 TA13
Pentium is a registered trademark of Intel Corporation.
15
LT1575/LT1577
TYPICAL APPLICATIONS N
U
12V to 3.3V/9A (14A Peak) Hybrid Regulator
LT1575
1
2
3
4
8
7
6
5
SHDN
IPOS
INEG
V
IN
12V
Q1
IRLZ44
GND
OUT
GATE
COMP
C6
0.1µF
C21, 10pF
C1, 470pF
R9
2k
12V
C22, 1000pF
R1
C14
150µF
16V
+
C11
150µF
16V
+
C12
150µF
16V
+
C13
150µF
16V
+
C17
1µF
C15
1µF
2.1k, 1%
C16
1µF
V
CORE
R2
1.21k
1%
3.3V
13
V
1µF
IN
9
1
2
3
4
5
6
16
14
15
12
11
8
X7R
Q2
Q3
EXTV
TG
CC
CERAMIC
0805 CASE
×40
L1
C
OSC
SW
R6
4µH
C3, 0.1µF
C8, 68pF
C7, 0.1µF
0.0075Ω
RUN/SS
BOOST
LTC1435
+
+
C18
C20
I
INTV
C23
1µF
TH
CC
R3
100
R4
100
1000µF 1000µF
C10, 1000pF
D1, CMDSH-3
10V
10V
SFB
BG
C9
1500pF
+
C19
1000µF
10V
SGND
S
+
C2, 1000pF
7
–
V
OS
S
R5
16.5k
PGND
10
D2
MBRS330T3
R7
35.7k
+
C5
0.1µF
C4, 4.7µF
1575/77 TA16
L1
= COILTRONICS CTX02-13199
R8
15K
Q2, Q3 = SILICONIX SUD50N03-10
Transient Response to a 10A Load Step
1575/77 TA17
200µs/DIV
16
LT1575/LT1577
U
TYPICAL APPLICATIONS N
3.3V to 2.8V ±100mV at 5.7A with Sense-Less Current Limit and Timer Latchoff
INPUT
3.3V
+
+
C2
330µF
6.3V
C1
330µF
6.3V
R2
10Ω
FAULT RESET
C7
10µF
LT1575-2.8
12V
1
2
3
4
8
7
6
5
SHDN
IPOS
INEG
RTN
V
IN
Q1
IRL3303
GND
OUT
GATE
COMP
C3
680pF
V
CORE
R1
C6
0.1µF
2.8V
4.7k
C5
22pF
+
C8 TO C31*
C4
1000pF
1µF
1575/77 TA14
*X7R CERAMIC 0805 CASE
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
8
7
6
5
4
0.255 ± 0.015*
(6.477 ± 0.381)
1
2
3
0.130 ± 0.005
0.300 – 0.325
0.045 – 0.065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
0.125
0.020
(0.508)
MIN
(3.175)
MIN
+0.035
0.325
–0.015
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
+0.889
8.255
(
)
N8 1197
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
17
LT1575/LT1577
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
5
8
6
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.053 – 0.069
3
4
2
0.010 – 0.020
(0.254 – 0.508)
× 45°
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 0996
18
LT1575/LT1577
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
16
15
14
13
12
11
10
9
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
5
7
8
1
2
3
4
6
0.010 – 0.020
(0.254 – 0.508)
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0° – 8° TYP
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
0.016 – 0.050
0.406 – 1.270
S16 0695
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT1575/LT1577
U
TYPICAL APPLICATION
LT1577 Split Plane System
FAULT RESET
INPUT
5V
C1
C2
330µF
6.3V
+
+
330µF
6.3V
1/2 LT1577
1/2 LT1577
1
16
15
14
13
5
6
7
8
12
11
10
9
SHDN1 IPOS1
SHDN2 IPOS2
2
V
INEG1
GATE1
V
INEG2
GATE2
12V
IN1
IN2
3
4
Q1
IRFZ24
Q2
IRFZ24
GND1
GND2
C3
0.33µF
R1
R5
3.9Ω
OUT-3.3 COMP1
OUT-2.8 COMP2
3.9Ω
V
V
CORE
I/O
R2
R6
7.5k
2.8V
3.3V
3.9k
C5
10pF
C7
10pF
C21 TO
C44*
1µF
C9 TO
C20*
1µF
C4
1µF
C6
1500pF
C8
1000pF
*X7R CERAMIC 0805 CASE
1575/77 TA15
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1266
Current Mode, Step-Up/Down Switching Regulator Controller
Synchronous N- or P-Channel FETs, Comparator/Low
Battery Detector
LTC1392
Micropower Temperature, Power Supply and Differential
Voltage Monitor
Temperature to Bits Control
LTC1430
LTC1435
High Power Step-Down Switching Regulator Controller
Voltage Mode, 5V to 3.xxV at >10A
High Efficiency, Low Noise Synchronous Step-Down
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Current Mode with Wide Input Voltage Range
LTC1553
LTC1553L
LT1573
Digitally Controlled Synchronous Switching Regulator Controller
Digitally Controlled Synchronous Switching Regulator Controller
Low Dropout Regulator Driver
Controller for Pentium II Processor, Buck Conversion
from 5V or 12V Main Power
Controller for Pentium II Processor, Buck Conversion
from 5V Main Power
Drives Low Cost PNP Transistor for High Power,
Low Dropout Applications
LT1580
7A, Very Low Dropout Linear Regulator
0.54V Dropout at 7A, Fixed 2.5V
GTL+ Regulator
and Adjustable
OUT
LT1585-1.5
Fixed 1.5V, 5A Low Dropout Fast Response Regulator
15757f LT/TP 0598 4K • PRINTED IN THE USA
LINEAR TECHNOLOGY CORPORATION 1996
20 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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