LT1640AH_技术文档

LT4250L/LT4250H

Negative 48V

Hot Swap Controller

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FEATURES

DESCRIPTIO

TheLT^®4250L/LT4250Hare8-pin,negative48VHotSwap^TM

controllers that allow a board to be safely inserted and

removedfromalivebackplane. Inrushcurrentislimitedto

aprogrammablevaluebycontrollingthegatevoltageofan

external N-channel pass transistor. The pass transistor is

turned off if the input voltage is less than the program-

mable undervoltage threshold or greater than the over-

voltage threshold. A programmable current limit protects

the system against shorts. After a 500µs timeout the

current limit activates the electronic circuit breaker. The

PWRGD (LT4250L) or PWRGD (LT4250H) signal can be

used to directly enable a power module. The LT4250L is

designed for modules with a low enable input and the

LT4250H for modules with a high enable input.

■

Allows Safe Board Insertion and Removal

from a Live –48V Backplane

■

Circuit Breaker Immunity to Voltage Steps and

Current Spikes

■

Programmable Inrush and

Short-Circuit Current Limits

■

Pin Compatible with LT1640L/LT1640H

■

Operates from –20V to –80V

■

Programmable Overvoltage Protection

■

Programmable Undervoltage Lockout

■

Power Good Control Output

■

^{Bell-Core Compa}U^{tible ON/OFF Threshold}

APPLICATIO S

■

The LT4250L/LT4250H are available in 8-pin PDIP and SO

packages.

Central Office Switching

■

–48V Distributed Power Systems

■

, LTC and LT are registered trademarks of Linear Technology Corporation.

Negative Power Supply Control

Hot Swap is a trademark of Linear Technology Corporation.

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TYPICAL APPLICATIO

–48V RTN

(SHORT PIN)

–48V RTN

R4^†

Voltage Step On Input Supply

8

549k

1%

V

DD

3

2

UV =

UV

OV

R5^†

6.49k

1%

38.5V

1

LT4250L

PWRGD

UV

RELEASE

AT 43V

R6^†

10k

1%

OV =

71V

V

SENSE

5

GATE

6

DRAIN

7

EE

V

AND

EE

DRAIN

20V/DIV

4

R3^†

1k, 5%

*

0.1µF

10V

C1^†

470nF

25V

R2

10Ω

5%

C2^†

15nF

100V

–48V

INPUT 1

R1^†

0.02Ω

5%

I

(Q1)

D

5A/DIV

2

Q1

IRF530

ON/OFF

1

9

8

+

–

+

–48V

5V

V

500µs/DIV

IN

OUT

SENSE

INPUT 2

C3

0.1µF

100V

C4

+

C5

+

7

6

5

* DIODES INC. SMAT70A

100µF

TRIM

100µF

16V

^†THESE COMPONENTS ARE APPLICATION

SPECIFIC AND MUST BE SELECTED BASED

UPON OPERATING CONDITIONS AND DESIRED

PERFORMANCE. SEE APPLICATIONS

INFORMATION.

100V

–

SENSE

4

–

V

IN

OUT

4250 TA01

LUCENT

JW050A1-E

4250lhf

1

LT4250L/LT4250H

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ABSOLUTE MAXIMUM RATINGS

(Note 1), All Voltages Referred to V_EE

Supply Voltage (V_DD– V_EE) .................... –0.3V to 100V

PWRGD, PWRGD Pins ........................... –0.3V to 100V

SENSE, GATE Pins.................................... –0.3V to 20V

UV, OV Pins .............................................. –0.3V to 60V

DRAIN Pin .................................................. –2V to 100V

Maximum Junction Temperature ......................... 125°C

Operating Temperature Range

LT4250LC/LT4250HC ............................. 0°C to 70°C

LT4250LI/LT4250HI .......................... –40°C to 85°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

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/O

PACKAGE RDER I FOR ATIO

ORDER PART

NUMBER

TOP VIEW

PWRGD

OV

1

2

3

4

8

7

6

5

V

DD

PWRGD

OV

1

2

3

4

8

7

6

5

V

DD

LT4250LCN8

LT4250LCS8

LT4250LIN8

LT4250LIS8

LT4250HCN8

LT4250HCS8

LT4250HIN8

LT4250HIS8

DRAIN

GATE

DRAIN

GATE

UV

V

SENSE

V

SENSE

EE

N8 PACKAGE

8-LEAD PDIP

S8 PACKAGE

N8 PACKAGE

8-LEAD PDIP

S8 PACKAGE

8-LEAD PLASTIC SO

S8 PART MARKING

T_JMAX= 125°C, θ_JA= 120°C/W (N8)

_JMAX= 125°C, θ_JA= 150°C/W (S8)

T_JMAX= 125°C, θ_JA= 120°C/W (N8)

T_JMAX= 125°C, θ_JA= 150°C/W (S8)

T

4250L

4250LI

4250H

4250HI

Consult LTC Marketing for parts specified with wider operating temperature ranges.

The ● denotes the specifications which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T_A= 25°C. (Note 2), V_DD= 48V, V_EE= 0V unless otherwise noted.

SYMBOL PARAMETER

DC

CONDITIONS

MIN

TYP

MAX

UNITS

V

Supply Voltage Operating Range

Supply Current

●

20

80

5

V

mA

V

DD

I

UV = 3V, OV = V , SENSE = V

EE

1.6

15.4

50

DD

EE

V

Undervoltage Lockout

UVL

CL

Current Limit Trip Voltage

GATE Pin Pull-Up Current

GATE Pin Pull-Down Current

SENSE Pin Current

V

= (V

– V )

EE

40

–30

24

60

–60

70

mV

µA

mA

µA

V

CL

SENSE

I

Gate Drive On, V

Gate Drive OFF

= V

EE

–45

PU

GATE

50

PD

V

= 50mV

SENSE

–20

SENSE

∆V

External Gate Drive

(V

GATE

– V ), 20V ≤ V ≤ 80V

●

10

13.5

1.255

1.125

130

18

GATE

EE

DD

V

UV Pin High Threshold Voltage

UV Pin Low Threshold Voltage

UV Pin Hysteresis

UV Increasing

UV Decreasing

1.240

1.105

1.270

1.145

V

UVH

V

UVL

UVHY

INUV

mV

µA

V

I

UV Pin Input Current

V

= V

●

–0.02

1.255

1.235

–0.5

1.275

1.255

UV

EE

V

OV Pin High Threshold Voltage

OV Pin Low Threshold Voltage

OV Increasing

OV Decreasing

1.235

1.210

OVH

OVL

V

4250lhf

2

LT4250L/LT4250H

ELECTRICAL CHARACTERISTICS ^The● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 2), V_DD= 48V, V_EE= 0V unless otherwise noted.

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

20

MAX

UNITS

mV

µA

V

OV Pin Hysteresis

OVHY

INOV

I

OV Pin Input Current

DRAIN Low Threshold

GATE High Threshold

Drain Input Bias Current

PWRGD Output Low Voltage

V

= V

●

–0.03

1.6

–0.5

2.3

OV

EE

V

– V , DRAIN Decreasing

1.1

10

V

DL

DRAIN

EE

∆V

GATE

– V Decreasing

GATE

1.3

V

GH

I

V

= 48V

●

80

500

µA

DRAIN

V

PWRGD (LT4250L), (V

– V ) < V

OL

DRAIN

EE

DL

I

= 1mA

= 5mA

●

0.48

1.2

0.8

3.0

V

OUT

PWRGD Output Low Voltage

(PWRGD – DRAIN)

PWRGD (LT4250H), V

= 1mA

= 5V

DRAIN

I

●

0.75

1.0

V

OUT

I

Output Leakage

PWRGD (LT4250L), V

PWRGD (LT4250H), V

= 48V, V

= 80V

●

0.05

10

µA

OH

DRAIN

PWRGD

= 0V, V

PWRGD

AC

t

OV High to GATE Low

UV Low to GATE Low

Figures 1a, 2

Figures 1a, 3

Figures 1a, 2

Figures 1a, 3

Figures 1a, 4a

Figures 1b, 4b

1.7

1.5

5.5

6.5

1

µs

PHLOV

PHLUV

PLHOV

PLHUV

PHLSENSE

PHLCB

PHLDL

OV Low to GATE High

UV High to GATE High

SENSE High to Gate Low

Current Limit to GATE Low

DRAIN Low to PWRGD Low

DRAIN Low to (PWRGD – DRAIN) High (LT4250H) Figures 1a, 5a

GATE High to PWRGD Low (LT4250L) Figures 1a, 5b

GATE High to (PWRGD – DRAIN) High (LT4250H) Figures 1a, 5b

3

500

(LT4250L) Figures 1a, 5a

1

µs

t

1.5

µs

PHLGH

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: All currents into device pins are positive; all currents out of device

pins are negative. All voltages are referenced to V unless otherwise

EE

specified.

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TYPICAL PERFOR A CE CHARACTERISTICS

Supply Current vs Supply Voltage

Supply Current vs Temperature

Gate Voltage vs Supply Voltage

1.6

1.5

1.4

1.3

1.2

1.1

1.0

15

14

13

12

11

10

9

1.8

1.7

1.6

1.5

T = 25°C

A

T

A

= 25°C

V

= 48V

DD

1.4

1.3

1.2

1.1

0

8

7

6

20

40

SUPPLY VOLTAGE (V)

80

0

100

60

–50 –25

0

25

50

75

100

0

80

100

20

40

60

TEMPERATURE (°C)

SUPPLY VOLTAGE (V)

1640 G01

1640 G02

1640 G03

4250lhf

3

LT4250L/LT4250H

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TYPICAL PERFOR A CE CHARACTERISTICS

Current Limit Trip Voltage

Gate Pull-Up Current

vs Temperature

Gate Voltage vs Temperature

vs Temperature

15.0

14.5

48

47

46

45

44

43

42

41

40

55

54

V

= 48V

DD

V

= 0V

GATE

53

14.0

13.5

52

51

50

49

13.0

12.5

12.0

48

–50 –25

0

25

50

75

100

–50

0

25

50

75

100

–25

75

–50

–25

0

25

50

100

TEMPERATURE (°C)

1640 G04

1640 G05

1640 G06

Gate Pull-Down Current

vs Temperature

PWRGD Output Impedance

vs Temperature (LT4250H)

PWRGD Output Low Voltage

vs Temperature (LT4250L)

8

7

55

52

49

0.5

0.4

0.3

0.2

0.1

0

V

– V > 2.4V

EE

V

= 2V

I

= 1mA

DRAIN

GATE

OUT

6

5

46

43

40

4

3

2

–50 –25

0

25

50

75

100

–50 –25

0

25

50

75

100

–50 –25

0

25

50

75

100

TEMPERATURE (°C)

1640 G09

1640 G07

1640 G08

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PIN FUNCTIONS

PWRGD/PWRGD(Pin1):PowerGoodOutputPin.Thispin

willlatchapowergoodindicationwhenV_DRAINiswithinV_DL

of V_EEand V_GATEis within V_GHof ∆V_GATE. This pin can be

connected directly to the enable pin of a power module.

ThisconditionislatcheduntiltheGATEpinisturnedoffvia

the UV, OV, UVLO or the electronic circuit breaker.

When the DRAIN pin of the LT4250H is above V_EEby more

than V_DLor V_GATEis more than V_GHfrom ∆V_GATE, the

PWRGD pin will sink current to the DRAIN pin which pulls

the module’s enable pin low, forcing it off. When V_DRAIN

drops below V_DLand V_GATErises above V_GH, the PWRGD

sink current is turned off, allowing the module’s pull-up

current to pull the enable pin high and turn on the module.

ThisconditionislatcheduntiltheGATEpinisturnedoffvia

the UV, OV, UVLO or the electronic circuit breaker.

4250lhf

When the DRAIN pin of the LT4250L is above V_EEby more

than V_DLor V_GATEis more than V_GHfrom ∆V_GATE, the

PWRGD pin will be high impedance, allowing the pull-up

current of the module’s enable pin to pull the pin high and

turn the module off. When V_DRAINdrops below V_DLand

V_GATErises above V_GH, the PWRGD pin sinks current to

V_EE, pulling the enable pin low and turning on the module.

4

LT4250L/LT4250H

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PIN FUNCTIONS

OV (Pin 2): Analog Overvoltage Input. When OV is pulled If the current limit value is set to twice the normal

above the 1.255V threshold, an overvoltage condition is operating current, only 25mV is dropped across the

detected and the GATE pin will be immediately pulled low. sense resistor during normal operation. To disable the

The GATE pin will remain low until OV drops below the current limit feature, V_EEand SENSE can be shorted

1.235V threshold.

together.

UV (Pin 3): Analog Undervoltage Input. When UV is GATE (Pin 6): Gate Drive Output for the External

pulled below the 1.125V threshold, an undervoltage N-Channel MOSFET. The GATE pin will go high when the

condition is detected and the GATE pin will be immedi- following start-up conditions are met: the UV pin is high,

ately pulled low. The GATE pin will remain low until UV the OV pin is low, (V_SENSE– V_EE) < 50mV and the V_DDpin

rises above the 1.255 threshold.

is greater than V_UVLOH. The GATE pin is pulled high by a

45µA current source and pulled low with a 50mA current

source. During current limit the GATE pin is pulled low

using a 100mA current source.

The UV pin is also used to reset the electronic circuit

breaker. If the UV pin is cycled low and high following the

trip of the circuit breaker, the circuit breaker is reset and

a normal power-up sequence will occur. The response DRAIN (Pin 7): Analog Drain Sense Input. Connect this

timeforthispinis1.5µs. Addanexternalcapacitortothis pintothedrainoftheexternalN-channelMOSFETandthe

pin for additional filtering.

V^–pin of the power module. When the DRAIN pin is

below V_DL, the PWRGD/PWRGD pin will latch to indicate

the switch is on.

V_EE(Pin 4): Negative Supply Voltage Input. Connect to

the lower potential of the power supply.

V_DD(Pin 8): Positive Supply Voltage Input. Connect this

pin to the higher potential of the power supply inputs and

the V⁺pin of the power module. An undervoltage lockout

circuit disables the chip until the V_DDpin is greater than

the 16V V_UVLOHthreshold.

SENSE (Pin 5): Circuit Breaker Sense Pin. With a sense

resistor placed in the supply path between V_EEand

SENSE, the overcurrent condition will pull down the

GATE pin and regulate the voltage across the resistor to

be 50mV. If the overcurrent condition exists for more

than500µstheelectroniccircuitbreakerwilltripandturn

off the external MOSFET.

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BLOCK DIAGRA

V

DD

–

UV

V

AND

CC

UVLO

REFERENCE

GENERATOR

REF

+

OUTPUT

DRIVE

PWRGD/PWRGD

REF

–

LOGIC

+

50mV

OV

–

+

–

500µs

DELAY

GATE

DRIVER

+

–

+

–

+

V

DL

V

GH

–

V

∆V

GATE

EE

4250 BD

DRAIN

GATE

V

EE

SENSE

4250lhf

5

LT4250L/LT4250H

R

5k

+

V

20V

PWRGD/PWRGD

OV

V

DD

–

PWRGD/PWRGD

OV

V

DD

5V

+

–

48V

+

48V

–

DRAIN

V

OV

V

DRAIN

LT4250L/LT4250H

10k

10Ω

UV

GATE

IRF530

UV

GATE

V

UV

0.1µF

V

UV

V

SENSE

V

SENSE

EE

SENSE

10Ω

1640 F01a

4250 F01b

Figure 1a. Test Circuit 1

Figure 1b. Test Circuit 2

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TIMING DIAGRAMS

2V

1.255V

OV

2V

0V

1.125V

1.235V

1.255V

UV

0V

t

PLHOV

t

PHLOV

PHLUV

PLHUV

GATE

1V

4250 F02

4250 F03

Figure 2. OV to GATE Timing

Figure 3. UV to GATE Timing

100mV

SENSE

60mV

UV

V

EE

t

PHLCB

t

PHLSENSE

1V

GATE

1V

4250 F04b

4250 F04a

Figure 4b. Active Current Limit Timeout

Figure 4a. SENSE to GATE Timing

1.4V

∆V

– V

= 0

GATE

1.4V

GATE

DRAIN

V

EE

t

PHLGH

t

PHLDL

1V

PWRGD

DRAIN

1V

V

EE

V

EE

1.4V

∆V

– V

= 0

GATE

1.4V

V

EE

t

PHLGH

1V

t

PHLDL

PWRGD

1V

4250 F05a

V

– V

= 0

DRAIN

4250 F05b

PWRGD

V

– V

= 0V

DRAIN

PWRGD

Figure 5a. DRAIN to PWRGD/PWRGD Timing

Figure 5b. GATE to PWRGD/PWRGD Timing

4250lhf

6

LT4250L/LT4250H

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APPLICATIONS INFORMATION

Hot Circuit Insertion

where C_Lis the total load capacitance = C3 + C4 + module

input capacitance.

Whencircuitboardsareinsertedintoalive –48Vbackplane,

the bypass capacitors at the input of the board’s power

module or switching power supply can draw huge tran-

sient currents as they charge up. The transient currents

can cause permanent damage to the board’s components

and cause glitches on the system power supply.

Capacitor C1 and resistor R3 prevent Q1 from momen-

tarily turning on when the power pins first make contact.

Without C1 and R3, capacitor C2 would pull the gate of Q1

uptoavoltageroughlyequaltoV_EE•C2/C_GS(Q1)beforethe

LT4250 could power up and actively pull the gate low. By

placing capacitor C1 in parallel with the gate capacitance

of Q1 and isolating them from C2 using resistor R3 the

problem is solved. The value of C1 is given by:

The LT4250 is designed to turn on a board’s supply

voltage in a controlled manner, allowing the board to be

safely inserted or removed from a live backplane. The chip

also provides undervoltage, overvoltage and overcurrent

protection while keeping the power module off until its

input voltage is stable and within tolerance.

V

_INMAX− V_TH

C1=

• C2 + C_GD

(

)

V_TH

C1 35 • C2 for V_INMAX= 72V

Power Supply Ramping

where V_THis the MOSFET’s minimum gate threshold and

V_INMAXis the maximum operating input voltage.

The input to the power module on a board is controlled by

placing an external N-channel pass transistor (Q1) in the

power path (Figure 6a, all waveforms are with respect to

the V_EEpin of the LT4250). R1 provides current fault

detection and R2 prevents high frequency oscillations.

Resistors R4, R5 and R6 provide undervoltage and over-

voltage sensing. By ramping the gate of Q1 up at a slow

rate, the inrush current charging load capacitors C3 and

C4 can be limited to a safe value when the board makes

connection.

R3 should not exceed a value that produces an

R3 • C2 time-constant of 150µs. A 1k value for R3 will

ensure this for C2 values up to 150nF.

The waveforms are shown in Figure 6b. When the power

pins make contact, they bounce several times. While the

contactsarebouncing,theLT4250sensesanundervoltage

condition and the GATE is immediately pulled low when

the power pins are disconnected.

Resistor R3 and capacitor C2 act as a feedback network to

accuratelycontroltheinrushcurrent.TheC2capacitorcan

be calculated with the following equation:

Once the power pins stop bouncing, the GATE pin starts to

ramp up. When Q1 turns on, the GATE voltage is held

constant by the feedback network of R3 and C2. When the

DRAIN voltage has finished ramping, the GATE pin then

ramps to its final value.

C2 = (45µA • C_L)/I_INRUSH

–48V RTN

(SHORT PIN)

–48V RTN

MODULE

INRUSH

C3

TURN-ON

CURRENT

0.1µF

VICOR

MODULE

TURN-ON

8

100V

R4

549k

1%

500mA/DIV

VI-J30-CY

+

V

C4

+

–

DD

5V

C5

V

OUT

IN

100µF

3

2

UV = 38.5V

OV = 71V

UV

OV

GATE –V

100V

EE

+

R5

6.49k

1%

1

10V/DIV

LT4250H

PWRGD

DRAIN

GATE IN

–

100µF

16V

V

OUT

R6

10k

1%

IN

V

EE

SENSE

5

GATE

6

DRAIN

50V/DIV

R3

4

7

1k, 5%

V

EE

R2

C1

50V/DIV

10Ω

5%

C2

15nF

100V

470nF

25V

CONTACT

*

R1

0.02Ω

BOUNCE

3

4

5%

4250 F06a

–48V

25ms/DIV

1

2

Q1

IRF530

* DIODES INC. SMAT70A

4250 F06b

Figure 6b. Inrush Control Waveforms

Figure 6a. Inrush Control Circuitry

4250lhf

7

LT4250L/LT4250H

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APPLICATIONS INFORMATION

Current Limit/Electronic Circuit Breaker

The LT4250 guards against voltage steps on the input

supply. A positive voltage step (increasing in magnitude)

on the input supply causes an inrush current that is

proportional to the voltage slew rate I = C_L• ∆V/∆T. If the

inrush exceeds 50mV/R_SENSE, the current limit will acti-

vate as shown in Figure 8. The GATE pin pulls low, limiting

the current to 50mV/R_SENSE. At this level the MOSFET

drain will not follow the source as the input voltage rapidly

changes, but instead remains at the voltage stored on the

load capacitance. The load capacitance begins to charge

at a current of 50mV/R_SENSE, but not for long. As the load

capacitance charges, C2 pushes back on the gate and

limits the MOSFET current in a manner identical to the

initialstart-upconditionwhichislessthantheshortcircuit

limiting value of 50mV/R_SENSE. Thus the circuit breaker

does not trip. To ensure correct operation under input

voltage step conditions, R_SENSEmust be chosen to pro-

vide a current limit value greater than the sum of the load

current and the dynamic current in the load capacitance.

The LT4250 features a current limit function that protects

against short circuits or excessive supply currents. If the

current limit is active for more than 500µs the electronic

circuit breaker will trip. By placing a sense resistor

between the V_EEand SENSE pin, the current limit will be

activated whenever the voltage across the sense resistor

is greater than 50mV.

Note that the current limit threshold should be set suffi-

ciently high to account for the sum of the load current and

the inrush current. The maximum value of the inrush

current is given by:

40mV

R_SENSE

I_INRUSH≤ 0.8•

– I_LOAD,

where the 0.8 factor is used as a worst case margin

combined with the minimum trip voltage (40mV).

For C2 values less than 10nF a positive voltage step on the

input supply can result in the Q1 turning off momentarily

which can shut down the output. By adding an additional

resistor and diode, Q1 remains on during the voltage step.

This is shown as D1 and R7 in Figure 9. The purpose of D1

is to shunt current around R7 when the power pins first

makecontactandallowC1toholdtheGATElow. Thevalue

of R7 should be sized to generate an R7 • C1 time constant

of 33µs.

In the case of a short circuit, the current limit circuitry

activates and immediately pulls the GATE low, servos the

SENSE voltage to 50mV, and starts a 500µs timer. The

MOSFETcurrentislimitedto50mV/R_SENSE(seeFigure7).

Iftheshortcircuitpersistsformorethan500µs, thecircuit

breaker trips and pulls the GATE pin low, shutting off the

MOSFET. The circuit breaker is reset by pulling UV low, or

by cycling power to the part. If the short circuit clears

before the 500µs timing interval the current limit will

deactivate and release the GATE.

Under some conditions, a short circuit at the output can

cause the input supply to dip below the UV threshold. The

LT4250 turns off once and then turns on until the elec-

tronic circuit breaker is tripped. This can be minimized by

adding a deglitching delay to the UV pin with a capacitor

from UV to V_EE. This capacitor forms an RC time constant

with the resistors at UV, allowing the input supply to

recover before the UV pin resets the circuit breaker.

DRAIN

50V/DIV

GATE

10V/DIV

I

(Q1)

D

5A/DIV

1ms/DIV

Figure 7. Short-Circuit Protection Waveforms

4250lhf

8

LT4250L/LT4250H

U

W U U

APPLICATIONS INFORMATION

A circuit that automatically resets the circuit breaker after

a current fault is shown in Figure 10. Transistors Q2 and

Q3 along with R7, R8, C4 and D1 form a programmable

one-shot circuit. Before a short occurs, the GATE pin is

pulled high and Q3 is turned on, pulling node 2 to V_EE.

Resistor R8 turns off Q2. When a short occurs, the GATE

pin is pulled low and Q3 turns off. Node 2 starts to charge

C4 and Q2 turns on, pulling the UV pin low and resetting

thecircuitbreaker.AssoonasC4isfullycharged,R8turns

off Q2, UV goes high and the GATE starts to ramp up. Q3

turns back on and quickly pulls node 2 back to V_EE. Diode

D1 clamps node 3 one diode drop below V_EE. The duty

cycle is set to 10% to prevent Q1 from overheating.

–48V RTN

(SHORT PIN)

–48V RTN

8

R4

549k

1%

C3

0.1µF

100V

V

DD

3

2

UV

OV

R5

6.49k

1%

1

LT4250H

PWRGD

+

C4

22µF

100V

V

AND

EE

DRAIN

20V/DIV

R6

10k

1%

V

SENSE

5

GATE

6

DRAIN

7

EE

R3

1k

5%

4

I

(Q1)

D

R7

5A/DIV

C2

3.3nF

100V

*

220Ω

R2

D1

5%

10Ω

BAT85

5%

R1

0.02Ω

5%

C1

3

4

150nF

25V

500µs/DIV

–48V

* DIODES INC. SMAT70A

4250 F09

1

2

Q1

IRF530

Figure 8. Voltage Step on

Input Supply Waveforms

Figure 9. Circuit for Input Steps with Small C2 (<10nF)

–48V RTN

(SHORT PIN)

–48V RTN

8

R7

1M

5%

R6

549k

1%

R4

549k

1%

V

DD

2

3

2

UV

OV

C4

1µF

100V

1

LT4250L

PWRGD

C3

100µF

100V

+

R9

R5

V

EE

SENSE

5

GATE

6

DRAIN

7

10k 16.5k

Q2

1%

4

2N2222

R3

1k, 5%

3

Q3

ZVN3310

R2

10Ω

5%

C1

470nF

25V

*

C2

15nF

100V

R8

510k

5%

R1

0.02Ω

5%

D1

1N4148

3

4

–48V

4250 F10a

1

2

Q1

IRF530

* DIODES INC. SMAT70A

NODE 2

50V/DIV

GATE

2V/DIV

1s/DIV

Figure 10. Automatic Restart After Current Fault

4250lhf

9

LT4250L/LT4250H

U

W U U

APPLICATIONS INFORMATION

Undervoltage and Overvoltage Detection

internal transistor Q3 is turned off and I₁and Q2 clamp the

PWRGD pin one SAT drop (≈0.3V) above the DRAIN pin.

Transistor Q2 sinks the module’s pull-up current and the

module turns off.

The UV (Pin 3) and OV (Pin 2) pins can be used to detect

undervoltage and overvoltage conditions at the power

supply input. The UV and OV pins are internally connected

to analog comparators with 130mV and 20mV of hyster- When the DRAIN voltage drops below V_DLand the GATE

esisrespectively.WhentheUVpinfallsbelowitsthreshold voltage is high, Q3 will turn on, shorting the bottom of I₁

or the OV pin rises above its threshold, the GATE pin is to DRAIN and turning Q2 off. The pull-up current in the

immediatelypulledlow. TheGATEpinwillbeheldlowuntil module pulls the PWRGD pin high and enables the

UV is high and OV is low.

module.

The undervoltage and overvoltage trip voltages can be When the DRAIN voltage of the LT4250L is high with

programmed using a three resistor divider as shown in respecttoV_EEortheGATEvoltageislow, theinternalpull-

Figure 11. With R4 = 549k, R5 = 6.49k and R6 = 10K, the down transistor Q2 is off and the PWRGD pin is in a high

undervoltage threshold is set to 38.5V (with a 43V release impedance state (Figure 13). The PWRGD pin will be

from undervoltage) and the overvoltage threshold is set to pulledhighbythemodule’sinternalpull-upcurrentsource,

71V. The resistor divider will also gain up the hysteresis turning the module off. When the DRAIN voltage drops

at the UV pin and OV pin to 4.5V and 1.2V at the input belowV_DLandtheGATEvoltageishigh,Q2willturnonand

respectively.

the PWRGD pin will pull low, enabling the module.

The PWRGD signal can also be used to turn on an LED or

optoisolator to indicate that the power is good as shown

in Figure 14.

PWRGD/PWRGD Output

The PWRGD/PWRGD output can be used to directly en-

able a power module when the input voltage to the module

is within tolerance. The LT4250L has a PWRGD output for Gate Pin Voltage Regulation

modules with an active low enable input, and the LT4250H

has a PWRGD output for modules with an active high

enable input.

When the supply voltage to the chip is more than 20V, the

GATEpinvoltageisregulatedat13.5VaboveV_EE. Thegate

voltage will be no greater than 18V for supply voltages up

When the DRAIN voltage of the LT4250H is high with to 80V.

respect to V_EE(Figure 12) or the GATE voltage is low, the

ACTIVE HIGH

ENABLE MODULE

–48V RTN

(SHORT PIN)

+

–48V RTN

V

IN

OUT

8

(SHORT PIN)

V

DD

LT4250H

PWRGD

Q2

1

–48V RTN

R4

I

1

+

–

GATE

+

ON/OFF

3

2

8

UV

OV

C3

R4

R5

R6

V

DD

V

GH

R5

R6

Q3

EE

3

2

–

R4 + R5+ R6

R5 + R6

+

V

= 1.255

UV

OV

+

–

(

)

V

–

DL

V

OUT

V

LT4250L/LT4250H

OV

IN

+

–

7

DRAIN

R3

R4 + R5+ R6

R6

∆V

V

EE

SENSE

GATE

6

GATE

V

EE

4

5

4

*

–48V

C2

C1

4250 F11

R2

3

4

R1

4250 F12

–48V

1

2

Q1

* DIODES INC. SMAT70A

Figure 11. Undervoltage and Overvoltage Sensing

Figure 12. Active High Enable Module

4250lhf

10

LT4250L/LT4250H

W U U

U

APPLICATIO S I FOR ATIO

–48V RTN

(SHORT PIN)

ACTIVE LOW

ENABLE MODULE

–48V RTN

(SHORT PIN)

PWRGD

+

–48V RTN

V

OUT

IN

R7

8

R4

549k

1%

51k

V

5%

DD

LT4250L

V

DD

PWRGD

Q2

1

R4

3

2

+

ON/OFF

+

–

UV

3

2

GATE

R5

6.49k

1%

UV

C3

LT4250L

PWRGD

1

R5

R6

V

GH

MOC207

OV

V

–

+

–

+

V

R6

10k

1%

EE

–

OV

V

DL

SENSE

5

GATE

6

DRAIN

7

V

OUT

EE

IN

+

–

7

DRAIN

4

R3

1k, 5%

C3

+

∆V

GATE

V

EE

GATE

6

SENSE

5

100µF

4

100V

R2

10Ω

5%

C1

470nF

25V

*

C2

15nF

100V

*

R3

R1

0.02Ω

5%

C2

C1

R2

3

4

3

4

R1

–48V

4250 F14

1

2

Q1

IRF530

–48V

4250 F13

* DIODES INC. SMAT70A

1

2

Q1

* DIODES INC. SMAT70A

Figure 14. Using PWRGD to Drive an Optoisolator

Figure 13. Active Low Enable Module

U

PACKAGE DESCRIPTIO

N8 Package

8-Lead PDIP (Narrow .300 Inch)

(Reference LTC DWG # 05-08-1510)

0.400*

(10.160)

MAX

0.130 ± 0.005

0.300 – 0.325

0.045 – 0.065

(3.302 ± 0.127)

(1.143 – 1.651)

(7.620 – 8.255)

8

1

7

6

5

0.065

(1.651)

TYP

0.255 ± 0.015*

(6.477 ± 0.381)

0.009 – 0.015

(0.229 – 0.381)

0.125

0.020

(0.508)

MIN

(3.175)

MIN

+0.035

–0.015

2

4

3

0.325

0.018 ± 0.003

0.100

(2.54)

BSC

+0.889

8.255

(0.457 ± 0.076)

(

)

N8 1098

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

S8 Package

8-Lead Plastic Small Outline (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1610)

0.189 – 0.197*

(4.801 – 5.004)

0.010 – 0.020

(0.254 – 0.508)

7

5

8

6

× 45°

0.053 – 0.069

(1.346 – 1.752)

0.004 – 0.010

(0.101 – 0.254)

0.008 – 0.010

(0.203 – 0.254)

0°– 8° TYP

0.150 – 0.157**

(3.810 – 3.988)

0.228 – 0.244

(5.791 – 6.197)

0.016 – 0.050

(0.406 – 1.270)

0.050

(1.270)

BSC

0.014 – 0.019

(0.355 – 0.483)

TYP

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

SO8 1298

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

1

2

3

4

4250lhf

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

11

LT4250L/LT4250H

U

TYPICAL APPLICATION

Using an EMI Filter Module

using the Lucent FLTR100V10 filter module is shown in

Figure 15. When using a filter, an optoisolator is required

to prevent common mode transients from destroying the

PWRGD and ON/OFF pins.

Many applications place an EMI filter module in the power

path to prevent switching noise of the module from being

injected back onto the power supply. A typical application

–48V RTN

(SHORT PIN)

–48V RTN

R7

51k

5%

8

LUCENT

V

DD

JW050A1-E

MOC207

1

2

9

8

7

1

7

+

R4

549k

1%

5V

V

OUT

PWRGD

IN

SENSE

+

C7

3

2

+

V

OUT

ON/OFF

TRIM

UV

DRAIN

LT4250L

GATE

100µF

16V

IN

C2

15nF

100V

R5

6.49k

1%

C3

0.1µF

100V

C4

0.1µF

100V

C5

100µF

100V

C6

+

LUCENT

FLTR100V10

0.1µF

6

5

–

6

SENSE

R3

1k

100V

OV

V

4

–

V

OUT

R6

10k

1%

IN

OUT

CASE

IN

SENSE

5

5%

EE

CASE

1N4003

R2

10Ω

5%

C1

470nF

25V

4

3

R1

0.02Ω

5%

4250 F15

*

3

4

–48V

* DIODES INC. SMAT70A

1

2

Q1

IRF530

Figure 15. Typical Application Using a Filter Module

RELATED PARTS

PART NUMBER

LTC^®1421

DESCRIPTION

COMMENTS

Operates from 3V to 12V

Dual Hot Swap Controller with Additional –12V Control

Hot Swap Controller in SO-8

LTC1422

System Reset Output with Programmable Delay

LT4250 is a Pin-Compatible Upgrade to LT1640

LT1640AH/LT1640AL

LT1641-1/LT1641-2

LTC1642

–48V Hot Swap Controller in SO-8

+48V Hot Swap Controller in SO-8

Fault Protected Hot Swap Controller

PCI Hot Swap Controller

Foldback Current Limit, 9V to 80V, Auto-Retry/Latch-Off

Operates Up to 16.5V, Protected to 33V

LTC1643

3.3V, 5V, 12V, –12V Supplies for PCI Bus

LTC1645

Dual Hot Swap Controller

Operates from 1.2V to 12V, Power Sequencing

3.3V, 5V Supplies with Precharge and Local PCI Reset Logic

Dual ON Pins for Supplies from 3V to 15V

LTC1646

Dual CompactPCI Hot Swap Controller

Dual Hot Swap Controller

LTC1647

LTC4211

Hot Swap Controller with Multifunction Current Control

–48 Hot Swap Controller in SOT-23

2.5V to 16.5V Supplies, Active Inrush Current Limiting

LTC4251

Active Current Limiting, Fast Comparator

for Catastrophic Faults

LTC4252

–48 Hot Swap Controller in MSOP

Active Current Limiting, Fast Comparator for Catastrophic

Faults, Separate UV/0V Pins, Power-Good Output

4250lhf

LT/TP 0402 2K • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

12

●

LINEAR TECHNOLOGY CORPORATION 2001

(408)432-1900 FAX:(408)434-0507 www.linear-tech.com


型号：	LT1640AH
厂家：	Linear
描述：	Negative 48V Hot Swap Controller 负48V热插拔控制器控制器
文件：	总12页 (文件大小：231K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT1640AH [Linear]

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