LT1713IMS8 [Linear]
Single/Dual, 7ns, Low Power,3V/5V/±5V Rail-to-Rail Comparators; 单/双通道，为7ns ，低功耗， 3V / 5V / ± 5V轨到轨比较器
| 型号： | LT1713IMS8 |
| 厂家： | 
Linear |
| 描述： | Single/Dual, 7ns, Low Power,3V/5V/±5V Rail-to-Rail Comparators |
| 文件： | 总16页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1713/LT1714
Single/Dual, 7ns, Low Power,
3V/5V/±5V Rail-to-Rail Comparators
U
FEATURES
DESCRIPTIO
■
Ultrafast: 7ns at 20mV Overdrive
The LT®1713/LT1714 are UltraFastTM 7ns, single/dual
comparators featuring rail-to-rail inputs, rail-to-rail
complementary outputs and an output latch. Optimized
for 3V and 5V power supplies, they operate over a single
supply voltage range from 2.4V to 12V or from ±2.4V to
±6V dual supplies.
8.5ns at 5mV Overdrive
■
Rail-to-Rail Inputs
■
Rail-to-Rail Complementary Outputs
(TTL/CMOS Compatible)
■
Specified at 2.7V, 5V and ±5V Supplies
■
Low Power (Per Comparator): 5mA
Output Latch
The LT1713/LT1714 are designed for ease of use in a
variety of systems. In addition to wide supply voltage
■
■
Inputs Can Exceed Supplies Without Phase Reversal
LT1713: 8-Lead MSOP Package
LT1714: 16-Lead Narrow SSOP Package
flexibility, rail-to-rail input common mode range extends
100mV beyond both supply rails and the outputs are
protected against phase reversal for inputs extending
furtherbeyondtherails. Also, therail-to-railinputsmaybe
taken to opposite rails with no significant increase in input
current. The rail-to-rail matched complementary outputs
interface directly to TTL or CMOS logic and can sink 10mA
towithin0.5VofGNDorsource10mAtowithin0.7VofV+.
■
■
U
APPLICATIO S
■
High Speed Automatic Test Equipment
■
Current Sense for Switching Regulators
■
Crystal Oscillator Circuits
The LT1713/LT1714 have internal TTL/CMOS compatible
latches for retaining data at the outputs. Each latch holds
data as long as its latch pin is held high. Latch pin
hysteresis provides protection against slow moving or
noisy latch signals. The LT1713 is available in the 8-lead
MSOP package. The LT1714 is available in the 16-lead
narrow SSOP package.
■
High Speed Sampling Circuits
■
High Speed A/D Converters
■
Pulse Width Modulators
Window Comparators
■
■
Extended Range V/F Converters
Fast Pulse Height/Width Discriminators
Line Receivers
High Speed Triggers
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
UltraFast is a trademark of Linear Technology Corporation.
■
U
TYPICAL APPLICATIO
A 4× NTSC Subcarrier Voltage-Tunable Crystal Oscillator
5V
LT1713/LT1714 Propagation Delay
vs Input Overdrive
47k* LT1004-2.5
1N4148
1M*
3.9k*
1k*
V
IN
0V TO 5V
9.0
8.5
8.0
7.5
1M
T
= 25°C
= 5V
A
+
V
V
V
–
= 0V
MV-209
VARACTOR
DIODE
5V
= 100mV
STEP
1M
0.047µF
C SELECT
+
t
PD
1M
2k
(CHOOSE FOR CORRECT
PLL LOOP RESPONSE)
–
100pF
t
PD
7.0
6.5
390Ω
Y1** 15pF 100pF
+
6.0
5.5
5.0
LT1713
FREQUENCY
OUTPUT
–
171314 TA01
2k
0
10
20
40
50
60
30
200pF
INPUT OVERDRIVE (mV)
* 1% FILM RESISTOR
** NORTHERN ENGINEERING LABS C-2350N-14.31818MHz
171314 TA02
1
LT1713/LT1714
W W
U W
ABSOLUTE AXI U RATI GS
(Note 1)
Supply Voltage
Output Current (Continuous) .............................. ±20mA
Operating Temperature Range ................ –40°C to 85°C
Specified Temperature Range (Note 2)... –40°C to 85°C
Junction Temperature.......................................... 150°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
V+ to V–............................................................ 12.6V
V+ to GND ........................................................ 12.6V
V– to GND .............................................–10V to 0.3V
Differential Input Voltage ................................... ±12.6V
Latch Pin Voltage...................................................... 7V
Input and Latch Current..................................... ±10mA
U W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
ORDER PART
NUMBER
LATCH
ENABLE A
GND
NUMBER
–IN A
+IN A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TOP VIEW
LT1713CMS8
LT1713IMS8
LT1714CGN
LT1714IGN
–
V
Q A
Q A
Q B
Q B
+
V
1
2
3
4
8 Q OUT
7 Q OUT
6 GND
5 LATCH
ENABLE
+
V
+IN
–IN
+
V
–
V
–
V
MS8 PACKAGE
MS8 PART MARKING
GN PART MARKING
+IN B
–IN B
GND
LATCH
ENABLE B
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 250°C/ W
LTRD
LTUK
1714
1714I
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 120°C/ W
Consult factory for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 2.7V or V+ = 5V, V– = 0V, VCM = V+/2, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
V
V
Positive Supply Voltage Range
Input Offset Voltage (Note 4)
●
●
2.4
7
V
+
+
R = 50Ω, V = V /2
0.5
4
5
mV
mV
mV
mV
OS
S
CM
R = 50Ω, V = V /2 (Note 11)
S
CM
R = 50Ω, V = 0V
0.7
1
S
CM
+
R = 50Ω, V = V
S
CM
∆V /∆T Input Offset Voltage Drift
●
●
5
µV/°C
OS
I
Input Offset Current
0.1
1
2
µA
µA
OS
I
Input Bias Current (Note 5)
–7
–1.5
2
5
µA
µA
B
●
●
–15
+
V
Input Voltage Range (Note 9)
Common Mode Rejection Ratio
–0.1
V + 0.1
V
CM
+
+
+
+
CMRR
V
V
V
V
= 5V, 0V ≤ V ≤ 5V
60
58
57
55
70
70
dB
dB
dB
dB
CM
= 5V, 0V ≤ V ≤ 5V
●
●
CM
= 2.7V, 0V ≤ V ≤ 2.7V
CM
= 2.7V, 0V ≤ V ≤ 2.7V
CM
2
LT1713/LT1714
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 2.7V or V+ = 5V, V– = 0V, VCM = V+/2, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
+
PSRR
Positive Power Supply Rejection Ratio
2.4V ≤ V ≤ 7V, V = 0V
65
60
80
dB
dB
CM
●
●
–
–
+
PSRR
Negative Power Supply Rejection Ratio
–7V ≤ V ≤ 0V, V = 5V, V = 5V
65
60
80
dB
dB
CM
A
V
Small-Signal Voltage Gain (Note 10)
Output Voltage Swing HIGH
1.5
3
V/mV
V
+
+
+
I
I
= 1mA, V = 5V, V
= 50mV
●
●
V – 0.5 V – 0.2
V
V
OH
OUT
OUT
OVERDRIVE
+
+
+
= 10mA, V = 5V, V
= 50mV
V – 0.7 V – 0.4
OVERDRIVE
V
Output Voltage Swing LOW
I
I
= –1mA, V = 50mV
OVERDRIVE
●
●
0.20
0.35
0.4
0.5
V
V
OL
OUT
= –10mA, V
= 50mV
OUT
+
OVERDRIVE
+
I
I
Positive Supply Current (Per Comparator)
Negative Supply Current (Per Comparator)
V = 5V, V
= 1V
= 1V
5
6.5
8.0
mA
mA
OVERDRIVE
●
–
+
V = 5V, V
3
4.0
4.5
mA
mA
OVERDRIVE
●
●
●
●
V
V
Latch Pin High Input Voltage
Latch Pin Low Input Voltage
Latch Pin Current
2.4
V
V
IH
IL
0.8
10
+
I
t
V
= V
µA
IL
PD
LATCH
Propagation Delay (Note 6)
∆V = 100mV, V
∆V = 100mV, V
∆V = 100mV, V
= 20mV
= 20mV
= 5mV
8.0
11.0
12.5
ns
ns
ns
IN
OVERDRIVE
OVERDRIVE
OVERDRIVE
●
IN
9.0
0.5
4
IN
∆t
Differential Propagation Delay (Note 6)
Output Rise Time
∆V = 100mV, V
= 20mV
3
ns
ns
PD
IN
OVERDRIVE
t
t
t
t
t
t
f
t
10% to 90%
90% to 10%
r
f
Output Fall Time
4
ns
Latch Propagation Delay (Note 7)
Latch Setup Time (Note 7)
Latch Hold Time (Note 7)
8
ns
LPD
SU
1.5
0
ns
ns
H
Minimum Latch Disable Pulse Width (Note 7)
Maximum Toggle Frequency
Output Timing Jitter
8
ns
DPW
MAX
V
V
= 100mV Sine Wave
65
15
MHz
IN
P-P
= 630mV (0dBm) Sine Wave, f = 30MHz
ps
RMS
JITTER
IN
P-P
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 5V, V– = –5V, VCM = 0V, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL PARAMETER
CONDITIONS
MIN
2.4
–7
TYP
MAX
UNITS
+
V
V
V
Positive Supply Voltage Range
●
●
7
0
V
V
–
Negative Supply Voltage Range (Note 3)
Input Offset Voltage (Note 4)
R = 50Ω, V = 0V
0.5
3
4
mV
mV
mV
mV
OS
S
CM
R = 50Ω, V = 0V
●
S
CM
R = 50Ω, V = –5V
0.7
1
S
CM
R = 50Ω, V = 5V
S
CM
∆V /∆T Input Offset Voltage Drift
●
●
●
5
µV/°C
OS
I
Input Offset Current
0.1
1
2
µA
µA
OS
I
Input Bias Current (Note 5)
–7
–15
–1.5
2
5
µA
µA
B
3
LT1713/LT1714
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 5V, V– = –5V, VCM = 0V, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Voltage Range
●
●
●
●
–5.1
5.1
V
CM
CMRR
Common Mode Rejection Ratio
–5V ≤ V ≤ 5V
62
60
70
80
80
3
dB
dB
CM
+
+
PSRR
PSRR
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
2.4V ≤ V ≤ 7V, V = –5V
68
65
dB
dB
CM
–
–
–7V ≤ V ≤ 0V, V = 5V
65
60
dB
dB
CM
A
V
Small-Signal Voltage Gain (Note 10)
Output Voltage Swing HIGH (Note 8)
1V ≤ V
≤ 4V, R =
∞
1.5
V/mV
V
OUT
L
I
I
= 1mA, V
= 50mV
= 50mV
●
●
4.5
4.3
4.8
4.6
V
V
OH
OUT
OUT
OVERDRIVE
= 10mA, V
OVERDRIVE
V
Output Voltage Swing LOW (Note 8)
I
I
= –1mA, V
= 50mV
OVERDRIVE
●
●
0.20
0.35
0.4
0.5
V
V
OL
OUT
OUT
OVERDRIVE
= –10mA, V
= 50mV
+
I
I
Positive Supply Current (Per Comparator)
Negative Supply Current (Per Comparator)
V
= 1V
5.5
7.5
9.0
mA
mA
OVERDRIVE
●
–
V
= 1V
3.5
4.5
5.0
mA
mA
OVERDRIVE
●
●
●
●
V
V
Latch Pin High Input Voltage
Latch Pin Low Input Voltage
Latch Pin Current
2.4
V
V
IH
IL
0.8
10
+
I
t
V
= V
LATCH
µA
IL
PD
Propagation Delay (Note 6)
∆V = 100mV, V
= 20mV
= 20mV
= 5mV
7
10
12
ns
ns
ns
IN
IN
IN
OVERDRIVE
OVERDRIVE
OVERDRIVE
∆V = 100mV, V
●
∆V = 100mV, V
8.5
0.5
4
∆t
Differential Propagation Delay (Note 6)
Output Rise Time
∆V = 100mV, V
= 20mV
3
ns
ns
PD
IN
OVERDRIVE
t
t
t
t
t
t
f
t
10% to 90%
90% to 10%
r
f
Output Fall Time
4
ns
Latch Propagation Delay (Note 7)
Latch Setup Time (Note 7)
Latch Hold Time (Note 7)
8
ns
LPD
SU
1.5
0
ns
ns
H
Minimum Latch Disable Pulse Width (Note 7)
Maximum Toggle Frequency
Output Timing Jitter
8
ns
DPW
MAX
V
V
= 100mV Sine Wave
65
15
MHz
IN
IN
P-P
= 630mV (0dBm) Sine Wave, f = 30MHz
ps
RMS
JITTER
P-P
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LT1713C/LT1714C are guaranteed to meet specified
performance from 0°C to 70°C. They are designed, characterized and
expected to meet specified performance from –40°C to 85°C but are not
tested or QA sampled at these temperatures. The LT1713I/LT1714I are
guaranteed to meet specified performance from –40°C to 85°C.
Note 6: Propagation delay (t ) is measured with the overdrive added to
PD
the actual V . Differential propagation delay is defined as:
OS
+
–
∆t = t
– t . Load capacitance is 10pF. Due to test system
PD
PD
PD
requirements, the LT1713/LT1714 propagation delay is specified with a
1kΩ load to ground for ±5V supplies, or to mid-supply for 2.7V or 5V
single supplies.
Note 7: Latch propagation delay (t ) is the delay time for the output to
LPD
respond when the latch pin is deasserted. Latch setup time (t ) is the
interval in which the input signal must remain stable prior to asserting the
Note 3: The negative supply should not be greater than the ground pin
voltages and the maximum voltage across the positive and negative
supplies should not be greater than 12V.
SU
latch signal. Latch hold time (t ) is the interval after the latch is asserted in
H
which the input signal must remain stable. Latch disable pulse width
Note 4: Input offset voltage (V ) is defined as the average of the two
OS
(t
) is the width of the negative pulse on the latch enable pin that
+
DPW
voltages measured by forcing first one output, then the other to V /2.
latches in new data on the data inputs.
Note 5: Input bias current (I ) is defined as the average of the two input
B
currents.
4
LT1713/LT1714
ELECTRICAL CHARACTERISTICS
+
+
Note 10: The LT1713/LT1714 voltage gain is tested at V = 5V and
Note 8: Output voltage swings are characterized and tested at V = 5V and
–
+
+
–
V = –5V only. Voltage gain at single supply V = 5V and V = 2.7V is
guaranteed by design and correlation.
Note 11: Input offset voltage over temperature at V = 2.7V is guaranteed
V = 0V. They are designed and expected to meet these same
–
specifications at V = –5V.
+
Note 9: The input voltage range is tested under the more demanding
+
–
by design and characterization.
conditions of V = 5V and V = –5V. The LT1713/LT1714 are designed
–
and expected to meet these specifications at V = 0V.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Input Offset Voltage
vs Temperature
Propagation Delay
Propagation Delay
vs Temperature
vs Load Capacitance
2.5
2.0
14
12
10
8
16
14
12
10
8
+
+
V
V
V
V
V
C
= 5V
= 0V
V
V
V
= 5V
= 0V
–
–
= 2.5V
+
= 2.5V
CM
OD
CM
t
PD
1.5
= 20mV
= 100mV
1.0
STEP
LOAD
= 10pF
–
t
PD
0.5
+
0
t
PD
6
–0.5
–1.0
–1.5
–2.0
–2.5
–
6
t
PD
T
= 25°C
= 5V
A
+
V
V
V
V
V
4
–
4
= 0V
= 2.5V
CM
OD
2
2
= 20mV
= 100mV
STEP
0
–50
0
–50
0
25
50
75 100 125
–25
–25
0
25
50
75
125
80
LOAD CAPACITANCE (pF)
120
100
0
20
40
60
100
TEMPERATURE (°C)
TEMPERATURE (°C)
171314 G01
171314 G03
171314 G02
Propagation Delay
vs Input Common Mode Voltage
Propagation Delay
vs Positive Supply Voltage
Positive Supply Current
vs Positive Supply Voltage
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
7.0
6.5
6.0
5.5
5.0
4.5
4.0
10.0
9.5
9.0
8.5
T
= 25°C
T
= 25°C
= 0V
A
A
–
∆V = 100mV
V
V
V
V
C
IN
I
= 0
= 2.5V
OUT
CM
OD
STEP
LOAD
–
= 20mV
V
= –5V
+
= 100mV
t
PD
= 10pF
+
–
t
V
= 0V
PD
8.0
7.5
–
–
t
PD
t
PD
T
= 25°C
= 5V
A
+
V
V
V
V
C
–
7.0
6.5
6.0
= 0V
= 20mV
OD
= 100mV
= 10pF
STEP
LOAD
0.5
1.5
3.5
2
4
8
10
12
14
2
6
8
10
12
–0.5
4.5
5.5
0
6
2.5
4
POSITIVE SUPPLY VOLTAGE (V)
INPUT COMMON MODE (V)
POSITIVE SUPPLY VOLTAGE (V)
171314 G04
171314 G05
171314 G06
5
LT1713/LT1714
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Positive Supply Current
vs Switching Frequency
Negative Supply Current
Input Bias Current
vs Negative Supply Voltage
vs Input Common Mode Voltage
3
2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
40
35
30
25
20
15
10
5
T
V
V
= 25°C
= 5V
T
= 25°C
T
= 25°C
= 5V
A
A
A
+
+
∆V = 100mV
V
V
C
IN
–
–
= 0V
I
= 0
= 0V
OUT
1
∆V = 0mV
= 10pF
+
IN
LOAD
V
= 5V
0
–1
–2
–3
–4
–5
+
V
= 2.7V
–6
0
20
10
SWITCHING FREQUENCY (MHz)
0
–2
–3 –4
–5
–7
–1
0
1
2
6
0
30
40
–6
–1
3
4
5
NEGATIVE SUPPLY VOLTAGE (V)
INPUT COMMON MODE VOLTAGE (V)
171314 G07
171314 G08
171314 G09
Input Bias Current
vs Temperature
Output High Voltage
vs Source Current
Output Low Voltage
vs Sink Current
5.0
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
–1
–2
–3
–4
+
–
T
V
V
= 25°C
= 5V
V
V
V
= 5V
= 0V
A
+
–
= 0V
= 2.5V
CM
∆V = 100mV
IN
T
V
V
= 25°C
= 5V
A
+
–
= 0V
∆V = 100mV
IN
–25
0
25
50
75
125
–50
100
0.01
1
0.01
1
0.1
10
0.1
10
LOADING SOURCE CURRENT (mA)
LOADING SINK CURRENT (mA)
TEMPERATURE (°C)
171314 G10
171314 G11
171314 G12
Output Timing Jitter
vs Switching Frequency
Output Rising Edge, 5V Supply
Output Falling Edge, 5V Supply
200
180
160
140
120
100
80
T
= 25°C
= 5V
A
+
V
V
V
V
–
= 0V
VIN
VIN
= 2.5V
CM
= 630mV
IN
P-P
(0dBm) SINE WAVE
VOUT
VOUT
60
40
171314 G14
171314 G15
20
0
0
40
60
80
20
FREQUENCY (MHz)
171314 G13
6
LT1713/LT1714
U
U
U
PI FU CTIO S
LT1713
V+ (Pin 1): Positive Supply Voltage, Usually 5V.
GND (Pin 6): Ground Supply Voltage, Usually 0V.
+IN (Pin 2): Noninverting Input.
Q (Pin 7): Noninverting Output.
Q (Pin 8): Inverting Output.
–IN (Pin 3): Inverting Input.
V– (Pin 4): Negative Supply Voltage, Usually 0V or –5V.
LATCH ENABLE (Pin 5): Latch Enable Input. With a logic
high the output is latched.
LT1714
Q B (Pin 11): Noninverting Output of B Channel
–IN A (Pin 1): Inverting Input of A Channel Comparator.
Comparator.
+IN A (Pin 2): Noninverting Input of A Channel
Comparator.
V– (Pins3,6):NegativeSupplyVoltage,Usually–5V.Pins
3 and 6 should be connected together externally.
V+ (Pins 4, 5): Positive Supply Voltage, Usually 5V. Pins
4 and 5 should be connected together externally.
Q B (Pin 12): Inverting Output of B Channel
Comparator.
Q A (Pin 13): Inverting Output of A Channel
Comparator.
Q A (Pin 14): Noninverting Output of A Channel
Comparator.
+IN B (Pin 7): Noninverting Input of B Channel
Comparator.
GND (Pin 15): Ground Supply Voltage of A Channel
Comparator, Usually 0V
–IN B (Pin 8): Inverting Input of B Channel Comparator.
LATCH ENABLE A (Pin 16): Latch Enable Input of A Chan-
nel Comparator. With a logic high, the A output is latched.
LATCHENABLEB(Pin9):LatchEnableInputofBChannel
Comparator. With a logic high, the B output is latched.
GND (Pin 10): Ground Supply Voltage of B Channel
Comparator, Usually 0V.
7
LT1713/LT1714
W U U
U
APPLICATIO S I FOR ATIO
Common Mode Considerations
Latch Pin Dynamics
The internal latches of the LT1713/LT1714 comparators
retaintheinputdata(outputlatched)whentheirrespective
latch pin goes high. The latch pin will float to a low state
when disconnected, but it is better to ground the latch
when a flow-through condition is desired. The latch pin is
designed to be driven with either a TTL or CMOS output.
It has built-in hysteresis of approximately 100mV, so that
slow moving or noisy input signals do not impact latch
performance. For the LT1714, if only one of the compara-
tors is being used at a given time, it is best to latch the
second comparator to avoid any possibility of interactions
between the two comparators in the same package.
The LT1713/LT1714 are specified for a common mode
range of –5.1V to 5.1V on a ±5V supply, or a common
moderangeof–0.1Vto5.1Vonasingle5Vsupply.Amore
general consideration is that the common mode range is
from 100mV below the negative supply to 100mV above
the positive supply, independent of the actual supply volt-
age. The criteria for common mode limit is that the output
still responds correctly to a small differential input signal.
When either input signal falls outside the common mode
limit, the internal PN diode formed with the substrate can
turn on resulting in significant current flow through the
die. Schottky clamp diodes between the inputs and the
supply rails speed up recovery from excessive overdrive
conditions by preventing these substrate diodes from
turning on.
High Speed Design Techniques
A substantial amount of design effort has made the
LT1713/LT1714 relatively easy to use. As with most high
speed comparators, careful attention to PC board layout
and design is important in order to prevent oscillations.
The most common problem involves power supply by-
passing which is necessary to maintain low supply im-
pedance. Resistance and inductance in supply wires and
PC traces can quickly build up to unacceptable levels,
thereby allowing the supply voltages to move as the
supply current changes. This movement of the supply
voltages will often result in improper operation. In addi-
tion, adjacent devices connected through an unbypassed
supply can interact with each other through the finite
supply impedances.
Input Bias Current
Input bias current is measured with the outputs held at
2.5V with a 5V supply voltage. As with any rail-to-rail
differential input stage, the LT1713/LT1714 bias current
flows into or out of the device depending upon the com-
mon mode level. The input circuit consists of an NPN pair
and a PNP pair. For inputs near the negative rail, the NPN
pair is inactive, and the input bias current flows out of the
device; for inputs near the positive rail, the PNP pair is
inactive,andthesecurrentsflowintothedevice.Forinputs
far enough away from the supply rails, the input bias
currentwillbesomecombinationoftheNPNandPNPbias
currents. As the differential input voltage increases, the
inputcurrentofeachpairwillincreaseforoneoftheinputs
and decrease for the other input. Large differential input
voltages result in different input currents as the input
stage enters various regions of operation. To reduce the
influence of these changing input currents on system
operation, use a low source resistance.
Bypass capacitors furnish a simple solution to this prob-
lem by providing a local reservoir of energy at the device,
thus keeping supply impedance low. Bypass capacitors
should be as close as possible to the LT1713/LT1714
supply pins. A good high frequency capacitor, such as a
0.1µF ceramic, is recommended in parallel with a larger
capacitor, such as a 4.7µF tantalum.
8
LT1713/LT1714
W U U
APPLICATIO S I FOR ATIO
U
Poor trace routes and high source impedances are also
common sources of problems. Keep trace lengths as
short as possible and avoid running any output trace
adjacent to an input trace to prevent unnecessary cou-
pling. If output traces are longer than a few inches,
provide proper termination impedances (typically 100Ω
to400Ω)toeliminateanyreflectionsthatmayoccur. Also
keep source impedances as low as possible, preferably
much less than 1kΩ.
this isolation as shown in Figure 1, a typical topside layout
of the LT1713/LT1714 on a multilayer PC board. Shown is
thetopsidemetaletchincludingtraces,pinescapeviasand
the land pads for a GN16 LT1713/LT1714 and its adjacent
X7R 0805 bypass capacitors. The V+, V– and GND traces
all shield the inputs from the outputs. Although the two V–
pins are connected internally, they should be shorted to-
gether externally as well in order for both to function as
shields. The same is true for the twoV+ pins. The two GND
pins are not connected internally, but in most applications
they are both connected directly to the ground plane.
The input and output traces should also be isolated from
one another. Power supply traces can be used to achieve
1714 F01
Figure 1. Typical LT1714 Topside Metal for Multilayer PCB Layout
9
LT1713/LT1714
W U U
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APPLICATIO S I FOR ATIO
Hysteresis
LT1713/LT1714 are completely flexible regarding the ap-
plication of hysteresis, due to rail-to-rail inputs and the
complementary outputs. Specifically, feedback resistors
can be connected from one or both outputs to their
corresponding inputs without regard to common mode
considerations. Figure 2 shows several configurations.
Anotherusefultechniquetoavoidoscillationsistoprovide
positive feedback, also known as hysteresis, from the
output to the input. Increased levels of hysteresis, how-
ever, reduce the sensitivity of the device to input voltage
levels, so the amount of positive feedback should be
tailored to particular system requirements. The
100k
50k
Q
V
+
–
IN
Q
Q
Q
50Ω
50Ω
50Ω
+
–
LT1713
V
V
+
–
V
+
–
IN
IN
IN
LT1713
LT1713
V
Q
REF
50k
+
–
V
V
V
= 5V
= –5V
= 5mV
(ALL 3 CASES)
Q
50Ω
HYST
100k
171314 F02
Figure 2. Various Configurations for Introducing Hysteresis
10
LT1713/LT1714
U
TYPICAL APPLICATIO S
The circuit works well with the resistor values shown, but
other sets of values can be used. The starting point is the
characteristic impedance, ZO, of the twisted-pair cable.
The input impedance of the resistive network should
match the characteristic impedance and is given by:
Simultaneous Full Duplex 75Mbaud Interface
with Only Two Wires
The circuit of Figure 3 shows a simple, fully bidirectional,
differential 2-wire interface that gives good results to
75Mbaud, using the LT1714. Eye diagrams under condi-
tions of unidirectional and bidirectional communication
are shown in Figures 4 and 5. Although not as pristine as
the unidirectional performance of Figure 4, the perfor-
mance under simultaneous bidirectional operation is still
excellent. Because the LT1714 input voltage range ex-
tends 100mV beyond both supply rails, the circuit works
with a full ±3V (one whole VS up or down) of ground
potential difference.
R1||(R2 +R3)
RIN = 2 •RO •
R + 2 • R1||(R2 +R3)
[
]
O
This comes out to 120Ω for the values shown. The
Thevenin equivalent source voltage is given by:
(R2 +R3 –R1)
VTH = VS •
(R2 +R3 +R1)
RO
•
R + 2 • R1||(R2 +R3)
[
]
O
750k
14
750k
3V
3V
4
4
2
1
2
+
–
14
+
1/2
1/2
LT1714
RxD
RxD
LT1714
LE
16
LE
1
13
13
–
16
3
15
3
15
750k
750k
3V
3V
100k
11
100k
11
R1C
3V
R1A
R2A
R2C
3V
499Ω
499Ω
2.55k
2.55k
49.9Ω
49.9Ω
49.9Ω
49.9Ω
5
5
7
8
7
8
+
+
1/2
LT1714
LE
10
R
R
1/2
R3A
124Ω
R3C
124Ω
OA
OB
TxD
TxD
140Ω
140Ω
LT1714
LE
12
12
–
–
10
6
6-FEET
6
R1D
499Ω
TWISTED PAIR
R3B
124Ω
R1B
499Ω
R3D
124Ω
9
9
Z
≈ 120Ω
O
R2D
2.55k
DIODES: BAV99
R2B
2.55k
100k
×4
100k
171314 F03
Figure 3. 75Mbaud Full Duplex Interface on Two Wires
11
LT1713/LT1714
TYPICAL APPLICATIO S
U
171112 F05
171112 F04
Figure 5. Performance When Operated Simultaneous
Bidirectionally (Full Duplex). Crosstalk Appears as Noise.
Eye is Slightly Shut But Performance is Still Excellent
Figure 4. Performance of Figure 3’s Circuit When
Operated Unidirectionally. Eye is Wide Open
The LT1713 is set up as a crystal oscillator. The varactor
diode is biased from the tuning input. The tuning network
is arranged so a 0V to 5V drive provides a reasonably
symmetric, broad tuning range around the 14.31818MHz
center frequency. The indicated selected capacitor sets
tuningbandwidth. Itshouldbepickedtocomplementloop
response in phase locking applications. Figure 6 is a plot
oftuninginputvoltageversusfrequencydeviation. Tuning
deviation from the 4× NTSC 14.31818MHz center fre-
quency exceeds ±240ppm for a 0V to 5V input.
This amounts to an attenuation factor of 0.0978 with the
values shown. (The actual voltage on the lines will be cut
in half again due to the 120Ω ZO.) The reason this
attenuation factor is important is that it is the key to
deciding the ratio between the R2-R3 resistor divider in
the receiver path. This divider allows the receiver to reject
the large signal of the local transmitter and instead sense
the attenuated signal of the remote transmitter. Note that
in the above equations, R2 and R3 are not yet fully
determined because they only appear as a sum. This
allows the designer to now place an additional constraint
on their values. The R2-R3 divide ratio should be set to
equal half the attenuation factor mentioned above or:
1 Using the design value of R2 + R3 = 2.653k rather than the implementation value of 2.55k +
124Ω = 2.674k.
R3/R2 = 1/2 • 0.09761.
9
14.3217MHz
8
7
6
Having already designed R2 + R3 to be 2.653k (by allocat-
ing input impedance across RO, R1 and R2 + R3 to get the
requisite 120Ω), R2 and R3 then become 2529Ω and
123.5Ω respectively. The nearest 1% value for R2 is 2.55k
and that for R3 is 124Ω.
5
4
3
2
1
0
14.31818MHz
Voltage-Tunable Crystal Oscillator
14.314.0MHz
1
The front page application is a variant of a basic crystal
oscillator that permits voltage tuning of the output fre-
quency.Suchvoltage-controlledcrystaloscillators(VCXO)
are often employed where slight variation of a stable
carrier is required. This example is specifically intended to
provide a 4× NTSC sub-carrier tunable oscillator suitable
for phase locking.
0
4
5
2
3
INPUT VOLTAGE (V)
171112 F06
Figure 6. Control Voltage vs Output Frequency for the First Page
Application Circuit. Tuning Deviation from Center Frequency
Exceeds ±240ppm
12
LT1713/LT1714
U
TYPICAL APPLICATIO S
1MHz Series Resonant Crystal Oscillator
caused by the fast edge of the comparator output feeding
back through crystal capacitance. Amplitude stability of
the sine wave is maintained by the fact that the sine wave
is basically a filtered version of the square wave. Hence,
theusualamplitudecontrolloopsassociatedwithsinusoi-
daloscillatorsarenotnecessary.2 Thesinewaveisfiltered
and buffered by the fast, low noise LT1806 op amp. To
removetheglitch, theLT1806isconfiguredasabandpass
filter with a Q of 5 and unity-gain center frequency of
1MHz, with its output shown as the bottom trace of
Figure 8.Distortionwasmeasuredat–70dBcand–60dBc
on the second and third harmonics, respectively.
with Square and Sinusoid Outputs
Figure 7 shows a classic 1MHz series resonant crystal
oscillator. At series resonance, the crystal is a low imped-
ance and the positive feedback connection is what brings
about oscillation at the series resonant frequency. The RC
feedback around the other path ensures that the circuit
does not find a stable DC operating point and refuse to
oscillate. The comparator output is a 1MHz square wave
(top trace of Figure 8) with jitter measured at better than
28psRMS on a 5V supply and 40psRMS on a 3V supply. At
Pin 2 of the comparator, on the other side of the crystal, is
a clean sine wave except for the presence of the small high
frequency glitch (middle trace of Figure 8). This glitch is
2 Amplitude will be a linear function of comparator output swing, which is supply dependent
and therefore adjustable. The important difference here is that any added amplitude
stabilization or control loop will not be faced with the classical task of avoiding regions of
nonoscillation versus clipping.
C4
100pF
R10
1k
R5
6.49k
C5
100pF
R6
162Ω
1MHz
AT-CUT
C3
100pF
R4
210Ω
V
R7
15.8k
S
V
S
7
2
3
–
+
V
R1
1k
S
6
R9
2k
SINE
LT1806
4
1
2
3
+
–
1
7
V
S
SQUARE
R2
1k
LT1713
LE
C2
0.1µF
R8
2k
171314 F07
8
4
5
6
R3
1k
C1
0.1µF
Figure 7. LT1713 Comparator is Configured as a Series Resonant Xtal Oscillator.
LT1806 Op Amp is Configured in a Q = 5 Bandpass with fC = 1MHz
3V/DIV
1V/DIV
1V/DIV
171112 F08
200ns/DIV
Figure 8. Oscillator Waveforms with VS = 3V. Top is Comparator Output. Middle is
Xtal Feedback to Pin 2 at LT1713 (Note the Glitches). Bottom is Buffered, Inverted
and Bandpass Filtered with a Q = 5 by LT1806
13
LT1713/LT1714
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 ± 0.004*
(3.00 ± 0.102)
8
7
6
5
0.118 ± 0.004**
(3.00 ± 0.102)
0.193 ± 0.006
(4.90 ± 0.15)
1
2
3
4
0.043
(1.10)
MAX
0.034
(0.86)
REF
0.007
(0.18)
0° – 6° TYP
SEATING
PLANE
0.009 – 0.015
(0.22 – 0.38)
0.021 ± 0.006
(0.53 ± 0.015)
0.005 ± 0.002
(0.13 ± 0.05)
0.0256
(0.65)
BSC
MSOP (MS8) 1100
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
14
LT1713/LT1714
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
0.009
(0.229)
REF
16 15 14 13 12 11 10 9
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
2
3
4
5
6
7
8
0.015 ± 0.004
(0.38 ± 0.10)
× 45°
0.053 – 0.068
(1.351 – 1.727)
0.004 – 0.0098
(0.102 – 0.249)
0.007 – 0.0098
(0.178 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.0250
(0.635)
BSC
0.008 – 0.012
(0.203 – 0.305)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 1098
U
TYPICAL APPLICATIO
Rail-to-Rail Pulse Width Modulator
current flow. The circuit of Figure 9 shows an example of
a binary modulation scheme, in this case pulse width
modulation.
Using the LT1714
Binary modulation schemes are used in order to improve
efficiency and reduce physical circuit size. They do this by
reducing the power dissipation in the output driver tran-
sistors. In a normal Class A or Class AB amplifier, voltage
drop and current flow exist simultaneously in the output
transistors and power losses proportional to V • I occur.
In a binary modulation scheme, the output transistors,
whetherbipolarorFET, areswitchedhard-onandhard-off
so that voltage drops do not occur simultaneously with
The LT1809 is configured as an integrator in order to
generate nice linear rail-to-rail voltage ramps. The polarity
of the ramp is determined by the output of the LT1714’s
comparator A into R4. The heavy hysteresis of R1 around
theLT1714’scomparatorAcombinedwiththefeedbackof
the LT1809 force the devices to perpetually reverse each
other, resulting in a 1MHz triangle wave. This constitutes
the usual first half of any pulse width modulator, but the
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.
15
LT1713/LT1714
U
TYPICAL APPLICATIO
example, with their inherent lowpass characteristic. Care
must be taken to avoid cross conduction in the output
power transistors.
forte of this particular implementation is that it is rail-to-
rail allowing a full-scale analog input. Once the triangle
wave is achieved, the remainder of the pulse width modu-
latoriseasy,andisconstitutedbydoingasimplecompari-
sonusingthesecondhalfoftheLT1714.Thetrianglewave
and the relatively slow moving analog signal (the one to be
modulatedortodothemodulation,dependingonhowyou
look at it) are fed into the inputs of comparator B, whose
output is then the PWM representation of the analog input
voltage. The higher the analog input voltage, the wider the
output pulse. The time averaged output level is thus
proportional to the analog input voltage. This binary
output can then be fed into power transistors with direct
control over motor or speaker winding current, for
Thelinearityofthepulsewidthmodulatedsignalcaneasily
be ascertained by putting a simple 2-pole RC filter at the
output(asshowninFigure9).Thisdemodulatesthesignal
which can then be viewed and compared with the original
inputsignalonanoscilloscope.Usingaspectrumanalyzer
and a 1kHz reference signal, this circuit’s distortion prod-
ucts were measured as better than –50dBc (0.3%) to
about 3.5VP-P, degrading to –30dBc (3%) as the circuit
clips at 5VP-P on a single 5V supply.
ANTIALIASING
FILTER
R1
26.1Ω
1k
ANALOG
INPUT
+
C1
500pF
V
C4
0.001µF
+
V
16kHz ANALOG FILTER
R2
2k
+
V
FOR LINEARITY MEASUREMENT
2
4
+
14
7
8
5
+
R4
1k
10k
A
V
+
11
R3
2k
1
499Ω
B
1/2 LT1714
2
13
–
1
1/2 LT1714
C5
0.01µF
C6
0.001µF
12
7
21Ω
16
–
6
15
LT1809
10
–
3
9
3
C3
100pF
+
6
4
171314 F09
R5
1k
+
V
COMPLEMENTARY
1MHz PWM
1MHz
TRIANGLE
WAVE
C2
0.01µF
R6
1k
OUTPUTS
+
V
= 2.7V TO 7V
Figure 9. Rail-to-Rail 1MHz Pulse Width Modulator
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
Industry Standard 10ns Comparator
LT1016
UltraFast Precision Comparator
LT1116
12ns Single Supply Ground Sensing Comparator
7ns, UltraFast Single Supply Comparator
60ns, Low Power, Single Supply Comparator
Single Supply Version of the LT1016
6mA Single Supply Comparator
450µA Single Supply Comparator
LT1394
LT1671
LT1711/LT1712
LT1719
Single/Dual, 4.5ns, 3V/5V/±5V Rail-to-Rail Comparators Faster Versions of LT1713/LT1714
4.5ns, Single Supply 3V/5V Comparator
4mA Comparator with Rail-to-Rail Outputs
Dual/Quad Version of the LT1719
LT1720/LT1721
Dual/Quad, 4.5ns, Single Supply Comparator
171314f LT/TP 0501 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2000
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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