LT1739 [Linear]
Dual 500mA, 200MHz xDSL Line Driver Amplifier; 双500毫安， 200MHz的xDSL线路驱动放大器
| 型号： | LT1739 |
| 厂家： | 
Linear |
| 描述： | Dual 500mA, 200MHz xDSL Line Driver Amplifier |
| 文件： | 总20页 (文件大小：282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1739
Dual 500mA, 200MHz
xDSL Line Driver Amplifier
U
FEATURES
DESCRIPTIO
TheLT®1739isa500mAminimumoutputcurrent,dualop
amp with outstanding distortion performance. The ampli-
fiersaregain-of-tenstable, butcanbeeasilycompensated
for lower gains. The extended output swing allows for
lowersupplyrailstoreducesystempower. Supplycurrent
is set with an external resistor to optimize power dissipa-
tion. The LT1739 features balanced, high impedance in-
puts with low input bias current and input offset voltage.
Active termination is easily implemented for further sys-
tempowerreduction.Short-circuitprotectionandthermal
shutdown insure the device’s ruggedness.
■
3mm × 4mm High Power DFN Package
■
Exceeds All Requirements For Full Rate,
Downstream ADSL Line Drivers
±500mA Minimum IOUT
■
■
±11.1V Output Swing, VS = ±12V, RL = 100Ω
■
±10.9V Output Swing, VS = ±12V, IL = 250mA
■
Low Distortion: –82dBc at 1MHz, 2VP-P Into 50Ω
■
Power Saving Adjustable Supply Current
■
Power Enhanced TSSOP-20 Small Footprint Package
■
200MHz Gain Bandwidth
■
600V/µs Slew Rate
■
Specified at ±12V and ±5V
The outputs drive a 100Ω load to ±11.1V with ±12V
supplies, and ±10.9V with a 250mA load. The LT1739 is a
pin-for-pin replacement for the LT1794 in xDSL line driver
applications and requires no circuit changes.
U
APPLICATIO S
■
High Density ADSL Central Office Line Drivers
■
The LT1739 is available in the very small, thermally
enhanced, 3mm × 4mm DFN package or a 20-lead TSSOP
for maximum port density in central office line driver
applications. For a dual version of the LT1739, see the
LT6301 data sheet.
High Efficiency ADSL, HDSL2, G.lite,
SHDSL Line Drivers
Buffers
Test Equipment Amplifiers
Cable Drivers
■
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
TYPICAL APPLICATIO
High Efficiency ±12V Supply ADSL Central Office Line Driver
12V
3mm × 4mm DFN Package
R
BIAS
Bottom View
24.9k
+IN
+
SHDN
12.7Ω
1/2
LT1739
EXPOSED
THERMAL
PAD
–
1k
1:2*
0.8mm
110Ω
110Ω
100Ω
1000pF
1739 TA01
1k
1739 TA02
3mm
4mm
*COILCRAFT X8390-A OR EQUIVALENT
= 10mA PER AMPLIFIER
–
I
SUPPLY
WITH R
12.7Ω
1/2
LT1739
= 24.9k
BIAS
SHDNREF
–IN
+
–12V
1739fas, sn1739
1
LT1739
ABSOLUTE MAXIMUM RATINGS
W W
U W
(Note 1)
Supply Voltage (V+ to V–) ................................. ±13.5V
Input Current ..................................................... ±10mA
Output Short-Circuit Duration (Note 2)........... Indefinite
Operating Temperature Range ............... – 40°C to 85°C
Specified Temperature Range (Note 3).. – 40°C to 85°C
Junction Temperature
FE Package ....................................................... 150°C
UE Package ...................................................... 125°C
Storage Temperature Range
FE Package ....................................... –65°C to 150°C
UE Package ...................................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
U
W U
PACKAGE/ORDER INFORMATION
TOP VIEW
ORDER PART
ORDER PART
–
NUMBER
NUMBER
–
V
1
2
20
V
TOP VIEW
NC
–IN
19 NC
LT1739CFE
LT1739IFE
LT1739CUE
LT1739IUE
–
–IN A
+IN A
1
2
3
4
5
6
12 V
3
18 OUT
+
11 OUT A
+
+IN
4
17
V
SHDN
10
9
V
V
SHDN
SHDNREF
+IN
5
16 NC
+
SHDNREF
+IN B
6
15 NC
+
7
14
V
8
OUT B
UE PART
MARKING
–
–IN
8
13 OUT
–IN B
7
V
NC
9
12 NC
–
UE12 PACKAGE
12-LEAD (4mm × 3mm) PLASTIC DFN
–
V
10
11
V
1739
1739I
TJMAX = 125°C, θJA = 60°C/W, θJC = 3°C/W (Note 4)
FE PACKAGE
20-LEAD PLASTIC TSSOP
UNDERSIDE METAL CONNECTED TO V –
TJMAX = 150°C, θJA = 40°C/W, θJC = 3°C/W (Note 4)
UNDERSIDE METAL CONNECTED TO V –
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C.
VCM = 0V, pulse tested, ±5V ≤ VS ≤ ±12V, VSHDNREF = 0V, RBIAS = 24.9k between V+ and SHDN unless otherwise noted. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage
1
5.0
7.5
mV
mV
OS
●
Input Offset Voltage Matching
0.3
5.0
7.5
mV
mV
●
●
Input Offset Voltage Drift
Input Offset Current
10
µV/°C
I
I
100
500
800
nA
nA
OS
●
●
●
Input Bias Current
±0.1
±4
±6
µA
µA
B
Input Bias Current Matching
100
500
800
nA
nA
e
Input Noise Voltage Density
Input Noise Current Density
f = 10kHz
f = 10kHz
8
nV/√Hz
pA/√Hz
n
i
0.8
n
1739fas, sn1739
2
LT1739
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C.
CM = 0V, pulse tested, ±5V ≤ VS ≤ ±12V, VSHDNREF = 0V, RBIAS = 24.9k between V+ and SHDN unless otherwise noted. (Note 3)
V
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
R
Input Resistance
V
= (V – 2V) to (V + 2V)
●
5
50
6.5
MΩ
MΩ
IN
CM
Differential
C
Input Capacitance
3
pF
IN
+
+
Input Voltage Range (Positive)
Input Voltage Range (Negative)
(Note 5)
(Note 5)
+
●
●
V – 2
V – 1
V
V
–
–
V + 1
V + 2
–
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain (Note 8)
V
= (V – 2V) to (V + 2V)
74
66
83
88
dB
dB
CM
●
●
●
●
●
●
●
●
V = ±4V to ±12V
S
74
66
dB
dB
A
V = ±12V, V
S
= ±10V, R = 40Ω
63
57
76
dB
dB
VOL
OUT
L
V = ±5V, V
S
= ±3V, R = 25Ω
60
54
70
dB
dB
OUT
L
V
Output Swing (Note 8)
V = ±12V, R = 100Ω
S
10.9
10.7
11.1
10.9
4.0
3.9
±V
±V
OUT
L
V = ±12V, I = 250mA
S
10.6
10.4
±V
±V
L
V = ±5V, R = 25Ω
S
3.7
3.5
±V
±V
L
V = ±5V, I = 250mA
S
3.6
3.4
±V
±V
L
I
I
Maximum Output Current (Note 8)
Supply Current per Amplifier
V = ±12V, R = 1Ω
500
1200
10
mA
OUT
S
S
L
V = ±12V, R
= 24.9k (Note 6)
8.0
6.7
13.5
15.0
mA
mA
mA
mA
mA
S
BIAS
●
V = ±12V, R
= 32.4k (Note 6)
= 43.2k (Note 6)
= 66.5k (Note 6)
8
6
4
S
BIAS
BIAS
BIAS
V = ±12V, R
S
V = ±12V, R
S
V = ±5V, R
= 24.9k (Note 6)
2.2
1.8
3.4
5.0
5.8
mA
mA
S
BIAS
●
●
Supply Current in Shutdown
Output Leakage in Shutdown
Channel Separation (Note 8)
V
V
= 0.4V
0.1
0.3
1
1
mA
mA
SHDN
SHDN
= 0.4V
V = ±12V, V
S
= ±10V, R = 40Ω
80
77
110
dB
dB
OUT
L
SR
Slew Rate
V = ±12V, A = –10, (Note 7)
300
100
600
200
–85
–82
200
V/µs
V/µs
dBc
S
V
V = ±5V, A = –10, (Note 7)
S
V
HD2
HD3
GBW
Differential 2nd Harmonic Distortion
Differential 3rd Harmonic Distortion
Gain Bandwidth
V = ±12V, A = 10, 2V , R = 50Ω, 1MHz
S V P-P L
V = ±12V, A = 10, 2V , R = 50Ω, 1MHz
dBc
S
V
P-P
L
f = 1MHz
MHz
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
maximum dissipation of the package is exceeded, the device will go into
thermal shutdown and be protected.
Note 2: Applies to short circuits to ground only. A short circuit between
the output and either supply may permanently damage the part when
operated on supplies greater than ±10V.
Note 5: Guaranteed by the CMRR tests.
+
Note 6: R
is connected between V and the SHDN pin, with the
BIAS
SHDNREF pin grounded.
Note 3: The LT1739C is guaranteed to meet specified performance from
0°C to 85°C and is designed, characterized and expected to meet these
extended temperature limits, but is not tested at –40°C. The LT1739I is
guaranteed to meet the extended temperature limits.
Note 4: Thermal resistance varies depending upon the amount of PC board
metal attached to the device and rate of air flow over the device. If the
Note 7: Slew rate is measured at ±5V on a ±10V output signal while
operating on ±12V supplies and ±1V on a ±3V output signal while
operating on ±5V supplies.
Note 8: This parameter of the LT1739CUE/LT1739IUE is 100% tested at
room temperature, but is not tested at –40°C, 0°C or 85°C.
1739fas, sn1739
3
LT1739
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Supply Current
Input Common Mode Range
vs Supply Voltage
Input Bias Current
vs Ambient Temperature
vs Ambient Temperature
+
15
14
13
12
11
10
9
200
180
160
140
120
100
80
V
T
= 25°C
V
I
= ±12V
S
PER AMPLIFIER = 10mA
V
= ±12V
BIAS
A
S
∆V > 1mV
R
= 24.9k TO SHDN
–0.5
–1.0
–1.5
–2.0
OS
S
V
= 0V
SHDNREF
2.0
1.5
1.0
0.5
60
8
40
7
20
6
–
V
0
5
–50 –30 –10
10
30
50
70
90
–50 –30 –10 10
30
50
70
90
2
4
8
10
12
14
6
SUPPLY VOLTAGE (±V)
TEMPERATURE (°C)
TEMPERATURE (°C)
1739 G03
1739 G01
1739 G02
Output Short-Circuit Current
vs Ambient Temperature
Output Saturation Voltage
vs Ambient Temperature
Input Noise Spectral Density
+
100
10
1
100
10
1
800
780
760
740
720
700
680
660
640
620
600
V
V
I
= ±12V
PER AMPLIFIER = 10mA
T
= 25°C
= ±12V
V
S
= ±12V
S
S
A
S
V
I
–0.5
–1.0
PER AMPLIFIER = 10mA
R
L
= 100Ω
S
e
i
I
I
= 250mA
n
LOAD
–1.5
SINKING
1.5
1.0
0.5
SOURCING
n
= 250mA
LOAD
R
L
= 100Ω
–
0.1
0.1
100k
V
–50
30
TEMPERATURE (°C)
70
–30 –10 10
50
90
–30 –10
30
50
70
90
–50
10
1
10
100
1k
10k
FREQUENCY (Hz)
TEMPERATURE (°C)
1739 G04
1739 G05
1739 G06
Open-Loop Gain and Phase
vs Frequency
–3dB Bandwidth
vs Supply Current
Slew Rate vs Supply Current
120
100
80
120
45
40
35
30
25
20
15
10
5
1000
900
800
700
600
500
400
300
200
100
0
T
= 25°C
= ±12V
= 10
A
S
V
T
= 25°C
= ±12V
= –10
= 1k
A
S
V
80
V
A
V
A
PHASE
40
R
= 100Ω
L
R
L
RISING
60
0
40
–40
–80
–120
–160
–200
–240
–280
FALLING
20
GAIN
0
–20
–40
–60
–80
T
= 25°C
= ±12V
= –10
A
S
V
V
A
R
= 100Ω
L
I
PER AMPLIFIER = 10mA
S
0
100k
1M
10M
100M
2
4
6
8
10
12
14
2
3
4
5
6
7
8
9
10 11 12 13 14 15
FREQUENCY (Hz)
SUPPLY CURRENT PER AMPLIFIER (mA)
SUPPLY CURRENT PER AMPLIFIER (mA)
1739 G07
1739 G08
1739 G09
1739fas, sn1739
4
LT1739
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Frequency Response
vs Supply Current
CMRR vs Frequency
PSRR vs Frequency
100
90
30
25
20
15
100
90
80
70
60
50
40
30
20
10
0
T
= 25°C
V
S
A
V
= ±12V
= 10
A
S
V
A
S
= ±12V
= 10
= 10mA PER AMPLIFIER
S
V
V
= ±12V
I
= 10mA PER AMPLIFIER
S
I
80
70
2mA PER AMPLIFIER
60
50
10
5
10mA PER AMPLIFIER
15mA PER AMPLIFIER
(–) SUPPLY
40
30
20
10
0
0
–5
(+) SUPPLY
–10
–15
–20
–10
0.1
1
10
100
1k
10k
100k
1M
10M 100M
0.01
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (Hz)
FREQUENCY (MHz)
1739 G10
1739 G12
1739 G11
Output Impedance vs Frequency
ISHDN vs VSHDN
Supply Current vs VSHDN
35
1000
100
10
2.5
2.0
1.5
T
= 25°C
±12V
A
S
T
V
V
= 25°C
= ±12V
SHDNREF
T
V
V
= 25°C
= ±12V
S
A
S
A
V
30
25
20
15
10
5
= 0V
= 0V
SHDNREF
I
PER
S
AMPLIFIER = 2mA
I
S
PER
AMPLIFIER = 10mA
1
1.0
0.5
0
I
PER
S
AMPLIFIER = 15mA
0.1
0.01
0
0.01
0.1
1
10
100
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
(V)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
(V)
FREQUENCY (MHz)
V
V
SHDN
SHDN
1739 G13
1739 G14
1739 G14
Differential Harmonic Distortion
vs Frequency
Differential Harmonic Distortion
vs Output Amplitude
–40
–50
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
f = 1MHz
V
= 10V
P-P
O
A
S
V
T
= 25°C
= ±12V
= 10
A
S
V
T
= 25°C
= ±12V
= 10
V
A
V
A
R
= 50Ω
L
R
= 50Ω
PER AMPLIFIER = 10mA
L
–60
I
S
PER AMPLIFIER = 10mA
I
S
HD3
HD2
–70
–80
HD3
–90
HD2
–100
0
2
4
6
8
10 12 14 16 18
100 200 300 400 500 600 700 800 900 1000
V
OUT(P-P)
FREQUENCY (kHz)
1739 G16
1739 G17
1739fas, sn1739
5
LT1739
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Differential Harmonic Distortion
vs Supply Current
Undistorted Output Swing
vs Frequency
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
20
15
10
5
V
V
A
= 10V
P-P
O
S
V
= ±12V
= 10
R
= 50Ω
L
f = 1MHz, HD3
f = 100kHz, HD2
SFDR > 40dB
T
= 25°C
= ±12V
= 10
A
S
V
V
A
f = 100kHz, HD3
f = 1MHz, HD2
R
I
= 50Ω
L
S
PER AMPLIFIER = 10mA
0
2
3
4
5
6
11
100k
300k
1M
3M
10M
7
8
9
10
FREQUENCY (Hz)
I
PER AMPLIFIER (mA)
SUPPLY
1739 G18
1739 G19
TEST CIRCUIT
SUPPLY BYPASSING
12V
+
12V
+
0.1µF
0.1µF
4.7µF
+
V
R
BIAS
4.7µF
0.1µF
+
+IN A
4.7µF
+
–
SHDN
V
–12V
OUT(P-P)
A
OUT A
–IN A
12.7Ω
1:2*
10k
1k
–12V
110Ω
OUT (+)
OUT (–)
R
≈ 50Ω
L
E
SPLITTER
100 LINE LOAD
IN
0.01µF
110Ω
49.9Ω
1k
MINICIRCUITS
ZSC5-2-2
10k
12.7Ω
–
–IN B
+IN B
OUT B
SHDNREF
1739 TC
B
V
+
–
*COILCRAFT X8390-A OR EQUIVALENT
AMPLITUDE SET AT EACH AMPLIFIER OUTPUT
V
OUTP-P
DISTORTION MEASURED ACROSS LINE LOAD
–12V
1739fas, sn1739
6
LT1739
W U U
APPLICATIO S I FOR ATIO
U
The LT1739 is a high speed, 200MHz gain bandwidth
product, dual voltage feedback amplifier with high output
current drive capability, 500mA source and sink. The
LT1739 is ideal for use as a line driver in xDSL data
communication applications. The output voltage swing
has been optimized to provide sufficient headroom when
operating from ±12V power supplies in full-rate ADSL
applications. The LT1739 also allows for an adjustment of
the operating current to minimize power consumption. In
addition, the LT1739 is available in small footprint
3mm × 4mm DFN and 20-lead TSSOP surface mount
package to minimize PCB area in multiport central office
DSL cards.
on supply current per amplifier with RBIAS connected
between the SHDN pin and the 12V V+ supply of the
LT1739 and the approximate design equations. Figure 3
illustratesthesamecontrolwithRBIAS connectedbetween
the SHDNREF pin and ground while the SHDN pin is tied
to V+. Either approach is equally effective.
SHDN
5I
2k
I
2I
2I
1k
To minimize signal distortion, the LT1739 amplifiers are
decompensated to provide very high open-loop gain at
high frequency. As a result each amplifier is frequency
stable with a closed-loop gain of 10 or more. If a closed-
loop gain of less than 10 is desired, external frequency
compensating components can be used.
TO
START-UP
I
BIAS
CIRCUITRY
TO AMPLIFIERS
BIAS CIRCUITRY
1739 F01
SHDNREF
2
I
I
=
I
= I
SHDN SHDNREF
BIAS
5
PER AMPLIFIER (mA) = 64 • I
SUPPLY
BIAS
Figure 1. Internal Current Biasing Circuitry
Setting the Quiescent Operating Current
30
25
+
V
S
= ±12V
V
= 12V
Power consumption and dissipation are critical concerns
in multiport xDSL applications. Two pins, Shutdown
(SHDN) and Shutdown Reference (SHDNREF), are pro-
vided to control quiescent power consumption and allow
for the complete shutdown of the driver. The quiescent
current should be set high enough to prevent distortion
induced errors in a particular application, but not so high
that power is wasted in the driver unnecessarily. A good
startingpointtoevaluatetheLT1739istosetthequiescent
current to 10mA per amplifier.
R
BIAS
SHDN
+
20
15
10
5
V
– 1.2V
• 25.6
≈
I
PER AMPLIFIER (mA)
+
S
R
+ 2k
BIAS
V
– 1.2V
R
=
• 25.6 – 2k
BIAS
I
PER AMPLIFIER (mA)
S
SHDNREF
0
7
10
40
70
100
130
160
190
R
BIAS
(kΩ)
1739 F02
Figure 2. RBIAS to V+ Current Control
TheinternalbiasingcircuitryisshowninFigure1.Ground-
ingtheSHDNREFpinanddirectlydrivingtheSHDNpinwith
a voltage can control the operating current as seen in the
Typical Performance Characteristics. When the SHDN pin
is less than SHDNREF + 0.4V, the driver is shut down and
consumes typically only 100µA of supply current and the
outputs are in a high impedance state. Part to part varia-
tions, however, will cause inconsistent control of the qui-
escentcurrentifdirectvoltagedriveoftheSHDNpinisused.
45
40
35
30
25
20
15
10
5
+
V
S
= ±12V
V
= 12V
SHDN
+
V
R
– 1.2V
• 64
≈
I
S
PER AMPLIFIER (mA)
+ 5k
BIAS
+
V
– 1.2V
R
BIAS
=
• 64 – 5k
I
S
PER AMPLIFIER (mA)
SHDNREF
R
BIAS
0
4
7
10 30 50 70 90 100 130 150 170 190 210 230 250 270 290
(kΩ)
Usingasingleexternalresistor, RBIAS, connectedinoneof
two ways provides a much more predictable control of the
quiescent supply current. Figure 2 illustrates the effect
R
BIAS
1739 F03
Figure 3. RBIAS to Ground Current Control
1739fas, sn1739
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LT1739
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APPLICATIO S I FOR ATIO
Logic Controlled Operating Current
LinearTechnologyforassistanceinimplementingasingle
supply design with operating current control. These
modes can be useful for overall system power manage-
ment when full power transmissions are not necessary.
The DSP controller in a typical xDSL application can have
I/O pins assigned to provide logic control of the LT1739
line driver operating current. As shown in Figure 4 one or
two logic control inputs can set two or four different
operating modes. The logic inputs add or subtract current
to the SHDN input to set the operating current. The one
logic input example selects the supply current to be either
full power, 10mA per amplifier or just 2mA per amplifier,
which significantly reduces the driver power consumption
while maintaining less than 2Ω output impedance to
frequencies less than 1MHz. This low power mode retains
termination impedance at the amplifier outputs and the
line driving back termination resistors. With this termina-
tion, while a DSL port is not transmitting data, it can still
sense a received signal from the line across the back-
termination resistors and respond accordingly.
Shutdown and Recovery
The ultimate power saving action on a completely idle port
istofullyshutdownthelinedriverbypullingtheSHDNpin
to within 0.4V of the SHDNREF potential. As shown in
Figure 5 complete shutdown occurs in less than 10µs and,
more importantly, complete recovery from the shut down
state to full operation occurs in less than 2µs. The biasing
circuitry in the LT1739 reacts very quickly to bring the
amplifiers back to normal operation.
VSHDN
SHDNREF = 0V
The two logic input control provides two intermediate
(approximately 7mA per amplifier and 5mA per amplifier)
operating levels between full power and termination
modes. For proper operation of the current control cir-
cuitry, it is necessary that the SHDNREF pin be biased at
least 2V more positive than V–. In single supply applica-
tions where V– is at ground potential, special attention to
the DC bias of the SHDNREF pin is required. Contact
AMPLIFIER
OUTPUT
1794 F05
Figure 5. Shutdown and Recovery Timing
12V OR V
LOGIC
Two Control Inputs
RESISTOR VALUES (kΩ)
R
SHDN
V
Power Dissipation and Heat Management
LOGIC
R
SHDN
TO V (12V)
R
TO V
LOGIC
CC
SHDN
3V 3.3V 5V
R
R
C1
V
LOGIC
3V 3.3V 5V
V
C1
SHDN
R
R
R
V
40.2 43.2 60.4 4.99 6.81 19.6
11.5 13.0 21.5 8.66 10.7 20.5
19.1 22.1 36.5 14.3 17.8 34.0
SUPPLY CURRENT PER AMPLIFIER (mA)
C0
xDSL applications require the line driver to dissipate a
significant amount of power and heat compared to other
components in the system. The large peak to RMS varia-
tions of DMT and CAP ADSL signals require high supply
voltages to prevent clipping, and the use of a step-up
transformer to couple the signal to the telephone line can
require high peak current levels. These requirements
result in the driver package having to dissipate significant
amounts of power. Several multiport cards inserted into
a rack in an enclosed central office box can add up to
many, many watts of power dissipation in an elevated
ambienttemperatureenvironment. TheLT1739hasbuilt-
in thermal shutdown circuitry that will protect the ampli-
fiers if operated at excessive temperatures, however data
SHDN
0V
V
C0
2k
C1
CO
C0
V
C1
H
H
L
H
L
H
L
10
7
5
10
7
5
10
7
5
10
7
5
10
7
5
10
7
5
SHDNREF
L
2
2
2
2
2
2
12V OR V
One Control Input
LOGIC
RESISTOR VALUES (kΩ)
R
SHDN
V
R
TO V (12V)
R
SHDN
TO V
LOGIC
SHDN
3V 3.3V 5V
CC
LOGIC
R
C
V
R
3V 3.3V 5V
LOGIC
V
C
0V
SHDN
40.2 43.2 60.4 4.99 6.81 19.6
7.32 8.25 13.7 5.49 6.65 12.7
SUPPLY CURRENT PER AMPLIFIER (mA)
10
2
SHDN
R
C
2k
V
C
H
L
10
2
10
2
10
2
10
2
10
2
1739 F04
SHDNREF
transmissions will be seriously impaired. It is important in
Figure 4. Providing Logic Input Control of Operating Current
1739fas, sn1739
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LT1739
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APPLICATIO S I FOR ATIO
U
thedesignofthePCBandcardenclosuretotakemeasures
to spread the heat developed in the driver away to the
ambientenvironmenttopreventthermalshutdown(which
occurs when the junction temperature of the LT1739
exceeds 165°C).
the upper power transistor of one amplifier, while sourc-
ing current, and the lower power transistor of the other
amplifier, while sinking current. The total device power
dissipation is then:
PD = PQUIESCENT + PQ(UPPER) + PQ(LOWER)
Estimating Line Driver Power Dissipation
PD = (V+ – V–) • IQ + (V+ – VOUTARMS) •
ILOAD + (V– – VOUTBRMS) • ILOAD
Figure 6 is a typical ADSL application shown for the
purpose of estimating the power dissipation in the line
driver. Due to the complex nature of the DMT signal,
which looks very much like noise, it is easiest to use the
RMS values of voltages and currents for estimating the
driver power dissipation. The voltage and current levels
shown for this example are for a full-rate ADSL signal
driving 20dBm or 100mWRMS of power on to the 100Ω
telephone line and assuming a 0.5dBm insertion loss in
the transformer. The quiescent current for the LT1739 is
set to 10mA per amplifier.
With no signal being placed on the line and the amplifier
biased for 10mA per amplifier supply current, the quies-
cent driver power dissipation is:
PDQ = 24V • 20mA = 480mW
This can be reduced in many applications by operating
with a lower quiescent current value.
When driving a load, a large percentage of the amplifier
quiescent current is diverted to the output stage and
becomes part of the load current. Figure 7 illustrates the
total amount of biasing current flowing between the + and
– power supplies through the amplifiers as a function of
load current. As much as 60% of the quiescent no load
operating current is diverted to the load.
ThepowerdissipatedintheLT1739isacombinationofthe
quiescent power and the output stage power when driving
a signal. The two amplifiers are configured to place a
differential signal on to the line. The Class AB output stage
in each amplifier will simultaneously dissipate power in
12V
24.9k – SETS I PER AMPLIFIER = 10mA
Q
20mA DC
2V
RMS
SHDN
+IN
+
17.4Ω
A
–
1k
1:1.7
110Ω
110Ω
I
= 57mA
RMS
100Ω
3.16V
RMS
LOAD
1000pF
1k
–
+
17.4Ω
1739 F06
B
SHDNREF
–IN
–12V
–2V
RMS
Figure 6. Estimating Line Driver Power Dissipation
1739fas, sn1739
9
LT1739
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APPLICATIO S I FOR ATIO
25
compact circuit layout to allow more ports to be imple-
mented on any given size PCB.
20
15
10
5
Fortunately xDSL circuit boards use multiple layers of
metal for interconnection of components. Areas of metal
beneath the LT1739 connected together through several
small 13 mil vias can be effective in conducting heat away
from the driver package. The use of inner layer metal can
free up top and bottom layer PCB area for external compo-
nent placement.
0
–240 –200 –160 –120 –80
–40
0
40
80
120
160
200
240
I
(mA)
LOAD
1739 F07
Figure8showsexamplesofPCBmetalbeingusedforheat
spreading. These are provided as a reference for what
might be expected when using different combinations of
metalareaondifferentlayersofaPCB.Theseexamplesare
with a 4-layer board using 1oz copper on each. The most
effective layers for spreading heat are those closest to the
LT1739 junction. The small TSSOP and DFN packages are
very effective for compact line driver designs. Both pack-
ages also have an exposed metal heat sinking pad on the
bottom side which, when soldered to the PCB top layer
metal, directly conducts heat away from the IC junction.
Solderingthethermalpadtotheboardproducesathermal
resistance from junction to case, θJC, of approximately
3°C/W.
Figure 7. IQ vs ILOAD
At full power to the line the driver power dissipation is:
PD(FULL) = 24V • 8mA + (12V – 2VRMS) • 57mARMS
+ [|–12V – (–2VRMS)|] • 57mARMS
PD(FULL) = 192mW + 570mW + 570mW = 1.332W*
The junction temperature of the driver must be kept less
than the thermal shutdown temperature when processing
a signal. The junction temperature is determined from the
following expression:
TJ = TAMBIENT (°C) + PD(FULL) (W) • θJA (°C/W)
θJA is the thermal resistance from the junction of the
LT1739 to the ambient air, which can be minimized by
heat-spreading PCB metal and airflow through the enclo-
sure as required. For the example given, assuming a
maximum ambient temperature of 85°C and keeping the
junction temperature of the LT1739 to 140°C maximum,
themaximumthermalresistancefromjunctiontoambient
required is:
Asaminimum, theareadirectlybeneaththepackageonall
PCB layers can be used for heat spreading. Limiting the
area of metal to just that of the exposed metal heat sinking
pad however is not very effective, particularly if the ampli-
fiers are required to dissipate significant power levels.
This is shown in Figure 8 for both the TSSOP and DFN
packages. Expanding the area of metal on various layers
significantly reduces the overall thermal resistance. If
possible, an entire unbroken plane of metal close to the
heat sinking pad is best for multiple drivers on one PCB
card. The addition of vias (small 13mil or smaller holes
which fill during PCB plating) connecting all layers of heat
spreading metal also helps to reduce operating tempera-
tures of the driver. These too are shown in Figure 8.
140°C – 85°C
θJA(MAX)
=
= 41.3°C/ W
1.332W
Heat Sinking Using PCB Metal
Designing a thermal management system is often a trial
and error process as it is never certain how effective it is
until it is manufactured and evaluated. As a general rule,
the more copper area of a PCB used for spreading heat
away from the driver package, the more the operating
junction temperature of the driver will be reduced. The
limit to this approach however is the need for very
Important Note: The metal planes used for heat sinking
the LT1739 are electrically connected to the negative
supply potential of the driver, typically –12V. These
planes must be isolated from any other power planes
used in the board design.
*Note:Designtechniquesexisttosignificantlyreducethisvalue.(SeeLineDrivingBackTermination)
1739fas, sn1739
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LT1739
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When PCB cards containing multiple ports are inserted
into a rack in an enclosed cabinet, it is often necessary to
provide airflow through the cabinet and over the cards. As
seen in the graph of Figure 8, this is also very effective in
further reducing the junction-to-ambient thermal resis-
tance of each line driver.
STILL AIR θ
PACKAGE
TOP LAYER
2ND LAYER
3RD LAYER
BOTTOM LAYER
JA
TSSOP
100°C/W
TSSOP
50°C/W
TSSOP
45°C/W
DFN
130°C/W
DFN
75°C/W
1739 F08a
Typical Reduction in θ with
JA
Laminar Airflow Over the Device
0
–10
–20
–30
–40
–50
–60
% REDUCTION RELATIVE
TO θ IN STILL AIR
JA
0
100 200 300 400 500 600 700 800 900 1000
AIRFLOW (LINEAR FEET PER MINUTE, lfpm)
1739 F08b
Figure 8. Examples of PCB Metal Used for Heat Dissipation. Driver Package Mounted on Top Layer.
Heat Sink Pad Soldered to Top Layer Metal. Metal Areas Drawn to Scale of Package Size
1739fas, sn1739
11
LT1739
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APPLICATIO S I FOR ATIO
Layout and Passive Components
parallel combination of RC and RG is less than or equal to
RF/9. For lowest distortion and DC output offset, a series
capacitor, CC, can be used to reduce the noise gain at
lower frequencies. The break frequency produced by RC
and CC should be less than 5MHz to minimize peaking.
With a gain bandwidth product of 200MHz the LT1739
requires attention to detail in order to extract maximum
performance. Use a ground plane, short lead lengths and
acombinationofRF-qualitysupplybypasscapacitors(i.e.,
0.1µF). As the primary applications have high drive cur-
rent, use low ESR supply bypass capacitors (1µF to 10µF).
Figure 10 shows compensation in the noninverting con-
figuration. The RC, CC network acts similarly to the invert-
ing case. The input impedance is not reduced because the
network is bootstrapped. This network can also be placed
between the inverting input and an AC ground.
The parallel combination of the feedback resistor and gain
settingresistorontheinvertinginputcancombinewiththe
input capacitance to form a pole that can cause frequency
peaking. In general, use feedback resistors of 1k or less.
Anothercompensationschemefornoninvertingcircuitsis
shown in Figure 11. The circuit is unity gain at low
frequency and a gain of 1 + RF/RG at high frequency. The
DC output offset is reduced by a factor of ten. The
techniques of Figures 10 and 11 can be combined as
shown in Figure 12. The gain is unity at low frequencies,
1 + RF/RG at mid-band and for stability, a gain of 10 or
greater at high frequencies.
Compensation
The LT1739 is stable in a gain 10 or higher for any supply
andresistiveload.Itiseasilycompensatedforlowergains
with a single resistor or a resistor plus a capacitor.
Figure 9showsthatforinvertinggains, aresistorfromthe
inverting node to AC ground guarantees stability if the
R
R
V
V
F
O
= 1 +
+
–
I
V
G
I
R
F
R
C
V
(R || R ) ≤ R /9
C
O
C
G
F
V
V
–R
F
O
R
C
=
G
–
+
1
R
I
G
(OPTIONAL)
< 5MHz
V
I
2πR C
C
C
R
F
(R || R ) ≤ R /9
R
V
C
G
F
C
O
C
C
1
R
G
< 5MHz
(OPTIONAL)
2πR C
C
C
1739 F09
1739 F10
Figure 9. Compensation for Inverting Gains
Figure 10. Compensation for Noninverting Gains
V
V
O
+
+
–
= 1 (LOW FREQUENCIES)
V
I
V
G
I
i
R
F
R
C
V
O
= 1 +
(HIGH FREQUENCIES)
C
V
O
R
G
–
C
R
G
≤ R /9
V
O
F
R
F
= 1 AT LOW FREQUENCIES
R
F
V
I
1
< 5MHz
R
F
R
2πR C
G
C
= 1 +
= 1 +
AT MEDIUM FREQUENCIES
R
G
R
C
G
C
BIG
C
R
F
(R || R )
AT HIGH FREQUENCIES
C
G
1739 F11
1739 F12
Figure 11. Alternate Noninverting Compensation
Figure 12. Combination Compensation
1739fas, sn1739
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LT1739
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In differential driver applications, as shown on the first
page of this data sheet, it is recommended that the gain
setting resistor be comprised of two equal value resistors
connected to a good AC ground at high frequencies. This
ensures that the feedback factor of each amplifier remains
less than 0.1 at any frequency. The midpoint of the
resistors can be directly connected to ground, with the
resulting DC gain to the VOS of the amplifiers, or just
bypassed to ground with a 1000pF or larger capacitor.
Eliminating ∆VP, we get the following:
(1 + RP2/RP1) = (1 + RF/RG)/(1 – 1/n)
For example, reducing RBT by a factor of n = 4, and with an
amplifer gain of (1 + RF/RG) = 10 requires that RP2/RP1
= 12.3.
Note that the overall gain is increased:
RP2 / R +R
VO
V
I
(
)
P2
P1
=
1+ 1/n / 1+R /R − R / R +R
) (
(
[
)
]
(
)
[
]
F
G
P1 P2
P1
Line Driving Back-Termination
The standard method of cable or line back-termination is
shown in Figure 13. The cable/line is terminated in its
characteristic impedance (50Ω, 75Ω, 100Ω, 135Ω, etc.).
Aback-terminationresistoralsoequaltothechararacteristic
impedance should be used for maximum pulse fidelity of
outgoing signals, and to terminate the line for incoming
signals in a full-duplex application. There are three main
drawbacks to this approach. First, the power dissipated in
the load and back-termination resistors is equal so half of
the power delivered by the amplifier is wasted in the
termination resistor. Second, the signal is halved so the
gain of the amplifer must be doubled to have the same
overall gain to the load. The increase in gain increases
noise and decreases bandwidth (which can also increase
distortion). Third, the output swing of the amplifier is
doubled which can limit the power it can deliver to the load
for a given power supply voltage.
CABLE OR LINE WITH
CHARACTERISTIC IMPEDANCE R
L
+
–
V
I
R
BT
V
O
R
L
R
F
1739 F13
R
= R
1
2
BT
O
L
V
V
R
G
=
(1 + R /R )
F
G
I
Figure 13. Standard Cable/Line Back Termination
R
P2
R
P1
+
–
V
I
V
R
V
O
A
BT
V
P
R
L
R
F
1739 F14
An alternate method of back-termination is shown in
Figure 14. Positive feedback increases the effective back-
termination resistance so RBT can be reduced by a factor
ofn.Toanalyzethiscircuit,firstgroundtheinput.AsRBT
RL/n, and assuming RP2>>RL we require that:
R
G
R
L
n
FOR R
1 +
=
BT
1
n
R
R
P1
F
= 1 –
=
R
R
+ R
(
G)(
)
P1 P2
R
/(R + R
)
P1
P2 P2
∆VA = ∆VO (1 – 1/n) to increase the effective value of
V
O
R
P1
1 + 1/n
=
–
V
R
+ R
I
P2
P1
R
F
RBT by n.
1 +
R
(
)
G
∆VP = ∆VO (1 – 1/n)/(1 + RF/RG)
∆VO = ∆VP (1 + RP2/RP1)
Figure 14. Back Termination Using Postive Feedback
1739fas, sn1739
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LT1739
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APPLICATIO S I FOR ATIO
over the standard line driving approach resulting in lower
peak current requirements. With lower current and less
power loss in the back termination resistors, this driver
dissipatesonly1Wofpower, a30%reduction. (Additional
power savings are possible by further reducing the termi-
nation resistors’ value).
V
+
I
V
R
BT
A
V
O
–
R
L
n
FOR R
n =
=
BT
R
F
1
R
F
1 –
R
R
R
R
G
G
L
L
R
P
R
R
P
P
R
R
R
F
F
Whilethepowersavingsofpositivefeedbackareattractive
there is one important system consideration to be ad-
dressed, received signal sensitivity. The signal received
from the line is sensed across the back termination resis-
tors. With positive feedback, signals are present on both
ends of the RBT resistors, reducing the sensed amplitude.
Extra gain may be required in the receive channel to
compensate,oracompletelyseparatereceivepathmaybe
implementedthroughaseparatelinecouplingtransformer.
1 +
+
R
V
O
G
P
=
R
F
V
I
R
R
F
2 1 –
(
)
P
–
+
R
BT
–V
O
1739 F15
–V
A
–V
I
Figure 15. Back Termination Using Differential Postive Feedback
A demo board, DC306A-C, is available for the LT1739CFE.
This demo board is a complete line driver with an LT1361
receiverincluded. Itallowstheevaluationofbothstandard
and active termination approaches. It also has circuitry
built in to evaluate the effects of operating with reduced
supply current. The schematic of this demo board is
shown in Figure 17.
A simpler method of using positive feedback to reduce the
back-termination is shown in Figure 15. In this case, the
drivers are driven differentially and provide complemen-
tary outputs. Grounding the inputs, we see there is invert-
ing gain of –RF/RP from –VO to VA
∆VA = ∆VO (RF/RP)
and assuming RP >> RL, we require
∆VA = ∆VO (1 – 1/n)
solving
Considerations for Fault Protection
The basic line driver design, shown on the front page of
this data sheet, presents a direct DC path between the
outputs of the two amplifiers. An imbalance in the DC
biasing potentials at the noninverting inputs through
eitherafaultconditionorduringturn-onofthesystemcan
create a DC voltage differential between the two amplifier
outputs. This condition can force a considerable amount
of current to flow as it is limited only by the small valued
back-termination resistors and the DC resistance of the
transformerprimary.Thishighcurrentcanpossiblycause
the power supply voltage source to drop significantly
impacting overall system performance. If left unchecked,
the high DC current can heat the LT1739 to thermal
shutdown.
RF/RP = 1 – 1/n
So to reduce the back-termination by a factor of 3 choose
RF/RP = 2/3. Note that the overall gain is increased to:
VO/VI = (1 + RF/RG + RF/RP)/[2(1 – RF/RP)]
Using positive feedback is often referred to as active
termination.
Figure 18 shows a full-rate ADSL line driver incorporating
positive feedback to reduce the power lost in the back
terminationresistorsby40%yetstillmaintainstheproper
impedance match to the100Ω characteristic line imped-
ance. This circuit also reduces the transformer turns ratio
1739fas, sn1739
14
LT1739
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Using DC blocking capacitors, as shown in Figure 16, to
AC couple the signal to the transformer eliminates the
possibility for DC current to flow under any conditions.
These capacitors should be sized large enough to not
impairthefrequencyresponsecharacteristicsrequiredfor
the data transmission.
create fast voltage transitions themselves that can be
coupled through the transformer to the outputs of the line
driver. Several hundred volt transient signals can appear
at the primary windings of the transformer with current
intothedriveroutputslimitedonlybythebacktermination
resistors. While the LT1739 has clamps to the supply rails
at the output pins, they may not be large enough to handle
thesignificanttransientenergy. Externalclampingdiodes,
such as BAV99s, at each end of the transformer primary
help to shunt this destructive transient energy away from
the amplifier outputs.
Another important fault related concern has to do with
very fast high voltage transients appearing on the tele-
phone line (lightning strikes for example). TransZorbs®,
varistors and other transient protection devices are often
used to absorb the transient energy, but in doing so also
TransZorb is a registered trademark of General Instruments, GSI
12V
12V –12V
24.9k
SHDN
0.1µF
BAV99
+IN
+
12.7Ω
1/2
LT1739
–
1k
1:2
110Ω
110Ω
LINE
LOAD
1000pF
1k
0.1µF
–
12.7Ω
1/2
LT1739
SHDNREF
BAV99
–IN
+
–12V
12V –12V
1739 F16
Figure 16. Protecting the Driver Against Load Faults and Line Transients
1739fas, sn1739
15
LT1739
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APPLICATIO S I FOR ATIO
V
CC
C1
0.1µF
C8
0.1µF
100V
R1
10
E4
14
15.4Ω
1/2W
2010
LINE (+)
4
E2
U1
LT1121CST-5
SOT233
5V
DD
+
17
18
DRV (+)
U2A
LT1739CFE
V
2
7
JP1
1
3
R2
10k
R23
OPT
3
3
1
OUT
IN
5
–
GND
2
C3
C2
4
+
+
2
C9
1µF
25V
3216
1
1µF
25V
3216
8
6
0.1µF
V
CC
20 11 10
1
C15
OPT
R3
1k
E5
LINE (–)
V
COILCRAFT
X8504-A
EE
R21
10k
C12
0.1µF
100V
3
E1
R4
R24
107Ω
V
CC
C5
C7
R22
10k
2.49k
+
+
+
2
R5
OPT
C6
10µF
35V
1µF
25V
3216
C18
OPT
1206
0.1µF
PLACE C4 AND C5
AS CLOSE TO
U2 AS POSSIBLE
JP6
C16
1000pF
R25
107Ω
7343
R6
1
E3
2.49k
GND
C4
C11
1µF
25V
3216
0.1µF
25V
C10
0.1µF
E7
RCV (+)
IN
0603
R7
1k
R8
E6
15.4Ω
1/2W
2010
V
EE
7
8
E8
DRV (–)
+
JP2
2
1
U2B
LT1739CFE
3
13
C13
0.1µF
V
CC
R26
OPT
6
–
3
8
19
+
C17
OPT
U3A
LT1361CS8
1
E9
RCV (+)
R9
R10
1k
12
2
9
10k
V
2
DD
ON/OFF
ON
1
–
2
4
3
V
EE
JP3
7
5
8
E10
ON/OFF
R11
1.6k
R12
1k
V
EE
+
C14
0.1µF
U4B
R13
10k
LT1541CS8
6
R15
OPT
R14
1.6k
–
4
R16
1k
FIXED
ADJ
3
R19
1k
2
1
3
6
5
E11
C0NTROL
+
–
V
JP4
FMMT3904
R17
21.5k
U3B
7
U4A
1
Q1
E12
R18
10k
LT1361CS8
LT1541CS8
RCV (–)
1
2
2
–
+
R20
9.31k
2
1
3
E13
RCV (–)
IN
JP5
V
BIAS
V
BIAS
1739 SD
Figure 17. LT1739, LT1361 ADSL Demo Board (DC306A-C)
1739fas, sn1739
16
LT1739
W
W
SI PLIFIED SCHE ATIC
(one amplifier shown)
+
V
Q9
Q10
Q13
Q17
Q3
Q4
Q7
Q8
C1
Q14
R1
Q1
Q5
+IN
C2
OUT
Q6
Q2
–IN
Q15
Q18
Q16
Q12
Q11
–
V
1739 SS
1739fas, sn1739
17
LT1739
U
PACKAGE DESCRIPTIO
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CA
6.40 – 6.60*
(.252 – .260)
4.95
(.195)
4.95
(.195)
20 1918 17 16 15 14 1312 11
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
2.74
(.108)
6.40
BSC
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0° – 8°
0.65
(.0256)
BSC
0.45 – 0.75
(.018 – .030)
0.09 – 0.20
(.0036 – .0079)
0.05 – 0.15
(.002 – .006)
FE20 (CA) TSSOP 0203
0.195 – 0.30
(.0077 – .0118)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
1739fas, sn1739
18
LT1739
U
PACKAGE DESCRIPTIO
UE12 Package
12-Lead Plastic DFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1695)
0.58 ±0.05
3.40 ±0.05
2.24 ±0.05 (2 SIDES)
1.70 ±0.05
0.23 ± 0.05
0.50
BSC
3.30 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.38 ± 0.10
4.00 ±0.10
(2 SIDES)
R = 0.115
TYP
7
12
R = 0.20
TYP
3.00 ±0.10 1.70 ± 0.10
(2 SIDES)
(2 SIDES)
PIN 1
TOP MARK
PIN 1
NOTCH
(UE12) DFN 0102
6
0.23 ± 0.05
1
0.75 ±0.05
0.200 REF
0.50
BSC
3.30 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE IS A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
1739fas, sn1739
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LT1739
U
TYPICAL APPLICATIO
12V
24.9k
SHDN
+IN
+
13.7Ω
1/2
LT1739
–
1k
1:1.2*
1.65k
1.65k
182Ω
100Ω
LINE
1000pF
182Ω
1k
*COILCRAFT X8502-A OR EQUIVALENT
1W DRIVER POWER DISSIPATION
1.15W POWER CONSUMPTION
–
13.7Ω
SHDNREF
1/2
LT1739
–IN
+
1739 F17
–12V
Figure 18. ADSL Line Driver Using Active Termination
RELATED PARTS
PART NUMBER
LT1361
DESCRIPTION
COMMENTS
±15V Operation, 1mV V , 1µA I
Dual 50MHz, 800V/µs Op Amp
OS
B
LT1794
Dual 500mA, 200MHz xDSL Line Driver
Dual 500mA, 50MHz Current Feedback Amplifier
Dual 100MHz, 750V/µs, 8nV/√Hz Op Amp
Dual 200mA, 700MHz Op Amp
ADSL CO Driver, Extended Output Swing, Low Power
Shutdown/Current Set Function, ADSL CO Driver
Low Noise, Low Power Differential Receiver, 4mA/Amplifier
12V Operation, 7mA/Amplifier, ADSL Modem Line Driver
12V Operation, MSOP Package, ADSL Modem Line Driver
ADSL CO Driver in SSOP Package
LT1795
LT1813
LT1886
LT1969
Dual 200mA, 700MHz Op Amp with Power Control
Dual 500mA, 200MHz xDSL Line Driver
LT6300
1739fas, sn1739
LT/TP 0602 1.5K REV A • PRINTED IN THE USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2001
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