LT1765EFE#PBF [Linear]
LT1765 - Monolithic 3A, 1.25MHz Step-Down Switching Regulators; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C;
| 型号： | LT1765EFE#PBF |
| 厂家： | 
Linear |
| 描述： | LT1765 - Monolithic 3A, 1.25MHz Step-Down Switching Regulators; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总20页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
Monolithic 3A, 1.25MHz
Step-Down Switching Regulator
FEATURES
DESCRIPTION
The LT®1765 is a 1.25MHz monolithic buck switching
regulator. A high efficiency 3A, 0.09Ω switch is included
on the die together with all the control circuitry required
to construct a high frequency, current mode switching
regulator. Current mode control provides fast transient
response and excellent loop stability.
n
3A Switch in a Thermally Enhanced 16-Lead
TSSOP or 8-Lead SO Package
n
Constant 1.25MHz Switching Frequency
n
Wide Operating Voltage Range: 3V to 25V
n
High Efficiency 0.09Ω Switch
1.2V Feedback Reference Voltage
n
n
Uses Low Profile Surface Mount Components
New design techniques achieve high efficiency at high
switching frequencies over a wide operating voltage
range. A low dropout internal regulator maintains con-
sistent performance over a wide range of inputs from
24V systems to Li-Ion batteries. An operating supply
current of 1mA improves efficiency, especially at lower
output currents. Shutdown reduces quiescent current to
15μA. Maximum switch current remains constant at all
duty cycles. Synchronization allows an external logic level
signal to increase the internal oscillator into the range of
1.6MHz to 2MHz.
n
Low Shutdown Current: 15μA
n
Synchronizable to 2MHz
n
Current Mode Loop Control
n
Constant Maximum Switch Current Rating at
All Duty Cycles*
n
Available in 8-Lead SO and 16-Lead Thermally
Enhanced TSSOP Packages
APPLICATIONS
n
DSL Modems
Full cycle-by-cycle current control and thermal shutdown
are provided. High frequency operation allows the reduc-
tion of input and output filtering components and permits
the use of chip inductors.
n
Portable Computers
n
Regulated Wall Adapters
n
Battery-Powered Systems
n
Distributed Power
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
*Patent Pending
TYPICAL APPLICATION
5V to 3.3V Step-Down Converter
Efficiency vs Load Current
90
CMDSH-3
V
V
= 10V
OUT
IN
= 5V
0.18μF
85
80
75
70
1.5μH
OUTPUT
3.3V
BOOST
INPUT
5V
V
IN
V
SW
2.5A
2.2μF
CERAMIC
LT1765-3.3
OFF ON
SHDN
SYNC GND
FB
V
C
4.7μF
CERAMIC
2.2nF
UPS120
1765 TA01
1.0
1.5
0
2.0
0.5
SWITCH CURRENT (A)
1765 • TAO1a
1765fd
1
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
(Note 1)
ABSOLUTE MAXIMUM RATINGS
Input Voltage ........................................................... 25V
BOOST Pin Above SW ............................................. 20V
Max BOOST Pin Voltage............................................35V
SHDN Pin................................................................. 25V
FB Pin Current......................................................... 1mA
SYNC Pin Current ................................................... 1mA
Operating Junction Temperature Range
(Note 2)................................................. –40°C to 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................ 300°C
PIN CONFIGURATION
TOP VIEW
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
NC
TOP VIEW
BOOST
BOOST
1
2
3
4
8
7
6
5
SYNC
V
SYNC
IN
V
IN
V
C
V
IN
V
C
17
SW
SW
FB
SW
FB
SHDN
NC
GND
SHDN
NC
S8 PACKAGE
8-LEAD PLASTIC SO
GND
GND
T
= 125°C, θ = 90°C/W, θ
= 30°C/W
JMAX
JA
JC(PIN 4)
FE PACKAGE
16-LEAD PLASTIC TSSOP
GROUND PIN CONNECTED TO LARGE COPPER AREA
θ
= 45°C/W, θ
= 10°C/W
JC(PAD)
JA
EXPOSED PAD (PIN 17) SOLDERED TO LARGE COPPER PLANE
ORDER INFORMATION
LEAD FREE FINISH
LT1765EFE#PBF
LT1765EFE-1.8#PBF
LT1765EFE-2.5#PBF
LT1765EFE-3.3#PBF
LT1765EFE-5#PBF
LT1765ES8#PBF
LEAD BASED FINISH
LT1765EFE
TAPE AND REEL
PART MARKING
1765EFE
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
LT1765EFE#TRPBF
LT1765EFE-1.8#TRPBF
LT1765EFE-2.5#TRPBF
LT1765EFE-3.3#TRPBF
LT1765EFE-5#TRPBF
LT1765ES8#TRPBF
TAPE AND REEL
16-Lead Plastic TSSOP
16-Lead Plastic TSSOP
16-Lead Plastic TSSOP
16-Lead Plastic TSSOP
16-Lead Plastic TSSOP
8-Lead Plastic SO
1765EFE-1.8
1765EFE-2.5
1765EFE-3.3
1765EFE-5
1765
PART MARKING
1765EFE
PACKAGE DESCRIPTION
16-Lead Plastic TSSOP
16-Lead Plastic TSSOP
16-Lead Plastic TSSOP
16-Lead Plastic TSSOP
16-Lead Plastic TSSOP
8-Lead Plastic SO
LT1765EFE#TR
LT1765EFE-1.8
LT1765EFE-1.8#TR
LT1765EFE-2.5#TR
LT1765EFE-3.3#TR
LT1765EFE-5#TR
1765EFE-1.8
1765EFE-2.5
1765EFE-3.3
1765EFE-5
1765
LT1765EFE-2.5
LT1765EFE-3.3
LT1765EFE-5
LT1765ES8
LT1765ES8#TR
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
1765fd
2
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VIN = 15V, VC = 0.8V, Boost = VIN + 5V, SHDN, SYNC and switch open unless otherwise noted.
PARAMETER
CONDITIONS
MIN
3
TYP
4
MAX
6
UNITS
A
Maximum Switch Current Limit
Oscillator Frequency
Switch On Voltage Drop
l
l
l
l
3.3V < V < 25V
1.1
1.25
270
2.6
1
1.6
430
2.73
1.3
MHz
mV
V
IN
I = 3A
V
IN
V
IN
Undervoltage Lockout
Supply Current
(Note 3)
2.47
mA
Shutdown Supply Current
V
SHDN
= 0V, V = 25V, V = 0V
15
35
55
μA
μA
IN
SW
l
Feedback Voltage
3V < V < 25V, 0.4V < V < 0.9V
LT1765 (Adj)
1.182
1.176
1.2
1.218
1.224
V
V
IN
C
l
l
l
l
l
l
(Note 3)
LT1765-1.8
LT1765-2.5
LT1765-3.3
LT1765-5
1.764
2.45
3.234
4.9
1.8
2.5
1.836
2.55
3.366
5.1
V
V
3.3
V
5
V
FB Input Current
LT1765 (Adj)
–0.25
–0.5
μA
l
l
l
l
FB Input Resistance
LT1765-1.8
LT1765-2.5
LT1765-3.3
LT1765-5
10.5
14.7
19
15
21
27.5
42
21
30
39
60
kΩ
kΩ
kΩ
kΩ
29
FB Error Amp Voltage Gain
0.4V < V < 0.9V
150
500
80
350
850
120
110
5
C
l
l
l
FB Error Amp Transconductance
1300
160
μMho
μA
μA
A/V
V
ΔI
VC
= 10μA
V Pin Source Current
C
V
V
= V
= V
– 17%
FB
FB
NOM
NOM
V Pin Sink Current
C
+ 17%
70
180
V Pin to Switch Current Transconductance
C
V Pin Minimum Switching Threshold
Duty Cycle = 0%
0.4
0.9
90
C
V Pin 3A ISW Threshold
C
V
Maximum Switch Duty Cycle
V = 1.2V, I = 800mA, V = 6V
85
80
%
%
C
SW
IN
l
l
Minimum Boost Voltage Above Switch
Boost Current
I
SW
= 3A
1.8
2.7
V
l
l
I
SW
I
SW
= 1A (Note 4)
= 3A (Note 4)
20
70
30
140
mA
mA
l
l
l
SHDN Threshold Voltage
1.27
4
1.33
7
1.40
10
V
μA
SHDN Threshold Current Hysteresis
SHDN Input Current (Shutting Down)
SYNC Threshold Voltage
SHDN = 60mV Above Threshold
–7
–10
1.5
–13
2.2
2
μA
V
SYNC Input Frequency
1.6
MHz
kΩ
SYNC Pin Resistance
I
= 1mA
20
SYNC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: Minimum input voltage is defined as the voltage where the internal
regulator enters lockout. Actual minimum input voltage to maintain a
regulated output will depend on output voltage and load current. See
Applications Information.
Note 2: The LT1765E is guaranteed to meet performance specifications
from 0°C to 125°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls.
Note 4: Current flows into the BOOST pin only during the on period of the
switch cycle.
1765fd
3
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
TYPICAL PERFORMANCE CHARACTERISTICS
FB vs Temperature (Adj)
Switch On Voltage Drop
350
300
250
200
150
100
50
1.220
T
= 125°C
A
1.215
1.210
1.205
1.200
1.195
1.190
1.185
1.180
T
= –40°C
A
T
= 25°C
A
0
2
1
SWITCH CURRENT (A)
3
–25
0
25
50
75
125
0
–50
100
TEMPERATURE (°C)
1765 G02
1765 G01
Oscillator Frequency
SHDN Threshold vs Temperature
1.40
1.38
1.36
1.34
1.32
1.30
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
1765 G04
1765 G03
SHDN Supply Current vs VIN
SHDN IP Current vs Temperature
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SHDN = 0V
SHDN = 0V
0
5
10
15
(V)
20
25
30
0
5
10
15
(V)
20
25
30
V
V
IN
IN
1765 G05
1765 G05
1765fd
4
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Input Voltage for
2.5V Out
SHDN Supply Current
3.5
3.3
3.1
2.9
2.7
2.5
300
250
200
150
100
50
V
IN
= 15V
0
0.001
0.01
0.1
1
0
0.2 0.4 0.6 0.8
1
1.2 1.4
LOAD CURRENT (A)
SHUTDOWN VOLTAGE (V)
1765 G07
1765 G08
Input Supply Current
Current Limit Foldback
1200
1000
800
600
400
200
0
4
3
2
1
0
40
30
20
10
0
UNDERVOLTAGE
LOCKOUT
SWITCH CURRENT
FB CURRENT
0
0.2
0.4
0.6
0.8
1
1.2
0
5
10
15
20
25
30
FEEDBACK VOLTAGE (V)
INPUT VOLTAGE (V)
1765 G10
1765 G09
Maximum Load Current,
VOUT = 5V
Maximum Load Current,
VOUT = 2.5V
3.0
2.8
2.6
2.4
2.2
3.0
2.8
2.6
2.4
2.2
2.0
L = 4.7μH
L = 4.7μH
L = 2.2μH
L = 2.2μH
L = 1.5μH
L = 1.5μH
20
0
5
10
15
20
25
0
5
10
15
25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
1765 G12
1765 G11
1765fd
5
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
PIN FUNCTIONS
FB: The feedback pin is used to set output voltage using
anexternalvoltagedivider(adjustableversion)thatgener-
ates 1.2V at the pin when connected to the desired output
voltage. Thefixedvoltage1.8V, 2.5V, 3.3Vand5Vversions
have the divider network included internally and the FB pin
is connected directly to the output. If required, the current
limit can be reduced during start up or short-circuit when
the FB pin is below 0.5V (see the Current Limit Foldback
graphintheTypicalPerformanceCharacteristicssection).
An impedance of less than 5kΩ on the adjustable version
at the FB pin is needed for this feature to operate.
V
: The switch pin is the emitter of the on-chip power
SW
NPN switch. This pin is driven up to the input pin voltage
during switch on time. Inductor current drives the switch
pin negative during switch off time. Negative voltage must
be clamped with an external catch diode with a V <0.8V.
BR
Both V pins of the TSSOP package must be shorted
SW
together on the PC board.
SYNC: The sync pin is used to synchronize the internal
oscillator to an external signal. It is directly logic compat-
ible and can be driven with any signal between 20% and
80% duty cycle. The synchronizing range is from 1.6MHz
to 2MHz. See Synchronization section in Applications
Information for details. When not in use, this pin should
be grounded.
BOOST: The BOOST pin is used to provide a drive voltage,
higher than the input voltage, to the internal bipolar NPN
power switch.
V : This is the collector of the on-chip power NPN switch.
SHDN: The shutdown pin is used to turn off the regula-
tor and to reduce input drain current to a few microam-
peres. The 1.33V threshold can function as an accurate
undervoltage lockout (UVLO), preventing the regulator
from operating until the input voltage has reached a pre-
determined level. Float or pull high to put the regulator in
the operating mode.
IN
Thispinpowerstheinternalcircuitryandinternalregulator.
At NPN switch on and off, high di/dt edges occur on this
pin. Keep the external bypass capacitor and catch diode
close to this pin. All trace inductance on this path will
create a voltage spike at switch off, adding to the V volt-
CE
age across the internal NPN. Both V pins of the TSSOP
IN
package must be shorted together on the PC board.
V : The V pin is the output of the error amplifier and the
C
C
GND: The GND pin acts as the reference for the regulated
output, so load regulation will suffer if the “ground” end of
the load is not at the same voltage as the GND pin of the
IC. This condition will occur when load current or other
currents flow through metal paths between the GND pin
and the load ground point. Keep the ground path short
between the GND pin and the load and use a ground plane
when possible. Keep the path between the input bypass
and the GND pin short. The exposed GND pad and/or GND
pins of the package are directly attached to the internal
tab. These pins/pad should be attached to a large copper
area to reduce thermal resistance.
input of the peak switch current comparator. It is normally
used for frequency compensation, but can do double duty
as a current clamp or control loop override. This pin sits
at about 0.4V for very light loads and 0.9V at maximum
load. It can be driven to ground to shut off the output.
1765fd
6
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
BLOCK DIAGRAM
The LT1765 is a constant frequency, current mode buck
converter. This means that there is an internal clock and
twofeedbackloopsthatcontrolthedutycycleofthepower
switch. In addition to the normal error amplifier, there is a
current sense amplifier that monitors switch current on a
cycle-by-cyclebasis.Aswitchcyclestartswithanoscillator
resonant frequency of the inductor and output capacitor,
thenanabrupt180°shiftwilloccur.Thecurrentfedsystem
will have 90° phase shift at a much lower frequency, but
will not have the additional 90° shift until well beyond
the LC resonant frequency. This makes it much easier to
frequency compensate the feedback loop and also gives
much quicker transient response.
pulsewhichsetstheR flip-floptoturntheswitchon.When
S
switch current reaches a level set by the inverting input of
the comparator, the flip-flop is reset and the switch turns
off. Output voltage control is obtained by using the output
of the error amplifier to set the switch current trip point.
This technique means that the error amplifier commands
current to be delivered to the output rather than voltage.
A voltage fed system will have low phase shift up to the
High switch efficiency is attained by using the BOOST pin
to provide a voltage to the switch driver which is higher
than the input voltage, allowing the switch to be saturated.
Thisboostedvoltageisgeneratedwithanexternalcapacitor
and diode. A comparator connected to the shutdown pin
disables the internal regulator, reducing supply current.
0.005Ω
INPUT
+
–
CURRENT
SENSE
INTERNAL
CC
2.5V BIAS
REGULATOR
AMPLIFIER
V
VOLTAGE GAIN = 40
SLOPE COMP
BOOST
∑
0.4V
1.25MHz
S
R
SYNC
Q1
POWER
SWITCH
OSCILLATOR
R
DRIVER
CURRENT
COMPARATOR
S
FLIP-FLOP
CIRCUITRY
+
–
SHUTDOWN
COMPARATOR
V
SW
PARASITIC DIODES
DO NOT FORWARD BIAS
7μA
–
+
–
FB
1.33V
+
ERROR
V
C
AMPLIFIER
= 850μMho
1.2V
INTERNAL
CC
g
SHDN
m
V
GND
3μA
1765 F01
Figure 1. Block Diagram
1765fd
7
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
FB RESISTOR NETWORK
rating and turn-on surge problems. Y5V or similar type
ceramics can be used since the absolute value of capaci-
tance is less important and has no significant effect on
loopstability.Ifoperationisrequiredclosetotheminimum
input required by the output or the LT1765, a larger value
may be required. This is to prevent excessive ripple caus-
ing dips below the minimum operating voltage resulting
in erratic operation.
If an output voltage of 1.8V, 2.5V, 3.3V or 5V is required,
the respective fixed option part, -1.8, -2.5, -3.3 or -5,
should be used. The FB pin is tied directly to the output;
the necessary resistive divider is already included on
the part. For other voltage outputs, the adjustable part
should be used and an external resistor divider added.
The suggested resistor (R2) from FB to ground is 10k.
This reduces the contribution of FB input bias current to
output voltage to less than 0.25%. The formula for the
Iftantalumcapacitorsareused,valuesinthe22μFto470μF
range are generally needed to minimize ESR and meet
ripple current and surge ratings. Care should be taken to
ensure the ripple and surge ratings are not exceeded. The
AVX TPS and Kemet T495 series tantalum capacitors are
surgerated.AVXrecommendsderatingcapacitoroperating
voltage by 2:1 for high surge applications.
resistor (R1) from V
to FB is:
OUT
R2(VOUT –1.2)
1.2–R2(0.25μA)
R1=
LT1765 (ADJ)
V
SW
OUTPUT
OUTPUT CAPACITOR
ERROR
AMPLIFIER
Unliketheinputcapacitor,RMSripplecurrentintheoutput
capacitor is normally low enough that ripple current rating
is not an issue. The current waveform is triangular, with
an RMS value given by:
1.2V
+
–
R1
+
FB
R2
10k
0.29 V
V −V
IN OUT
1765 F02
(
OUT)(
)
IRIPPLE RMS
=
V
C
GND
(
)
L f V
( )( )
(
)
IN
Figure 2. Feedback Network
The LT1765 will operate with both ceramic and tantalum
output capacitors. Ceramic capacitors are generally cho-
sen for their small size, very low ESR (effective series
resistance), and good high frequency operation. Ceramic
output capacitors in the 1μF to 10μF range, X7R or X5R
type are recommended.
INPUT CAPACITOR
Step-down regulators draw current from the input supply
in pulses. The rise and fall times of these pulses are very
fast. The input capacitor is required to reduce the voltage
ripple at the input of LT1765 and to force the switching
current into a tight local loop, thereby minimizing EMI.
The RMS ripple current can be calculated from:
Tantalum capacitors are usually chosen for their bulk
capacitance properties, useful in high transient load ap-
plications. ESR rather than absolute value defines output
ripple at 1.25MHz. Typical LT1765 applications require a
tantalum capacitor with less than 0.3Ω ESR at 22μF to
500μF, see Table 2. This ESR provides a useful zero in the
frequency response. Ceramic output capacitors with low
2
IRIPPLE RMS =IOUT VOUT V − V
/ V
(
)
IN
OUT
IN
(
)
Ceramiccapacitorsareidealforinputbypassing.Athigher
switching frequency, the energy storage requirement of
the input capacitor is reduced so values in the range of
1μF to 4.7μF are suitable for most applications. Their high
frequency capacitive nature removes most ripple current
ESR usually require a larger V capacitor or an additional
C
series R to compensate for this.
1765fd
8
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
Table 2. Surface Mount Solid Tantalum Capacitor ESR
and Ripple Current
(VOUT)(VIN – VOUT
2(L)(f)(VIN)
)
IOUT MAX
=
(
)
IP –
E Case Size
ESR (Max, Ω)
0.1 to 0.3
Ripple Current (A)
0.7 to 1.1
0.4
Continuous Mode
AVX TPS, Sprague 593D
AVX TAJ
For V = 8V, V
= 5V and L = 3.3μH,
IN
OUT
0.7 to 0.9
D Case Size
5 8−5
( )(
)
IOUT(MAX) = 3−
AVX TPS, Sprague 593D
C Case Size
0.1 to 0.3
0.2 (typ)
0.7 to 1.1
0.5 (typ)
2 3.3•10−6 1.25•106
8
( )
(
)(
)
= 3−0.23= 2.77A
AVX TPS
Figure3showsacomparisonofoutputrippleforaceramic
and tantalum capacitor at 200mA ripple current.
Note that the worst case (minimum output current avail-
able) condition is at the maximum input voltage. For the
same circuit at 15V, maximum output current would be
only 2.6A.
V
OUT
USING 47μF, 0.1Ω
TANTALUM CAPACITOR
(10mV/DIV)
Inductor Selection
Theoutputinductorshouldhaveasaturationcurrentrating
greater than the peak inductor current set by the current
comparator of the LT1765. The peak inductor current will
depend on the output current, input and output voltages
and the inductor value:
V
USING 2.2μF
OUT
CERAMIC CAPACITOR
(10mV/DIV)
V
SW
(5V/DIV)
1765 F03
0.2μs/DIV
VOUT V −V
(
)
IN
OUT
IPEAK =IOUT
+
2 L f V
( )( )
(
)
Figure 3. Output Ripple Voltage Waveform
IN
V = Maximum input voltage
IN
INDUCTOR CHOICE AND MAXIMUM OUTPUT
CURRENT
f = Switching frequency, 1.25MHz
If an inductorwith a peak current lowerthan the maximum
switch current of the LT1765 is chosen a soft-start circuit
in Figure 10 should be used. Also, short-circuit conditions
should not be allowed because the inductor may saturate
resulting in excessive power dissipation.
Maximum output current for an LT1765 buck converter is
equal to the maximum switch rating (I ) minus one half
P
peak to peak inductor ripple current. The LT1765 main-
tains a constant switch current rating at all duty cycles.
(Patent Pending)
Also, consideration should be given to the resistance
of the inductor. Inductor conduction loses are directly
proportional to the DC resistance of inductor. Sometime,
the manufacturers will also provide maximum current
rating based on the allowable losses in the inductor. Care
should be taken, however. At high input voltages and low
DCR, excessive switch current could flow during shorted
output condition.
For most applications, the output inductor will be in the
1μH to 10μH range. Lower values are chosen to reduce
thephysicalsizeoftheinductor,highervaluesallowhigher
outputcurrentsduetoreducedpeaktopeakripplecurrent.
The following formula gives maximum output current for
continuousmodeoperation,implyingthatthepeaktopeak
ripple (2x the term on the right) is less than the maximum
switch current.
SuitableinductorsareavailablefromCoilcraft,Coiltronics,
Dale, Sumida, Toko, Murata, Panasonic and other
manufacturers.
1765fd
9
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
Table 3
The boost diode can be connected to the input, although,
caremustbetakentopreventthe2xV boostvoltagefrom
IN
VALUE
(μH)
IRMS
(Amps)
DCR
(Ω)
HEIGHT
(mm)
PART NUMBER
Coiltcraft
exceeding the BOOST pin absolute maximum rating. The
additional voltage across the switch driver also increases
powerloss,reducingefficiency.Ifavailable,anindependent
supply can be used with a local bypass capacitor.
DO1608C-222
Sumida
2.2
2.4
0.07
2.9
CDRH3D16-1R5
CDRH4D18-1R0
CDC5D23-2R2
CR43-1R4
1.5
1.0
2.2
1.4
2.6
1.6
1.7
2.2
2.5
2.6
0.043
0.035
0.03
1.8
2.0
2.5
3.5
3.0
A 0.18μF boost capacitor is recommended for most ap-
plications. Almost any type of film or ceramic capacitor
is suitable, but the ESR should be <1Ω to ensure it can
be fully recharged during the off time of the switch. The
capacitor value is derived from worst-case conditions of
700ns on-time, 90mA boost current, and 0.7V discharge
ripple.Thisvalueisthenguardbandedby2xforsecondary
factors such as capacitor tolerance, ESR and temperature
effects. The boost capacitor value could be reduced under
less demanding conditions, but this will not improve cir-
cuit operation or efficiency. Under low input voltage and
low load conditions, a higher value capacitor will reduce
discharge ripple and improve start up operation.
0.056
0.013
CDRH5D28-2R6
Toko
(D62F)847FY-2R4M
(D73LF)817FY-2R2M
2.4
2.2
2.5
2.7
0.037
0.03
2.7
3.0
CATCH DIODE
The diode D1 conducts current only during switch off
time. Peak reverse voltage is equal to regulator input
voltage. Average forward current in normal operation can
be calculated from:
SHUTDOWN AND UNDERVOLTAGE LOCKOUT
IOUT V − VOUT
Figure 4 shows how to add undervoltage lockout (UVLO)
to the LT1765. Typically, UVLO is used in situations where
the input supply is current limited, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
loadtothesourceandcancausethesourcetocurrentlimit
or latch low under low source voltage conditions. UVLO
prevents the regulator from operating at source voltages
where these problems might occur.
(
IN
)
ID(AVG
=
)
V
IN
The only reason to consider a larger than 3A diode is the
worst-case condition of a high input voltage and shorted
output.Withashortedcondition,diodecurrentwillincreaseto
a typical value of 4A, determined by peak switch current limit
of the LT1765. A higher forward voltage will also limit switch
current. This is safe for short periods of time, but it would be
prudent to check with the diode manufacturer if continuous
operation under these conditions must be tolerated.
LT1765
BOOST PIN
V
SW
7μA
IN
INPUT
Formostapplications, theboostcomponentsarea0.18μF
capacitor and a CMDSH-3 diode. The anode is typically
connected to the regulated output voltage to generate a
1.33V
R1
R2
3μA
V
CC
OUTPUT
voltage approximately V
above V to drive the output
SHDN
OUT
IN
+
C1
stage.Theoutputdriverrequiresatleast2.7Vofheadroom
throughouttheonperiodtokeeptheswitchfullysaturated.
However, the output stage discharges the boost capacitor
during this on time. If the output voltage is less than 3.3V,
it is recommended that an alternate boost supply is used.
GND
1765 F04
Figure 4. Undervoltage Lockout
1765fd
10
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
An internal comparator will force the part into shutdown
threshold with a duty cycle between 20% and 80%. The
input can be driven directly from a logic level output. The
synchronizing range is equal to initial operating frequency
up to 2MHz. This means that minimum practical sync
frequency is equal to the worst-case high self-oscillating
frequency (1.6MHz), not the typical operating frequency
of 1.25MHz. Caution should be used when synchronizing
above 1.8MHz because at higher sync frequencies the
amplitude of the internal slope compensation used to
prevent subharmonic switching is reduced. This type of
subharmonic switching only occurs at input voltages less
than twice output voltage. Higher inductor values will tend
to eliminate this problem. See Frequency Compensation
section for a discussion of an entirely different cause of
subharmonic switching before assuming that the cause is
insufficient slope compensation. Application Note 19 has
more details on the theory of slope compensation.
below the minimum V of 2.6V. This feature can be used
IN
to prevent excessive discharge of battery-operated sys-
tems. If an adjustable UVLO threshold is required, the
shutdown pin can be used. The threshold voltage of the
shutdown pin comparator is 1.33V. A 3μA internal current
sourcedefaultstheopenpinconditiontobeoperating(see
Typical Performance Graphs). Current hysteresis is added
above the SHDN threshold. This can be used to set voltage
hysteresis of the UVLO using the following:
VH − VL
R1=
7μA
1.33V
R2=
V −1.33V
(
)
+3μA
H
R1
V – Turn-on threshold
H
LAYOUT CONSIDERATIONS
V – Turn-off threshold
L
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency, switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
in Figure 5, must be kept as short as possible. Shortening
this path will also reduce the parasitic trace inductance
of approximately 25nH/inch. At switch off, this parasitic
inductance produces a flyback spike across the LT1765
switch. When operating at higher currents and input volt-
ages, with poor layout, this spike can generate voltages
across the LT1765 that may exceed its absolute maximum
Example:switchingshouldnotstartuntiltheinputisabove
4.75V and is to stop if the input falls below 3.75V.
V = 4.75V
H
V = 3.75V
L
4.75V − 3.75V
R1=
= 143k
7μA
1.33V
R2 =
= 49.4k
4.75V − 1.33V
(
)
+ 3μA
143k
Keep the connections from the resistors to the SHDN
pin short and make sure that the interplane or surface
capacitance to the switching nodes are minimized. If high
resistorvaluesareused,theSHDNpinshouldbebypassed
with a 1nF capacitor to prevent coupling problems from
the switch node.
LT1765
L1
V
IN
SW
5V
HIGH
FREQUENCY
CIRCULATING
PATH
C3
D1 C1
V
IN
LOAD
SYNCHRONIZATION
The SYNC pin is used to synchronize the internal oscilla-
tor to an external signal. The SYNC input must pass from
a logic level low, through the maximum synchronization
1765 F05
Figure 5. High Speed Switching Path
1765fd
11
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
D2
MINIMIZE D1, C3
LT1765 LOOP
CMDSH-3
INPUT
15V
C2
0.18μF
V
IN
C3
GND
4.7μF
CERAMIC
L1
2.7μH
C3
KEEP FB AND V
C
OUTPUT
3.3V
BOOST
COMPONENTS AND
TRACES AWAY FROM
HIGH FREQUENCY,
HIGH INPUT
V
V
C
C
IN
SW
FB
C
D2
2.5A
LT1765-33
C2
OFF ON
SHDN
SYNC GND
COMPONENTS
V
C
C1
4.7μF
CERAMIC
D1
B220A
C
2.2nF
D1
L1
1765 F06
PLACE FEEDTHROUGHS
UNDER AND AROUND
GROUND PAD FOR
GOOD THERMAL
V
OUT
GND
C1
CONDUCTIVITY
KELVIN
SENSE
OUT
1765 F6a
V
Figure 6. Typical Application and Layout (Topside Only Shown)
rating. A ground plane should always be used under the
switcher circuitry to prevent interplane coupling and
overall noise.
THERMAL CALCULATIONS
Power dissipation in the LT1765 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit cur-
rent, and input quiescent current. The following formulas
showhowtocalculateeachoftheselosses.Theseformulas
assume continuous mode operation, so they should not
be used for calculating efficiency at light load currents.
The V and FB components should be kept as far away as
C
possible from the switch and boost nodes. The LT1765
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability
or subharmonic like oscillation.
Switch loss:
2
RSW OUT
I
V
OUT
(
) (
)
Board layout also has a significant effect on thermal
resistance. The exposed pad or GND pin is a continuous
copper plate that runs under the LT1765 die. This is the
best thermal path for heat out of the package as can be
P
SW
=
+ 17ns I
V
f
(
OUT)( IN)( )
V
IN
Boost current loss for VBOOST = VOUT:
seen by the low θ of the exposed pad package. Reduc-
2
JC
VOUT
I
V
/50
(
)
OUT
ing the thermal resistance from Pin 4 or exposed pad
onto the board will reduce die temperature and increase
the power capability of the LT1765. This is achieved by
providing as much copper area as possible around this
pin/pad. Also, having multiple solder filled feedthroughs
to a continuous copper plane under LT1765 will help in
reducing thermal resistance. Ground plane is usually suit-
able for this purpose. In multilayer PCB designs, placing a
ground plane next to the layer with the LT1765 will reduce
thermal resistance to a minimum.
PBOOST
=
IN
Quiescent current loss:
PQ =V 0.001
IN
(
)
R
SW
= Switch resistance (≈0.13Ω at hot)
17ns = Equivalent switch current/voltage overlap time
f = Switch frequency
1765fd
12
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
Example: with V = 10V, V
= 5V and I = 2A:
DIE TEMPERATURE MEASUREMENT
IN
OUT
OUT
If a true die temperature is required, a measurement of the
SYNC to GND pin resistance can be used. The SYNC pin
resistanceacrosstemperaturemustfirstbecalibrated,with
no significant output load, in an oven. An initial value of
40k with a temperature coefficient of 0.16%/°C is typical.
The same measurement can then be used in operation to
indicate the die temperature.
0.13 2 2 5
(
)( ) ( )
P
=
+ 17 •10−9 2 10 1.25 •106
( )( )
SW
(
)
(
)
10
=0.26 + 0.43 = 0.69W
5 2 2 /50
( ) (
)
= 0.1W
PBOOST
=
10
P =10 0.001 = 0.01W
(
)
Q
FREQUENCY COMPENSATION
Total power dissipation, P , is 0.69 + 0.1 + 0.01 = 0.8W.
TOT
Before starting on the theoretical analysis of frequency
response,thefollowingshouldberemembered—theworse
the board layout, the more difficult the circuit will be to
stabilize. This is true of almost all high frequency analog
circuits,readthe‘LAYOUTCONSIDERATIONS’sectionfirst.
Common layout errors that appear as stability problems
aredistantplacementofinputdecouplingcapacitorand/or
ThermalresistancefortheLT176516-leadTSSOPexposed
pad package is influenced by the presence of internal or
backside planes. With a full plane under the package,
thermal resistance will be about 45°C/W. With no plane
under the package, thermal resistance will increase to
about 110°C/W. For the exposed pad package θ
=
JC(PAD)
catch diode, and connecting the V compensation to a
C
10°C/W. Thermalresistanceisdominatedbyboardperfor-
mance. To calculate die temperature, use the appropriate
thermalresistancenumberandaddinworst-caseambient
temperature:
groundtrackcarryingsignificantswitchcurrent.Inaddition,
the theoretical analysis considers only first order ideal
component behavior. For these reasons, it is important
that a final stability check is made with production layout
and components.
T = T + θ
JA (PTOT)
J
A
When estimating ambient, remember the nearby catch
diode will also be dissipating power.
TheLT1765usescurrentmodecontrol.Thisalleviatesmany
of the phase shift problems associated with the inductor.
The basic regulator loop is shown in Figure 7, with both
tantalum and ceramic capacitor equivalent circuits. The
V
( )
F
V − V
I
(
OUT)( LOAD
)
IN
PDIODE
=
VIN
LT1765 can be considered as two g blocks, the error
m
amplifier and the power stage.
V = Forward voltage of diode (assume 0.5V at 2A)
F
0.5 10−5 2
(
)(
)( )
LT1765
PDIODE
=
= 0.5W
CURRENT MODE
10
V
SW
OUTPUT
POWER STAGE
ERROR
g
m
= 5mho
AMPLIFIER
Notice that the catch diode’s forward voltage contributes
a significant loss in the overall system efficiency. A larger,
lower V diode can improve efficiency by several percent.
R1
R2
FB
–
TANTALUM CERAMIC
g
=
m
F
850μmho
ESR
C1
ESL
C1
+
500k
1.2V
+
Typical thermal resistance of the board θ is 35°C/W. At
B
GND
V
C
an ambient temperature of 25°C,
R
T = T + θ (P ) + θ (P )
DIODE
C
J
A
JA TOT
B
C
F
C
C
T = 25 + 45 (0.8) + 35 (0.5) = 79°C
J
1765 F07
Figure 7. Model for Loop Response
1765fd
13
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
Figure 8 shows the overall loop response with a 330pF VC
capacitor and a typical 100μF tantalum output capacitor.
The response is set by the following terms:
Second, if the loop gain is not rolled sufficiently at the
switching frequency, output ripple will perturb the V pin
C
enough to cause unstable duty cycle switching similar
to subharmonic oscillation. This may not be apparent
at the output. Small signal analysis will not show this
since a continuous time system is assumed. If needed,
an additional capacitor (C ) can be added to the V pin to
Error amplifier:
DC gain set by g and R = 850μ • 500k = 425.
m
L
–1
Pole set by C and R = (2π • 500k • 330p) = 965Hz.
F
L
F
C
–1 –1
Unity-gain set by C and g = (2π • 330p • 850μ )
=
form a pole at typically one fifth the switching frequency
F
m
410kHz.
(If R = ~ 5k, C = ~ 100pF)
C
F
Power stage:
Whencheckingloopstability,thecircuitshouldbeoperated
overtheapplication’sfullvoltage,currentandtemperature
range.Anytransientloadsshouldbeappliedandtheoutput
voltage monitored for a well-damped behavior.
DC gain set by g and R (assume 5Ω) = 5 • 5 = 25.
Pole set by C
Unity-gain set by C
8kHz.
m
L
–1
and R = (2π • 100μ • 10) = 159Hz.
OUT
L
–1 –1
and g = (2π • 100μ • 5 )
=
OUT
m
CONVERTER WITH BACKUP OUTPUT REGULATOR
Tantalum output capacitor:
Zero set by C and C = (2π • 100μ • 0.1) = 15.9kHz.
Insystemswithaprimaryandbackupsupply,forexample,
a battery powered device with a wall adapter input, the
output of the LT1765 can be held up by the backup supply
with its input disconnected. In this condition, the SW pin
–1
OUT
ESR
ThezeroproducedbytheESRofthetantalumoutputcapaci-
tor is very useful in maintaining stability. Ceramic output
capacitors do not have a zero due to very low ESR, but are
dominated by their ESL. They form a notch in the 1MHz to
10MHz range. Without this zero, the V pole must be made
dominant. A typical value of 2.2nF will achieve this.
will source current into the V pin. If the SHDN pin is held
IN
at ground, only the shutdown current of 6μA will be pulled
via the SW pin from the second supply. With the SHDN pin
floating, the LT1765 will consume its quiescent operating
C
current of 1mA. The V pin will also source current to
IN
If better transient response is required, a zero can be
any other components connected to the input line. If this
load is greater than 10mA or the input could be shorted to
ground, a series Schottky diode must be added, as shown
in Figure 9. With these safeguards, the output can be held
added to the loop using a resistor (R ) in series with the
C
compensation capacitor. As the value of R is increased,
C
transient response will generally improve, but two effects
limit its value. First, the combination of output capacitor
at voltages up to the V absolute maximum rating.
IN
ESRandalargeR maystoploopgainrollingoffaltogether.
C
BUCK CONVERTER WITH ADJUSTABLE SOFT-START
80
180
150
120
90
V
C
C
= 5V
OUT
OUT
C
= 100μF, 0.1Ω
Large capacitive loads or high input voltages can cause
high input currents at start-up. Figure 10 shows a circuit
that limits the dv/dt of the output at start-up, controlling
the capacitor charge rate. The buck converter is a typical
60
= 330pF
R /C = 0
C
F
I
= 1A
LOAD
40
PHASE
GAIN
20
configuration with the addition of R3, R4, C and Q1. As
SS
the output starts to rise, Q1 turns on, regulating switch
0
60
current via the V pin to maintain a constant dv/dt at the
C
–20
–40
30
output.Outputrisetimeiscontrolledbythecurrentthrough
C
defined by R4 and Q1’s V . Once the output is in
SS
BE
0
10
100
1k
10k
100k
1M
regulation, Q1 turns off and the circuit operates normally.
FREQUENCY (Hz)
R3 is transient protection for the base of Q1.
1765 F08
Figure 8. Overall Loop Response
1765fd
14
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
CMDSH-3
0.18μF
MBRS330T3*
REMOVABLE
5μH
BOOST
3.3V, 2A
4.7μF
ALTERNATE
SUPPLY
V
V
IN
SW
INPUT
83k
LT1765-3.3
SHDN
SYNC GND
FB
V
C
28.5k
2.2μF
2.2nF
B220A
1765 F09
* ONLY REQUIRED IF ADDITIONAL LOADS ON THE INPUT CAN SINK >10mA
Figure 9. Dual Source Supply with 6μA Reverse Leakage
D2
CMDSH-3
Dual Output Converter
ThecircuitinFigure11generatesbothpositiveandnegative
5Voutputswithasinglepieceofmagnetics.Thetwoinduc-
tors shown are actually just two windings on a standard
B H Electronics inductor. The topology for the 5V output
is a standard buck converter. The –5V topology would be
a simple flyback winding coupled to the buck converter
if C4 were not present. C4 creates a SEPIC (single-ended
primary inductance converter) topology which improves
regulation and reduces ripple current in L1. Without C4,
the voltage swing on L1B compared to L1A would vary
due to relative loading and coupling losses. C4 provides a
low impedance path to maintain an equal voltage swing in
L1B, improving regulation. In a flyback converter, during
switch on time, all the converter’s energy is stored in L1A
only, since no current flows in L1B. At switch off, energy
is transferred by magnetic coupling into L1B, powering
the –5V rail. C4 pulls L1B positive during switch on time,
causing current to flow, and energy to build in L1B and
C4. At switch off, the energy stored in both L1B and C4
supply the –5V rail. This reduces the current in L1A and
changes L1B current waveform from square to triangular.
For details on this circuit, including maximum output cur-
rents, see Design Note 100
C2
0.18μF
L1
5μH
OUTPUT
5V
BOOST
INPUT
12V
V
V
SW
IN
2.5A
+
C1
LT1765-5
D1
C3
100μF
2.2μF
SHDN
SYNC GND
FB
C
V
C
SS
R3
2k
15nF
Q1
C
C
1765 F10
330pF
R4
47k
D1: B220A
Q1: 2N3904
Figure 10. Buck Converter with Adjustable Soft Start
(R4)(CSS)(VOUT
(VBE)
)
RiseTime =
Using the values shown in Figure 10,
(47 •103)(15•10–9)(5)
RiseTime =
= 5ms
0.7
The ramp is linear and rise times in the order of 100ms are
possible. Since the circuit is voltage controlled, the ramp
rate is unaffected by load characteristics and maximum
output current is unchanged. Variants of this circuit can
be used for sequencing multiple regulator outputs.
1765fd
15
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
D2
CMDSH-3
C2
0.18μF
L1A*
BOOST
OUTPUT
5V AT 1.5A
INPUT
12V
V
V
SW
IN
LT1765-5
SHDN
SYNC GND
FB
4.7μF
V
C
6.3V
C3
2.2μF
25V
R
C
CERAMIC
3.3k
D1
C
C
CERAMIC
4700pF
GND
C4
4.7mF
6.3V
4.7μF
16V
CERAMIC
L1B*
CERAMIC
OUTPUT
†
–5V AT 1.1A
* L1 IS A SINGLE CORE WITH TWO WINDINGS
COILTRONICS CTX5-1A
D3
1765 F11a
†
IF LOAD CAN GO TO ZERO, AN OPTIONAL
PRELOAD OF 1k TO 5k MAY BE USED TO
IMPROVE LOAD REGULATION
D1, D3: B220A
Figure 11a. Dual Output Converter
1200
1000
800
600
400
200
0
10
100
1000
10000
5V LOAD CURRENT (mA)
1765 F11b
Figure 11b. Dual Output Converter (Output Currents)
1765fd
16
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
D2
CMDSH-3
C2
0.22μF
L1
3μH
BOOST
INPUT
5V
V
V
IN
SW
U1
LT1765-5
FB
22μF
SHDN
GND SYNC
C1
D1
B220A
V
C
10μF
6.3V X5R
CERAMIC
C3
2.2μF
D3
B220A
C
C
1800pF
16V X5R
CERAMIC
C
F
R
100pF
C
2.4k
OUTPUT
–5V AT 1A
L1: CDRH6D28-3R0
1765 F12
Figure 12. Positive-to-Negative Low Output Ripple Converter
D2
CMDSH-3
INPUT
–5V
S
S
S
C2
0.22μF
L1
2.5μH
BOOST
S
S
V
IN
V
SW
U1
LT1765FE
S
FB
SHDN
GND SYNC
D1
C1
V
C
UPS120
2.2μF
S
S
6.3V X5R
C3
R2
10k
R1
64.9k
C
22μF
C
4700pF
16V X5R
CERAMIC
C
F
R
100pF
C
6.8k
S
S
S
S
S
S
OUTPUT
–9V AT 1A
L1: CDRH5D28-2R5
BOLD LINES INDICATE HIGH CURRENT PATHS
1765 F13
Figure 13. Negative Boost Converter
1765fd
17
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
PACKAGE DESCRIPTION
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BB
4.90 – 5.10*
(.193 – .201)
3.58
(.141)
3.58
(.141)
16 1514 13 12 1110
9
6.60 p 0.10
4.50 p 0.10
2.94
(.116)
6.40
(.252)
BSC
SEE NOTE 4
2.94
(.116)
0.45 p 0.05
1.05 p 0.10
0.65 BSC
5
7
8
1
2
3
4
6
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.0433)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE16 (BB) TSSOP 0204
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
1765fd
18
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
.045 p .005
NOTE 3
.050 BSC
7
5
8
6
.245
MIN
.160 p .005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 p .005
TYP
1
3
4
2
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
(0.254 – 0.508)
× 45°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
NOTE:
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
SO8 0303
1765fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
V : 7.3V to 45V/64V, V
LT1074/LT1074HV
4.4A (I ), 100kHz, High Efficiency Step-Down DC/DC Converter
= 2.21V, I = 8.5mA,
Q
OUT
IN
OUT(MIN)
I
= 10μA, DD5/7, TO220-5/7
SD
LT1076/LT1076HV
LT1676
1.6A (I ), 100kHz, High Efficiency Step-Down DC/DC Converter
V : 7.3V to 45V/64V, V
SD
= 2.21V, I = 8.5mA,
Q
OUT
IN
OUT(MIN)
I
= 10μA, DD5/7, TO220-5/7
60V, 440mA (I ), 100kHz, High Efficiency Step-Down DC/DC
V : 7.4V to 60V, V
SD
= 1.24V, I = 3.2mA,
OUT
IN
OUT(MIN) Q
Converter
I
< 2.5μA, SO-8
LT1765
25V, 2.75A (I ), 1.25MHz, High Efficiency Step-Down DC/DC
V : 3V to 25V, V
= 1.20V, I = 1mA,
OUT
IN
OUT(MIN) Q
Converter
I
< 15μA, SO-8, TSSOP16E
SD
LT1766
60V, 1.2A (IOUT), 200kHz, High Efficiency Step-Down DC/DC
Converter
V : 5.5V to 60V, V
SD
= 1.20V, I = 2.5mA,
OUT(MIN) Q
IN
I
< 25μA, TSSOP16/E
LT1767
25V, 1.2A (I ), 1.25MHz, High Efficiency Step-Down DC/DC
V : 3V to 25V, V
= 1.20V, I = 1mA,
OUT(MIN) Q
OUT
IN
Converter
I
< 6μA, MS8/E
SD
LT1776
40V, 550mA (I ), 200kHz, High Efficiency Step-Down DC/DC
V : 7.4V to 40V, V
SD
= 1.24V, I = 3.2mA,
OUT(MIN) Q
OUT
IN
Converter
I
< 30μA, N8, SO-8
LT1940
25V, Dual 1.2A (I ), 1.1MHz, High Efficiency Step-Down
V : 3V to 25V, V
= 1.2V, I = 3.8mA,
OUT(MIN) Q
OUT
IN
DC/DC Converter
I
= < 1μA, TSSOP16E
SD
LT1956
60V, 1.2A (I ), 500kHz, High Efficiency Step-Down DC/DC
V : 5.5V to 60V, V
SD
= 1.20V, I = 2.5mA,
Q
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
Converter
I
< 25μA, TSSOP16/E
LT1976
60V, 1.2A (I ), 200kHz, High Efficiency Step-Down DC/DC
V : 3.3V to 60V, V
= 1.20V, I = 100μA,
Q
OUT
IN
SD
Converter with Burst Mode® Operation
80V, 50mA, Low Noise Linear Regulator
I
< 1μA, TSSOP16E
LT3010
V : 1.5V to 80V, V
= 1.28V, I = 30μA,
Q
IN
SD
I
< 1μA, MS8E
LTC3407
LTC3412
LTC3414
LT3430/LT3431
LT3433
Dual 600mA (I ), 1.5MHz, Synchronous Step-Down DC/DC
V : 2.5V to 5.5V, V
= 0.6V, I = 40μA,
Q
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
Converter
I
< 1μA, MS10E
SD
2.5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
V : 2.5V to 5.5V, V
= 0.8V, I = 60μA,
Q
OUT
IN
SD
I
< 1μA, TSSOP16E
4A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
V : 2.3V to 5.5V, V
= 0.8V, I = 64μA,
Q
OUT
IN
SD
I
< 1μA, TSSOP20E
60V, 2.75A (I ), 200kHz/500kHz, High Efficiency Step-Down
V : 5.5V to 60V, V
= 1.20V, I = 2.5mA,
Q
OUT
IN
SD
DC/DC Converter
I
= 30μA, TSSOP16E
60V, 400mA (I ), 200kHz, High Efficiency Step-Up/Step-Down
V : 4V to 60V, V
SD
= 3.3V to 20V, I = 100μA,
Q
OUT
IN
OUT(MIN)
DC/DC Converter with Burst Mode Operation
I
< 1μA, TSSOP16E
LTC3727/LTC3727-1 36V, 500kHz, High Efficiency Step-Down DC/DC Converter
V : 4V to 36V, V
SD
= 0.8V, I = 670μA,
Q
IN
OUT(MIN)
I
< 20μA, QFN32, SSOP28
Burst Mode is a registered trademark of Linear Technology Corporation.
1765fd
LT 0608 REV D • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2001
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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