LT1766EGN_技术文档

LT1766/LT1766-5

5.5V to 60V 1.5A, 200kHz

Step-Down Switching Regulator

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FEATURES

DESCRIPTIO

■

Wide Input Range: 5.5V to 60V

The LT^®1766/LT1766-5 are 200kHz monolithic buck

switching regulators that accept input voltages up to 60V.

A high efficiency 1.5A, 0.2Ω switch is included on the die

alongwithallthenecessaryoscillator,controlandlogiccir-

cuitry. A current mode control architecture delivers fast

transient response and excellent loop stability.

■

1.5A Peak Switch Current

■

Constant 200kHz Switching Frequency

Saturating Switch Design: 0.2Ω

■

Peak Switch Current Rating Maintained Over

Full Duty Cycle Range

■

Low Effective Supply Current: 2.5mA

Special design techniques and a new high voltage process

achieve high efficiency over a wide input range. Efficiency

ismaintainedoverawideoutputcurrentrangebyusingthe

output to bias the circuitry and by utilizing a supply boost

capacitortosaturatethepowerswitch.Patentedcircuitry*

maintainspeakswitchcurrentoverthefulldutycyclerange.

A shutdown pin reduces supply current to 25µA and the

device can be externally synchronized from 228kHz to

700kHz with logic level inputs.

■

Low Shutdown Current: 25µA

■

1.2V Feedback Reference Voltage (LT1766)

■

5V Fixed Output (LT1766-5)

Easily Synchronizable

Cycle-by-Cycle Current Limiting

■

Small 16-Pin SSOP and Thermally Enhanced

TSSOP Packages

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APPLICATIO S

The LT1766/LT1766-5 are available in a 16-pin fused-lead

SSOPpackageoraTSSOPpackagewithexposedbackside

for improved thermal performance.

■

High Voltage, Industrial and Automotive

■

Portable Computers

■

Battery-Powered Systems

, LTC and LT are registered trademarks of Linear Technology Corporation.

■

Battery Chargers

*Patent # 6, 498, 466

■

Distributed Power Systems

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TYPICAL APPLICATIO

5V Buck Converter

1N4148W

6

0.33µF

BOOST

47µH

V

IN

Efficiency vs Load Current

OUT

4

2

5.5V*

V

SW

5V

IN

2.2µF^†

100V

100

TO 60V

1A

10MQ060N

V

= 5V

LT1766

OUT

L = 47µH

V

= 12V

= 42V

+

CERAMIC

100µF 10V

SOLID

TANTALUM

IN

15

14

10

12

90

80

70

60

50

SHDN

BIAS

FB

OFF ON

15.4k

4.99k

SYNC

GND

V

C

1, 8, 9, 16

11

220pF

2.2k

0.022µF

0

0.25

0.50

0.75

1.00

1.25

1766 TA01

LOAD CURRENT (A)

1766 TA02

*FOR INPUT VOLTAGES BELOW 7.5V, SOME RESTRICTIONS MAY APPLY

^†TDK C4532X7R2A225K

1766fa

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LT1766/LT1766-5

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ABSOLUTE AXI U RATI GS

(Note 1)

Input Voltage (V_IN) ................................................. 60V

BOOST Pin Above SW ............................................ 35V

BOOST Pin Voltage ................................................. 68V

SYNC, SENSE Voltage (LT1766-5) ........................... 7V

SHDN Voltage ........................................................... 6V

BIAS Pin Voltage .................................................... 30V

FB Pin Voltage/Current (LT1766)................... 3.5V/2mA

Operating Junction Temperature Range

LT1766EFE/LT1766EFE-5/LT1766EGN/

LT1766EGN-5 (Note 8,10) ................. –40°C to 125°C

LT1766IFE/LT1766IFE-5/

LT1766IGN/LT1766IGN-5 (Note 8,10) –40°C to 125°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

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PACKAGE/ORDER I FOR ATIO

TOP VIEW

ORDER PART

NUMBER

ORDER PART

GND

SW

NC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND

SW

NC

1

2

3

4

5

6

7

8

16 GND

NUMBER

SHDN

SYNC

NC

15

14

13

12

11

10

9

SHDN

SYNC

NC

LT1766EFE

LT1766IFE

LT1766EFE-5

LT1766IFE-5

LT1766EGN

LT1766IGN

LT1766EGN-5

LT1766IGN-5

V

IN

V

IN

17

NC

BOOST

NC

FB/SENSE

NC

BOOST

NC

FB/SENSE

V

C

V

C

BIAS

GND

BIAS

GND

GN PART MARKING

GND

1766

1766I

17665

1766I5

FE PACKAGE

GN PACKAGE

16-LEAD PLASTIC SSOP

16-LEAD PLASTIC TSSOP

T_JMAX= 125°C, θ_JA= 45°C/W, θ_JC(PAD) = 10°C/W

T_JMAX= 125°C, θ_JA= 85°C/W, θ_JC(PIN 8) = 25°C/W

EXPOSED PAD (PIN 17) IS GND.

MUST BE SOLDERED TO PCB

FOUR CORNER PINS SOLDERED

TO GROUND PLANE

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at T_J= 25°C.

V

_IN= 15V, V_C= 1.5V, SHDN = 1V, BOOST open circuit, SW open circuit, unless otherwise noted.

PARAMETER CONDITIONS

5.5V ≤ V ≤ 60V

MIN

TYP

MAX

UNITS

Reference Voltage (V ) (LT1766)

1.204 1.219 1.234

1.195

V

REF

IN

V

+ 0.2 ≤ V ≤ V – 0.2

●

1.243

OL

C

OH

SENSE Voltage (LT1766-5)

5.5V ≤ V ≤ 60V

4.94

4.90

5

5.06

5.10

V

IN

V

+ 0.2V ≤ V ≤ V – 0.2V

OL

C OH

SENSE Pin Resistance (LT1766-5)

FB Input Bias Current (LT1766)

Error Amp Voltage Gain

9.5

13.8

–0.5

400

19

kΩ

µA

●

–1.5

(Notes 2, 9)

dl (V ) = ±10µA (Note 9)

200

V/V

Error Amp g

1500

1000

2000

3000

4200

µMho

m

C

V to Switch g

1.7

225

0.9

A/V

µA

V

C

m

EA Source Current

EA Sink Current

FB = 1V or V

= 4.1V

●

125

100

400

450

SENSE

FB = 1.4V or V

Duty Cycle = 0

SHDN = 1V

= 5.7V

SENSE

V Switching Threshold

C

V High Clamp

C

2.1

V

1766fa

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LT1766/LT1766-5

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at T_J= 25°C.

V_IN= 15V, V_C= 1.5V, SHDN = 1V, BOOST open circuit, SW open circuit, unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

2

MAX

UNITS

Switch Current Limit

Switch On Resistance

V Open, Boost = V + 5V, FB = 1V or V

C

= 4.1V

●

1.5

3

A

IN

SENSE

I

= 1.5A, Boost = V + 5V (Note 7)

0.2

0.3

0.4

Ω

SW

IN

Maximum Switch Duty Cycle

Switch Frequency

FB = 1V or V

= 4.1V

93

90

96

%

SENSE

V Set to Give DC = 50%

C

184

172

200

216

228

kHz

●

f

Line Regulation

5.5V ≤ V ≤ 60V

0.05

0.8

0.15

%/V

V

SW

IN

Frequency Shifting Threshold

Df = 10kHz

(Note 3)

Minimum Input Voltage

Minimum Boost Voltage

Boost Current (Note 5)

●

4.6

1.8

5.5

3

V

(Note 4) I ≤ 1.5A

V

SW

Boost = V + 5V, I = 0.5A

●

12

45

25

70

mA

IN

SW

Boost = V + 5V, I = 1.5A

IN

SW

Input Supply Current (I

)

(Note 6) V

= 5V

1.4

2.9

25

2.2

4.2

mA

VIN

BIAS

Bias Supply Current (I

(Note 6) V

= 5V

BIAS

Shutdown Supply Current

SHDN = 0V, V ≤ 60V, SW = 0V, V Open

75

200

µA

IN

C

●

Lockout Threshold

V Open

C

2.3

2.42

2.53

V

Shutdown Thresholds

V Open, Shutting Down

V Open, Starting Up

C

●

0.15

0.25

0.37

0.45

0.6

V

C

Minimum SYNC Amplitude

SYNC Frequency Range

SYNC Input Resistance

●

1.5

2.2

V

kHz

kΩ

228

700

20

Note 1: Absolute Maximum Ratings are those values beyond which the life

Note 7: Switch on resistance is calculated by dividing V to SW voltage by

the forced current (1.5A). See Typical Performance Characteristics for the

graph of switch voltage at other currents.

Note 8: The LT1766EGN, LT1766EGN-5, LT1766EFE and LT1766EFE-5 are

guaranteed to meet performance specifications from 0°C to 125°C

junction temperature. Specifications over the –40°C to 125°C operating

junction temperature range are assured by design, characterization and

correlation with statistical process controls. The LT1766IGN,

LT1766IGN-5, LT1766IFE and LT1766IFE-5 are guaranteed over the full

–40°C to 125°C operating junction temperature range.

IN

of a device may be impaired.

Note 2: Gain is measured with a V swing equal to 200mV above the low

C

clamp level to 200mV below the upper clamp level.

Note 3: Minimum input voltage is not measured directly, but is guaranteed

by other tests. It is defined as the voltage where internal bias lines are still

regulated so that the reference voltage and oscillator remain constant.

Actual minimum input voltage to maintain a regulated output will depend

upon output voltage and load current. See Applications Information.

Note 4: This is the minimum voltage across the boost capacitor needed to

guarantee full saturation of the internal power switch.

Note 9: Transconductance and voltage gain refer to the internal amplifier

exclusive of the voltage divider. To calculate gain and transconductance,

refer to the SENSE pin on fixed voltage parts. Divide the values shown by

Note 5: Boost current is the current flowing into the BOOST pin with the

pin held 5V above input voltage. It flows only during switch on time.

the ratio V /1.219.

OUT

Note 6: Input supply current is the quiescent current drawn by the input

pin when the BIAS pin is held at 5V with switching disabled. Bias supply

current is the current drawn by the BIAS pin when the BIAS pin is held at

5V. Total input referred supply current is calculated by summing input

Note 10: This IC includes overtemperature protection that is intended to

protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

supply current (I ) with a fraction of bias supply current (I

):

BIAS

VIN

I

= I + (I

)(V /V )

BIAS OUT IN

TOTAL

VIN

With V = 15V, V

= 5V, I = 1.4mA, I

= 2.9mA, I

= 2.4mA.

IN

OUT

VIN

BIAS

TOTAL

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LT1766/LT1766-5

TYPICAL PERFOR A CE CHARACTERISTICS

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Switch Peak Current Limit

FB Pin Voltage and Current

SHDN Pin Bias Current

2.5

2.0

1.5

1.0

1.234

1.229

1.224

1.219

2.0

1.5

250

200

150

100

12

T

A

= 25°C

CURRENT REQUIRED TO FORCE SHUTDOWN

(FLOWS OUT OF PIN). AFTER SHUTDOWN,

CURRENT DROPS TO A FEW µA

TYPICAL

VOLTAGE

CURRENT

1.0

0.5

0

GUARANTEED MINIMUM

1.214

1.209

1.204

AT 2.38V STANDBY THRESHOLD

(CURRENT FLOWS OUT OF PIN)

6

0

20

40

60

80

100

50

100 125

–50 –25

0

25

75

50

100 125

–50 –25

0

25

75

DUTY CYCLE (%)

JUNCTION TEMPERATURE (°C)

1766 G01

1766 G02

1766 G03

Lockout and Shutdown

Thresholds

Shutdown Supply Current

300

250

40

35

30

25

20

15

10

5

2.4

2.0

1.6

1.2

0.8

0.4

0

T

= 25°C

A

V

A

= 0V

SHDN

= 25°C

T

LOCKOUT

V

IN

= 60V

200

150

V

IN

= 15V

100

50

0

START-UP

SHUTDOWN

0

0.1

0.2

0.3

0.4

0.5

0

10

20

30

40

50

60

–50

–25

0

25

50

75

100

125

SHUTDOWN VOLTAGE (V)

INPUT VOLTAGE (V)

JUNCTION TEMPERATURE (°C)

1766 G06

1766 G05

1766 G04

Error Amplifier Transconductance

Frequency Foldback

3000

2500

2000

1500

1000

500

200

150

100

50

600

2500

2000

1500

1000

500

T

= 25°C

A

T = 25°C

A

PHASE

500

400

300

200

100

GAIN

V

C

SWITCHING

FREQUENCY

C

OUT

12pF

R

OUT

200k

–3

V

2 • 10

(

)

FB

ERROR AMPLIFIER EQUIVALENT CIRCUIT

= 50Ω

0

FB PIN

CURRENT

R

LOAD

–50

0

100

1k

10k

100k

1M

10M

–25

0

25

50

75

100

125

0

0.5

1.5

–50

1.0

FREQUENCY (Hz)

JUNCTION TEMPERATURE (°C)

V

FB

(V)

1766 G08

1766 G07

1766 G09

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LT1766/LT1766-5

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TYPICAL PERFOR A CE CHARACTERISTICS

Minimum Input Voltage with 5V

Output

Switching Frequency

BOOST Pin Current

230

220

210

200

190

180

170

7.5

7.0

6.5

6.0

5.5

5.0

45

40

35

30

25

20

15

10

5

T

= 25°C

T = 25°C

A

MINIMUM INPUT

VOLTAGE TO START

MINIMUM INPUT

VOLTAGE TO RUN

0

–50

–25

0

25

50

75

100

125

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

LOAD CURRENT (A)

1

0

0.5

1

1.5

JUNCTION TEMPERATURE (°C)

SWITCH CURRENT (A)

1766 G10

1766 G11

1766 G12

Switch Minimum ON Time

vs Temperature

V_CPin Shutdown Threshold

Switch Voltage Drop

600

500

400

300

2.1

1.9

450

400

350

300

250

200

150

100

50

T

= 125°C

J

1.7

1.5

1.3

1.1

0.9

T

= 25°C

J

200

100

0

T

= –40°C

J

0.7

0

0.5

1

1.5

50

100 125

50

100 125

–50 –25

0

25

75

–50 –25

0

25

75

SWITCH CURRENT (A)

JUNCTION TEMPERATURE (°C)

1766 G14

1766 G15

1766 G13

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PI FU CTIO S

GND (Pins 1, 8, 9, 16, 17): The GND pin connections act

as the reference for the regulated output, so load regula-

tion will suffer if the “ground” end of the load is not at the

same voltage as the GND pins of the IC. This condition will

occur when load current or other currents flow through

metal paths between the GND pins and the load ground.

Keep the paths between the GND pins and the load ground

short and use a ground plane when possible. The GND pin

also acts as a heat sink and should be soldered to a large

copper plane to reduce thermal resistance. For the FE

package, the exposed pad should be soldered to the

coppergroundplaneunderneaththedevice. (SeeApplica-

tions Information—Layout Considerations.)

SW (Pin 2): The switch pin is the emitter of the on-chip

power NPN switch. This pin is driven up to the input pin

voltage during switch on time. Inductor current drives the

switch pin negative during switch off time. Negative volt-

age is clamped with the external catch diode. Maximum

negative switch voltage allowed is –0.8V.

NC (Pins 3, 5, 7, 13): No Connection.

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LT1766/LT1766-5

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PI FU CTIO S

V_IN(Pin 4): This is the collector of the on-chip power NPN

switch. V_INpowers the internal control circuitry when a

voltage on the BIAS pin is not present. High dI/dt edges

occur on this pin during switch turn on and off. Keep the

path short from the V_INpin through the input bypass

capacitor, through the catch diode back to SW. All trace

inductanceonthispathwillcreateavoltagespikeatswitch

off, adding to the V_CEvoltage across the internal NPN.

FB/SENSE (Pin 12): The feedback pin is used to set the

output voltage using an external voltage divider that gen-

erates 1.22V at the pin for the desired output voltage. The

5V fixed output voltage parts have the divider included on

the chip and the FB pin is used as a SENSE pin, connected

directly to the 5V output. Three additional functions are

performed by the FB pin. When the pin voltage drops

below 0.6V, switch current limit is reduced and the exter-

nal SYNC function is disabled. Below 0.8V, switching

frequency is also reduced. See Feedback Pin Functions in

Applications Information for details.

BOOST (Pin 6): The BOOST pin is used to provide a drive

voltage, higher than the input voltage, to the internal

bipolarNPNpowerswitch. Withoutthisaddedvoltage, the

typical switch voltage loss would be about 1.5V. The

additional BOOST voltage allows the switch to saturate

and voltage loss approximates that of a 0.2Ω FET struc-

ture, but with much smaller die area.

SYNC (Pin 14): The SYNC pin is used to synchronize the

internal oscillator to an external signal. It is directly logic

compatible and can be driven with any signal between

10% and 90% duty cycle. The synchronizing range is

equal to initial operating frequency up to 700kHz. See

Synchronizing in Applications Information for details.

BIAS (Pin 10): The BIAS pin is used to improve efficiency

when operating at higher input voltages and light load

current. Connecting this pin to the regulated output volt-

age forces most of the internal circuitry to draw its

operating current from the output voltage rather than the

input supply. This architecture increases efficiency espe-

cially when the input voltage is much higher than the

output. Minimum output voltage setting for this mode of

operation is 3V.

SHDN (Pin 15): The SHDN pin is used to turn off the

regulator and to reduce input drain current to a few

microamperes. This pin has two thresholds: one at 2.38V

to disable switching and a second at 0.4V to force com-

plete micropower shutdown. The 2.38V threshold func-

tions as an accurate undervoltage lockout (UVLO);

sometimes used to prevent the regulator from delivering

power until the input voltage has reached a predetermined

level.

V_C(Pin 11) The V_Cpin is the output of the error amplifier

and the input of the peak switch current comparator. It is

normally used for frequency compensation, but can also

serve as a current clamp or control loop override. V_Csits

at about 0.9V for light loads and 2.1V at maximum load. It

can be driven to ground to shut off the regulator, but if

driven high, current must be limited to 4mA.

If the SHDN pin functions are not required, the pin can

either be left open (to allow an internal bias current to lift

the pin to a default high state) or be forced high to a level

not to exceed 6V.

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BLOCK DIAGRA

The LT1766 is a constant frequency, current mode buck

converter. This means that there is an internal clock and

twofeedbackloopsthatcontrolthedutycycleofthepower

switch. In addition to the normal error amplifier, there is a

current sense amplifier that monitors switch current on a

cycle-by-cycle basis. A switch cycle starts with an oscilla-

tor pulse which sets the R_Sflip-flop to turn the switch on.

When switch current reaches a level set by the inverting

input of the comparator, the flip-flop is reset and the

switch turns off. Output voltage control is obtained by

using the output of the error amplifier to set the switch

current trip point. This technique means that the error

amplifier commands current to be delivered to the output

rather than voltage. A voltage fed system will have low

phase shift up to the resonant frequency of the inductor

and output capacitor, then an abrupt 180° shift will occur.

1766fa

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LT1766/LT1766-5

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BLOCK DIAGRA

The current fed system will have 90° phase shift at a much

lower frequency, but will not have the additional 90° shift

until well beyond the LC resonant frequency. This makes

itmucheasiertofrequencycompensatethefeedbackloop

and also gives much quicker transient response.

regulated output voltage). This will improve efficiency if

the BIAS pin voltage is lower than regulator input voltage.

High switch efficiency is attained by using the BOOST pin

to provide a voltage to the switch driver which is higher

than the input voltage, allowing switch to be saturated.

This boosted voltage is generated with an external

capacitor and diode. Two comparators are connected to

the shutdown pin. One has a 2.38V threshold for under-

voltage lockout and the second has a 0.4V threshold for

complete shutdown.

Most of the circuitry of the LT1766 operates from an

internal 2.9V bias line. The bias regulator normally draws

power from the regulator input pin, but if the BIAS pin is

connected to an external voltage higher than 3V, bias

powerwillbedrawnfromtheexternalsource(typicallythe

V

IN

4

R

LIMIT

R

SENSE

–

+

2.9V BIAS

REGULATOR

INTERNAL

CC

BIAS

10

V

CURRENT

COMPARATOR

SLOPE COMP

Σ

SYNC 14

BOOST

6

ANTISLOPE COMP

SHUTDOWN

COMPARATOR

200kHz

OSCILLATOR

–

+

S

Q1

POWER

SWITCH

R

DRIVER

CIRCUITRY

S

FLIP-FLOP

R

0.4V

5.5µA

2

SW

SHDN 15

+

–

FREQUENCY

FOLDBACK

LOCKOUT

COMPARATOR

×1

Q2

FOLDBACK

CURRENT

LIMIT

V

C(MAX)

CLAMP

Q3

ERROR

AMPLIFIER

= 2000µMho

CLAMP

–

+

12

FB

g

m

11

1.22V

2.38V

V

C

GND

1, 8, 9, 16, 17

1766 F01

Figure 1. LT1766 Block Diagram

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LT1766/LT1766-5

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APPLICATIO S I FOR ATIO

FEEDBACK PIN FUNCTIONS

switching regulator to operate at very low duty cycles,

and the average current through the diode and inductor

is equal to the short-circuit current limit of the switch

(typically 2A for the LT1766, folding back to less than

1A). Minimum switch on time limitations would prevent

the switcher from attaining a sufficiently low duty cycle

if switching frequency were maintained at 200kHz, so

frequency is reduced by about 5:1 when the feedback pin

voltagedropsbelow0.8V(seeFrequencyFoldbackgraph).

This does not affect operation with normal load condi-

tions; one simply sees a gear shift in switching frequency

during start-up as the output voltage rises.

The feedback (FB) pin on the LT1766 is used to set output

voltage and provide several overload protection features.

The first part of this section deals with selecting resistors

to set output voltage and the remaining part talks about

foldback frequency and current limiting created by the FB

pin. Please read both parts before committing to a final

design. The 5V fixed output voltage part (LT1766-5) has

internaldividerresistorsandtheFBpinisrenamedSENSE,

connected directly to the output.

The suggested value for the output divider resistor (see

Figure 2) from FB to ground (R2) is 5k or less, and a

formula for R1 is shown below. The output voltage error

caused by ignoring the input bias current on the FB pin is

less than 0.25% with R2 = 5k. A table of standard 1%

values is shown in Table 1 for common output voltages.

Please read the following if divider resistors are increased

above the suggested values.

In addition to lower switching frequency, the LT1766 also

operates at lower switch current limit when the feedback

pin voltage drops below 0.6V. Q2 in Figure 2 performs this

function by clamping the V_Cpin to a voltage less than its

normal 2.1V upper clamp level. This foldback current limit

greatly reduces power dissipation in the IC, diode and in-

ductor during short-circuit conditions. External synchro-

nization is also disabled to prevent interference with fold-

back operation. Again, it is nearly transparent to the user

under normal load conditions. The only loads that may be

affected are current source loads which maintain full load

current with output voltage less than 50% of final value. In

theseraresituationsthefeedbackpincanbeclampedabove

0.6Vwithanexternaldiodetodefeatfoldbackcurrentlimit.

Caution: clamping the feedback pin means that frequency

shifting will also be defeated, so a combination of high in-

putvoltageanddeadshortedoutputmaycausetheLT1766

to lose control of current limit.

R2 V

−1.22

1.22

(

)

OUT

R1=

Table 1

OUTPUT

VOLTAGE

(V)

R1

% ERROR AT OUTPUT

R2

(NEAREST 1%) DUE TO DISCREET 1%

(k

Ω

)

(k

Ω

)

RESISTOR STEPS

+0.32

3

3.3

5

4.99

4.75

4.47

4.32

4.12

7.32

8.45

15.4

18.7

24.9

30.9

36.5

46.4

–0.43

–0.30

6

+0.38

8

+0.20

The internal circuitry which forces reduced switching

frequency also causes current to flow out of the feedback

pin when output voltage is low. The equivalent circuitry is

shown in Figure 2. Q1 is completely off during normal

operation. If the FB pin falls below 0.8V, Q1 begins to

conduct current and reduces frequency at the rate of

approximately 1.4kHz/µA. To ensure adequate frequency

foldback (under worst-case short-circuit conditions), the

external divider Thevinin resistance must be low enough

to pull 115µA out of the FB pin with 0.44V on the pin (R_DIV

≤ 3.8k). The net result is that reductions in frequency and

current limit are affected by output voltage divider imped-

ance. Although divider impedance is not critical, caution

10

12

15

–0.54

+0.24

–0.27

More Than Just Voltage Feedback

The feedback pin is used for more than just output

voltage sensing. It also reduces switching frequency and

current limit when output voltage is very low (see the

Frequency Foldback graph in Typical Performance Char-

acteristics). This is done to control power dissipation in

both the IC and in the external diode and inductor during

short-circuit conditions. A shorted output requires the

1766fa

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LT1766/LT1766-5

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APPLICATIO S I FOR ATIO

U

V

SW

LT1766

L1

TO FREQUENCY

SHIFTING

OUTPUT

5V

1.4V

Q1

ERROR

AMPLIFIER

R1

1.2V

+

–

R4

2k

R3

1k

FB

+

C1

BUFFER

Q2

R2

5k

TO SYNC CIRCUIT

V

GND

C

1766 F02

Figure 2. Frequency and Current Limit Foldback

should be used if resistors are increased beyond the

suggested values and short-circuit conditions occur with

high input voltage. High frequency pickup will increase

and the protection accorded by frequency and current

foldback will decrease.

V

AT I

= 1A

OUT

40mV/DIV

0.5A/DIV

= 0.1A

INDUCTOR CURRENT

AT I = 1A

CHOOSING THE INDUCTOR

OUT

For most applications, the output inductor will fall into the

range of 15µH to 100µH. Lower values are chosen to

reduce physical size of the inductor. Higher values allow

more output current because they reduce peak current

seen by the LT1766 switch, which has a 1.5A limit. Higher

values also reduce output ripple voltage.

INDUCTOR CURRENT

AT I = 0.1A

OUT

V

= 40V

OUT

L = 47µH

2.5µs/DIV

1766 F03

IN

= 5V

C = 100µF, 10V, 0.1Ω

Figure 3. LT1766 Ripple Voltage Waveform

When choosing an inductor you will need to consider

output ripple voltage, maximum load current, peak induc-

tor current and fault current in the inductor. In addition,

other factors such as core and copper losses, allowable

component height, EMI, saturation and cost should also

be considered. The following procedure is suggested as a

way of handling these somewhat complicated and con-

flicting requirements.

value to achieve a desirable output ripple voltage level. If

output ripple voltage is of less importance, the subse-

quent suggestions in Peak Inductor and Fault Current

and EMI will additionally help in the selection of the

inductor value.

Peak-to-peak output ripple voltage is the sum of a triwave

(created by peak-to-peak ripple current (I_LP-P) times ESR)

and a square wave (created by parasitic inductance (ESL)

and ripple current slew rate). Capacitive reactance is

assumed to be small compared to ESR or ESL.

Output Ripple Voltage

Figure 3 shows a typical output ripple voltage waveform

for the LT1766. Ripple voltage is determined by ripple

current (I_LP-P) through the inductor and the high

frequencyimpedanceoftheoutputcapacitor.Thefollow-

ing equations will help in choosing the required inductor

dI

dt

V_RIPPLE= I

ESR + ESL

_LP-P)( ) (

(

)

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APPLICATIO S I FOR ATIO

where:

or not the inductor must withstand continuous fault

conditions.

ESR = equivalent series resistance of the output

capacitor

If maximum load current is 0.5A, for instance, a 0.5A

inductor may not survive a continuous 2A overload condi-

tion. Dead shorts will actually be more gentle on the

inductor because the LT1766 has frequency and current

limit foldback.

ESL = equivalent series inductance of the output

capacitor

dI/dt = slew rate of inductor ripple current = V_IN/L

Peak-to-peak ripple current (I_LP-P) through the inductor

and into the output capacitor is typically chosen to be

between 20% and 40% of the maximum load current. It is

approximated by:

Peak switch and inductor current can be significantly

higher than output current, especially with smaller induc-

tors and lighter loads, so don’t omit this step. Powdered

iron cores are forgiving because they saturate softly,

whereas ferrite cores saturate abruptly. Other core

V

V – V

IN OUT

(

=

_OUT)(

)

I_LP-P

Table 2

V

f L

_IN)( )( )

(

VENDOR/

PART NO.

VALUE

H)

I

DCR

(Ohms)

HEIGHT

(mm)

DC

(

µ

(Amps)

Example: with V_IN= 40V, V_OUT= 5V, L = 47µH, ESR = 0.1Ω

and ESL = 10nH, output ripple voltage can be approxi-

mated as follows:

Coiltronics

CTX15-1P

15

33

47

68

1.4

1.1

1.3

1.4

2.4

1.9

1.7

1.4

0.087

0.08

4.2

6

CTX15-1

CTX33-2P

0.126

0.106

0.099

0.146

0.19

5 40 − 5

( )(

)

I_P-P

dI

=

= 0.465A

CTX33-2

6

40 47 •10⁻⁶200 •10³

( )

(

)(

)

UP2-330

5.9

40

UP2-470

=

= 10⁶• 0.85

47 •10⁻⁶

UP2-680

dt

UP2-101

100

0.277

V_RIPPLE= 0.465A 0.1 + 10 •10⁻⁹10⁶0.85

(

)(

)

(

)

(

)(

)

Sumida

= 0.0465 + 0.0085 = 55mV_P-P

CDRH6D28-150M

CDRH6D38-150M

CDRH6D28-330M

CDRH104R-330M

CDRH125-330M

CDRH104R-470M

CDRH125-470M

CDRH6D38-680M

CDRH104R-680M

CDRH125-680M

CDRH104R-101M

CDRH125-101M

Coilcraft

15

1.4

1.6

0.076

0.062

0.122

0.069

0.044

0.095

0.058

0.173

0.158

0.093

0.225

0.120

3

4

To reduce output ripple voltage further requires an in-

crease in the inductor value or a reduction in the capacitor

ESR. The latter can effect loop stability since the ESR

forms a useful zero in the overall loop response. Typically

the inductor value is adjusted with the trade-off being a

physically larger inductor with the possibility of increased

component height and cost. Choosing a smaller inductor

with lighter loads may result in discontinuous operation

but the LT1766 is designed to work well in both continu-

ous or discontinuous mode.

33

0.97

2.1

3

33

3.8

6

33

2.1

47

2.1

3.8

6

47

1.8

68

0.75

1.5

4

68

3.8

6

68

1.5

100

1.35

1.3

3.8

6

Peak Inductor Current and Fault Current

DT3316P-153

DT3316P-333

DT3316P-473

15

33

47

1.8

1.3

1

0.06

0.09

0.11

5

To ensure that the inductor will not saturate, the peak

inductor current should be calculated knowing the maxi-

mum load current. An appropriate inductor should then

bechosen.Inaddition,adecisionshouldbemadewhether

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APPLICATIO S I FOR ATIO

U

materials fall somewhere in between. The following for-

mula assumes continuous mode of operation, but errs

only slightly on the high side for discontinuous mode, so

it can be used for all conditions.

Maximum load current would be equal to maximum

switch current for an infinitely large inductor, but with

finite inductor size, maximum load current is reduced by

one-halfpeak-to-peakinductorcurrent(I_LP-P).Thefollow-

ing formula assumes continuous mode operation, imply-

ing that the term on the right is less than one-half of I_P.

V_OUTV – V_OUT

(

)( ^IN

)

(I_LP-P

2

)

I_PEAK= I_OUT

+

= I_OUT+

2 V f L

( )( ^IN)( )( )

I_OUT(MAX)

=

Continuous Mode

EMI

V

OUT

+ V V − V

– V

I_LP-P

2

(

_F)(

)

IN

OUT F

I_P–

=I_P−

Decide if the design can tolerate an “open” core geometry

like a rod or barrel, which have high magnetic field

radiation, or whether it needs a closed core like a toroid to

prevent EMI problems. This is a tough decision because

the rods or barrels are temptingly cheap and small and

there are no helpful guidelines to calculate when the

magnetic field radiation will be a problem.

2 L f V

( )( )(

)

IN

For V_OUT= 5V, V_IN= 8V, V_F(D1)= 0.63V, f = 200kHz and

L = 20µH:

5 + 0.63 8 − 5 – 0.63

(

)(

)

8

I_{OUT MAX}₎= 1.5 −

(

2 20 •10⁻⁶200•10³

( )

)(

)

=1.5 − 0.21= 1.29A

Additional Considerations

Note that there is less load current available at the higher

inputvoltagebecauseinductorripplecurrentincreases.At

V_IN= 15V, duty cycle is 33% and for the same set of

conditions:

After making an initial choice, consider additional factors

such as core losses and second sourcing, etc. Use the

experts in Linear Technology’s Applications department if

you feel uncertain about the final choice. They have

experience with a wide range of inductor types and can tell

you about the latest developments in low profile, surface

mounting, etc.

5 + 0.63 15 − 5 – 0.63

(

)(

)

I

_OUT(MAX)= 1.5 −

2 20 •10⁻⁶200•10³15

( )

)(

)

= 1.5 − 0.44 = 1.06A

Maximum Output Load Current

To calculate actual peak switch current with a given set of

conditions, use:

Maximum load current for a buck converter is limited by

themaximumswitchcurrentrating(I_P).Thecurrentrating

fortheLT1766is1.5A. Unlikemostcurrentmodeconvert-

ers, the LT1766 maximum switch current limit does not

fall off at high duty cycles. Most current mode converters

suffer a drop off of peak switch current for duty cycles

above 50%. This is due to the effects of slope compensa-

tion required to prevent subharmonic oscillations in cur-

rent mode converters. (For detailed analysis, see Applica-

tion Note 19.)

I_LP-P

2

I_{SW PEAK}= I_OUT

+

(

)

(V_OUT+ V ) V − V

– V

F

(

)

F

IN

OUT

= I_OUT

2 L f V

( )( )(

)

IN

Reduced Inductor Value and Discontinuous Mode

If the smallest inductor value is of most importance to a

converter design, in order to reduce inductor size/cost,

discontinuous mode may yield the smallest inductor solu-

tion. The maximum output load current in discontinuous

mode, however, must be calculated and is defined later in

The LT1766 is able to maintain peak switch current limit over

thefulldutycyclerangebyusingpatentedcircuitry*tocancel

the effects of slope compensation on peak switch current

without affecting the frequency compensation it provides.

*Patent # 6, 498, 466

this section.

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Discontinuous mode is entered when the output load

current is less than one-half of the inductor ripple current

(I_LP-P). In this mode, inductor current falls to zero before

thenextswitchturnon(seeFigure8). Buckconverterswill

beindiscontinuousmodeforoutputloadcurrentgivenby:

Short-Circuit Considerations

The LT1766 is a current mode controller. It uses the V_C

node voltage as an input to a current comparator which

turns off the output switch on a cycle-by-cycle basis as

this peak current is reached. The internal clamp on the V_C

node, nominally 2V, then acts as an output switch peak

current limit. This action becomes the switch current limit

specification. The maximum available output power is

then determined by the switch current limit.

(V_OUT+ V )(V – V_OUT– V )

F

IN

F

I_OUT

<

(2)(V )(f)(L)

IN

Discontinuous Mode

The inductor value in a buck converter is usually chosen

large enough to keep inductor ripple current (I_LP-P) low;

this is done to minimize output ripple voltage and maxi-

mize output load current. In the case of large inductor

values, as seen in the equation above, discontinuous

mode will be associated with “light loads.”

A potential controllability problem could occur under

short-circuit conditions. If the power supply output is

short circuited, the feedback amplifier responds to the low

output voltage by raising the control voltage, V_C, to its

peak current limit value. Ideally, the output switch would

be turned on, and then turned off as its current exceeded

thevalueindicatedbyV_C.However,thereisfiniteresponse

time involved in both the current comparator and turnoff

of the output switch. These result in a minimum on time

t_ON(MIN). When combined with the large ratio of V_INto

(V_F+ I • R), the diode forward voltage plus inductor I • R

voltage drop, the potential exists for a loss of control.

Expressed mathematically the requirement to maintain

control is:

When choosing small inductor values, however, discon-

tinuous mode will occur at much higher output load

currents. The limit to the smallest inductor value that can

be chosen is set by the LT1766 peak switch current (I_P)

and the maximum output load current required, given by:

2

I_P

I_OUT(MAX)

Discontinuous Mode

=

(2)(I_LP-P

)

2

I

(f)(L)(V )

IN

(_P) (

)

=

V_F+I•R

2(V_OUT+ V )(V – V_OUT– V )

F

IN

F

f • t_ON

≤

V

IN

Example: For V_IN= 15V, V_OUT= 5V, V_F= 0.63V, f = 200kHz

where:

and L = 10µH.

f = switching frequency

(1.5)²•(200•10³)(10^–5)(15)

2(5 + 0.63)(15 – 5 – 0.63)

I_OUT(MAX)

t_ON= switch minimum on time

V_F= diode forward voltage

V_IN= Input voltage

=

Discontinuous

Mode

I • R = inductor I • R voltage drop

I_OUT(MAX)

Discontinuous Mode

= 0.639A

If this condition is not observed, the current will not be

limited at I_PK, but will cycle-by-cycle ratchet up to some

higher value. Using the nominal LT1766 clock frequency

of 200KHz, a V_INof 40V and a (V_F+ I • R) of say 0.7V, the

maximum t_ONto maintain control would be approximately

90ns, an unacceptably short time.

What has been shown here is that if high inductor ripple

current and discontinuous mode operation can be toler-

ated, small inductor values can be used. If a higher output

load current is required, the inductor value must be

increased. If I_OUT(MAX)no longer meets the discontinuous

mode criteria, use the I_OUT(MAX)equation for continuous

mode; the LT1766 is designed to operate well in both

modes of operation, allowing a large range of inductor

values to be used.

The solution to this dilemma is to slow down the oscillator

when the FB pin voltage is abnormally low thereby indicat-

ing some sort of short-circuit condition. Oscillator fre-

quency is unaffected until FB voltage drops to about 2/3 of

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APPLICATIO S I FOR ATIO

U

tantalum capacitors fail during very high turn-on surges,

which do not occur at the output of regulators. High

discharge surges, such as when the regulator output is

dead shorted, do not harm the capacitors.

its normal value. Below this point the oscillator frequency

decreases roughly linearly down to a limit of about 40kHz.

Thisloweroscillatorfrequencyduringshort-circuitcondi-

tions can then maintain control with the effective mini-

mum on time.

Unlike the input capacitor, RMS ripple current in the

output capacitor is normally low enough that ripple cur-

rent rating is not an issue. The current waveform is

triangular with a typical value of 125mA_RMS. The formula

to calculate this is:

It is recommended that for [V_IN/(V_OUT+ V_F)] ratios > 10,

a soft-start circuit should be used to control the output

capacitor charge rate during start-up or during recovery

from an output short circuit, thereby adding additional

control over peak inductor current. See Buck Converter

with Adjustable Soft-Start later in this data sheet.

Output capacitor ripple current (RMS):

0.29 V

_OUT)(

=

V − V

IN OUT

(

)

I_{RIPPLE RMS}

(

)

OUTPUT CAPACITOR

L f V

( )( )(

)

IN

The output capacitor is normally chosen by its effective

series resistance (ESR), because this is what determines

output ripple voltage. To get low ESR takes volume, so

physically smaller capacitors have high ESR. The ESR

range for typical LT1766 applications is 0.05Ω to 0.2Ω. A

typical output capacitor is an AVX type TPS, 100µF at 10V,

with a guaranteed ESR less than 0.1Ω. This is a “D” size

surface mount solid tantalum capacitor. TPS capacitors

are specially constructed and tested for low ESR, so they

give the lowest ESR for a given volume. The value in

microfarads is not particularly critical, and values from

22µF to greater than 500µF work well, but you cannot

cheat mother nature on ESR. If you find a tiny 22µF solid

tantalumcapacitor, itwillhavehighESR, andoutputripple

voltage will be terrible. Table 2 shows some typical solid

tantalum surface mount capacitors.

Ceramic Capacitors

Higher value, lower cost ceramic capacitors are now

becoming available. They are generally chosen for their

good high frequency operation, small size and very low

ESR (effective series resistance). Their low ESR reduces

output ripple voltage but also removes a useful zero in the

loop frequency response, common to tantalum capaci-

tors. To compensate for this, a resistor R_Ccan be placed

in series with the V_Ccompensation capacitor C_C. Care

must be taken however, since this resistor sets the high

frequency gain of the error amplifier, including the gain at

the switching frequency. If the gain of the error amplifier

is high enough at the switching frequency, output ripple

voltage (although smaller for a ceramic output capacitor)

may still affect the proper operation of the regulator. A

filter capacitor C_Fin parallel with the R_C/C_Cnetwork is

suggested to control possible ripple at the V_Cpin. An “All

Ceramic” solution is possible for the LT1766 by choosing

the correct compensation components for the given

application.

Table 3. Surface Mount Solid Tantalum Capacitor ESR

and Ripple Current

E Case Size

ESR (Max,

Ω

)

Ripple Current (A)

AVX TPS, Sprague 593D

D Case Size

0.1 to 0.3

0.2 (typ)

0.7 to 1.1

AVX TPS, Sprague 593D

C Case Size

0.7 to 1.1

0.5 (typ)

Example: For V_IN= 8V to 40V, V_OUT= 3.3V at 1A, the

LT1766 can be stabilized, provide good transient re-

sponse and maintain very low output ripple voltage using

the following component values: (refer to the first page of

this data sheet for component references) C3 = 2.2µF,

R_C= 4.7k, C_C= 15nF, C_F= 220pF and C1 = 47µF. See

Application Note 19 for further detail on techniques for

proper loop compensation.

AVX TPS

Many engineers have heard that solid tantalum capacitors

are prone to failure if they undergo high surge currents.

This is historically true, and type TPS capacitors are

speciallytestedforsurgecapability,butsurgeruggedness

is not a critical issue with the output capacitor. Solid

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APPLICATIO S I FOR ATIO

rated. AVX recommends derating capacitor operating

voltage by 2:1 for high surge applications.

INPUT CAPACITOR

Step-down regulators draw current from the input supply

in pulses. The rise and fall times of these pulses are very

fast. The input capacitor is required to reduce the voltage

ripple this causes at the input of LT1766 and force the

switching current into a tight local loop, thereby minimiz-

ing EMI. The RMS ripple current can be calculated from:

CATCH DIODE

HighestefficiencyoperationrequirestheuseofaSchottky

type diode. DC switching losses are minimized due to its

low forward voltage drop, and AC behavior is benign due

to its lack of a significant reverse recovery time. Schottky

diodes are generally available with reverse voltage ratings

ofupto60Vandeven100V, andarepricecompetitivewith

other types.

2

I_{RIPPLE RMS}= I_OUTV_OUTV – V

/ V

IN

(

)

IN

OUT

(

)

Ceramiccapacitorsareidealforinputbypassing.At200kHz

switching frequency, the energy storage requirement of

the input capacitor suggests that values in the range of

2.2µF to 20µF are suitable for most applications. If opera-

tionisrequiredclosetotheminimuminputrequiredbythe

output of the LT1766, a larger value may be required. This

is to prevent excessive ripple causing dips below the

minimum operating voltage resulting in erratic operation.

The use of so-called “ultrafast” recovery diodes is gener-

ally not recommended. When operating in continuous

mode, the reverse recovery time exhibited by “ultrafast”

diodes will result in a slingshot type effect. The power

internalswitchwillrampupV_INcurrentintothediodeinan

attempt to get it to recover. Then, when the diode has

finallyturnedoff,sometensofnanosecondslater,theV_SW

node voltage ramps up at an extremely high dV/dt, per-

haps 5 to even 10V/ns! With real world lead inductances,

the V_SWnode can easily overshoot the V_INrail. This can

result in poor RFI behavior and if the overshoot is severe

enough, damage the IC itself.

Depending on how the LT1766 circuit is powered up you

may need to check for input voltage transients.

The input voltage transients may be caused by input

voltage steps or by connecting the LT1766 converter to an

already powered up source such as a wall adapter. The

sudden application of input voltage will cause a large

surge of current in the input leads that will store energy in

the parasitic inductance of the leads. This energy will

causetheinputvoltagetoswingabovetheDClevelofinput

power source and it may exceed the maximum voltage

rating of input capacitor and LT1766.

The suggested catch diode (D1) is an International Recti-

fier 10MQ060N Schottky. It is rated at 1.5A average

forward current and 60V reverse voltage. Typical forward

voltage is 0.63V at 1A. The diode conducts current only

during switch off time. Peak reverse voltage is equal to

regulatorinputvoltage.Averageforwardcurrentinnormal

operation can be calculated from:

The easiest way to suppress input voltage transients is to

addasmallaluminumelectrolyticcapacitorinparallelwith

the low ESR input capacitor. The selected capacitor needs

to have the right amount of ESR in order to critically

dampen the resonant circuit formed by the input lead

inductance and the input capacitor. The typical values of

ESRwillfallintherangeof0.5Ωto2Ωandcapacitancewill

fall in the range of 5µF to 50µF.

I_OUTV – V

(

)

IN

OUT

I_D(AVG)

=

V

IN

This formula will not yield values higher than 1.5A with

maximum load current of 1.5A. The only reason to

consider a larger diode is the worst-case condition of a

high input voltage and shorted output. With a shorted

condition, diode current will increase to a typical value of

2A, determined by peak switch current limit. This is safe

forshortperiodsoftime, butitwouldbeprudenttocheck

with the diode manufacturer if continuous operation

under these conditions must be tolerated.

If tantalum capacitors are used, values in the 22µF to

470µF range are generally needed to minimize ESR and

meet ripple current and surge ratings. Care should be

taken to ensure the ripple and surge ratings are not

exceeded. The AVX TPS and Kemet T495 series are surge

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SHUTDOWN FUNCTION AND UNDERVOLTAGE

LOCKOUT

BOOST PIN

Formostapplications, theboostcomponentsarea0.33µF

capacitor and a 1N4148W diode. The anode is typically

connected to the regulated output voltage to generate a

voltage approximately V_OUTabove V_INto drive the output

stage. However, the output stage discharges the boost

capacitor during the on time of the switch. The output

driver requires at least 3V of headroom throughout this

period to keep the switch fully saturated. If the output

voltage is less than 3.3V, it is recommended that an

alternate boost supply is used. The boost diode can be

connected to the input, although, care must be taken to

prevent the 2× V_INboost voltage from exceeding the

BOOST pin absolute maximum rating. The additional

voltage across the switch driver also increases power

loss, reducing efficiency. If available, and independent

supply can be used with a local bypass capacitor.

Figure 4 shows how to add undervoltage lockout (UVLO)

totheLT1766. Typically, UVLOisusedinsituationswhere

the input supply is current limited, or has a relatively high

source resistance. A switching regulator draws constant

power from the source, so source current increases as

source voltage drops. This looks like a negative resistance

loadtothesourceandcancausethesourcetocurrentlimit

or latch low under low source voltage conditions. UVLO

prevents the regulator from operating at source voltages

where these problems might occur.

Threshold voltage for lockout is about 2.38V. A 5.5µA bias

currentflowsout ofthepinatthisthreshold. Theinternally

generated current is used to force a default high state on

the shutdown pin if the pin is left open. When low shut-

down current is not an issue, the error due to this current

can be minimized by making R_LO10k or less. If shutdown

currentisanissue, R_LOcanberaisedto100k, buttheerror

due to initial bias current and changes with temperature

should be considered.

A 0.33µF boost capacitor is recommended for most appli-

cations. Almost any type of film or ceramic capacitor is

suitable, but the ESR should be <1Ω to ensure it can be

fully recharged during the off time of the switch. The

capacitor value is derived from worst-case conditions of

4700ns on time, 42mA boost current and 0.7V discharge

ripple. The boost capacitor value could be reduced under

less demanding conditions, but this will not improve

circuitoperationorefficiency.Underlowinputvoltageand

low load conditions, a higher value capacitor will reduce

discharge ripple and improve start-up operation.

R_LO= 10k to 100k 25k suggested

(

)

R_LOV − 2.38V

(

)

IN

R_HI=

2.38V −R_LO5.5µA

(

)

V_IN= Minimum input voltage

R

FB

L1

LT1766

OUTPUT

V

SW

2.38V

+

–

IN

INPUT

STANDBY

R

HI

5.5µA

+

SHDN

C1

+

–

TOTAL

SHUTDOWN

C2

LO

0.4V

GND

1766 F04

Figure 4. Undervoltage Lockout

1766fa

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APPLICATIO S I FOR ATIO

Keep the connections from the resistors to the shutdown

pin short and make sure that interplane or surface capaci-

tance to the switching nodes are minimized. If high

resistor values are used, the shutdown pin should be

bypassed with a 1000pF capacitor to prevent coupling

problems from the switch node. If hysteresis is desired in

the undervoltage lockout point, a resistor R_FBcan be

added to the output node. Resistor values can be calcu-

lated from:

compensation used to prevent subharmonic switching is

reduced. This type of subharmonic switching only occurs

at input voltages less than twice output voltage. Higher

inductor values will tend to eliminate this problem. See

Frequency Compensation section for a discussion of an

entirely different cause of subharmonic switching before

assuming that the cause is insufficient slope compensa-

tion. Application Note 19 has more details on the theory

of slope compensation.

At power-up, when V_Cis being clamped by the FB pin (see

Figure2,Q2),thesyncfunctionisdisabled.Thisallowsthe

frequency foldback to operate in the shorted output con-

dition. During normal operation, switching frequency is

controlledbytheinternaloscillatoruntiltheFBpinreaches

0.6V, after which the SYNC pin becomes operational. If no

synchronization is required, this pin should be connected

to ground.

R_LOV − 2.38 ∆V/V

+1 + ∆V

(

)

[

IN

OUT

]

R_HI=

2.38 −R_LO5.5µA

(

)

R = R

V

/

∆V

(

)

(

)

FB

HI

OUT

25k suggested for R_LO

V_IN= Input voltage at which switching stops as input

voltage descends to trip level

∆V = Hysteresis in input voltage level

LAYOUT CONSIDERATIONS

Example: output voltage is 5V, switching is to stop if input

voltage drops below 12V and should not restart unless

input rises back to 13.5V. ∆V is therefore 1.5V and

V_IN= 12V. Let R_LO= 25k.

As with all high frequency switchers, when considering

layout,caremustbetakeninordertoachieveoptimalelec-

trical, thermal and noise performance. For maximum effi-

ciency, switch rise and fall times are typically in the nano-

second range. To prevent noise both radiated and con-

ducted, the high speed switching current path, shown in

Figure 5, must be kept as short as possible. This is imple-

mented in the suggested layout of Figure 6. Shortening

this path will also reduce the parasitic trace inductance of

approximately 25nH/inch. At switch off, this parasitic in-

ductance produces a flyback spike across the LT1766

switch. When operating at higher currents and input volt-

ages, with poor layout, this spike can generate voltages

acrosstheLT1766thatmayexceeditsabsolutemaximum

25k 12 − 2.38 1.5/5 +1 + 1.5

(

)

[

]

R_HI=

2.38 – 25k 5.5µA

(

25k 10.41

(

)

=

= 116k

2.24

R_FB= 116k 5/1.5 = 387k

(

)

SYNCHRONIZING

The SYNC input must pass from a logic level low, through

the maximum synchronization threshold with a duty cycle

between 10% and 90%. The input can be driven directly

from a logic level output. The synchronizing range is equal

to initial operating frequency up to 700kHz. This means

that minimum practical sync frequency is equal to the

worst-case high self-oscillating frequency (228kHz), not

the typical operating frequency of 200kHz. Caution should

be used when synchronizing above 265kHz because at

highersyncfrequenciestheamplitudeoftheinternalslope

LT1766

L1

5V

HIGH

FREQUENCY

CIRCULATING

PATH

V

IN

C3

D1 C1

LOAD

1766 F05

Figure 5. High Speed Switching Path

1766fa

16

LT1766/LT1766-5

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APPLICATIO S I FOR ATIO

U

CONNECT TO

GROUND PLANE

GND

L1

FOR THE FE PACKAGE, THE

EXPOSED PAD (PIN 17) SHOULD

BE PROPERLY SOLDERED TO

THE GROUND PLANE.

NOTE: BOOST AND BIAS

COPPER TRACES ARE ON

A SEPARATE LAYER FROM

THE GROUND PLANE

C1

MINIMIZE LT1766

C3-D1 LOOP

D2

V

OUT

D1

C3

C2

GND

1

GND

SW

GND 16

SHDN

KELVIN SENSE

2

3

4

5

6

7

8

15

14

13

V

OUT

SYNC

R1

V

IN

LT1766

FB

12

11

R2

V

C

BOOST

GND

C

FB

BIAS 10

GND

C

F

9

V

IN

R

C

KEEP FB AND V COMPONENTS

C

AWAY FROM HIGH FREQUENCY,

HIGH CURRENT COMPONENTS

C

PLACE FEEDTHROUGH AROUND

GROUND PINS (4 CORNERS) FOR

GOOD THERMAL CONDUCTIVITY

1766 F06

Figure 6. Suggested Layout

rating. A ground plane should always be used under the

switcher circuitry to prevent interplane coupling and over-

all noise.

package, the exposed pad (Pin 17) should be soldered to

the copper ground plane underneath the device.

PARASITIC RESONANCE

The V_Cand FB components should be kept as far away as

possible from the switch and boost nodes. The LT1766

pinout has been designed to aid in this. The ground for

these components should be separated from the switch

current path. Failure to do so will result in poor stability or

subharmonic like oscillation.

Resonance or “ringing” may sometimes be seen on the

switch node (see Figure 7). Very high frequency ringing

followingswitchrisetimeiscausedbyswitch/diode/input

capacitor lead inductance and diode capacitance. Schot-

tky diodes have very high “Q” junction capacitance that

can ring for many cycles when excited at high frequency.

If total lead length for the input capacitor, diode and

switchpathis1inch,theinductancewillbeapproximately

25nH. At switch off, this will produce a spike across the

NPN output device in addition to the input voltage. At

highercurrentsthisspikecanbeintheorderof10Vto20V

or higher with a poor layout, potentially exceeding the

absolute max switch voltage. The path around switch,

catch diode and input capacitor must be kept as short as

possibletoensurereliableoperation.Whenlookingatthis,

a >100MHz oscilloscope must be used, and waveforms

Board layout also has a significant effect on thermal

resistance. Pins 1, 8, 9 and 16, GND, are a continuous

copper plate that runs under the LT1766 die. This is the

best thermal path for heat out of the package. Reducing

the thermal resistance from Pins 1, 8, 9 and 16 onto the

board will reduce die temperature and increase the power

capability of the LT1766. This is achieved by providing as

much copper area as possible around these pins. Adding

multiple solder filled feedthroughs under and around

these four corner pins to the ground plane will also help.

Similar treatment to the catch diode and coil terminations

will reduce any additional heating effects. For the FE

should be observed on the leads of the package. This

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APPLICATIO S I FOR ATIO

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SW RISE

SW FALL

SWITCH NODE

VOLTAGE

10V/DIV

0.2A/DIV

2V/DIV

INDUCTOR

CURRENT

AT I

= 0.1A

OUT

1766 F08

V

= 40V

OUT

L = 47µH

1µs/DIV

IN

50ns/DIV

1766 F07

= 5V

Figure 7. Switch Node Resonance

Figure 8. Discontinuous Mode Ringing

switch off spike will also cause the SW node to go below

ground. The LT1766 has special circuitry inside which

mitigates this problem, but negative voltages over 0.8V

lasting longer than 10ns should be avoided. Note that

100MHz oscilloscopes are barely fast enough to see the

details of the falling edge overshoot in Figure 7.

Boost current loss:

2

V_OUT

I

/36

OUT

(

)

P_BOOST

=

V

IN

Quiescent current loss:

P = V 0.0015 + V 0.003

OUT

(

)

(

)

A second, much lower frequency ringing is seen during

switch off time if load current is low enough to allow the

inductor current to fall to zero during part of the switch off

time (see Figure 8). Switch and diode capacitance reso-

nate with the inductor to form damped ringing at 1MHz to

10 MHz. This ringing is not harmful to the regulator and it

hasnotbeenshowntocontributesignificantlytoEMI. Any

attempt to damp it with a resistive snubber will degrade

efficiency.

Q

IN

R_SW= Switch resistance (≈0.3) hot

t_EFF= Effective switch current/voltage overlap time

= (t_r+ t_f+ t_Ir+ t_If)

t_r= (V_IN/1.2)ns

t_f= (V_IN/1.7)ns

t_Ir= t_If= (I_OUT/0.05)ns

f = Switch frequency

Example: with V_IN= 40V, V_OUT= 5V and I_OUT= 1A:

THERMAL CALCULATIONS

0.3 1 ²5

(

)( ) ( )

P_SW

=

+ 97•10⁻⁹1/2 1 40 200 •10³

(

)

( )( )

(

)

Power dissipation in the LT1766 chip comes from four

sources: switch DC loss, switch AC loss, boost circuit

current,andinputquiescentcurrent.Thefollowingformu-

las show how to calculate each of these losses. These

formulas assume continuous mode operation, so they

should not be used for calculating efficiency at light load

currents.

40

= 0.04 + 0.388 = 0.43W

2

5 1/36

( )

(

)

P_BOOST

=

= 0.02W

40

P_Q= 40(0.0015)+ 5(0.003) = 0.08W

Switch loss:

Total power dissipation in the IC is given by:

P_TOT= P_SW+ P_BOOST+ P_Q

2

R_SWI_OUTV_OUT

(

) (

)

P_SW

=

+ t_EFF(1/2) I_OUT

V

f

= 0.43W + 0.02W + 0.08W = 0.53W

(

)( ^IN)( )

V

IN

1766fa

18

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U

Thermal resistance for the LT1766 packages is influenced

Die temperature can peak for certain combinations of V_IN,

V_OUTand load current. While higher V_INgives greater

switch AC losses, quiescent and catch diode losses, a

lower V_INmay generate greater losses due to switch DC

losses. In general, the maximum and minimum V_INlevels

should be checked with maximum typical load current for

calculation of the LT1766 die temperature. If a more

accurate die temperature is required, a measurement of

the SYNC pin resistance (to GND) can be used. The SYNC

pin resistance can be measured by forcing a voltage no

greaterthan0.5Vatthepinandmonitoringthepincurrent

over temperature in an oven. This should be done with

minimal device power (low V_INand no switching

(V_C= 0V)) in order to calibrate SYNC pin resistance with

ambient (oven) temperature.

by the presence of internal or backside planes.

SSOP (GN16) Package: With a full plane under the GN16

package, thermal resistance will be about 85°C/W.

TSSOP(ExposedPad)Package:Withafullplaneunderthe

TSSOPpackage, thermalresistancewillbeabout45°C/W.

To calculate die temperature, use the proper thermal

resistance number for the desired package and add in

worst-case ambient temperature:

T_J= T_A+ (θ_JA• P_TOT

)

When estimating ambient, remember the nearby catch

diode and inductor will also be dissipating power:

(V )(V – V_OUT)(I_LOAD

)

F

IN

Note: Some of the internal power dissipation in the IC, due

to BOOST pin voltage, can be transferred outside of the IC

to reduce junction temperature, by increasing the voltage

drop in the path of the boost diode D2 (see Figure 9). This

reduction of junction temperature inside the IC will allow

higher ambient temperature operation for a given set of

conditions. BOOST pin circuitry dissipates power given

by:

P_DIODE

=

V

IN

V_F= Forward voltage of diode (assume 0.63V at 1A)

(0.63)(40 – 5)(1)

40

P_INDUCTOR= (I_LOAD)²(R_L)

P_DIODE

=

= 0.55W

R_L= Inductor DC resistance (assume 0.1Ω)

P_INDUCTOR(1)²(0.1) = 0.1W

V_OUT• (I_SW/ 36) • V_C2

P_DISS(BOOST)

=

V

IN

Only a portion of the temperature rise in the external

inductoranddiodeiscoupledtothejunctionoftheLT1766.

Based on empirical measurements the thermal effect on

LT1766 junction temperature due to power dissipation in

the external inductor and catch diode can be calculated as:

Typically V_C2(the boost voltage across the capacitor C2)

equals Vout. This is because diodes D1 and D2 can be

considered almost equal, where:

V_C2= V_OUT– V_FD2– (–V_FD1) = V_OUT

∆T_J(LT1766) ≈ (P_DIODE+ P_INDUCTOR)(10°C/W)

Hencetheequationusedforboostcircuitrypowerdissipa-

tion given in the previous Thermal Calculations section is

stated as:

Using the example calculations for LT1766 dissipation,

the LT1766 die temperature will be estimated as:

T_J= T_A+ (θ_JA• P_TOT) + [10 • (P_DIODE+ P_INDUCTOR)]

V_OUT•(I_SW/36)•V_OUT

P_DISS(BOOST)

=

With the GN16 package (θ_JA= 85°C/W), at an ambient

temperature of 60°C:

V

IN

Here it can be seen that boost power dissipation increases

as the square of V_OUT. It is possible, however, to reduce

V_C2below V_OUTto save power dissipation by increasing

the voltage drop in the path of D2. Care should be taken

that V_C2does not fall below the minimum 3.3V boost

T_J= 60 + (85 • 0.53) + (10 • 0.65) = 112°C

With the TSSOP package (θ_JA= 45°C/W), at an ambient

temperature of 60°C:

T_J= 60 + (45 • 0.53) + (10 • 0.65) = 90°C

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For an FE package with thermal resistance of 45°C/W,

ambient temperature savings would be, T(ambient) sav-

ings = 0.116W • 45°C/W = 5c. For a GN Package with

thermal resistance of 85°C/W, ambient temperature sav-

ings would be T/(ambient) savings = 0.116 • 85°C/W =

10c. The 7V zener should be sized for excess of 0.116W

operation. The tolerances of the zener should be consid-

voltage required for full saturation of the internal power

switch.Foroutputvoltagesof5V,V_C2isapproximately5V.

During switch turn on, V_C2will fall as the boost capacitor

C2 is dicharged by the boost pin. In the previous Boost Pin

section, the value of C2 was designed for a 0.7V droop in

V_C2= V_DROOP. Hence, an output voltage as low as 4V

would still allow the minimum 3.3V for the boost function

usingtheC2capacitorcalculated.Ifatargetoutputvoltage

of 12V is required, however, an excess of 8V is placed

across the boost capacitor which is not required for the

boost function but still dissipates additional power.

ered to ensure minimum V_C2exceeds 3.3V + V_DROOP

.

Input Voltage vs Operating Frequency Considerations

TheabsolutemaximuminputsupplyvoltagefortheLT1766

is specified at 60V. This is based solely on internal semi-

conductor junction breakdown effects. Due to internal

power dissipation, the actual maximum V_INachievable in

a particular application may be less than this.

What is required is a voltage drop in the path of D2 to

achieve minimal power dissipation while still maintaining

minimum boost voltage across C2. A zener, D4, placed in

series with D2 (see Figure 9), drops voltage to C2.

A detailed theoretical basis for estimating internal power

loss is given in the section, Thermal Considerations. Note

that AC switching loss is proportional to both operating

frequency and output current. The majority of AC switch-

ing loss is also proportional to the square of input voltage.

Example:theBOOSTpinpowerdissipationfora20Vinput

to 12V output conversion at 1A is given by:

D2

D4

For example, while the combination of V_IN= 40V, V_OUT

=

D2

5V at 1A and f_OSC= 200kHz may be easily achievable,

simultaneously raising V_INto 60V and f_OSCto 700kHz is

not possible. Nevertheless, input voltage transients up to

60V can usually be accommodated, assuming the result-

ing increase in internal dissipation is of insufficient time

duration to raise die temperature significantly.

C2

D1

BOOST

LT1766

L1

V

SW

IN

OUT

IN

C3

SHDN

BIAS

FB

R1

+

A second consideration is controllability. A potential limi-

SYNC

GND

C1

R2

V

C

tation occurs with a high step-down ratio of V_INto V_OUT

,

asthisrequiresacorrespondinglynarrowminimumswitch

on time. An approximate expression for this (assuming

continuous mode operation) is given as follows:

C

F

R

C

V

_OUT+ V_F

Min t_ON

=

1766 F09

V_IN(f_OSC

)

Figure 9. Boost Pin, Diode Selection

where:

12•(1/36)•12

P_BOOST

=

= 0.2W

V_IN= input voltage

20

V_OUT= output voltage

V_F= Schottky diode forward drop

f_OSC= switching frequency

If a 7V zener D4 is placed in series with D2, then power

dissipation becomes :

A potential controllability problem arises if the LT1766 is

called upon to produce an on time shorter than it is able to

12•(1/36)•5

P_BOOST

=

= 0.084W

20

produce. Feedback loop action will lower then reduce the

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U

V_Ccontrol voltage to the point where some sort of cycle-

LT1766

skipping or odd/even cycle behavior is exhibited.

CURRENT MODE

POWER STAGE

V

SW

OUTPUT

ERROR

g

m

= 2mho

In summary:

AMPLIFIER

C

FB

R1

FB

–

CERAMIC

ESL

TANTALUM

ESR

1. Be aware that the simultaneous requirements of high

V_IN, high I_OUTand high f_OSCmay not be achievable in

practice due to internal dissipation. The Thermal Con-

siderations section offers a basis to estimate internal

power.Inquestionablecasesaprototypesupplyshould

be built and exercised to verify acceptable operation.

g

=

m

2000µmho

+

R

1.22V

O

200k

+

R

LOAD

C1

GND

V

C

R2

R

C

F

C

1766 F10

2. The simultaneous requirements of high V_IN, low V_OUT

and high f_OSCcan result in an unacceptably short

minimum switch on time. Cycle skipping and/or odd/

even cycle behavior will result although correct output

voltage is usually maintained.

Figure 10. Model for Loop Response

80

180

150

120

90

60

GAIN

FREQUENCY COMPENSATION

40

20

Before starting on the theoretical analysis of frequency

response,thefollowingshouldberemembered—theworse

the board layout, the more difficult the circuit will be to

stabilize. This is true of almost all high frequency analog

circuits, read the Layout Considerations section first.

Common layout errors that appear as stability problems

are distant placement of input decoupling capacitor and/

or catch diode, and connecting the V_Ccompensation to a

ground track carrying significant switch current. In addi-

tion, the theoretical analysis considers only first order

non-ideal component behavior. For these reasons, it is

important that a final stability check is made with produc-

tion layout and components.

PHASE

0

60

–20

–40

30

0

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

R

1766 F11

V

= 42V

= 5V

= 500mA

= 100µF, 10V, 0.1Ω

= 2.2k

= 22nF

= 220pF

IN

OUT

LOAD

OUT

C

F

V

I

C

Figure 11. Overall Loop Response

ity. This ESR, however, contributes significantly to the

ripple voltage at the output (see Output Ripple Voltage in

the Applications Section). It is possible to reduce capaci-

torsizeandoutputripplevoltagebyreplacingthetantalum

output capacitor with a ceramic output capacitor because

of its very low ESR. The zero provided by the tantalum

output capacitor must now be reinserted back into the

loop. Alternatively there may be cases where, even with

the tantalum output capacitor, an additional zero is re-

quired in the loop to increase phase margin for improved

transient response.

The LT1766 uses current mode control. This alleviates

many of the phase shift problems associated with the

inductor. The basic regulator loop is shown in Figure 10.

The LT1766 can be considered as two g_mblocks, the error

amplifier and the power stage.

Figure 11 shows the overall loop response. At the V_Cpin,

the frequency compensation components used are:

R_C= 2.2k, C_C= 0.022µF and C_F= 220pF. The output

capacitor used is a 100µF, 10V tantalum capacitor with

typical ESR of 100mΩ.

A zero can be added into the loop by placing a resistor, R_C,

at the V_Cpin in series with the compensation capacitor, C_C

or by placing a capacitor, CFB, between the output and the

FB pin.

TheESRofthetantalumoutputcapacitorprovidesauseful

zerointheloopfrequencyresponseformaintainingstabil-

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APPLICATIO S I FOR ATIO

When using R_C, the maximum value has two limitations.

First, thecombinationofoutputcapacitorESRandR_Cmay

stopthelooprollingoffaltogether. Second, iftheloopgain

is not rolled off sufficiently at the switching frequency,

output ripple will peturb the V_Cpin enough to cause

unstable duty cycle switching similar to subharmonic

oscillations. If needed, an additional capacitor CF can be

addedacrosstheR_C/C_CnetworkfromtheV_Cpintoground

to further suppress V_Cripple voltage.

CONVERTER WITH BACKUP OUTPUT REGULATOR

In systems with a primary and backup supply, for ex-

ample, a battery powered device with a wall adapter input,

the output of the LT1766 can be held up by the backup

supply with the LT1766 input disconnected. In this condi-

tion, the SW pin will source current into the V_INpin. If the

SHDN pin is held at ground, only the shut down current of

25µAwillbepulledviatheSWpinfromthesecondsupply.

With the SHDN pin floating, the LT1766 will consume its

quiescentoperatingcurrentof1.5mA. TheV_INpinwillalso

source current to any other components connected to the

input line. If this load is greater than 10mA or the input

could be shorted to ground, a series Schottky diode must

be added, as shown in Figure 12. With these safeguards,

the output can be held at voltages up to the V_INabsolute

maximum rating.

With a tantalum output capacitor, the LT1766 already

includesaresistor,R_Candfiltercapacitor,CF,attheV_Cpin

(see Figures 10 and 11) to compensate the loop over the

entire V_INrange (to allow for stable pulse skipping for high

V_IN-to-V_OUTratios ≥10). A ceramic output capacitor can

stillbeusedwithasimpleadjustmenttotheresistorR_Cfor

stable operation. (See Ceramic Capacitors section for

stabilizingLT1766).Ifadditionalphasemarginisrequired,

a capacitor, CFB, can be inserted between the output and

FB pin but care must be taken for high output voltage

applications. Sudden shorts to the output can create

unacceptably large negative transients on the FB pin.

BUCK CONVERTER WITH ADJUSTABLE SOFT-START

Large capacitive loads or high input voltages can cause

high input currents at start-up. Figure 13 shows a circuit

that limits the dv/dt of the output at start-up, controlling

the capacitor charge rate. The buck converter is a typical

configuration with the addition of R3, R4, C_SSand Q1.

As the output starts to rise, Q1 turns on, regulating switch

current via the V_Cpin to maintain a constant dv/dt at the

output. Output rise time is controlled by the current

through C_SSdefined by R4 and Q1’s V_BE. Once the output

is in regulation, Q1 turns off and the circuit operates

normally. R3 is transient protection for the base of Q1.

For V_IN-to-V_OUTratios <10, higher loop bandwidths are

possiblebyreadjustingthefrequencycompensationcom-

ponents at the V_Cpin.

When checking loop stability, the circuit should be oper-

ated over the applications’s full voltage, current and tem-

perature range. Proper loop compensation may be ob-

tained by emperical methods as described in detail in

Application Notes 19 and 76.

D2

1N4148W

C2

0.33µF

D3

L1

47µH

10MQ060N

BOOST

REMOVABLE

INPUT

V

LT1766 SW

IN

5V, 1A

R3

ALTERNATE

SUPPLY

BIAS

54k

R1

SHDN

SYNC

15.4k

FB

+

C1

100µF

10V

R2

4.99k

GND

V

C

D1

10MQ060N

R4

25k

R

C

2.2k

C3

2.2µF

C

F

220pF

C

0.022µF

1766 F12

Figure 12. Dual Source Supply with 25µA Reverse Leakage

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At switch off, energy is transferred by magnetic coupling

into L1B, powering the –5V rail. C4 pulls L1B positive

duringswitchontime, causingcurrenttoflow, andenergy

to build in L1B and C4. At switch off, the energy stored in

both L1B and C4 supply the –5V rail. This reduces the

current in L1A and changes L1B current waveform from

square to triangular. For details on this circuit, including

maximum output currents, see Design Note 100.

R4 C_SSV_OUT

( )( )(

)

RiseTime =

V_BE

Using the values shown in Figure 10,

47 •10³15•10^–9

5

( )

(

)(

)

Rise Time =

= 5ms

0.7

The ramp is linear and rise times in the order of 100ms are

possible. Since the circuit is voltage controlled, the ramp

rate is unaffected by load characteristics and maximum

outputcurrentisunchanged. Variantsofthiscircuitcanbe

used for sequencing multiple regulator outputs.

D2

1N4148W

C2

0.33µF

L1A*

50µH

BOOST

LT1766

V

OUT1

V

IN

5V

7.5V

V

SW

IN

(SEE DN100

FOR MAX I

TO 60V

)

OUT

R1

SHDN

SYNC

GND

C1

D2

15.4k

C3

2.2µF

100V

CER

+

100µF

10V

1N4148W

FB

OUTPUT

R2

5V

V

TANT

INPUT

40V

C

C2

0.33µF

4.99k

1A

L1

47µH

D1

C

F

BOOST

BIAS

SW

R

C

220pF

2.2k

V

IN

C3

C

+

C1

100µF

R1

D1

2.2µF

50V

CER

0.022µF

LT1766

15.4k

GND

C4

C5

+

SHDN

SYNC GND

FB

C

100µF

10V

L1B*

D3

R2

4.99k

10V

TANT

V

TANT

V

OUT2

C

SS

15nF

–5V^†

C

F

* L1 IS A SINGLE CORE WITH TWO WINDINGS

COILTRONICS #CTX50-3A

1766 F14

R3

2k

Q1

220pF

R

C

†

IF LOAD CAN GO TO ZERO, AN OPTIONAL

2.2k

1766 F13

PRELOAD OF 1k TO 5k MAY BE USED TO

IMPROVE LOAD REGULATION

D1, D3: 10MQ060N

C

R4

47k

0.022µF

Figure 14. Dual Output SEPIC Converter

Figure 13. Buck Converter with Adjustable Soft-Start

DUAL OUTPUT SEPIC CONVERTER

POSITIVE-TO-NEGATIVE CONVERTER

The circuit in Figure 14 generates both positive and

negative 5V outputs with a single piece of magnetics. The

two inductors shown are actually just two windings on a

standard Coiltronics inductor. The topology for the 5V

output is a standard buck converter. The –5V topology

would be a simple flyback winding coupled to the buck

converter if C4 were not present. C4 creates a SEPIC

(single-ended primary inductance converter) topology

which improves regulation and reduces ripple current in

L1. Without C4, the voltage swing on L1B compared to

L1A would vary due to relative loading and coupling

losses. C4 provides a low impedance path to maintain an

equal voltage swing in L1B, improving regulation. In a

flybackconverter,duringswitchontime,alltheconverter’s

energyisstoredinL1Aonly, sincenocurrentflowsinL1B.

The circuit in Figure 15 is a positive-to-negative topology

using a grounded inductor. It differs from the standard

approach in the way the IC chip derives its feedback signal

because the LT1766 accepts only positive feedback sig-

nals. Thegroundpinmustbetiedtotheregulatednegative

output. A resistor divider to the FB pin then provides the

proper feedback voltage for the chip.

Thefollowingequationcanbeusedtocalculatemaximum

load current for the positive-to-negative converter:

(V )(V_OUT

)

IN

I_P–

(V_OUT)(V – 0.3)

IN

2(V_OUT+ V )(f)(L)

IN

I_MAX

=

(V_OUT+ V – 0.3)(V_OUT+ V )

IN

F

1766fa

23

LT1766/LT1766-5

W U U

U

APPLICATIO S I FOR ATIO

Output current where continuous mode is needed:

I_P= Maximum rated switch current

V_IN= Minimum input voltage

V_OUT= Output voltage

V_F= Catch diode forward voltage

0.3 = Switch voltage drop at 1.5A

(V )²(I_P)²

IN

I_CONT

>

4(V + V_OUT)(V + V_OUT+ V )

IN

F

Minimum inductor discontinuous mode:

Example: with V_IN(MIN)= 5.5V, V_OUT= 12V, L = 18µH,

V_F= 0.63V, I_P= 1.5A: I_MAX= 0.280A.

2(V_OUT)(I_OUT

(f)(I_P)²

)

L_MIN

=

OUTPUT DIVIDER

Minimum inductor continuous mode:

Refer to Applications Information Feedback Pin Functions

to calculate R1 and R2 for the (negative) output voltage

(V )(V_OUT

IN

)

L_MIN

=

(from Table 1).

(V_OUT+ V )

†

F

D2

1N4148W

2(f)(V + V_OUT) I_P–I_OUT1+

IN

V

IN

C2

L1*

0.33µF

†

18µH

INPUT

BOOST

LT1766

For a 40V to –12V converter using the LT1766 with peak

switch current of 1.5A and a catch diode of 0.63V:

V

5.5V TO

48V

V

SW

FB

IN

R1

44.2k

(40)²(1.5)²

4(40 +12)(40 +12 + 0.63)

GND

V

C

C1

C3

+

D1

100µF

25V

2.2µF

100V

CER

I_CONT

>

= 0.573A

10MQO60N

C

TANT

R2

4.99k

C

R

F

OUTPUT**

–12V, 0.25A

For a load current of 0.25A, this says that discontinuous

mode can be used and the minimum inductor needed is

found from:

1766 F15

* INCREASE L1 TO 30µH OR 60µH FOR HIGHER CURRENT APPLICATIONS.

SEE APPLICATIONS INFORMATION

** MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE

AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION

†

FOR V > 44V AND V

= –12V, ADDITIONAL VOLTAGE DROP IN THE

IN

OUT

2(12)(0.25)

(200 •10³)(1.5)²

PATH OF D2 IS REQUIRED TO ENSURE BOOST PIN MAXIMUM RATING IS

L_MIN

=

= 13.3µH

NOT EXCEEDED. SEE APPLICATIONS INFORMATION (BOOST PIN VOLTAGE)

Figure 15. Positive-to-Negative Converter

In practice, the inductor should be increased by about

30% over the calculated minimum to handle losses and

variations in value. This suggests a minimum inductor of

18µH for this application.

Inductor Value

The criteria for choosing the inductor is typically based on

ensuring that peak switch current rating is not exceeded.

This gives the lowest value of inductance that can be used,

but in some cases (lower output load currents) it may give

a value that creates unnecessarily high output ripple

voltage.

Ripple Current in the Input and Output Capacitors

Positive-to-negativeconvertershavehighripplecurrentin

the input capacitor. For long capacitor lifetime, the RMS

value of this current must be less than the high frequency

ripple current rating of the capacitor. The following for-

mula will give an approximate value for RMS ripple cur-

rent. This formula assumes continuous mode and large

inductor value. Small inductors will give somewhat higher

ripple current, especially in discontinuous mode. The

exactformulasareverycomplexandappearinApplication

Note 44, pages 29 and 30. For our purposes here a fudge

The difficulty in calculating the minimum inductor size

needed is that you must first decide whether the switcher

will be in continuous or discontinuous mode at the critical

point where switch current reaches 1.5A. The first step is

to use the following formula to calculate the load current

above which the switcher must use continuous mode. If

your load current is less than this, use the discontinuous

mode formula to calculate minimum inductor needed. If

load current is higher, use the continuous mode formula.

factor (ff) is used. The value for ff is about 1.2 for higher

1766fa

24

LT1766/LT1766-5

W U U

APPLICATIO S I FOR ATIO

U

load currents and L ≥15µH. It increases to about 2.0 for

Keep in mind that during start-up and output overloads,

average diode current may be much higher than with

normalloads.Careshouldbeusedifdiodesratedlessthan

1A are used, especially if continuous overload conditions

must be tolerated.

smaller inductors at lower load currents.

V_OUT

V

IN

Input Capacitor I_RMS= (ff)(I_OUT

)

ff = 1.2 to 2.0

BOOST Pin Voltage

The output capacitor ripple current for the positive-to-

negative converter is similar to that for a typical buck

regulator—it is a triangular waveform with peak-to-peak

value equal to the peak-to-peak triangular waveform of the

inductor. The low output ripple design in Figure 15 places

the input capacitor between V_INand the regulated negative

output. This placement of the input capacitor significantly

reduces the size required for the output capacitor (versus

placing the input capacitor between V_INand ground).

To ensure that the BOOST pin voltage does not exceed its

absolute maximum rating of 68V with respect to device

GND pin voltage, care should be taken in the generation of

boost voltage. For the conventional method of generating

boostvoltage, showninFigure1, thevoltageattheBOOST

pin during switch on time is approximately given by:

V

_BOOST(GND pin) = (V_IN– V_GNDPIN) + V_C2

where:

V_C2= (D2+) – V_D2– (D1+) + V_D1

The peak-to-peak ripple current in both the inductor and

output capacitor (assuming continuous mode) is:

= voltage across the “boost” capacitor

For the positive-to-negative converter shown in Figure 15,

theconventionalBuckoutputnodeisgrounded(D2+)=0V

and the catch diode (D1+) is connected to the negative

output = V_OUT= –12V. Absolute maximum ratings should

also be observed with the GND pin now at –12V. It can be

seen that for V_D1= V_D2:

DC • V

IN

I_P-P

=

f •L

V

_OUT+ V

F

DC = Duty Cycle =

V

_OUT+ V + V

IN F

I_P-P

I_COUT(RMS) =

12

V_C2= (D2+) – (D1+) = |V_OUT| = 12V

The maximum V_INvoltage allowed for the device (GND pin

at –12V) is 48V.

The output ripple voltage for this configuration is as low as

the typical buck regulator based predominantly on the

inductor’s triangular peak-to-peak ripple current and the

ESR of the chosen capacitor (see Output Ripple Voltage in

Applications Information).

The maximum V_INvoltage allowed without exceeding the

BOOST pin voltage absolute maximum rating is given by:

V

_IN(MAX)= Boost (Max) + (V_GNDPIN) – V_C2

Diode Current

V_IN(MAX)= 68 + (–12) – 12 = 44V

Average diode current is equal to load current. Peak diode

current will be considerably higher.

To increase usable V_INvoltage, V_C2must be reduced. This

can be achieved by placing a zener diode V_Z1(anode at

C2+) in series with D2.

Peak diode current:

Note: A maximum limit on V_Z1must be observed to

ensure a minimum V_C2is maintained on the “boost”

capacitor; referred to as “V_BOOST(MIN)” in the Electrical

Characteristics.

ContinuousMode =

(V + V_OUT

)

(V )(V_OUT)

IN

I_OUT

+

V

IN

2(L)(f)(V + V_OUT)

IN

2(I_OUT)(V_OUT

(L)(f)

)

DiscontinuousMode =

1766fa

25

LT1766/LT1766-5

U

PACKAGE DESCRIPTIO

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663,

Exposed Pad Variation BB)

4.90 – 5.10*

(.193 – .201)

3.58

(.141)

3.58

(.141)

16 1514 13 12 1110

9

6.60 ±0.10

4.50 ±0.10

2.94

(.116)

SEE NOTE 4

2.94

(.116)

6.40

BSC

0.45 ±0.05

1.05 ±0.10

0.65 BSC

5

7

8

1

2

3

4

6

RECOMMENDED SOLDER PAD LAYOUT

1.10

(.0433)

MAX

4.30 – 4.50*

(.169 – .177)

0° – 8°

0.65

(.0256)

BSC

0.45 – 0.75

0.09 – 0.20

0.05 – 0.15

(.018 – .030)

(.0036 – .0079)

(.002 – .006)

0.195 – 0.30

(.0077 – .0118)

FE16 (BB) TSSOP 0203

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

MILLIMETERS

(INCHES)

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

1766fa

26

LT1766/LT1766-5

U

PACKAGE DESCRIPTIO

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.189 – .196*

(4.801 – 4.978)

.045 ±.005

.009

(0.229)

REF

16 15 14 13 12 11 10 9

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 ±.0015

.0250 TYP

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

5

6

7

8

.015 ± .004

(0.38 ± 0.10)

× 45°

.053 – .068

(1.351 – 1.727)

.004 – .0098

(0.102 – 0.249)

.007 – .0098

(0.178 – 0.249)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.0250

(0.635)

BSC

.008 – .012

(0.203 – 0.305)

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

GN16 (SSOP) 0502

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

1766fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

27

LT1766/LT1766-5

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

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I

SD

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25V, 2.75A (I ), 1.25MHz, High Efficiency

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V : 3V to 25V, V

I : 15µA, S8, TSSOP16E

SD

: 1.20V, I : 1mA,

OUT

IN

OUT(MIN) Q

LT1766

60V, 1.2A (I ), 200kHz, High Efficiency

Step-Down DC/DC Converter

V : 5.5V to 60V, V

I : 25µA, TSSOP16/E

SD

: 1.20V, I : 2.5mA,

OUT

IN

OUT(MIN) Q

LT1767

25V, 1.2A (I ), 1.25MHz, High Efficiency

Step-Down DC/DC Converter

V : 3V to 25V, V

I : 6µA, MS8/E

SD

: 1.20V, I : 1mA,

OUT(MIN) Q

OUT

IN

LT1776

40V, 550mA (I ), 200kHz, High Efficiency

Step-Down DC/DC Converter

V : 7.4V to 40V, V

I : 30µA, N8,S8

SD

: 1.24V, I : 3.2mA,

OUT(MIN) Q

OUT

IN

LT1940

Dual Output 1.4A (I ) Constant 1.1MHz, High Efficiency

Step-Down DC/DC Converter

V : 3V to 25V, V

I : <1µA, TSSOP-16E

SD

: 1.20V, I : 2.5mA,

OUT ,

IN

OUT(MIN) Q

LT1956

60V, 1.2A (I ), 500kHz, High Efficiency

Step-Down DC/DC Converter

V : 5.5V to 60V, V

: 1.20V, I : 2.5mA,

Q

OUT

IN

OUT(MIN)

I

: 25µA, TSSOP16/E

SD

LT1976

60V, 1.2A (I ), 200kHz, Micropower (I = 100µA), High Efficiency

V : 3.3V to 60V, V

: 1.20V, I : 100µA,

Q

OUT

Q

IN

Step-Down DC/DC Converter

I

: <1µA, TSSOP16/E

SD

LT3010

80V, 50mA, Low Noise Linear Regulator

V : 1.5V to 80V, V

IN

: 1.28V, I : 30µA,

Q

I

: <1µA, MS8E

SD

LTC3412

LTC3414

LT3430/LT3431

LT3433

2.5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter

V : 2.5V to 5.5V, V

: 0.8V, I : 60µA,

Q

OUT

IN

OUT(MIN)

I

: <1µA, TSSOP16E

SD

4A (I ), 4MHz, Synchronous Step-Down DC/DC Converter

V : 2.3V to 5.5V, V

: 0.8V, I : 64µA,

Q

OUT

IN

OUT(MIN)

I

: <1µA, TSSOP20E

SD

60V, 2.75A (I ), 200kHz/500kHz, High Efficiency

V : 5.5V to 60V, V

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OUT

IN

OUT(MIN) Q

Step-Down DC/DC Converters

I : 30µA, TSSOP16E

SD

High Voltage, Micropower (I = 100µA), Buck-Boost DC/DC Converter

V : 4V to 60V, I : 100µA, 500mA Switch Current,

Q

IN

Q

TSSOP16E

LTC3727/LTC3727-1

36V, 500kHz, High Efficiency Step-Down DC/DC Controllers

V : 4V to 36V, V

: 0.8V, I : 670µA,

IN

OUT(MIN) Q

I

: 20µA, QFN-32, SSOP-28

SD

ThinSOT is a trademark of Linear Technology Corporation.

1766fa

LT/TP 0903 1K • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

28

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

LINEAR TECHNOLOGY CORPORATION 2001

This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.


型号：	LT1766EGN
厂家：	Linear
描述：	5.5V to 60V 1.5A, 200kHz Step-Down Switching Regulator 5.5V至60V 1.5A ， 200kHz的降压型开关稳压器稳压器开关
文件：	总29页 (文件大小：311K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT1766EGN [Linear]

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