LT1792IS8#TR [Linear]
LT1792 - Low Noise, Precision, JFET Input Op Amp; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C;
| 型号： | LT1792IS8#TR |
| 厂家： | 
Linear |
| 描述： | LT1792 - Low Noise, Precision, JFET Input Op Amp; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C 运算放大器 放大器电路 |
| 文件： | 总12页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1792
Low Noise, Precision,
JFET Input Op Amp
U
FEATURES
DESCRIPTIO
The LT®1792 achieves a new standard of excellence in
noise performance for a JFET op amp. The 4.2nV/√Hz
voltage noise combined with low current noise and
picoamperebiascurrentsmaketheLT1792anidealchoice
for amplifying low level signals from high impedance
capacitive transducers.
■
100% Tested Low Voltage Noise: 6nV/√Hz Max
■
A Grade 100% Temperature Tested
■
Voltage Gain: 1.2 Million Min
■
Offset Voltage Over Temp: 800µV Max
■
Gain-Bandwidth Product: 5.6MHz Typ
■
Guaranteed Specifications with ±5V Supplies
TheLT1792isunconditionallystableforgainsof 1ormore,
even with load capacitances up to 1000pF. Other key
features are 600µV VOS and a voltage gain of over 4 million.
Each individual amplifier is 100% tested for voltage noise,
slew rate and gain bandwidth.
U
APPLICATIO S
■
Photocurrent Amplifiers
Hydrophone Amplifiers
■
■
High Sensitivity Piezoelectric Accelerometers
The design of the LT1792 has been optimized to achieve
true precision performance with an industry standard
pinout in the SO-8 package. Specifications are also pro-
vided for ±5V supplies.
■
Low Voltage and Current Noise Instrumentation
Amplifier Front Ends
■
Two and Three Op Amp Instrumentation Amplifiers
■
Active Filters
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
TYPICAL APPLICATIO
Low Noise Hydrophone Amplifier with DC Servo
1kHz Input Noise Voltage Distribution
V
= ±15V
= 25°C
270 OP AMPS TESTED
5V TO 15V
R3
S
A
R1*
3.9k
40
30
20
10
0
T
100M
7
–
2
6
OUTPUT
LT1792
3
+
C2
C1*
R2
200Ω
4
0.47µF
–5V TO –15V
R4
1M
R8
100M
–
+
2
3
C
T
R6
100k
HYDRO-
PHONE
6
R5
1M
LT1097
R7
1M
3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
INPUT VOLTAGE NOISE (nV/√Hz)
DC OUTPUT ≤ 2.5mV FOR T < 70°C
A
1792 TA02
OUTPUT VOLTAGE NOISE = 128nV/√Hz AT 1kHz (GAIN = 20)
C1 ≈ C ≈ 100pF TO 5000pF; R4C2 > R8C ; *OPTIONAL
1792 TA01
T
T
1
LT1792
ABSOLUTE AXI U RATI GS
Supply Voltage ..................................................... ±20V
Differential Input Voltage ...................................... ±40V
Input Voltage (Equal to Supply Voltage)............... ±20V
Output Short-Circuit Duration ........................ Indefinite
Operating Temperature Range............... –40°C to 85°C
W W W
U
(Note 1)
Specified Temperature Range
Commercial (Note 8) ......................... –40°C to 85°C
Industrial ........................................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................ 300°C
W
U
/O
PACKAGE RDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
TOP VIEW
V
ADJ
OS
V
OS
ADJ
1
2
3
4
8
7
6
5
NC
1
2
3
4
NC
8
7
6
5
LT1792ACN8
LT1792CN8
LT1792AIN8
LT1792IN8
LT1792ACS8
LT1792CS8
LT1792AIS8
LT1792IS8
+
–IN A
+IN A
V+
–IN A
+IN A
V
A
A
OUT
OUT
–
–
V
V
ADJ
V
V
OS
ADJ
OS
S8 PACKAGE
N8 PACKAGE
8-LEAD PDIP
S8 PART MARKING
1792A 1792AI
8-LEAD PLASTIC SO
TJMAX = 140°C, θJA = 130°C/W
TJMAX = 160°C, θJA = 190°C/W
1792
1792I
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS TA = 25°C, VS = ±15V, VCM = 0V, unless otherwise noted. (Note 9)
LT1792AC/LT1792AI
LT1792C/LT1792I
SYMBOL PARAMETER
CONDITIONS (Note 2)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
V
Input Offset Voltage
0.2
0.4
0.6
1.0
0.2
0.4
0.8
1.3
mV
mV
OS
V = ±5V
S
I
I
Input Offset Current
Input Bias Current
Warmed Up (Note 3)
Warmed Up (Note 3)
0.1Hz to 10Hz
100
300
2.4
400
800
100
300
2.4
400
800
pA
pA
OS
B
e
Input Noise Voltage
Input Noise Voltage Density
µV
P-P
n
f = 10Hz
8.3
4.2
8.3
4.2
nV/√Hz
nV/√Hz
O
f = 1000Hz
O
6.0
6.0
i
Input Noise Current Density
f = 10Hz, f = 1000Hz (Note 4)
10
10
fA/√Hz
n
O
O
R
Input Resistance
Differential Mode
Common Mode
IN
11
11
10
10
10
10
Ω
Ω
Ω
11
11
V
V
= –10V to 8V
= 8V to 11V
10
CM
CM
10
10
10
C
V
Input Capacitance
14
27
14
27
pF
pF
IN
V = ±5V
S
Input Voltage Range (Note 5)
13.0
13.5
–10.5 –11.0
13.0
13.5
–10.5 –11.0
V
V
CM
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
V
= –10V to 13V
85
88
105
105
82
83
100
98
dB
dB
CM
V = ±4.5V to ±20V
S
2
LT1792
TA = 25°C, VS = ±15V, VCM = 0V, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
LT1792C/LT1792I
MIN TYP MAX
LT1792AC/LT1792AI
SYMBOL PARAMETER
CONDITIONS
V = ±12V, R = 10k
MIN
1200 4800
600 4000
TYP
MAX
UNITS
A
V
Large-Signal Voltage Gain
Output Voltage Swing
1000 4500
500 3000
V/mV
V/mV
VOL
OUT
O
L
V = ±10V, R = 1k
O
L
R = 10k
±13.0 ±13.2
±12.0 ±12.3
±13.0 ±13.2
±12.0 ±12.3
V
V
L
R = 1k
L
SR
Slew Rate
R ≥ 2k (Note 7)
2.3
4.0
3.4
5.6
2.3
4.0
3.4
5.6
V/µs
L
GBW
Gain-Bandwidth Product
Supply Current
f = 100kHz
O
MHz
I
4.2
4.2
5.20
5.15
4.2
4.2
5.20
5.15
mA
mA
S
V = ±5V
S
Offset Voltage
R
(to V ) = 10k
10
10
mV
POT
EE
Adjustment Range
The ● denotes specifications which apply over the temperature range 0°C ≤ TA ≤ 70°C. VS = ±15V, VCM = 0V,
unless otherwise noted. (Note 9)
LT1792AC
TYP
LT1792C
TYP
SYMBOL PARAMETER
CONDITIONS (Note 2)
MIN
MAX
MIN
MAX
UNITS
V
Input Offset Voltage
●
●
0.4
0.6
0.8
1.2
0.8
1.2
2.7
3.2
mV
mV
OS
V = ±5V
S
∆V
∆Temp
Average Input Offset
Voltage Drift
(Note 6)
●
4
10
7
40
µV/°C
OS
I
I
Input Offset Current
●
●
180
500
180
500
pA
pA
OS
B
Input Bias Current
500
1800
500
1800
V
Input Voltage Range
●
●
12.9
13.4
12.9
13.4
V
V
CM
–10.0 –10.8
–10.0 –10.8
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain
V
= –10V to 12.9V
●
●
81
85
104
99
79
81
99
97
dB
dB
CM
V = ±4.5V to ±20V
S
A
V = ±12V, R = 10k
V = ±10V, R = 1k
●
●
900
500
3600
2600
800
400
3400
2400
V/mV
V/mV
VOL
O
L
O
L
V
Output Voltage Swing
R = 10k
R = 1k
L
●
●
±12.9 ±13.2
±11.9 ±12.15
±12.9 ±13.2
±11.9 ±12.15
V
V
OUT
L
SR
Slew Rate
R ≥ 2k(Note 7)
●
●
2.1
3.2
3.1
4.5
2.1
3.2
3.1
4.5
V/µs
L
GBW
Gain-Bandwidth Product
Supply Current
f = 100kHz
O
MHz
I
●
●
4.2
4.2
5.30
5.25
4.2
4.2
5.30
5.25
mA
mA
S
V = ±5V
S
3
LT1792
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the temperature range
–40°C ≤ TA ≤ 85°C. VS = ±15V, VCM = 0V, unless otherwise noted. (Notes 8, 9)
LT1792AC/LT1792AI
LT1792C/LT1792I
SYMBOL PARAMETER
CONDITIONS (Note 2)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
V
Input Offset Voltage
●
●
0.5
0.8
1.0
1.4
1.2
1.5
3.7
4.2
mV
mV
OS
V = ±5V
S
∆V
∆Temp
Average Input Offset
Voltage Drift
(Note 6)
●
4
10
7
40
µV/°C
OS
I
I
Input Offset Current
●
●
300
800
300
800
pA
pA
OS
B
Input Bias Current
1200 4000
13.0
–10.0 –10.5
1200 4000
13.0
–10.0 –10.5
V
Input Voltage Range
●
●
12.6
12.6
V
V
CM
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain
V
= –10V to 12.6V
●
●
80
83
103
98
78
79
98
96
dB
dB
CM
V = ±4.5V to ±20V
S
A
V = ±12V, R = 10k
V = ±10V, R = 1k
●
●
850
400
3300
2200
750
300
3000
2000
V/mV
V/mV
VOL
O
L
O
L
V
Output Voltage Swing
R = 10k
R = 1k
L
●
●
±12.8 ±13.1
±11.8 ±12.1
±12.8 ±13.1
±11.8 ±12.1
V
V
OUT
L
SR
Slew Rate
R ≥ 2k
●
●
2.0
2.9
3.0
4.3
2.0
2.9
3.0
4.3
V/µs
L
GBW
Gain-Bandwidth Product
Supply Current
f = 100kHz
O
MHz
I
●
●
4.2
4.2
5.40
5.35
4.2
4.2
5.40
5.35
mA
mA
S
V = ±5V
S
Note 1: Absolute Maximum Ratings are those values beyond which the
Note 6: This parameter is not 100% tested.
life of a device may be impaired.
Note 7: Slew rate is measured in A = –1; input signal is ±7.5V, output
V
Note 2: Typical parameters are defined as the 60% yield of parameter
measured at ±2.5V.
distributions of individual amplifiers.
Note 8: The LT1792AC and LT1792C are guaranteed to meet specified
performance from 0°C to 70°C and are designed, characterized and
expected to meet these extended temperature limits, but are not tested at
–40°C and 85°C. The LT1792I is guaranteed to meet the extended
temperature limits. The LT1792AC and LT1792AI grade are 100%
temperature tested for the specified temperature range.
Note 9: The LT1792 is measured in an automated tester in less than one
second after application of power. Depending on the package used,
power dissipation, heat sinking, and air flow conditions, the fully
warmed-up chip temperature can be 10°C to 50°C higher than the
ambient temperature.
Note 3: Warmed-up I and I readings are extrapolated to a chip
B
OS
temperature of 32°C from 25°C measurements and 32°C characterization
data.
Note 4: Current noise is calculated from the formula:
1/2
i = (2qI )
n
B
–19
where q = 1.6 • 10
coulomb. The noise of source resistors up to 200M
swamps the contribution of current noise.
Note 5: Input voltage range functionality is assured by testing offset
voltage at the input voltage range limits to a maximum of 2.3mV
(A grade), to 2.8mV (C grade).
4
LT1792
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Voltage Noise
vs Chip Temperature
0.1Hz to 10Hz Voltage Noise
Voltage Noise vs Frequency
100
10
1
10
9
8
7
6
5
4
3
2
1
0
V
= ±15V
V
= ±15V
= 25°C
S
S
A
T
1/f CORNER
30Hz
100
FREQUENCY (Hz)
1k
10k
100
125
0
2
4
6
8
10
1
10
–75
25
75
–50 –25
0
50
TEMPERATURE (°C)
TIME (SEC)
1792 G02
1792 G01
1792 G03
Input Bias and Offset Current
Over the Common Mode Range
Input Bias and Offset Current
vs Chip Temperature
Common Mode Limit
vs Temperature
+
V
0
–0.5
–1.0
–1.5
–2.0
400
300
200
100
0
100
30
T
= 25°C
= ±15V
V
= ±15V
A
S
S
V
NOT WARMED UP
+
V
= 5V TO 20V
10
3
1
I
B
4.0
3.5
3.0
2.5
BIAS CURRENT
0.3
0.1
0.03
0.01
I
OS
–
V
= –5V TO –20V
OFFSET CURRENT
–
V +2.0
–15 –10
–5
0
5
10
15
–75 –50 –25
0
25 50 75 100 125
–60
–20
20
60
100
140
COMMON-MODE RANGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
1792 G22
1792 G04
1792 G05
Common Mode Rejection Ratio
vs Frequency
Power Supply Rejection Ratio
vs Frequency
Voltage Gain vs Frequency
120
100
120
100
80
60
40
20
0
180
160
140
120
100
80
T
= 25°C
= ±15V
T
= 25°C
A
S
A
V
80
60
40
20
0
+PSRR
–PSRR
60
40
20
0
–20
1k
10k
100k
1M
10M
10
1k
10k 100k
1M
10M
0.01
1
10k
1M
100M
100
100
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
1792 G06
1792 G07
1792 G08
5
LT1792
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Gain and Phase Shift
Large-Signal Transient Response
Small-Signal Transient Response
vs Frequency
80
50
40
30
20
10
0
T
V
C
= 25°C
= ±15V
= 10pF
A
S
L
100
120
140
160
180
200
PHASE
GAIN
1792 G11
1792 G10
AV = 1
5µs/DIV
AV = 1
1µs/DIV
C
L = 10pF
CL = 10pF
VS = ±15V, ±5V
RL = 2k
–10
VS = ±15V
0.1
1
10
100
FREQUENCY (MHz)
1792 G09
Slew Rate and Gain-Bandwidth
Product vs Temperature
Output Voltage Swing
vs Load Current
Capacitive Load Handling
+
V
–0.8
–1.0
–1.2
–1.4
–1.6
2.0
50
40
30
20
10
0
6
5
4
3
2
1
0
12
10
8
V
= ±15V
= 25°C
≥ 10k
= 100mV
= 10
V
= ±15V
S
A
L
O
V
S
125°C
25°C
T
R
V
A
–55°C
P-P
R = 10k
C = 20pF
F
F
SR
V
= ±5V TO ±20V
S
6
1.8
GBWP
125°C
4
1.6
A
= 1
V
1.4
2
–55°C
1.2
25°C
A
= 10
V
–
V
+1.0
0
50 75
–75 –50 –25
0
25
100 125
0
2
4
8
0.1
1
100
1000 10000
–10 –8
–2
6
I
10
10
–6 –4
I
SINK
SOURCE
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
CAPACITIVE LOAD (pF)
1792 G14
1792 G12
1792 G13
THD and Noise vs Frequency for
Noninverting Gain
THD and Noise vs Frequency for
Inverting Gain
Warm-Up Drift
90
75
60
45
30
15
0
1
0.1
1
V
T
= ±15V
= 25°C
Z
V
A
= 2k 15pF
S
A
Z
V
A
= 2k 15pF
L
O
V
L
O
V
= 20V
= 20V
P-P
P-P
= –1, –10, –100
= 1, 10, 100
MEASUREMENT BANDWIDTH
= 10Hz TO 80kHz
MEASUREMENT BANDWIDTH
= 10Hz TO 80kHz
0.1
0.01
SO-8 PACKAGE
N8 PACKAGE
A
= 100
V
0.01
A
= –100
V
A
= –10
V
A
= 10
A = 1
V
A
= –1
V
V
0.001
0.0001
0.001
0.0001
NOISE FLOOR
1k
NOISE FLOOR
0
2
3
4
5
6
1
20
100
10k 20k
20
100
1k
10k 20k
TIME AFTER POWER ON (MINUTES)
FREQUENCY (Hz)
FREQUENCY (Hz)
1792 G17
1792 G15
1792 G16
6
LT1792
U W
TYPICAL PERFOR A CE CHARACTERISTICS
THD and Noise vs Output
Amplitude for Noninverting Gain
THD and Noise vs Output
Amplitude for Inverting Gain
1
1
0.1
Z
= 2k 15pF, f = 1kHz
O
Z
= 2k 15pF, f = 1kHz
L O
L
V
A
= 1, 10, 100
A
= –1, –10, –100
V
MEASUREMENT BANDWIDTH
= 10Hz TO 22kHz
MEASUREMENT BANDWIDTH
= 10Hz TO 22kHz
0.1
0.01
A
V
= 100
A
V
= –100
0.01
A
= –10
= –1
V
A
V
= 10
0.001
0.0001
0.001
0.0001
A
= 1
V
A
V
0.3
1
10
30
0.3
1
10
30
OUTPUT SWING (V
)
OUTPUT SWING (V
)
P-P
P-P
1792 G18
1792 G19
Short-Circuit Output Current
vs Temperature
Supply Current vs Temperature
40
35
30
25
20
15
10
5
V
= ±15V
S
V
= ±15V
= ±5V
S
SINK
SOURCE
4
V
S
3
75 100
75 100
125
–75 –50 –25
0
25 50
125
–75 –50 –25
0
25 50
TEMPERATURE (°C)
TEMPERATURE (°C)
1792 G20
1792 G21
W
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I FOR ATIO
PPLICATI
A
S
15V
15V
TheLT1792maybeinserteddirectlyintoOPA124, AD743,
AD745, AD645, AD544 and AD820 sockets with improved
noise performance. Offset nulling will be compatible with
these devices with the wiper of the potentiometer tied to
the negative supply (Figure 1a). No appreciable change in
offset voltage drift with temperature will occur when the
device is nulled with a potentiometer ranging from 10k to
200k. Finer adjustments can be made with resistors in
series with the potentiometer (Figure 1b).
–
–
+
2
2
3
7
7
6
4
6
3 +
4
5
5
∆V = ±1mV
∆V = ±10mV
OS
OS
1
1
10k 10k
50k
50k
–15V
1792 F01a
–15V
1792 F01b
Being a low voltage noise JFET op amp, the LT1792 can
replace many bipolar op amps that are used in amplifying
low level signals from high impedance transducers. The
(a)
(b)
Figure 1
7
LT1792
PPLICATI
best bipolar op amps, with higher current noise, will
eventuallyloseouttotheLT1792whentransducerimped-
ance increases. The low voltage noise of the LT1792
allows it to surpass most single JFET op amps available.
For the best performance versus area available anywhere,
the LT1792 is offered in the SO-8 surface mount package
with no degradation in performance.
W
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I FOR ATIO
S
A
1k
100
10
LT1007*
LT1792*
C
R
S
S
–
+
LT1007†
V
O
R
C
S
S
LT1792†
LT1792
LT1007
RESISTOR NOISE ONLY
The low voltage and current noise offered by the LT1792
makes it useful in a wide range of applications, especially
where high impedance, capacitive transducers are used
suchashydrophones,precisionaccelerometersandphoto
diodes. The total output noise in such a system is the gain
times the RMS sum of the op amp input referred voltage
noise, the thermal noise of the transducer, and the op amp
bias current noise times the transducer impedance.
Figure 2 shows total input voltage noise versus source
resistance. In a low source resistance (<5k) application
the op amp voltage noise will dominate the total noise.
ThismeanstheLT1792willbeatoutanyJFETopamp,only
the lowest noise bipolar op amps have the edge
at low source resistances. As the source resistance in-
creases from 5k to 50k, the LT1792 will match the best
bipolar op amps for noise performance, since the thermal
noise of the transducer (4kTR) begins to dominate the
total noise. A further increase in source resistance, above
50k, iswheretheopamp’scurrentnoisecomponent(2qIB
RTRANS) will eventually dominate the total noise. At these
high source resistances, the LT1792 will out perform
the lowest noise bipolar op amp due to the inherently low
1
100
1k 10k 100k 1M
SOURCE RESISTANCE (Ω)
10M 100M
1792 F02
SOURCE RESISTANCE = 2R = R
S
* PLUS RESISTOR
PLUS RESISTOR
†
1000pF CAPACITOR
2
2
V = A √V
+ 4kTR + 2qI • R
B
n
V
n (OP AMP)
Figure 2. Comparison of LT1792 and LT1007 Total Output
1kHz Voltage Noise Versus Source Resistance
current noise of FET input op amps. Clearly, the LT1792
will extend the range of high impedance transducers
that can be used for high signal-to-noise ratios. This
makes the LT1792 the best choice for high impedance,
capacitive transducers.
The high input impedance JFET front end makes the
LT1792 suitable in applications where very high charge
sensitivityisrequired. Figure3illustratestheLT1792inits
inverting and noninverting modes of operation. A charge
amplifierisshownintheinvertingmodeexample;herethe
gain depends on the principal of charge conservation at
R2
R
F
C
B
C
F
R
B
–
+
–
+
OUTPUT
OUTPUT
C
R
R1
S
S
TRANSDUCER
C
R
R
C
C
= C
C
S
S
B
B
S
S
S
B
B
F
F
= R
R
= R
R
C
R
S
S
> R1 OR R2
dQ
Q = CV; = I = C
dt
dV
dt
C
R
B
B
TRANSDUCER
1792 F03
Figure 3. Noninverting and Inverting Gain Configurations
8
LT1792
W
U
O U
I FOR ATIO
S
PPLICATI
A
the input of the LT1792. The charge across the transducer
capacitance, CS, is transferred to the feedback capacitor
CF, resulting in a change in voltage, dV, equal to dQ/CF.
The gain therefore is CF/CS. For unity gain, the CF should
equal the transducer capacitance plus the input capaci-
tance of the LT1792 and RF should equal RS. In the
noninverting mode example, the transducer current is
converted to a change in voltage by the transducer capaci-
tance; this voltage is then buffered by the LT1792 with a
gain of 1 + R1/R2. A DC path is provided by RS, which is
either the transducer impedance or an external resistor.
Since RS is usually several orders of magnitude greater
than the parallel combination of R1 and R2, RB is added to
balance the DC offset caused by the noninverting input
bias current and RS. The input bias currents, although
small at room temperature, can create significant errors at
highertemperature,especiallywithtransducerresistances
of up to 100M or more. The optimum value for RS is
determined by equating the thermal noise (4kTRS) to the
current noise times RS, [(2qIB) • RS], resulting in
RB = 2VT/IB (VT = 26mV at 25°C). A parallel capacitor, CB,
is used to cancel the phase shift caused by the op amp
input capacitance and RB.
expense of reduced dynamic range. To illustrate this
benefit, let’s take the following example:
An LT1792CS8 operates at an ambient temperature of
25°C with ±15V supplies, dissipating 159mW of power
(typical supply current = 5.3mA). The SO-8 package has a
θJA of 190°C/W, which results in a die temperature in-
crease of 30.2°C or a room temperature die operating
temperature of 55.2°C. At ±5V supplies, the die tempera-
ture increases by only one third of the previous amount or
10.1°C resulting in a typical die operating temperature of
only 35.1°C. A 20 degree reduction of die temperature is
achieved at the expense of a 20V reduction in dynamic
range.
To take full advantage of a wide input common mode
range, the LT1792 was designed to eliminate phase rever-
sal. Referring to the photographs shown in Figure 4, the
LT1792 is shown operating in the follower mode (AV = 1)
at±5Vsupplieswiththeinputswinging±5.2V. Theoutput
of the LT1792 clips cleanly and recovers with no phase
reversal. This has the benefit of preventing lock-up in
servo systems and minimizing distortion components.
High Speed Operation
Reduced Power Supply Operation
The low noise performance of the LT1792 was achieved
by making the input JFET differential pair large to maxi-
mize the first stage gain. Increasing the JFET geometry
The LT1792 can be operated from ±5V supplies for lower
power dissipation resulting in lower IB and noise at the
INPUT: ±5.2V Sine Wave
LT1792 Output
1792 F04a
1792 F03b
Figure 4. Voltage Follower with Input Exceeding the Common Mode Range ( VS = ±5V)
9
LT1792
PPLICATI
W
U
O U
I FOR ATIO
S
A
C
F
alsoincreasestheparasiticgatecapacitance, whichifleft
unchecked, can result in increased overshoot and ring-
ing. When the feedback around the op amp is resistive
(RF), a pole will be created with RF, the source resistance
and capacitance (RS, CS), and the amplifier input capaci-
tance (CIN = 27pF). In low gain configurations and with
RS and RF in the kilohm range (Figure 5), this pole can
create excess phase shift and even oscillation. A small
capacitor (CF) in parallel with RF eliminates this problem.
With RS(CS + CIN) = RFCF, the effect of the feedback pole
is completely removed.
R
F
–
+
C
OUTPUT
IN
R
C
S
S
1792 F05
Figure 5
U
O
TYPICAL APPLICATI S
Accelerometer Amplifier with DC Servo
C1
1250pF
C2
2µF
R1
100M
R2
18k
R3
2k
R4
R4C2 = R5C3 > R1 (1 + R2/R3) C1
OUTPUT = 0.8mV/pC* = 8.0mV/g**
DC OUTPUT ≤ 2.7mV
20M
–
+
2
3
6
R5
20M
LT1792
OUTPUT NOISE = 6nV/√Hz AT 1kHz
*PICOCOULOMBS
**g = EARTH’S GRAVITATIONAL CONSTANT
5V TO 15V
C3
2µF
ACCELEROMETER
B & K MODEL 4381
OR EQUIVALENT
–
+
7
2
3
6
LT1792
4
OUTPUT
1792 TA03
–5V TO –15V
10Hz Fourth Order Chebyshev Lowpass Filter (0.01dB Ripple)
C1
33nF
R2
237k
C3
10nF
R5
154k
15V
R3
R1
237k
249k
–
2
7
R4
154k
R6
V
IN
249k
–
+
2
3
6
LT1792
C2
100nF
6
+
3
V
LT1792
OUT
C4
330nF
4
–15V
1792 TA06
TYPICAL OFFSET ≈ 0.8mV
1% TOLERANCES
FOR V = 10V , V
= –121dB AT f > 330Hz
= – 6dB AT f = 16.3Hz
IN
P-P OUT
LOWER RESISTOR VALUES WILL RESULT IN LOWER THERMAL NOISE AND LARGER CAPACITORS
10
LT1792
U
O
TYPICAL APPLICATI S
Low Noise Light Sensor with DC Servo
C1
2pF
R1
1M
–
2
6
LT1792
+
OUTPUT
C2
0.022µF
3
D2
1N914
+
C
D
V
R2
100k
7
–
+
D1
1N914
2
3
R3
1k
6
2N3904
LT1792
4
R5
1k
R4
1k
–
V
HAMAMATSU
S1336-5BK
R2C2 > C1R1
C
D
V
O
= PARASITIC PHOTODIODE CAPACITANCE
= 100mV/µWATT FOR 200nm WAVE LENGTH
330mV/µWATT FOR 633nm WAVE LENGTH
1792 TA05
–
V
Paralleling Amplifiers to Reduce Voltage Noise
3
+
1k
1k
1k
An
6
6
6
LT1792
2
–
51Ω
51Ω
1k
1k
10k
3
2
15V
7
+
–
+
A2
LT1792
2
3
6
OUTPUT
LT1792
–
4
15V
7
–15V
3
2
+
A1
LT1792
–
4
1. ASSUME VOLTAGE NOISE OF LT1792 AND 51Ω SOURCE RESISTOR = 4.3nV/√Hz
2. GAIN WITH n LT1792s IN PARALLEL = n × 200
3. OUTPUT NOISE = √n × 200 × 4.3nV/√Hz
–15V
1k
51Ω
OUTPUT NOISE 4.3
n × 200
4. INPUT REFERRED NOISE =
=
nV/√Hz
n
√
5. NOISE CURRENT AT INPUT INCREASES n TIMES
1792 TA04
√
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LT1792
U
O
TYPICAL APPLICATI S
Light Balance Detection Circuit
Unity-Gain Buffer with Extended
Load Capacitance Drive Capability
R1
1M
R2
1k
C1
C1
I
1
2
2pF TO 8pF
–
PD1
PD2
R1
33Ω
–
V
LT1792
+
OUT
I
V
IN
C
V
OUT
LT1792
L
+
1792 TA08
C1 = C ≤ 0.1µF
1792 TA07
L
OUTPUT SHORT-CIRCUIT CURRENT
V
= 1M × (I – I )
1 2
OUT
(
30mA) WILL LIMIT THE RATE AT WHICH THE
PD1 PD2 = HAMAMATSU S1336-5BK
,
VOLTAGE CAN CHANGE ACROSS LARGE CAPACITORS
WHEN EQUAL LIGHT ENTERS PHOTODIODES, V
< 3mV.
OUT
dV
dt
I = C
(
)
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.400*
(10.160)
MAX
0.189 – 0.197*
(4.801 – 5.004)
7
8
6
5
8
7
6
5
0.255 ± 0.015*
(6.477 ± 0.381)
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
2
4
3
1
0.053 – 0.069
2
3
4
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
0.010 – 0.020
(0.254 – 0.508)
× 45°
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
0.125
(3.175)
MIN
0.020
(0.508)
MIN
*DIMENSION DOES NOT INCLUDE MOLD FLASH.
MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH.
INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 0996
+0.035
–0.015
0.325
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
+0.889
8.255
(
)
N8 1197
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1113
Low Noise Dual JFET Op Amp
Low Noise Dual JFET Op Amp
Low Noise Single Op Amp
Dual Version of LT1792, V
= 4.5nV/√Hz
NOISE
LT1169
Dual Version of LT1793, I = 10pA, V
= 6nV/√Hz
NOISE
B
LT1793
Lower I Version of LT1792, I = 10pA, V
= 6nV/√Hz
NOISE
B
B
1792f LTTP 0599 4K • PRINTED IN USA
12 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 1999
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
相关型号：
LT1793ACS8#TR
LT1793 - Low Noise, Picoampere Bias Current, JFET Input Op Amp; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
Linear
LT1793CN8#PBF
LT1793 - Low Noise, Picoampere Bias Current, JFET Input Op Amp; Package: PDIP; Pins: 8; Temperature Range: 0°C to 70°C
Linear
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