LT1794 [Linear]
Dual 500mA, 200MHz xDSL Line Driver Amplifier; 双500毫安， 200MHz的xDSL线路驱动放大器
| 型号： | LT1794 |
| 厂家： | 
Linear |
| 描述： | Dual 500mA, 200MHz xDSL Line Driver Amplifier |
| 文件： | 总20页 (文件大小：276K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1794
Dual 500mA, 200MHz
xDSL Line Driver Amplifier
U
FEATURES
DESCRIPTIO
TheLT®1794isa500mAminimumoutputcurrent,dualop
amp with outstanding distortion performance. The ampli-
fiersaregain-of-tenstable, butcanbeeasilycompensated
for lower gains. The extended output swing allows for
lowersupplyrailstoreducesystempower. Supplycurrent
is set with an external resistor to optimize power dissipa-
tion. The LT1794 features balanced, high impedance in-
puts with low input bias current and input offset voltage.
Active termination is easily implemented for further sys-
tempowerreduction.Short-circuitprotectionandthermal
shutdown insure the device’s ruggedness.
■
Exceeds All Requirements For Full Rate,
Downstream ADSL Line Drivers
■
±500mA Minimum IOUT
■
±11.1V Output Swing, VS = ±12V, RL = 100Ω
■
±10.9V Output Swing, VS = ±12V, IL = 250mA
■
Low Distortion: –82dBc at 1MHz, 2VP-P Into 50Ω
■
Power Saving Adjustable Supply Current
■
Power Enhanced Small Footprint Packages:
20-Lead TSSOP and 20-Lead SW
■
200MHz Gain Bandwidth
500V/µs Slew Rate
■
■
Specified at ±15V, ±12V and ±5V
The outputs drive a 100Ω load to ±11.1V with ±12V
supplies, and ±10.9V with a 250mA load. The LT1794,
with its increased swing on lower supplies, can be used to
upgrade LT1795 line driver applications.
U
APPLICATIO S
■
High Density ADSL Central Office Line Drivers
■
High Efficiency ADSL, HDSL2, G.lite,
The LT1794 is available in the very small, thermally
enhanced, 20-lead TSSOP for maximum port density in
line driver applications. The 20-lead SW is also available.
, LTC and LT are registered trademarks of Linear Technology Corporation.
SHDSL Line Drivers
Buffers
Test Equipment Amplifiers
Cable Drivers
■
■
■
U
TYPICAL APPLICATIO
High Efficiency ±12V Supply ADSL Central Office Line Driver
12V
R
BIAS
24.9k
+IN
+
SHDN
12.7Ω
1/2
LT1794
–
1k
1:2*
110Ω
110Ω
100Ω
1000pF
1k
*COILCRAFT X8390-A OR EQUIVALENT
= 10mA PER AMPLIFIER
–
I
SUPPLY
12.7Ω
1/2
LT1794
WITH R
= 24.9k
BIAS
SHDNREF
–IN
+
1794 TA01
–12V
1
LT1794
W W
U W
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Supply Voltage (V+ to V–) .................................... ±18V
Input Current ..................................................... ±10mA
Output Short-Circuit Duration (Note 2)........... Indefinite
Operating Temperature Range ............... – 40°C to 85°C
Specified Temperature Range (Note 3).. – 40°C to 85°C
Junction Temperature.......................................... 150°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
U
W U
PACKAGE/ORDER INFORMATION
ORDER PART
ORDER PART
TOP VIEW
TOP VIEW
NUMBER
NUMBER
–
–
V
1
2
20
V
NC
1
2
3
4
5
6
7
8
9
20 NC
+
NC
–IN
19 NC
+
LT1794CFE
LT1794IFE
LT1794CSW
LT1794ISW
V
19
V
3
18 OUT
+
OUT
18 OUT
–
+IN
4
17
V
–
V
17
16
15
14
V
V
V
V
SHDN
SHDNREF
+IN
5
16 NC
–
–
–
–
V
6
15 NC
+
–
V
7
14
V
–
V
–IN
8
13 OUT
–IN
+IN
13 –IN
NC
–
9
12 NC
–
12 +IN
V
10
11
V
SHDN 10
11 SHDNREF
FE PACKAGE
20-LEAD PLASTIC TSSOP
SW PACKAGE
20-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 40°C/W, θJC = 3°C/W (Note 4)
TJMAX = 150°C, θJA = 40°C/W, θJC = 3°C/W (Note 4)
UNDERSIDE METAL CONNECTED TO V–
Consult factory for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C.
VCM = 0V, pulse tested, ±5V ≤ VS ≤ ±15V, VSHDNREF = 0V, RBIAS = 24.9k between V+ and SHDN unless otherwise noted. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage
1
5.0
7.5
mV
mV
OS
●
Input Offset Voltage Matching
0.3
5.0
7.5
mV
mV
●
●
Input Offset Voltage Drift
Input Offset Current
10
µV/°C
I
I
100
500
800
nA
nA
OS
●
●
●
Input Bias Current
±0.1
±4
±6
µA
µA
B
Input Bias Current Matching
100
500
800
nA
nA
e
Input Noise Voltage Density
Input Noise Current Density
Input Resistance
f = 10kHz
8
nV/√Hz
pA/√Hz
n
i
f = 10kHz
0.8
n
+
–
R
V
= (V – 2V) to (V + 2V)
●
5
50
6.5
MΩ
MΩ
IN
CM
Differential
2
LT1794
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C.
VCM = 0V, pulse tested, ±5V ≤ VS ≤ ±15V, VSHDNREF = 0V, RBIAS = 24.9k between V+ and SHDN unless otherwise noted. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
C
Input Capacitance
3
pF
IN
+
+
Input Voltage Range (Positive)
Input Voltage Range (Negative)
(Note 5)
(Note 5)
+
●
●
V – 2
V – 1
V
V
–
–
V + 1
V + 2
–
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain
V
CM
= (V – 2V) to (V + 2V)
74
66
83
88
dB
dB
●
●
●
●
●
●
●
●
●
●
●
V = ±4V to ±15V
S
74
66
dB
dB
A
VOL
V = ±15V, V
S
= ±13V, R = 100Ω
70
64
82
dB
dB
OUT
L
V = ±12V, V
S
= ±10V, R = 40Ω
63
57
76
dB
dB
OUT
L
V = ±5V, V
S
= ±3V, R = 25Ω
60
54
70
dB
dB
OUT
L
V
OUT
Output Swing
V = ±15V, R = 100Ω
S
13.8
13.6
14.0
13.9
11.1
10.9
4.0
3.9
±V
±V
L
V = ±15V, I = 250mA
S
13.6
13.4
±V
±V
L
V = ±12V, R = 100Ω
S
10.9
10.7
±V
±V
L
V = ±12V, I = 250mA
S
10.6
10.4
±V
±V
L
V = ±5V, R = 25Ω
S
3.7
3.5
±V
±V
L
V = ±5V, I = 250mA
S
3.6
3.4
±V
±V
L
I
I
Maximum Output Current
V = ±15V, R = 1Ω
500
720
13
mA
OUT
S
S
L
Supply Current per Amplifier
V = ±15V, R
= 24.9k (Note 6)
10
8
18
20
mA
mA
S
BIAS
●
●
V = ±12V, R
= 24.9k (Note 6)
8.0
6.7
10
13.5
15.0
mA
mA
mA
mA
mA
S
BIAS
V = ±12V, R
= 32.4k (Note 6)
= 43.2k (Note 6)
= 66.5k (Note 6)
8
6
4
S
BIAS
BIAS
BIAS
V = ±12V, R
S
V = ±12V, R
S
V = ±5V, R
= 24.9k (Note 6)
2.2
1.8
3.4
5.0
5.8
mA
mA
S
BIAS
●
●
Supply Current in Shutdown
Output Leakage in Shutdown
Channel Separation
V
V
= 0.4V
0.1
0.3
1
1
mA
mA
SHDN
= 0.4V
SHDN
V = ±12V, V
S
= ±10V, R = 40Ω
80
77
110
dB
dB
OUT
L
SR
Slew Rate
V = ±15V, A = –10, (Note 7)
300
100
600
200
–85
–82
200
V/µs
V/µs
dBc
S
V
V = ±5V, A = –10, (Note 7)
S
V
HD2
HD3
GBW
Differential 2nd Harmonic Distortion
Differential 3rd Harmonic Distortion
Gain Bandwidth
V = ±12V, A = 10, 2V , R = 50Ω, 1MHz
S V P-P L
V = ±12V, A = 10, 2V , R = 50Ω, 1MHz
dBc
S
V
P-P
L
f = 1MHz
MHz
3
LT1794
ELECTRICAL CHARACTERISTICS
Note 4: Thermal resistance varies depending upon the amount of PC board
metal attached to the device. If the maximum dissipation of the package is
exceeded, the device will go into thermal shutdown and be protected.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Applies to short circuits to ground only. A short circuit between
the output and either supply may permanently damage the part when
operated on supplies greater than ±10V.
Note 5: Guaranteed by the CMRR tests.
+
Note 6: R
is connected between V and the SHDN pin.
BIAS
Note 3: The LT1794C is guaranteed to meet specified performance from
0°C to 70°C and is designed, characterized and expected to meet these
extended temperature limits, but is not tested at –40°C and 85°C. The
LT1794I is guaranteed to meet the extended temperature limits.
Note 7: Slew rate is measured at ±5V on a ±10V output signal while
operating on ±15V supplies and ±1V on a ±3V output signal while
operating on ±5V supplies.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current
Input Common Mode Range
vs Supply Voltage
Input Bias Current
vs Ambient Temperature
vs Ambient Temperature
+
200
180
160
140
120
100
80
15
14
13
12
11
10
9
V
T
= 25°C
V
I
= ±12V
S
PER AMPLIFIER = 10mA
V
= ±12V
BIAS
A
S
∆V > 1mV
R
= 24.9k TO SHDN
–0.5
–1.0
–1.5
–2.0
OS
S
V
= 0V
SHDNREF
2.0
1.5
1.0
0.5
60
8
40
7
20
6
–
V
0
5
10
30
50
70
90
–50 –30 –10 10
30
50
70
90
2
4
8
10
12
14
–50 –30 –10
6
SUPPLY VOLTAGE (±V)
TEMPERATURE (°C)
TEMPERATURE (°C)
1794 G03
1794 G01
1794 G02
Output Short-Circuit Current
vs Ambient Temperature
Output Saturation Voltage
vs Ambient Temperature
Input Noise Spectral Density
+
800
780
760
740
720
700
680
660
640
620
600
100
10
1
100
10
1
V
V
I
= ±12V
PER AMPLIFIER = 10mA
T
= 25°C
= ±12V
V
S
= ±12V
S
S
A
S
V
I
–0.5
–1.0
PER AMPLIFIER = 10mA
R
L
= 100Ω
S
e
i
I
I
= 250mA
n
LOAD
–1.5
SINKING
1.5
1.0
0.5
SOURCING
n
= 250mA
LOAD
R
L
= 100Ω
–
0.1
0.1
100k
V
–50
30
TEMPERATURE (°C)
70
–30 –10 10
50
90
–30 –10
30
50
70
90
–50
10
1
10
100
1k
10k
FREQUENCY (Hz)
TEMPERATURE (°C)
1794 G04
1794 G05
1794 G06
4
LT1794
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Open-Loop Gain and Phase
vs Frequency
–3dB Bandwidth
vs Supply Current
Slew Rate vs Supply Current
120
100
80
120
80
45
40
35
30
25
20
15
10
5
1000
900
800
700
600
500
400
300
200
100
0
T
= 25°C
= ±12V
= 10
A
S
V
T
= 25°C
= ±12V
= –10
= 1k
A
S
V
V
A
V
A
PHASE
40
R
= 100Ω
L
R
L
RISING
60
0
40
–40
–80
–120
–160
–200
–240
–280
FALLING
20
GAIN
0
–20
–40
–60
–80
T
= 25°C
= ±12V
= –10
A
S
V
V
A
R
= 100Ω
L
I
PER AMPLIFIER = 10mA
S
0
100k
1M
10M
100M
2
4
6
8
10
12
14
2
3
4
5
6
7
8
9
10 11 12 13 14 15
FREQUENCY (Hz)
SUPPLY CURRENT PER AMPLIFIER (mA)
SUPPLY CURRENT PER AMPLIFIER (mA)
1794 G07
1794 G08
1794 G09
Frequency Response
vs Supply Current
CMRR vs Frequency
PSRR vs Frequency
100
90
30
25
20
15
100
90
80
70
60
50
40
30
20
10
0
T
= 25°C
V
S
A
V
= ±12V
= 10
A
S
V
A
S
= ±12V
= 10
= 10mA PER AMPLIFIER
S
V
V
= ±12V
I
S
= 10mA PER AMPLIFIER
I
80
70
2mA PER AMPLIFIER
60
50
10
5
10mA PER AMPLIFIER
15mA PER AMPLIFIER
(–) SUPPLY
40
30
20
10
0
0
–5
(+) SUPPLY
–10
–15
–20
–10
0.1
1
10
100
1k
10k
100k
1M
10M 100M
0.01
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (Hz)
FREQUENCY (MHz)
1794 G10
1794 G12
1794 G11
Output Impedance vs Frequency
ISHDN vs VSHDN
Supply Current vs VSHDN
35
1000
100
10
2.5
2.0
1.5
T
= 25°C
±12V
A
S
T
V
V
= 25°C
= ±12V
SHDNREF
T
V
V
= 25°C
= ±12V
S
A
S
A
V
30
25
20
15
10
5
= 0V
= 0V
SHDNREF
I
PER
S
AMPLIFIER = 2mA
I
S
PER
AMPLIFIER = 10mA
1
1.0
0.5
0
I
S
PER
AMPLIFIER = 15mA
0.1
0.01
0
0.01
0.1
1
10
100
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
(V)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
(V)
FREQUENCY (MHz)
V
V
SHDN
SHDN
1734 G13
1794 G14
1794 G14
5
LT1794
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Differential Harmonic Distortion
vs Output Amplitude
Differential Harmonic Distortion
vs Frequency
–40
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
f = 1MHz
V
T
= 10V
P-P
O
A
S
V
L
T
= 25°C
= ±12V
= 10
= 25°C
= ±12V
= 10
A
S
V
–50
–60
V
A
V
A
R
I
= 50Ω
R
I
= 50Ω
PER AMPLIFIER = 10mA
L
S
PER AMPLIFIER = 10mA
S
HD3
HD2
–70
–80
HD3
–90
HD2
–100
0
2
4
6
8
10 12 14 16 18
100 200 300 400 500 600 700 800 900 1000
V
FREQUENCY (kHz)
OUT(P-P)
1794 G16
1794 G17
Differential Harmonic Distortion
vs Supply Current
Undistorted Output Swing
vs Frequency
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
20
15
10
5
V
V
A
= 10V
P-P
O
S
V
= ±12V
= 10
R
= 50Ω
L
f = 1MHz, HD3
SFDR > 40dB
f = 100kHz, HD2
T
= 25°C
= ±12V
= 10
A
V
A
S
V
f = 100kHz, HD3
f = 1MHz, HD2
R
L
= 50Ω
I
PER AMPLIFIER = 10mA
S
0
100k
300k
1M
3M
10M
2
3
4
5
6
11
7
8
9
10
FREQUENCY (Hz)
I
PER AMPLIFIER (mA)
SUPPLY
1794 G19
1794 G18
6
LT1794
TEST CIRCUIT
SUPPLY BYPASSING
12V
12V
0.1µF
+
0.1µF
0.1µF
4.7µF
+
R
SHDN
4.7µF
+
2
19
5
9
8
4.7µF
+
–
10 (SHDN)
3
V
–12V
OUT(P-P)
A
7
6
12.7Ω
1:2*
4
10k
1k
–12V
110Ω
110Ω
OUT (+)
OUT (–)
R
≈ 50Ω
L
E
SPLITTER
100 LINE LOAD
IN
0.01µF
49.9Ω
1k
MINICIRCUITS
ZSC5-2-2
10k
13
12.7Ω
–
18
1794 TC
B
12
17 11 (SHDNREF)
+
16
15
14
*COILCRAFT X8390-A OR EQUIVALENT
V
AMPLITUDE SET AT EACH AMPLIFIER OUTPUT
OUTP-P
DISTORTION MEASURED ACROSS LINE LOAD
–12V
W U U
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APPLICATIO S I FOR ATIO
The LT1794 is a high speed, 200MHz gain bandwidth
product, dual voltage feedback amplifier with high output
current drive capability, 500mA source and sink. The
LT1794 is ideal for use as a line driver in xDSL data
communication applications. The output voltage swing
has been optimized to provide sufficient headroom when
operating from ±12V power supplies in full-rate ADSL
applications. The LT1794 also allows for an adjustment of
the operating current to minimize power consumption. In
addition, the LT1794 is available in small footprint surface
mount packages to minimize PCB area in multiport central
office DSL cards.
Setting the Quiescent Operating Current
Power consumption and dissipation are critical concerns
in multiport xDSL applications. Two pins, Shutdown
(SHDN) and Shutdown Reference (SHDNREF), are pro-
vided to control quiescent power consumption and allow
for the complete shutdown of the driver. The quiescent
current should be set high enough to prevent distortion
induced errors in a particular application, but not so high
that power is wasted in the driver unnecessarily. A good
startingpointtoevaluatetheLT1794istosetthequiescent
current to 10mA per amplifier.
TheinternalbiasingcircuitryisshowninFigure1.Ground-
ingtheSHDNREFpinanddirectlydrivingtheSHDNpinwith
a voltage can control the operating current as seen in the
Typical Performance Characteristics. When the SHDN pin
is less than SHDNREF + 0.4V, the driver is shut down and
consumes typically only 100µA of supply current and the
To minimize signal distortion, the LT1794 amplifiers are
decompensated to provide very high open-loop gain at
high frequency. As a result each amplifier is frequency
stable with a closed-loop gain of 10 or more. If a closed-
loop gain of less than 10 is desired, external frequency
compensating components can be used.
7
LT1794
W U U
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APPLICATIO S I FOR ATIO
SHDN
outputs are in a high impedance state. Part to part varia-
tions however, will cause inconsistent control of the qui-
escentcurrentifdirectvoltagedriveoftheSHDNpinisused.
5I
2k
I
2I
Usingasingleexternalresistor, RBIAS, connectedinoneof
two ways provides a much more predictable control of the
quiescent supply current. Figure 2 illustrates the effect on
supply current per amplifier with RBIAS connected be-
tween the SHDN pin and the 12V V+ supply of the LT1794
and the approximate design equations. Figure 3 illustrates
the same control with RBIAS connected between the
SHDNREFpinandgroundwhiletheSHDNpinistiedtoV+.
Either approach is equally effective.
2I
1k
TO
START-UP
CIRCUITRY
I
BIAS
TO AMPLIFIERS
BIAS CIRCUITRY
1794 F01
SHDNREF
I = I
SHDN SHDNREF
2
I
I
=
BIAS
5
PER AMPLIFIER (mA) = 64 • I
BIAS
SUPPLY
Figure 1. Internal Current Biasing Circuitry
30
+
V
S
= ±12V
V
= 12V
25
R
BIAS
SHDN
+
20
15
10
5
V
R
– 1.2V
• 25.6
≈
I
PER AMPLIFIER (mA)
+
S
+ 2k
BIAS
V
– 1.2V
R
=
• 25.6 – 2k
BIAS
I
S
PER AMPLIFIER (mA)
SHDNREF
0
7
10
40
70
100
130
160
190
R
(kΩ)
BIAS
1794 F02
Figure 2. RBIAS to V+ Current Control
45
40
35
30
25
20
15
10
5
+
V
S
= ±12V
V
= 12V
SHDN
PER AMPLIFIER
+
V
R
– 1.2V
• 64
≈
I
(mA)
S
+ 5k
BIAS
+
V
– 1.2V
R
=
• 64 – 5k
BIAS
I
PER AMPLIFIER (mA)
S
SHDNREF
R
BIAS
0
4
7
10 30 50 70 90 100 130 150 170 190 210 230 250 270 290
(kΩ)
R
BIAS
1794 F03
Figure 3. RBIAS to Ground Current Control
8
LT1794
W U U
APPLICATIO S I FOR ATIO
U
Logic Controlled Operating Current
Shutdown and Recovery
The DSP controller in a typical xDSL application can have The ultimate power saving action on a completely idle port
I/O pins assigned to provide logic control of the LT1794 istofullyshutdownthelinedriverbypullingtheSHDNpin
line driver operating current. As shown in Figure 4 one or to within 0.4V of the SHDNREF potential. As shown in
two logic control inputs can control two or four different Figure 5 complete shutdown occurs in less than 10µs and,
operating modes. The logic inputs add or subtract current more importantly, complete recovery from the shut down
to the SHDN input to set the operating current. The one state to full operation occurs in less than 2µs. The biasing
logic input example selects the supply current to be either circuitry in the LT1794 reacts very quickly to bring the
full power, 10mA per amplifier or just 2mA per amplifier, amplifiers back to normal operation.
which significantly reduces the driver power consumption
while maintaining less than 2Ω output impedance to
frequencies less than 1MHz. This low power mode retains
termination impedance at the amplifier outputs and the
VSHDN
SHDNREF = 0V
line driving back termination resistors. With this termina-
tion, while a DSL port is not transmitting data, it can still
sense a received signal from the line across the back-
AMPLIFIER
termination resistors and respond accordingly.
OUTPUT
The two logic input control provides two intermediate
(approximately 7mA per amplifier and 5mA per amplifier)
operatinglevelsbetweenfullpowerandterminationmodes.
These modes can be useful for overall system power
1794 F05
management when full power transmissions are not
necessary.
Figure 5. Shutdown and Recovery Timing
12V OR V
LOGIC
Two Control Inputs
RESISTOR VALUES (kΩ)
TO V (12V)
R
SHDN
V
LOGIC
R
SHDN
R
TO V
SHDN LOGIC
CC
R
R
C1
V
LOGIC
3V 3.3V 5V
3V 3.3V 5V
V
C1
SHDN
R
R
R
V
40.2 43.2 60.4 4.99 6.81 19.6
11.5 13.0 21.5 8.66 10.7 20.5
19.1 22.1 36.5 14.3 17.8 34.0
SUPPLY CURRENT PER AMPLIFIER (mA)
C0
SHDN
0V
V
C0
2k
C1
CO
C0
V
C1
H
H
L
H
L
H
L
10
7
5
10
7
5
10
7
5
10
7
5
10
7
5
10
7
5
SHDNREF
LOGIC
L
2
2
2
2
2
2
12V OR V
One Control Input
RESISTOR VALUES (kΩ)
TO V (12V)
R
SHDN
V
R
R
TO V
LOGIC
SHDN
CC
SHDN
LOGIC
R
C
V
R
3V 3.3V 5V
3V 3.3V 5V
LOGIC
V
C
0V
SHDN
40.2 43.2 60.4 4.99 6.81 19.6
7.32 8.25 13.7 5.49 6.65 12.7
SUPPLY CURRENT PER AMPLIFIER (mA)
SHDN
2k
R
V
C
C
H
L
10
2
10
2
10
2
10
2
10
2
10
2
1794 F04
SHDNREF
Figure 4. Providing Logic Input Control of Operating Current
9
LT1794
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APPLICATIO S I FOR ATIO
Power Dissipation and Heat Management
Estimating Line Driver Power Dissipation
xDSL applications require the line driver to dissipate a
significant amount of power and heat compared to other
components in the system. The large peak to RMS varia-
tions of DMT and CAP ADSL signals require high supply
voltages to prevent clipping, and the use of a step-up
transformer to couple the signal to the telephone line can
require high peak current levels. These requirements
result in the driver package having to dissipate on the
order of 1W. Several multiport cards inserted into a rack
in an enclosed central office box can add up to many,
many watts of power dissipation in an elevated ambient
temperature environment. The LT1794 has built-in ther-
mal shutdown circuitry that will protect the amplifiers if
operated at excessive temperatures, however data trans-
missions will be seriously impaired. It is important in the
design of the PCB and card enclosure to take measures to
spread the heat developed in the driver away to the
ambientenvironmenttopreventthermalshutdown(which
occurs when the junction temperature of the LT1794
exceeds 165°C).
Figure 6 is a typical ADSL application shown for the
purpose of estimating the power dissipation in the line
driver. Due to the complex nature of the DMT signal,
which looks very much like noise, it is easiest to use the
RMS values of voltages and currents for estimating the
driver power dissipation. The voltage and current levels
shown for this example are for a full-rate ADSL signal
driving 20dBm or 100mWRMS of power on to the 100Ω
telephone line and assuming a 0.5dBm insertion loss in
the transformer. The quiescent current for the LT1794 is
set to 10mA per amplifier.
ThepowerdissipatedintheLT1794isacombinationofthe
quiescent power and the output stage power when driving
a signal. The two amplifiers are configured to place a
differential signal on to the line. The Class AB output stage
in each amplifier will simultaneously dissipate power in
the upper power transistor of one amplifier, while sourc-
ing current, and the lower power transistor of the other
amplifier, while sinking current. The total device power
dissipation is then:
PD = PQUIESCENT + PQ(UPPER) + PQ(LOWER)
PD = (V+ – V–) • IQ + (V+ – VOUTARMS) •
ILOAD + (V– – VOUTBRMS) • ILOAD
12V
24.9k – SETS I PER AMPLIFIER = 10mA
Q
20mA DC
2V
SHDN
RMS
+IN
+
17.4Ω
A
–
1k
1:1.7
110Ω
110Ω
I
= 57mA
RMS
100Ω
3.16V
RMS
LOAD
1000pF
1k
–
+
17.4Ω
1794 F06
B
SHDNREF
–IN
–12V
–2V
RMS
Figure 6. Estimating Line Driver Power Dissipation
10
LT1794
W U U
APPLICATIO S I FOR ATIO
U
With no signal being placed on the line and the amplifier
biased for 10mA per amplifier supply current, the quies-
cent driver power dissipation is:
heat-spreading PCB metal and airflow through the enclo-
sure as required. For the example given, assuming a
maximum ambient temperature of 85°C and keeping the
junction temperature of the LT1794 to 140°C maximum,
themaximumthermalresistancefromjunctiontoambient
required is:
P
DQ = 24V • 20mA = 480mW
This can be reduced in many applications by operating
with a lower quiescent current value.
140°C – 85°C
θJA(MAX)
=
= 41.3°C/ W
When driving a load, a large percentage of the amplifier
quiescent current is diverted to the output stage and
becomes part of the load current. Figure 7 illustrates the
total amount of biasing current flowing between the + and
– power supplies through the amplifiers as a function of
load current. As much as 60% of the quiescent no load
operating current is diverted to the load.
1.332W
Heat Sinking Using PCB Metal
Designing a thermal management system is often a trial
and error process as it is never certain how effective it is
until it is manufactured and evaluated. As a general rule,
the more copper area of a PCB used for spreading heat
away from the driver package, the more the operating
junction temperature of the driver will be reduced. The
limit to this approach however is the need for very com-
pact circuit layout to allow more ports to be implemented
on any given size PCB.
At full power to the line the driver power dissipation is:
P
D(FULL) = 24V • 8mA + (12V – 2VRMS) • 57mARMS
+ [|–12V – (–2VRMS)|] • 57mARMS
PD(FULL) = 192mW + 570mW + 570mW = 1.332W
The junction temperature of the driver must be kept less
than the thermal shutdown temperature when processing
a signal. The junction temperature is determined from the
following expression:
Fortunately xDSL circuit boards use multiple layers of
metal for interconnection of components. Areas of metal
beneath the LT1794 connected together through several
small 13 mil vias can be effective in conducting heat away
from the driver package. The use of inner layer metal can
free up top and bottom layer PCB area for external compo-
nent placement.
TJ = TAMBIENT (°C) + PD(FULL) (W) • θJA (°C/W)
θJA is the thermal resistance from the junction of the
LT1794 to the ambient air, which can be minimized by
25
20
15
10
5
0
–240 –200 –160 –120 –80
–40
0
40
80
120
160
200
240
I
(mA)
LOAD
1794 F07
Figure 7. IQ vs ILOAD
11
LT1794
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APPLICATIO S I FOR ATIO
Figure 8 shows four examples of PCB metal being used for
heatspreading. Theseareprovidedasareferenceforwhat
might be expected when using different combinations of
metalareaondifferentlayersofaPCB.Theseexamplesare
with a 4-layer board using 1oz copper on each. The most
effective layers for spreading heat are those closest to the
LT1794 junction. The LT1794IFE is used because the
small TSSOP package is most effective for very compact
line driver designs. This package also has an exposed
metal heat sinking pad on the bottom side which, when
solderedtothePCBtoplayermetal, directlyconductsheat
awayfromtheICjunction.Solderingthethermalpadtothe
board produces a thermal resistance from junction to
case, θJC, of approximately 3°C/W.
Example A utilizes the most total metal area and provides
the lowest thermal resistance. Example B however uses
less metal on the top and bottom layers and still achieves
reasonable thermal performance. For the most compact
board design, inner layer metal can be used for heat
dissipation. This is shown in examples C and D where
minimum metal is used on the top and none on the bottom
layers, only the 2nd and 3rd layers have a heat-conducting
plane. Example C, with the larger metal areas performs
better.
TOP LAYER
2nd LAYER
3rd LAYER
BOTTOM LAYER
VIA PATTERN
TOPOLOGY
EXAMPLE A
θ
= 40°C/W
JA
13MIL VIAS USED: 30
EXAMPLE B
θ
= 47°C/W
JA
13MIL VIAS USED: 35
EXAMPLE C
θ
= 51°C/W
JA
13MIL VIAS USED: 32
EXAMPLE D
θ
= 60°C/W
JA
13MIL VIAS USED: 22
1794 F08
SCALE:
1 INCH
Figure 8. Examples of PCB Metal Used for Heat Dissipation. LT1794IFE Driver Mounted on Top Layer.
Heat Sink Pad Soldered to Top Layer Metal. External Components Mounted on Bottom Layer
12
LT1794
W U U
APPLICATIO S I FOR ATIO
U
SimilarresultscanbeobtainedwiththeLT1794CSWinthe
wide SO-20 package. With this package heat is conducted
primarily through the V– pins, Pins 4 to 7 and 14 to 17;
these pins should be soldered directly to the PCB metal
plane.
Figure 9showsthatforinvertinggains,aresistorfromthe
inverting node to AC ground guarantees stability if the
parallel combination of RC and RG is less than or equal to
RF/9. For lowest distortion and DC output offset, a series
capacitor, CC, can be used to reduce the noise gain at
lower frequencies. The break frequency produced by RC
and CC should be less than 5MHz to minimize peaking.
Important Note: The metal planes used for heat sinking
the LT1794 are electrically connected to the negative
supply potential of the driver, typically –12V. These
planes must be isolated from any other power planes
used in the board design.
Figure 10 shows compensation in the noninverting con-
figuration. The RC, CC network acts similarly to the invert-
ing case. The input impedance is not reduced because the
network is bootstrapped. This network can also be placed
between the inverting input and an AC ground.
When PCB cards containing multiple ports are inserted
into a rack in an enclosed cabinet, it is often necessary to
provide airflow through the cabinet and over the cards.
This is also very effective in reducing the junction-to-
ambient thermal resistance of each line driver. To a limit,
this thermal resistance can be reduced approximately
5°C/W for every 100lfpm of laminar airflow.
Anothercompensationschemefornoninvertingcircuitsis
shown in Figure 11. The circuit is unity gain at low
frequency and a gain of 1 + RF/RG at high frequency. The
DC output offset is reduced by a factor of ten. The
techniques of Figures 10 and 11 can be combined as
shown in Figure 12. The gain is unity at low frequencies,
1 + RF/RG at mid-band and for stability, a gain of 10 or
greater at high frequencies.
Layout and Passive Components
With a gain bandwidth product of 200MHz the LT1794
requires attention to detail in order to extract maximum
performance. Use a ground plane, short lead lengths and
acombinationofRF-qualitysupplybypasscapacitors(i.e.,
0.1µF). As the primary applications have high drive cur-
rent, use low ESR supply bypass capacitors (1µF to 10µF).
R
R
V
V
F
O
= 1 +
+
–
I
V
G
I
R
C
V
O
(R || R ) ≤ R /9
C
C
G
F
C
1
(OPTIONAL)
< 5MHz
The parallel combination of the feedback resistor and gain
settingresistorontheinvertinginputcancombinewiththe
input capacitance to form a pole that can cause frequency
peaking. In general, use feedback resistors of 1k or less.
2πR C
C
C
R
F
R
G
1794 F10
Compensation
Figure 10. Compensation for Noninverting Gains
The LT1794 is stable in a gain 10 or higher for any supply
andresistiveload.Itiseasilycompensatedforlowergains
with a single resistor or a resistor plus a capacitor.
V
V
O
+
–
= 1 (LOW FREQUENCIES)
I
V
G
i
R
F
R
F
= 1 +
(HIGH FREQUENCIES)
V
O
R
G
V
V
–R
F
O
R
=
R
G
≤ R /9
G
F
–
+
R
I
G
R
F
V
I
1
< 5MHz
(R || R ) ≤ R /9
R
V
C
G
F
2πR C
C
O
G
C
R
C
C
C
1
< 5MHz
(OPTIONAL)
2πR C
C
C
C
1794 F09
1794 F11
Figure 11. Alternate Noninverting Compensation
Figure 9. Compensation for Inverting Gains
13
LT1794
W U U
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APPLICATIO S I FOR ATIO
CABLE OR LINE WITH
+
CHARACTERISTIC IMPEDANCE R
L
+
–
V
I
V
I
R
BT
R
C
V
C
O
V
O
–
C
R
L
V
V
O
R
F
= 1 AT LOW FREQUENCIES
R
I
F
1794 F13
R
= R
1
2
R
F
BT
O
L
= 1 +
= 1 +
AT MEDIUM FREQUENCIES
R
G
R
G
V
V
R
G
=
(1 + R /R )
F
G
I
C
BIG
R
F
AT HIGH FREQUENCIES
(R || R )
C
G
1794 F12
Figure 13. Standard Cable/Line Back Termination
Figure 12. Combination Compensation
R
P2
In differential driver applications, as shown on the first
page of this data sheet, it is recommended that the gain
setting resistor be comprised of two equal value resistors
connected to a good AC ground at high frequencies. This
ensures that the feedback factor of each amplifier remains
less than 0.1 at any frequency. The midpoint of the
resistors can be directly connected by ground, with the
resulting DC gain to the VOS of the amplifiers, or just
bypassed to ground with a 1000pF or larger capacitor.
R
P1
+
–
V
I
V
R
V
O
A
BT
V
P
R
L
R
F
1794 F14
R
G
R
L
n
FOR R
1 +
=
BT
1
n
R
R
P1
F
= 1 –
R
R
+ R
(
G)(
)
P1 P2
Line Driving Back-Termination
R
/(R + R
P2 P2
)
P1
V
O
R
P1
1 + 1/n
The standard method of cable or line back-termination is
shown in Figure 13. The cable/line is terminated in its
characteristic impedance (50Ω, 75Ω, 100Ω, 135Ω, etc.).
Aback-terminationresistoralsoequaltothechararacteristic
impedance should be used for maximum pulse fidelity of
outgoing signals, and to terminate the line for incoming
signals in a full-duplex application. There are three main
drawbacks to this approach. First, the power dissipated in
the load and back-termination resistors is equal so half of
the power delivered by the amplifier is wasted in the
termination resistor. Second, the signal is halved so the
gain of the amplifer must be doubled to have the same
overall gain to the load. The increase in gain increases
noise and decreases bandwidth (which can also increase
distortion). Third, the output swing of the amplifier is
doubled which can limit the power it can deliver to the load
for a given power supply voltage.
=
–
V
I
R
+ R
P2
P1
R
R
F
1 +
(
)
G
Figure 14. Back Termination Using Postive Feedback
ofn.Toanalyzethiscircuit,firstgroundtheinput.AsRBT
RL/n, and assuming RP2>>RL we require that:
=
VA = VO (1 – 1/n) to increase the effective value of
RBT by n.
VP = VO (1 – 1/n)/(1 + RF/RG)
VO = VP (1 + RP2/RP1)
Eliminating VP, we get the following:
(1 + RP2/RP1) = (1 + RF/RG)/(1 – 1/n)
For example, reducing RBT by a factor of n = 4, and with an
amplifer gain of (1 + RF/RG) = 10 requires that RP2/RP1
= 12.3.
An alternate method of back-termination is shown in
Figure 14. Positive feedback increases the effective back-
termination resistance so RBT can be reduced by a factor
14
LT1794
W U U
APPLICATIO S I FOR ATIO
U
Note that the overall gain is increased:
Figure 17 shows a full-rate ADSL line driver incorporating
positive feedback to reduce the power lost in the back
terminationresistorsby40%yetstillmaintainstheproper
impedance match to the100Ω characteristic line imped-
ance. This circuit also reduces the transformer turns ratio
over the standard line driving approach resulting in lower
peak current requirements. With lower current and less
power loss in the back termination resistors, this driver
dissipates only 1W of power, a 30% reduction.
RP2 / R +R
VO
V
I
(
)
P2
P1
=
1+ 1/n / 1+R /R − R / R +R
) (
)
(
[
)
]
(
[
]
F
G
P1 P2
P1
A simpler method of using positive feedback to reduce the
back-termination is shown in Figure 15. In this case, the
drivers are driven differentially and provide complemen-
tary outputs. Grounding the inputs, we see there is invert-
ing gain of –RF/RP from –VO to VA
Whilethepowersavingsofpositivefeedbackareattractive
there is one important system consideration to be ad-
dressed, received signal sensitivity. The signal received
from the line is sensed across the back termination resis-
tors. With positive feedback, signals are present on both
ends of the RBT resistors, reducing the sensed amplitude.
Extra gain may be required in the receive channel to
compensate,oracompletelyseparatereceivepathmaybe
implementedthroughaseparatelinecouplingtransformer.
VA = VO (RF/RP)
and assuming RP >> RL, we require
VA = VO (1 – 1/n)
solving
RF/RP = 1 – 1/n
So to reduce the back-termination by a factor of 3 choose
RF/RP = 2/3. Note that the overall gain is increased to:
A demo board, DC306A, is available for the LT1794. This
demo board is a complete line driver with an LT1361
receiverincluded. Itallowstheevaluationofbothstandard
and active termination approaches. It also has circuitry
built in to evaluate the effects of operating with reduced
supply current.
VO/VI = (1 + RF/RG + RF/RP)/[2(1 – RF/RP)]
Using positive feedback is often referred to as active
termination.
Considerations for Fault Protection
V
+
I
V
A
R
BT
V
O
The basic line driver design, shown on the front page of
this data sheet, presents a direct DC path between the
outputs of the two amplifiers. An imbalance in the DC
biasing potentials at the noninverting inputs through
eitherafaultconditionorduringturn-onofthesystemcan
create a DC voltage differential between the two amplifier
outputs. This condition can force a considerable amount
of current to flow as it is limited only by the small valued
back-termination resistors and the DC resistance of the
transformerprimary.Thishighcurrentcanpossiblycause
the power supply voltage source to drop significantly
impacting overall system performance. If left unchecked,
the high DC current can heat the LT1794 to thermal
shutdown.
–
R
L
n
FOR R
n =
=
BT
R
R
F
F
1
R
F
1 –
R
R
R
R
G
G
L
L
R
P
R
R
P
P
R
R
R
F
F
1 +
+
R
V
O
G
P
=
V
I
R
R
F
2 1 –
(
)
P
–
+
R
BT
–V
O
1794 F15
–V
A
–V
I
Figure 15. Back Termination Using Differential Postive Feedback
15
LT1794
W U U
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APPLICATIO S I FOR ATIO
Using DC blocking capacitors, as shown in Figure 16, to
AC couple the signal to the transformer eliminates the
possibility for DC current to flow under any conditions.
These capacitors should be sized large enough to not
impairthefrequencyresponsecharacteristicsrequiredfor
the data transmission.
create fast voltage transitions themselves that can be
coupled through the transformer to the outputs of the line
driver. Several hundred volt transient signals can appear
at the primary windings of the transformer with current
intothedriveroutputslimitedonlybythebacktermination
resistors. While the LT1794 has clamps to the supply rails
at the output pins, they may not be large enough to handle
thesignificanttransientenergy. Externalclampingdiodes,
such as BAV99s, at each end of the transformer primary
help to shunt this destructive transient energy away from
the amplifier outputs.
Another important fault related concern has to do with
very fast high voltage transients appearing on the tele-
phone line (lightning strikes for example). TransZorbs®,
varistors and other transient protection devices are often
used to absorb the transient energy, but in doing so also
TransZorb is a registered trademark of General Instruments, GSI
12V
12V –12V
24.9k
SHDN
0.1µF
BAV99
+IN
+
12.7Ω
1/2
LT1794
–
1k
1:2
110Ω
110Ω
LINE
LOAD
1000pF
1k
0.1µF
–
12.7Ω
1/2
LT1794
SHDNREF
BAV99
–IN
+
–12V
12V –12V
1794 F16
Figure 16. Protecting the Driver Against Load Faults and Line Transients
16
LT1794
W
W
SI PLIFIED SCHE ATIC
(one amplifier shown)
+
V
Q9
Q10
Q13
Q17
Q3
Q4
Q7
Q8
C1
Q14
R1
Q1
Q5
+IN
C2
OUT
Q6
Q2
–IN
Q15
Q18
Q16
Q12
Q11
–
V
1794 SS
17
LT1794
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CA
6.40 – 6.60*
(.252 – .260)
4.95
(.195)
4.95
(.195)
20 1918 17 16 15 14 1312 11
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
2.74
(.108)
6.40
BSC
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0° – 8°
0.65
(.0256)
BSC
0.45 – 0.75
(.018 – .030)
0.09 – 0.20
(.0036 – .0079)
0.05 – 0.15
(.002 – .006)
FE20 (CA) TSSOP 0203
0.195 – 0.30
(.0077 – .0118)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
18
LT1794
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
SW Package
20-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.496 – 0.512*
(12.598 – 13.005)
19 18
16 14 13 12 11
20
17
15
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0.291 – 0.299**
(7.391 – 7.595)
2
3
5
7
8
9
10
1
4
6
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
0.010 – 0.029
(0.254 – 0.737)
× 45°
0° – 8° TYP
0.050
(1.270)
BSC
0.004 – 0.012
0.009 – 0.013
(0.102 – 0.305)
NOTE 1
0.016 – 0.050
(0.406 – 1.270)
(0.229 – 0.330)
0.014 – 0.019
S20 (WIDE) 1098
(0.356 – 0.482)
TYP
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LT1794
U
TYPICAL APPLICATIO
12V
24.9k
SHDN
+IN
+
13.7Ω
1/2
LT1794
–
1k
1:1.2*
1.65k
1.65k
182Ω
100Ω
LINE
1000pF
182Ω
1k
*COILCRAFT X8502-A OR EQUIVALENT
1W DRIVER POWER DISSIPATION
1.15W POWER CONSUMPTION
–
13.7Ω
SHDNREF
1/2
LT1794
–IN
+
1794 F17
–12V
Figure 17. ADSL Line Driver Using Active Termination
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
±15V Operation, 1mV V , 1µA I
LT1361
Dual 50MHz, 800V/µs Op Amp
OS
B
LTC®1563-2
LT1795
Low Cost Active RC Lowpass Filter
Dual 500mA, 50MHz Current Feedback Amplifier
Dual 100MHz, 750V/µs, 8nV/√Hz Op Amp
Dual 200mA, 700MHz Op Amp
f Up to 360kHz, Differential Operation, ±5V Supplies
C
Shutdown/Current Set Function, ADSL CO Driver
LT1813
Low Noise, Low Power Differential Receiver, 4mA/Amplifier
12V Operation, 7mA/Amplifier, ADSL Modem Line Driver
LT1886
1794fs, sn1794 LT/TP 0501 4K • PRINTED IN THE USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 2001
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