LT1871EMS-7#PBF_技术文档

LTC1871-7

High Input Voltage,

Current Mode Boost,

Flyback and SEPIC Controller

DESCRIPTION

FEATURES

The LTC^®1871-7 is a current mode, boost, ﬂyback and

SEPICcontrolleroptimizedfordriving6V-ratedMOSFETs

inhighvoltageapplications.TheLTC1871-7worksequally

well in low or high power applications and requires few

componentstoprovideacompletepowersupplysolution.

Theswitchingfrequencycanbesetwithanexternalresistor

over a 50kHz to 1MHz range, and can be synchronized to

an external clock using the MODE/SYNC pin. Burst Mode

operation at light loads, a low minimum operating supply

voltage of 6V and a low shutdown quiescent current of

10μAmaketheLTC1871-7wellsuitedforbattery-operated

systems. For applications requiring constant frequency

operation, Burst Mode operation can be defeated using

the MODE/SYNC pin. The LTC1871-7 is available in the

10-lead MSOP package.

n

Optimized for High Input Voltage Applications

n

Wide Chip Supply Voltage Range: 6V to 36V

n

Internal 7V Low Dropout Voltage Regulator

Optimized for 6V-Rated MOSFETs

n

Current Mode Control Provides Excellent

Transient Response

n

High Maximum Duty Cycle (92% Typ)

n

2% RUN Pin Threshold with 100mV Hysteresis

n

1% Internal Voltage Reference

n

Micropower Shutdown: I = 10μA

Q

n

Programmable Operating Frequency

(50kHz to 1MHz) with One External Resistor

n

Synchronizable to an External Clock Up to 1.3 × f

OSC

User-Controlled Pulse Skip or Burst Mode^®Operation

Output Overvoltage Protection

n

Can be Used in a No R

Small 10-Lead MSOP Package

™ Mode for V < 36V

SENSE

DS

PARAMETER

LTC1871-7

7.0V

LTC1871

5.2V

INTV

CC

+

–

UV

5.6V

2.1V

APPLICATIONS

4.6V

1.9V

n

Telecom Power Supplies

L, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation.

No R is a trademark of Linear Technology Corporation. All other trademarks are the

n

42V Automotive Systems

SENSE

property of their respective owners.

n

24V Industrial Controls

IP Phone Power Supplies

n

TYPICAL APPLICATION

D3

10BQ060

V

OUT

V

IN

12V

36V TO 72V

3:1

2.2μF

100V

X7R

0.4A

604k

100k

D1

47μF

16V

X5R

26.7k

T1

VP1-0076

Q1

FMMT625

9.1V

10Ω

2.2nF

RUN

SENSE

D2

4148

I

V

IN

TH

3.4k

LTC1871-7

INTV

FB

CC

M1

FDC2512

FREQ

GATE

GND

12.4k

MODE/SYNC

0.1μF

X5R

4.7μF

X5R

0.12Ω

110k

120k

18717 F01

Figure 1. Small, Nonisolated 12V Flyback Telecom Housekeeping Supply

18717fc

1

LTC1871-7

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

V Voltage ............................................... –0.3V to 36V

IN

RUN

TH

FB

FREQ

MODE/

SYNC

1

2

3

4

5

10 SENSE

INTV Voltage............................................ –0.3V to 9V

CC

I

9

8

7

6

V

IN

INTV

INTV Output Current.......................................... 50mA

CC

GATE

GND

GATE Voltage ............................ –0.3V to V

I , FB Voltages ....................................... –0.3V to 2.7V

+ 0.3V

INTVCC

MS PACKAGE

10-LEAD PLASTIC MSOP

TH

RUN Voltage ............................................... –0.3V to 7V

MODE/SYNC Voltage.................................... –0.3V to 9V

FREQ Voltage ............................................ –0.3V to 1.5V

SENSE Pin Voltage.................................... –0.3V to 36V

Operating Temperature Range (Note 2)

T

JMAX

= 125°C, θ = 120°C/W

JA

LTC1871E-7 ......................................... –40°C to 85°C

LTC1871I-7 ........................................ –40°C to 125°C

Junction Temperature (Note 3) ............................ 125°C

Storage Temperature Range................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

ORDER INFORMATION

LEAD FREE FINISH

LT1871EMS-7#PBF

LT1871IMS-7#PBF

LEAD BASED FINISH

LT1871EMS-7

TAPE AND REEL

PART MARKING

LTG4

PACKAGE DESCRIPTION

10-Lead Plastic MSOP

PACKAGE DESCRIPTION

10-Lead Plastic MSOP

TEMPERATURE RANGE

–40°C to 85°C

LT1871EMS-7#TRPBF

LT1871IMS-7#TRPBF

TAPE AND REEL

LTBTR

–40°C to 125°C

PART MARKING

LTG4

TEMPERATURE RANGE

–40°C to 85°C

LT1871EMS-7#TR

LT1871IMS-7#TR

LT1871IMS-7

LTBTR

–40°C to 125°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

The l denotes the speciﬁcations which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 8V, V_RUN= 1.5V, R_FREQ= 80k, V_MODE/SYNC= 0V, unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loop

V

Minimum Input Voltage

6

V

IN(MIN)

I-Grade (Note 2)

(Note 4)

●

I

Q

Input Voltage Supply Current

Continuous Mode

V

= 5V, V = 1.4V, V = 0.75V

550

600

1000

1100

μA

MODE/SYNC

FB

ITH

= 5V, V = 1.4V, V = 0.75V,

I-Grade (Note 2)

●

MODE/SYNC

FB

ITH

Burst Mode Operation, No Load

Shutdown Mode

V

= 0V, V = 0.2V (Note 5)

280

500

600

μA

MODE/SYNC

ITH

V

= 0V, V = 0.2V (Note 5),

MODE/SYNC

ITH

I-Grade (Note 2)

V

RUN

V

RUN

= 0V

12

25

μA

= 0V, I-Grade (Note 2)

μA

18717fc

2

LTC1871-7

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 8V, V_RUN= 1.5V, R_FREQ= 80k, V_MODE/SYNC= 0V, unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

V

Rising RUN Input Threshold Voltage

Falling RUN Input Threshold Voltage

1.348

1.248

V

RUN

–

1.223

1.198

1.273

1.298

V

●

V

RUN Pin Input Threshold Hysteresis

50

35

100

5

150

175

60

mV

nA

RUN(HYST)

I-Grade (Note 2)

I

RUN Input Current

Feedback Voltage

RUN

V

ITH

= 0.2V (Note 5)

1.218

1.212

1.230

1.242

1.248

V

FB

●

V

= 0.2V (Note 5), I-Grade (Note 2)

= 0.2V (Note 5)

1.205

1.255

60

V

nA

ITH

I

FB Pin Input Current

Line Regulation

18

FB

ITH

ΔV

6V ≤ V ≤ 30V

0.002

–0.1

0.02

%/V

%

FB

IN

6V ≤ V ≤ 30V, I-Grade (Note 2)

●

IN

ΔV

Load Regulation

V

= 0V, V = 0.5V to 0.9V (Note 5)

–1

FB

MODE/SYNC

ITH

V

= 0V, V = 0.5V to 0.9V (Note 5)

–0.1

%

ITH

MODE/SYNC

ITH

I-Grade (Note 2)

– V in Percent

FB(NOM)

ΔV

ΔFB Pin, Overvoltage Lockout

V

2.5

6

10

%

μmho

V

FB(OV)

g

m

Error Ampliﬁer Transconductance

I

TH

Pin Load = 5μA (Note 5)

600

0.3

150

V

Burst Mode Operation I Pin Voltage

Falling I Voltage (Note 5)

ITH(BURST)

SENSE(MAX)

TH

Maximum Current Sense Input Threshold

Duty Cycle < 20%

120

100

180

200

70

mV

μA

Duty Cycle < 20%, I-Grade (Note 2)

●

I

SENSE Pin Current (GATE High)

SENSE Pin Current (GATE Low)

V

SENSE

V

SENSE

= 0V

35

SENSE(ON)

= 30V

0.1

5

μA

SENSE(OFF)

Oscillator

f

Oscillator Frequency

R

= 80k

250

50

300

350

kHz

%

OSC

FREQ

= 80k, I-Grade (Note 2)

●

FREQ

Oscillator Frequency Range

Maximum Duty Cycle

1000

97

I-Grade (Note 2)

50

D

87

92

MAX

87

98.5

1.30

%

f

Recommended Maximum Synchronized

Frequency Ratio

f

= 300kHz (Note 6)

1.25

25

SYNC/ OSC

OSC

= 300kHz (Note 6), I-Grade (Note 2)

t

MODE/SYNC Minimum Input Pulse Width

MODE/SYNC Maximum Input Pulse Width

Low Level MODE/SYNC Input Voltage

V

SYNC

V

SYNC

= 0V to 5V

ns

V

SYNC(MIN)

0.8/f

SYNC(MAX)

OSC

V

0.3

IL(MODE)

IH(MODE)

I-Grade (Note 2)

●

V

High Level MODE/SYNC Input Voltage

1.2

V

R

MODE/SYNC Input Pull-Down Resistance

Nominal FREQ Pin Voltage

50

kꢀ

V

MODE/SYNC

V

0.62

FREQ

Low Dropout Regulator

INTV Regulator Output Voltage

V

= 8V

6.5

7

7.5

V

INTVCC

CC

IN

= 8V, I-Grade (Note 2)

●

18717fc

3

LTC1871-7

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 8V, V_RUN= 1.5V, R_FREQ= 80k, V_MODE/SYNC= 0V, unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

Rising INTV

MIN

TYP

MAX

UNITS

UVLO

INTVCC Undervoltage Lockout Threshold

5.6

4.6

1.0

V

CC

Falling INTV

CC

UVLO Hysteresis

ΔV

INTVCC

INTV Regulator Line Regulation

8V ≤ V ≤ 15V

8

25

mV

CC

IN

ΔV

IN1

ΔV

INTVCC

INTV Regulator Line Regulation

15V ≤ V ≤ 30V

70

200

mV

CC

IN

ΔV

IN2

V

INTV Load Regulation

0 ≤ I

≤ 20mA, V = 8V

–2

–0.2

280

%

LDO(LOAD)

DROPOUT

CC

INTVCC

IN

INTV Regulator Dropout Voltage

V

IN

= 6V, INTV Load = 20mA

mV

CC

GATE Driver

t

GATE Driver Output Rise Time

GATE Driver Output Fall Time

C = 3300pF (Note 7)

17

8

100

ns

r

f

L

C = 3300pF (Note 7)

L

Note 4: The dynamic input supply current is higher due to power MOSFET

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

gate charging (Q • f ). See Applications Information.

G

OSC

Note 5: The LTC1871-7 is tested in a feedback loop that servos V to the

FB

reference voltage with the I pin forced to a voltage between 0V and 1.4V

TH

(the no load to full load operating voltage range for the I pin is 0.3V to

1.23V).

Note 6: In a synchronized application, the internal slope compensation

gain is increased by 25%. Synchronizing to a signiﬁcantly higher ratio will

reduce the effective amount of slope compensation, which could result in

subharmonic oscillation for duty cycles greater than 50%.

Note 2: The LTC1871E-7 is guaranteed to meet performance speciﬁcations

from 0°C to 70°C junction temperature. Speciﬁcations over the –40°C

to 85°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC1871I-7 is guaranteed over the full –40°C to 125°C operating junction

temperature range.

TH

Note 3: T is calculated from the ambient temperature T and power

J

A

Note 7: Rise and fall times are measured at 10% and 90% levels.

dissipation P according to the following formula:

D

T = T + (P • 120°C/W)

J

A

D

TYPICAL PERFORMANCE CHARACTERISTICS

FB Voltage vs Temp

FB Voltage Line Regulation

FB Pin Current vs Temperature

1.25

1.24

1.23

1.22

1.21

60

50

40

30

20

10

0

1.231

1.230

1.229

50 75

TEMPERATURE (°C)

–50 –25

0

25

100 125 150

0

5

10

15

V

20

(V)

25

30

35

–50

0

25 50 75 100 125 150

TEMPERATURE (°C)

–25

IN

18717 G01

18717 G02

18717 G03

18717fc

4

LTC1871-7

TYPICAL PERFORMANCE CHARACTERISTICS

Shutdown Mode I_Qvs V_IN

Shutdown Mode I_Qvs Temperature

Burst Mode I_Qvs V_IN

600

500

400

300

200

100

0

20

15

10

5

30

20

10

V

= 8V

IN

0

10

20

(V)

30

40

30

0

10

20

(V)

40

150

40

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

V

IN

18717 G06

18717 G04

18717 G05

Gate Drive Rise and

Fall Time vs C_L

Burst Mode I_Qvs Temperature

Dynamic I_Qvs Frequency

500

400

300

200

100

0

60

50

40

30

20

10

0

18

16

14

12

10

8

C

= 3300pF

L

I

= 600μA + Qg • f

Q(TOT)

RISE TIME

FALL TIME

6

4

2

0

–50

50

100 125

0

4000 6000 8000 10000 12000

(pF)

–25

0

25

75

2000

0

200

400

FREQUENCY (kHz)

1000 1200

600

800

TEMPERATURE (°C)

C

L

18717 G07

18717 G09

18717 G08

RUN Thresholds vs V_IN

RUN Thresholds vs Temperature

R_Tvs Frequency

1000

100

10

1.5

1.4

1.3

1.40

1.35

1.30

1.25

1.20

1.2

30

0

10

20

(V)

50 75

25

TEMPERATURE (°C)

200

400

600 700 800

1000

900

–50 –25

0

100 125 150

0

100

300

500

V

FREQUENCY (kHz)

IN

18717 G12

18717 G10

18717 G11

18717fc

5

LTC1871-7

TYPICAL PERFORMANCE CHARACTERISTICS

Maximum Sense Threshold

vs Temperature

Frequency vs Temperature

SENSE Pin Current vs Temperature

325

320

315

310

305

300

295

290

285

280

275

35

30

25

160

155

150

145

GATE HIGH

SENSE

V

= 0V

140

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

–50

50

100 125

–50

50

100 125

150

–25

0

25

75

150

–25

0

25

75

TEMPERATURE (°C)

18717 G14

18717 G13

18717 G15

INTV_CCDropout Voltage

vs Current, Temperature

INTV_CCLoad Regulation

INTV_CCLine Regulation

500

450

400

350

300

250

200

150

100

50

7.2

7.1

7.0

V

= 8V

IN

150°C

7.0

125°C

75°C

25°C

6.9

6.8

0°C

–50°C

6.9

0

40

0

10 20 30

50 60 70 80

25 30

0

5

10 15 20

(V)

35 40

0

5

10

15

20

V

INTV LOAD (mA)

CC

IN

CC

18717 G16

18717 G17

18717 G18

PIN FUNCTIONS

RUN (Pin 1): The RUN pin provides the user with an

accurate means for sensing the input voltage and pro-

gramming the start-up threshold for the converter. The

falling RUN pin threshold is nominally 1.248V and the

comparatorhas100mVofhysteresisfornoiseimmunity.

When the RUN pin is below this input threshold, the IC

I

(Pin 2): Error Ampliﬁer Compensation Pin. The

TH

current comparator input threshold increases with this

control voltage. Nominal voltage range for this pin is 0V

to 1.40V.

FB(Pin3):Receivesthefeedbackvoltagefromtheexternal

resistor divider across the output. Nominal voltage for

this pin in regulaton is 1.230V.

is shut down and the V supply current is kept to a low

IN

value (typ 10μA). The Absolute Maximum Rating for the

voltage on this pin is 7V.

FREQ (Pin 4): A resistor from the FREQ pin to ground

programstheoperatingfrequencyofthechip.Thenominal

voltage at the FREQ pin is 0.6V.

18717fc

6

LTC1871-7

PIN FUNCTIONS

MODE/SYNC (Pin 5): This input controls the operating

mode of the converter and allows for synchronizing the

operating frequency to an external clock. If the MODE/

SYNC pin is connected to ground, Burst Mode operation

a minimum of 4.7μF low ESR tantalum or ceramic ca-

pacitor. This 7V regulator has an undervoltage lockout

circuit with 5.6V and 4.6V rising and falling thresholds,

respectively.

isenabled.IftheMODE/SYNCpinisconnectedtoINTV ,

CC

V (Pin 9): Main Supply Pin. Must be closely decoupled

IN

or if an external logic-level synchronization signal is ap-

plied to this input, Burst Mode operation is disabled and

the IC operates in a continuous mode.

to ground.

SENSE (Pin 10): The Current Sense Input for the Control

Loop. Connect this pin to a resistor in the source of the

powerMOSFET. Alternatively, theSENSEpinmaybecon-

nected to the drain of the power MOSFET, in applications

GND (Pin 6): Ground Pin.

GATE (Pin 7): Gate Driver Output.

wherethemaximumV islessthan36V.Internalleading

DS

I

NTV (Pin 8): The Internal 7V Regulator Output. The

CC

edge blanking is provided for both sensing methods.

gate driver and control circuits are powered from this

voltage. Decouple this pin locally to the IC ground with

BLOCK DIAGRAM

RUN

+

–

1

BIAS AND

START-UP

CONTROL

SLOPE

COMPENSATION

C2

1.248V

V

IN

FREQ

4

V-TO-I

OV

OSC

9

0.6V

INTV

CC

I

OSC

MODE/SYNC

5

GATE

7

PWM LATCH

LOGIC

85mV

S

Q

R

50k

–

+

1.230V

GND

+

BURST

COMPARATOR

CURRENT

COMPARATOR

SENSE

10

+

–

0.30V

+

–

FB

C1

EA

–

+

3

g

m

1.230V

I

TH

2

V-TO-I

SLOPE

R

LOOP

INTV

8

I

CC

LOOP

7V

–

1.230V

TO

LDO

UV

1.230V

GND

START-UP

CONTROL

BIAS

V

6

REF

+

18717 BD

5.6V UP

4.6V DOWN

V

IN

18717fc

7

LTC1871-7

OPERATION

Main Control Loop

The nominal operating frequency of the LTC1871-7 is

programmedusingaresistorfromtheFREQpintoground

and can be controlled over a 50kHz to 1000kHz range. In

addition, the internal oscillator can be synchronized to

an external clock applied to the MODE/SYNC pin and can

be locked to a frequency between 100% and 130% of its

nominal value. When the MODE/SYNC pin is left open, it

is pulled low by an internal 50k resistor and Burst Mode

operation is enabled. If this pin is taken above 2V or an

externalclockisapplied, BurstModeoperationisdisabled

and the IC operates in continuous mode. With no load (or

an extremely light load), the controller will skip pulses in

order to maintain regulation and prevent excessive output

ripple.

The LTC1871-7 is a constant frequency, current mode

controller for DC/DC boost, SEPIC and ﬂyback converter

applications. With the LTC1871-7 the current control loop

can be closed by sensing the voltage drop either across

the power MOSFET switch or across a discrete sense

resistor, as shown in Figure 2.

D

L

V

C

IN

OUT

V

IN

+

SENSE

V

SW

GATE

GND

TheRUNpincontrolswhethertheICisenabledorisinalow

current shutdown state. A micropower 1.248V reference

and comparator C2 allow the user to program the supply

voltage at which the IC turns on and off (comparator C2

has 100mV of hysteresis for noise immunity). With the

RUN pin below 1.248V, the chip is off and the input supply

current is typically only 10μA.

GND

2a. SENSE Pin Connection for

Maximum Efﬁciency (V < 36V)

SW

D

L

V

IN

OUT

V

SW

V

IN

GATE

+

C

OUT

An overvoltage comparator OV senses when the FB pin

exceeds the reference voltage by 6.5% and provides a

reset pulse to the main RS latch. Because this RS latch is

reset-dominant, the power MOSFET is actively held off for

the duration of an output overvoltage condition.

SENSE

GND

R

S

GND

18717 F02

2b. SENSE Pin Connection for Precise

Control of Peak Current or for V > 36V

SW

The LTC1871-7 can be used either by sensing the voltage

drop across the power MOSFET or by connecting the

SENSE pin to a conventional shunt resistor in the source

of the power MOSFET, as shown in Figure 2. Sensing the

voltage across the power MOSFET maximizes converter

efﬁciency and minimizes the component count, but limits

theoutputvoltagetothemaximumratingforthispin(36V).

By connecting the SENSE pin to a resistor in the source

of the power MOSFET, the user is able to program output

voltages signiﬁcantly greater than 36V.

Figure 2. Using the SENSE Pin On the LTC1871-7

For circuit operation, please refer to the Block Diagram of

theICandFigure1.Innormaloperation,thepowerMOSFET

is turned on when the oscillator sets the PWM latch and

is turned off when the current comparator C1 resets the

latch. The divided-down output voltage is compared to an

internal 1.230V reference by the error ampliﬁer EA, which

outputs an error signal at the I pin. The voltage on the

TH

I

TH

pin sets the current comparator C1 input threshold.

Programming the Operating Mode

When the load current increases, a fall in the FB voltage

relative to the reference voltage causes the I pin to rise,

For applications where maximizing the efﬁciency at very

light loads (e.g., <100μA) is a high priority, the current in

theoutputdividercouldbedecreasedtoafewmicroamps

and Burst Mode operation should be applied (i.e., the

TH

which causes the current comparator C1 to trip at a higher

peak inductor current value. The average inductor current

will therefore rise until it equals the load current, thereby

maintaining output regulation.

MODE/SYNC pin should be connected to ground).

18717fc

8

LTC1871-7

OPERATION

In applications where ﬁxed frequency operation is more

critical than low current efﬁciency, or where the lowest

outputrippleisdesired,pulse-skipmodeoperationshould

be used and the MODE/SYNC pin should be connected

inductor current is 20% of its maximum value) followed

by long periods of sleep will be observed, thereby greatly

improvingconverterefﬁciency.Oscilloscopewaveformsil-

lustrating Burst Mode operation are shown in Figure 3.

to the INTV pin. This allows discontinuous conduction

CC

Pulse-Skip Mode Operation

mode (DCM) operation down to near the limit deﬁned

by the chip’s minimum on-time (about 175ns). Below

this output current level, the converter will begin to skip

cycles in order to maintain output regulation. Figures 3

and 4 show the light load switching waveforms for Burst

Mode and pulse-skip mode operation for the converter

in Figure 1.

With the MODE/SYNC pin tied to a DC voltage above 2V,

Burst Mode operation is disabled. The internal, 0.525V

buffered I burst clamp is removed, allowing the I

TH

pin to directly control the current comparator from no

load to full load. With no load, the I pin is driven below

TH

0.30V, the power MOSFET is turned off and sleep mode

is invoked. Oscilloscope waveforms illustrating this mode

of operation are shown in Figure 4.

Burst Mode Operation

Burst Mode operation is selected by leaving the MODE/

SYNC pin unconnected or by connecting it to ground. In

normaloperation,therangeontheI_THpincorrespondingto

no load to full load is 0.30V to 1.2V. In Burst Mode opera-

tion, if the error ampliﬁer EA drives the I_THvoltage below

0.525V, the buffered I_THinput to the current comparator

C1 will be clamped at 0.525V (which corresponds to 25%

of maximum load current). The inductor current peak is

then held at approximately 30mV divided by the power

MOSFET R_DS(ON). If the I_THpin drops below 0.30V, the

BurstModecomparatorB1willturnoffthepowerMOSFET

and scale back the quiescent current of the IC to 250μA

(sleep mode). In this condition, the load current will be

supplied by the output capacitor until the I_THvoltage rises

above the 50mV hysteresis of the burst comparator. At

light loads, short bursts of switching (where the average

When an external clock signal drives the MODE/SYNC

pin at a rate faster than the chip’s internal oscillator, the

oscillatorwillsynchronizetoit.Inthissynchronizedmode,

Burst Mode operation is disabled. The constant frequency

associated with synchronized operation provides a more

controlled noise spectrum from the converter, at the ex-

pense of overall system efﬁciency of light loads.

When the oscillator’s internal logic circuitry detects a

synchronizing signal on the MODE/SYNC pin, the in-

ternal oscillator ramp is terminated early and the slope

compensation is increased by approximately 30%. As

a result, in applications requiring synchronization, it is

recommended that the nominal operating frequency of

the IC be programmed to be about 75% of the external

clock frequency. Attempting to synchronize to too high an

MODE/SYNC = 0V

(Burst Mode OPERATION)

MODE/SYNC = INTV

CC

(PULSE SKIP MODE)

V

OUT

V

OUT

50mV/DIV

I

L

I

5A/DIV

L

5A/DIV

18717 F03

18717 F04

10μs/DIV

2μs/DIV

Figure 3. LTC1871-7 Burst Mode Operation

(MODE/SYNC = 0V) at Low Output Current

Figure 4. LTC1871-7 Low Output Current Operation with

Burst Mode Operation Disabled (MODE/SYNC = INTV_CC

)

18717fc

9

LTC1871-7

OPERATION

external frequency (above 1.3f ) can result in inadequate

logic circuitry within the LTC1871-7, as shown in Figure 7.

O

slopecompensationandpossiblesubharmonicoscillation

The INTV regulator can supply up to 50mA and must be

CC

(or jitter).

bypassed to ground immediately adjacent to the IC pins

with a minimum of 4.7μF tantalum or ceramic capacitor.

Good bypassing is necessary to supply the high transient

currents required by the MOSFET gate driver.

The external clock signal must exceed 2V for at least 25ns,

and should have a maximum duty cycle of 80%, as shown

in Figure 5. The MOSFET turn on will synchronize to the

rising edge of the external clock signal.

The LTC1871-7 contains an undervoltage lockout circuit

whichprotectstheexternalMOSFETfromswitchingatlow

gate-to-source voltages. This undervoltage circuit senses

Programming the Operating Frequency

the INTV voltage and has a 5.6V rising threshold and a

CC

The choice of operating frequency and inductor value is

a tradeoff between efﬁciency and component size. Low

frequency operation improves efﬁciency by reducing

MOSFET and diode switching losses. However, lower

frequency operation requires more inductance for a given

amount of load current.

4.6V falling threshold.

For input voltages that don’t exceed 8V (the absolute

maximumratingforINTV is9V),theinternallowdropout

CC

regulator in the LTC1871-7 is redundant and the INTV

CC

pin can be shorted directly to the V pin. With the INTV

IN

CC

pin shorted to V , however, the divider that programs the

IN

TheLTC1871-7usesaconstantfrequencyarchitecturethat

can be programmed over a 50kHz to 1000kHz range with

a single external resistor from the FREQ pin to ground, as

shown in Figure 1. The nominal voltage on the FREQ pin is

0.6V, and the current that ﬂows into the FREQ pin is used

to charge and discharge an internal oscillator capacitor. A

regulated INTV voltage will draw 14μA of current from

CC

theinputsupply, eveninshutdownmode. Forapplications

that require the lowest shutdown mode input supply cur-

rent, do not connect the INTV pin to V . Regardless

CC

IN

of whether the INTV pin is shorted to V or not, it is

CC

IN

always necessary to have the driver circuitry bypassed

graph for selecting the value of R for a given operating

frequency is shown in Figure 6.

T

with a 4.7μF ceramic capacitor to ground immediately

adjacent to the INTV and GND pins.

CC

INTV Regulator Bypassing and Operation

CC

In an actual application, most of the IC supply current is

used to drive the gate capacitance of the power MOSFET.

As a result, high input voltage applications in which a

large power MOSFET is being driven at high frequencies

An internal, P-channel low dropout voltage regulator

produces the 7V supply which powers the gate driver and

2V TO 7V

1000

100

10

MODE/

SYNC

t

= 25ns

MIN

0.8T

T

T = 1/f

O

GATE

D = 40%

I

L

100 200

400

600 700 800

1000

900

0

300

500

FREQUENCY (kHz)

18717 F05

18717 F06

Figure 5. MODE/SYNC Clock Input and Switching

Waveforms for Synchronized Operation

Figure 6. Timing Resistor (R_T) Value

18717fc

10

LTC1871-7

OPERATION

INPUT

SUPPLY

6V TO 30V

V

IN

–

+

1.230V

R2

P-CH

7V

C

IN

R1

INTV

CC

C

4.7μF

X5R

VCC

6V-RATED

POWER

GATE

GND

LOGIC

DRIVER

M1

MOSFET

GND

PLACE AS CLOSE AS

POSSIBLE TO DEVICE PINS

18717 F07

Figure 7. Bypassing the LDO Regulator and Gate Driver Supply

can cause the LTC1871-7 to exceed its maximum junc-

tion temperature rating. The junction temperature can be

estimated using the following equations:

Thisdemonstrateshowsigniﬁcantthegatechargecurrent

can be when compared to the static quiescent current in

the IC.

I

≈ I + f • Q

G

To prevent the maximum junction temperature from being

exceeded, the input supply current must be checked when

Q(TOT)

Q

P = V • (I + f • Q )

IC

IN

Q

G

operating in a continuous mode at high V . A tradeoff

IN

T = T + P • R

between the operating frequency and the size of the power

MOSFETmayneedtobemadeinordertomaintainareliable

IC junction temperature. Prior to lowering the operating

frequency, however, be sure to check with power MOSFET

J

A

IC

TH(JA)

The total quiescent current I

consists of the static

Q(TOT)

supply current (I ) and the current required to charge and

Q

dischargethegateofthepowerMOSFET.The10-pinMSOP

manufacturers for their latest-and-greatest low Q , low

G

package has a thermal resistance of R

= 120°C/W.

TH(JA)

R

devices. Power MOSFET manufacturing tech-

DS(ON)

As an example, consider a power supply with V =10V.

IN

nologies are continually improving, with newer and better

The switching frequency is 200kHz, and the maximum

performance devices being introduced almost yearly.

ambient temperature is 70°C. The power MOSFET chosen

is the FDS3670(Fairchild), which has a maximum R

Output Voltage Programming

DS(ON)

of 35mꢀ (at room temperature) and a maximum total

gate charge of 80nC (the temperature coefﬁcient of the

gate charge is low).

The output voltage is set by a resistor divider according

to the following formula:

R2

R1

ꢀ

ꢁ

ꢃ

ꢄ

I

= 600μA + 80nC • 200kHz = 16.6mA

Q(TOT)

V =1.230V • 1+

ꢂ

O

ꢅ

P = 10V • 16.6mA = 166mW

IC

T = 70°C + 120°C/W • 166mW = 89.9°C

The external resistor divider is connected to the output

as shown in Figure 1, allowing remote voltage sensing.

J

T

= 19.9°C

JRISE

18717fc

11

LTC1871-7

OPERATION

The resistors R1 and R2 are typically chosen so that the

error caused by the current ﬂowing into the FB pin dur-

ing normal operation is less than 1% (this translates to a

maximum value of R1 of about 250k).

The turn-on and turn-off input voltage thresholds are

programmed using a resistor divider according to the

following formulas:

R2

R1

ꢀ

ꢁ

ꢃ

ꢄ

V

=1.248V • 1+

ꢂ

ꢅ

IN(OFF)

Programming Turn-On and Turn-Off Thresholds with

the RUN Pin

R2

R1

ꢀ

ꢁ

ꢃ

ꢄ

V

=1.348V • 1+

ꢂ

ꢅ

IN(ON)

TheLTC1871-7containsanindependent,micropowervolt-

agereferenceandcomparatordetectioncircuitthatremains

active even when the device is shut down, as shown in

Figure 8. This allows users to accurately program an input

voltage at which the converter will turn on and off. The

falling threshold voltage on the RUN pin is equal to the

internal reference voltage of 1.248V. The comparator has

100mV of hysteresis to increase noise immunity.

The resistor R1 is typically chosen to be less than 1M.

For applications where the RUN pin is only to be used as

alogicinput,theusershouldbeawareofthe7VAbsolute

Maximum Rating for this pin! The RUN pin can be con-

nectedtotheinputvoltagethroughanexternal1Mresistor,

as shown in Figure 8c, for “always on” operation.

V

IN

+

R2

R1

RUN

COMPARATOR

RUN

+

BIAS AND

START-UP

CONTROL

6V

INPUT

SUPPLY

–

OPTIONAL

FILTER

CAPACITOR

1.248V

μPOWER

REFERENCE

GND

–

18717 F8a

Figure 8a. Programming the Turn-On and Turn-Off Thresholds Using the RUN Pin

V

IN

+

R2

1M

RUN

GND

COMPARATOR

+

–

RUN

COMPARATOR

6V

INPUT

SUPPLY

RUN

+

–

6V

1.248V

EXTERNAL

LOGIC CONTROL

1.248V

–

18717 F08b

18717 F08c

Figure 8b. On/Off Control Using External Logic

Figure 8c. External Pull-Up Resistor On

RUN Pin for “Always On” Operation

18717fc

12

LTC1871-7

APPLICATIONS INFORMATION

Application Circuits

The maximum duty cycle capability of the LTC1871-7 is

typically 92%. This allows the user to obtain high output

voltages from low input supply voltages.

AbasicLTC1871-7applicationcircuitisshowninFigure9.

External component selection is driven by the characteris-

tics of the load and the input supply. The ﬁrst topology to

be analyzed will be the boost converter, followed by SEPIC

(single-ended primary inductance converter).

Boost Converter: The Peak and Average Input Currents

ThecontrolcircuitintheLTC1871-7ismeasuringtheinput

current typically using a sense resistor in the MOSFET

source, so the output current needs to be reﬂected back

to the input in order to dimension the power MOSFET

properly. Based on the fact that, ideally, the output power

is equal to the input power, the maximum average input

current is:

Boost Converter: Duty Cycle Considerations

Foraboostconverteroperatinginacontinuousconduction

mode (CCM), the duty cycle of the main switch is:

ꢀ

_INꢃ

V_O+ V_D– V

D=

ꢂ

ꢅ

I_O(MAX)

V_O+ V_D

ꢁ

ꢄ

I

=

IN(MAX)

1–D_MAX

Thepeak input current is:

where V is the forward voltage of the boost diode. For

D

converters where the input voltage is close to the output

voltage,thedutycycleislowandforconvertersthatdevelop

a high output voltage from a low voltage input supply,

the duty cycle is high. The maximum output voltage for a

boost converter operating in CCM is:

I_O(MAX)

ꢀ

ꢁ

ꢂ

ꢄ

ꢅ

I

= 1+

•

ꢃ

ꢆ

IN(PEAK)

2

1–D_MAX

The maximum duty cycle, D

, should be calculated at

MAX

minimum V .

V

IN

IN(MIN)

V_O(MAX)

=

– V_D

1–D

(

)

MAX

V

IN

8V TO 28V

C

+

C

*

IN2

IN1

R3

10μF

50V

X5R

×2

L1

560μF

50V

1M

6.8μH

f = 250kHz

1

2

10

9

RUN

SENSE

D1

V

OUT

42V

I

V

IN

TH

1.5A

R

C

LTC1871-7

INTV

24k

C

3

4

5

8

7

6

OUT2

C

OUT1

FB

+

CC

10μF

C

C1

68μF

100V

×2

50V

X5R

×2

2.2nF

FREQ

GATE

GND

M1

C

4.7μF

X5R

VCC

MODE/SYNC

C

R

SENSE

0.005Ω

1W

C2

R

T

100k

1%

100pF

GND

R2

412k

1%

R1

12.4k

1%

18717 F09

C

:

SANYO 50MV560AXL (*RECOMMENDED FOR LAB EVALUATION

FOR SUPPLY LEAD LENGTHS GREATER THAN A FEW INCHES)

TDK C5750X5R1H106M

D1: DIODES INC B360B

L1: COOPER DR127-6R8

M1: SILICONIX/VISHAY Si7370DP

IN1

IN2

C

: SANYO 100CV68FS

OUT1

OUT2

: TDK C5750X5R1H106M

Figure 9. A High Efﬁciency 42V, 1.5A Automotive Boost Converter

18717fc

13

LTC1871-7

APPLICATIONS INFORMATION

χ

Boost Converter: Ripple Current ΔI and the ‘ ’ Factor

applications requiring a step-up converter that is short-

circuit protected, please refer to the applications section

covering SEPIC converters.

L

χ

The constant ‘ ’ in the equation above represents the

percentage peak-to-peak ripple current in the inductor,

relative to its maximum value. For example, if 30% ripple

The minimum required saturation current of the inductor

can be expressed as a function of the duty cycle and the

load current, as follows:

χ

current is chosen, then = 0.30, and the peak current is

15% greater than the average.

For a current mode boost regulator operating in CCM,

slope compensation must be added for duty cycles above

50% in order to avoid subharmonic oscillation. For the

LTC1871-7, thisrampcompensationisinternal. Havingan

internally ﬁxed ramp compensation waveform, however,

does place some constraints on the value of the inductor

and the operating frequency. If too large an inductor is

I_O(MAX)

ꢁ

ꢂ

ꢃ

ꢅ

ꢆ

I_L(SAT)ꢀ 1+

•

ꢄ

ꢇ

2

1–D_MAX

The saturation current rating for the inductor should be

checkedattheminimuminputvoltage(whichresultsinthe

highest inductor current) and maximum output current.

used, theresultingcurrentramp(ΔI )willbesmallrelative

L

Boost Converter: Operating in Discontinuous Mode

to the internal ramp compensation (at duty cycles above

50%), and the converter operation will approach voltage

mode(rampcompensationreducesthegainofthecurrent

loop). If too small an inductor is used, but the converter

is still operating in CCM (near critical conduction mode),

the internal ramp compensation may be inadequate to

prevent subharmonic oscillation. To ensure good current

mode gain and avoid subharmonic oscillation, it is recom-

mended that the ripple current in the inductor fall in the

range of 20% to 40% of the maximum average current.

For example, if the maximum average input current is

Discontinuous mode operation occurs when the load cur-

rent is low enough to allow the inductor current to run out

during the off-time of the switch, as shown in Figure 10.

Oncetheinductorcurrentisnearzero,theswitchanddiode

capacitancesresonatewiththeinductancetoformdamped

ringing at 1MHz to 10MHz. If the off-time is long enough,

the drain voltage will settle to the input voltage.

Depending on the input voltage and the residual energy

in the inductor, this ringing can cause the drain of the

power MOSFET to go below ground where it is clamped

by the body diode. This ringing is not harmful to the IC

and it has not been shown to contribute signiﬁcantly to

EMI. Any attempt to damp it with a snubber will degrade

the efﬁciency.

χ

1A, choose a ΔI between 0.2A and 0.4A, and a value ‘ ’

L

between 0.2 and 0.4.

Boost Converter: Inductor Selection

Givenanoperatinginputvoltagerange,andhavingchosen

the operating frequency and ripple current in the inductor,

the inductor value can be determined using the following

equation:

OUTPUT

VOLTAGE

200mV/DIV

INDUCTOR

CURRENT

1A/DIV

V

IN(MIN)

L =

•D_MAX

ꢀI_L• f

where:

MOSFET

DRAIN

VOLTAGE

20V/DIV

I_O(MAX)

ꢀI_L= ꢁ •

1–D_MAX

18717 F10

1μs/DIV

Remember that boost converters are not short-circuit

protected. Under a shorted output condition, the inductor

current is limited only by the input supply capability. For

Figure 10. Discontinuous Mode Waveforms

for the Converter Shown in Figure 9

18717fc

14

LTC1871-7

APPLICATIONS INFORMATION

Sense Resistor Selection

The gate drive voltage is set by the 7V INTV low drop

CC

regulator. Consequently, 6V rated MOSFETs are required

During the switch on-time, the control circuit limits the

maximum voltage drop across the sense resistor to about

150mV (at low duty cycle). The peak inductor current

in most high voltage LTC1871-7 applications.

Pay close attention to the BV

speciﬁcations for the

DSS

is therefore limited to 150mV/R

. The relationship

MOSFETs relative to the maximum actual switch voltage

in the application. The switch node can ring during the

turn-off of the MOSFET due to layout parasitics. Check the

switching waveforms of the MOSFET directly across the

drainandsourceterminalsusingtheactualPCboardlayout

(not just on a lab breadboard!) for excessive ringing.

SENSE

between the maximum load current, duty cycle and the

sense resistor R is:

SENSE

1–D_MAX

R

_SENSEꢀ V_SENSE(MAX)•

ꢁ

ꢂ

ꢃ

ꢅ

ꢇ

1+

•I

O(MAX)

ꢄ

ꢆ

2

TheV

termistypically150mVatlowdutycycle,

SENSE(MAX)

Calculating Power MOSFET Switching and Conduction

Losses and Junction Temperatures

and is reduced to about 100mV at a duty cycle of 92% due

to slope compensation, as shown in Figure 11.

In order to calculate the junction temperature of the power

MOSFET,thepowerdissipatedbythedevicemustbeknown.

This power dissipation is a function of the duty cycle, the

load current and the junction temperature itself (due to

It is worth noting that the 1 – D

relationship between

MAX

I

andR

cancauseboostconverterswithawide

O(MAX)

SENSE

input range to experience a dramatic range of maximum

input and output current. This should be taken into con-

sideration in applications where it is important to limit the

maximum current drawn from the input supply.

the positive temperature coefﬁcient of its R ). As a

DS(ON)

result, some iterative calculation is normally required to

determine a reasonably accurate value. Care should be

taken to ensure that the converter is capable of delivering

therequiredloadcurrentoveralloperatingconditions(line

voltage and temperature), and for the worst-case speci-

200

150

100

50

ﬁcations for V

and the R

of the MOSFET

SENSE(MAX)

listed in the manufacturer’s data sheet.

DS(ON)

The power dissipated by the MOSFET in a boost converter

is:

2

I

ꢀ

_O(MAX)ꢃ

P_FET

=

•R_DS(ON)•D •ꢆ_T

ꢅ

ꢂ

1–D

ꢁ

ꢄ

0

0.2

0.4

0.5

0.8

1.0

I_O(MAX)

DUTY CYCLE

2

+k • V_O

•

•C_RSS• f

18717 F11

1–D

(

)

Figure 11. Maximum SENSE Threshold Votlage vs Duty Cycle

2

The ﬁrst term in the equation above represents the I R

losses in the device, and the second term, the switching

losses.Theconstant,k=1.7,isanempiricalfactorinversely

related to the gate drive current and has the dimension

Boost Converter: Power MOSFET Selection

Important parameters for the power MOSFET include the

drain-to-sourcebreakdownvoltage(BV ),thethreshold

DSS

DS(ON)

of 1/current. The ρ term accounts for the temperature

T

voltage(V

),theon-resistance(R

)versusgate-

GS(TH)

coefﬁcientoftheR

oftheMOSFET, whichistypically

DS(ON)

to-source voltage, the gate-to-source and gate-to-drain

0.4%/°C. Figure 12 illustrates the variation of normalized

over temperature for a typical power MOSFET.

charges (Q and Q , respectively), the maximum drain

GS

D(MAX)

and R

GD

R

DS(ON)

current (I

) and the MOSFET’s thermal resistances

(R

).

TH(JA)

TH(JC)

18717fc

15

LTC1871-7

APPLICATIONS INFORMATION

2.0

The R

to be used in this equation normally includes

TH(JA)

the R

for the device plus the thermal resistance from

TH(JC)

the board to the ambient temperature in the enclosure.

1.5

1.0

0.5

0

Remember to keep the diode lead lengths short and to

observe proper switch-node layout (see Board Layout

Checklist) to avoid excessive ringing and increased dis-

sipation.

Boost Converter: Output Capacitor Selection

Contributions of ESR (equivalent series resistance), ESL

(equivalent series inductance) and the bulk capacitance

mustbeconsideredwhenchoosingthecorrectcomponent

for a given output ripple voltage. The effects of these three

parameters (ESR, ESL and bulk C) on the output voltage

ripple waveform are illustrated in Figure 13 for a typical

boost converter.

50

100

–50

150

0

JUNCTION TEMPERATURE (°C)

18717 F12

Figure 12. Normalized R_DS(ON)vs Temperature

From a known power dissipated in the power MOSFET, its

junction temperature can be obtained using the following

formula:

The choice of component(s) begins with the maximum

acceptable ripple voltage (expressed as a percentage of

the output voltage), and how this ripple should be divided

between the ESR step and the charging/discharging ΔV.

For the purpose of simplicity we will choose 2% for the

maximum output ripple, to be divided equally between the

ESRstepandthecharging/dischargingΔV.Thispercentage

ripple will change, depending on the requirements of the

application, and the equations provided below can easily

be modiﬁed.

T = T + P • R

J

A

FET

TH(JA)

The R

to be used in this equation normally includes

TH(JA)

the R

for the device plus the thermal resistance from

TH(JC)

the case to the ambient temperature (R

). This value

TH(CA)

of T can then be compared to the original, assumed value

J

used in the iterative calculation process.

Boost Converter: Output Diode Selection

To maximize efﬁciency, a fast switching diode with low

forwarddropandlowreverseleakageisdesired.Theoutput

diode in a boost converter conducts current during the

switch off-time. The peak reverse voltage that the diode

must withstand is equal to the regulator output voltage.

The average forward current in normal operation is equal

to the output current, and the peak current is equal to the

peak inductor current.

For a 1% contribution to the total ripple voltage, the ESR

of the output capacitor can be determined using the fol-

lowing equation:

0.01• V_O

ESR_COUTꢀ

I_IN(PEAK)

where:

I_O(MAX)

ꢀ

ꢁ

ꢂ

ꢄ

ꢅ

ꢀ

ꢁ

ꢂ

ꢄ

ꢅ

I

_D(PEAK)=I_L(PEAK)= 1+

•

I_IN(PEAK)= 1+

•

ꢃ

ꢆ

ꢃ

ꢆ

2

1–D_MAX

2

1–D_MAX

The power dissipated by the diode is:

P = I • V

For the bulk C component, which also contributes 1% to

the total ripple:

D

O(MAX)

D

I_O(MAX)

C_OUTꢀ

and the diode junction temperature is:

0.01• V_O• f

T = T + P • R

J

A

D

TH(JA)

18717fc

16

LTC1871-7

APPLICATIONS INFORMATION

L

D

For some designs it may be possible to choose a single

capacitortypethatsatisﬁesboththeESRandbulkCrequire-

ments for the design. In certain demanding applications,

however, the ripple voltage can be improved signiﬁcantly

by connecting two or more types of capacitors in paral-

lel. For example, using a low ESR ceramic capacitor can

minimize the ESR step, while an electrolytic capacitor can

be used to supply the required bulk C.

V

OUT

V

SW

C

R

L

IN

OUT

13a. Circuit Diagram

I

IN

I

L

Once the output capacitor ESR and bulk capacitance have

been determined, the overall ripple voltage waveform

should be veriﬁed on a dedicated PC board (see Board

Layout section for more information on component place-

ment). Lab breadboards generally suffer from excessive

series inductance (due to inter-component wiring), and

these parasitics can make the switching waveforms look

signiﬁcantly worse than they would be on a properly

designed PC board.

13b. Inductor and Input Currents

I

SW

t

ON

13c. Switch Current

I

D

t

OFF

I

O

Theoutputcapacitorinaboostregulatorexperienceshigh

RMS ripple currents, as shown in Figure 13. The RMS

output capacitor ripple current is:

13d. Diode and Output Currents

ΔV

COUT

V

OUT

V_O– V

(AC)

IN(MIN)

I_RMS(COUT)ꢀI_O(MAX)•

RINGING DUE TO

TOTAL INDUCTANCE

(BOARD + CAP)

V

IN(MIN)

ΔV

ESR

18717 F13

13e. Output Voltage Ripple Waveform

Note that the ripple current ratings from capacitor manu-

facturers are often based on only 2000 hours of life. This

makes it advisable to further derate the capacitor or to

choose a capacitor rated at a higher temperature than

required. Several capacitors may also be placed in parallel

to meet size or height requirements in the design.

Figure 13. Switching Waveforms for a Boost Converter

Boost Converter: Input Capacitor Selection

The input capacitor of a boost converter is less critical

than the output capacitor, due to the fact that the inductor

is in series with the input and the input current waveform

is continuous (see Figure 13b). The input voltage source

impedance determines the size of the input capacitor,

which is typically in the range of 10μF to 100μF. A low ESR

capacitor is recommended, although it is not as critical as

for the output capacitor.

In surface mount applications, multiple capacitors may

have to be placed in parallel in order to meet the ESR or

RMS current handling requirements of the application.

Aluminum electrolytic and dry tantalum capacitors are

both available in surface mount packages. In the case of

tantalum, it is critical that the capacitors have been surge

tested for use in switching power supplies. Also, ceramic

capacitors are now available with extremely low ESR, ESL

and high ripple current ratings.

The RMS input capacitor ripple current for a boost con-

verter is:

V

IN(MIN)

I

_RMS(CIN)= 0.3•

•D_MAX

L • f

18717fc

17

LTC1871-7

APPLICATIONS INFORMATION

Table 1. Recommended Component Manufacturers

VENDOR

COMPONENTS

TELEPHONE

(207) 282-5111

(952) 894-9590

(847) 639-6400

(407) 241-7876

(805) 446-4800

(408) 822-2126

(516) 847-3000

(310) 322-3331

(361) 992-7900

(408) 986-0424

(800) 245-3984

(617) 926-0404

(770) 436-1300

(847) 843-7500

(602) 244-6600

(714) 373-7334

(619) 661-6835

(847) 956-0667

(408) 573-4150

(562) 596-1212

(972) 243-4321

(408) 432-8020

(847) 699-3430

(847) 696-2000

(605) 665-9301

(800) 554-5565

(207) 324-4140

(631) 543-7100

WEB ADDRESS

avxcorp.com

AVX

Capacitors

Inductors, Transformers

Inductors

BH Electronics

Coilcraft

bhelectronics.com

coilcraft.com

Coiltronics

Diodes, Inc

Fairchild

Inductors

coiltronics.com

diodes.com

Diodes

MOSFETs

fairchildsemi.com

generalsemiconductor.com

irf.com

General Semiconductor

International Rectiﬁer

IRC

Diodes

MOSFETs, Diodes

Sense Resistors

Tantalum Capacitors

Toroid Cores

Diodes

irctt.com

Kemet

kemet.com

Magnetics Inc

Microsemi

Murata-Erie

Nichicon

mag-inc.com

microsemi.com

murata.co.jp

Inductors, Capacitors

Capacitors

nichicon.com

onsemi.com

On Semiconductor

Panasonic

Sanyo

Diodes

Capacitors

panasonic.com

sanyo.co.jp

Capacitors

Sumida

Inductors

sumida.com

Taiyo Yuden

TDK

Capacitors

t-yuden.com

Capacitors, Inductors

Heat Sinks

component.tdk.com

aavidthermalloy.com

nec-tokinamerica.com

tokoam.com

Thermalloy

Tokin

Capacitors

Toko

Inductors

United Chemicon

Vishay/Dale

Vishay/Siliconix

Vishay/Sprague

Zetex

Capacitors

chemi-com.com

vishay.com

Resistors

MOSFETs

vishay.com

Capacitors

vishay.com

Small-Signal Discretes

zetex.com

Please note that the input capacitor can see a very high

surge current when a battery is suddenly connected to

the input of the converter and solid tantalum capacitors

can fail catastrophically under these conditions. Be sure

to specify surge-tested capacitors!

which represents about 20% of the maximum 150mV

SENSE pin voltage. The corresponding average current

dependsupontheamountofripplecurrent.Lowerinductor

values (higher ΔI ) will reduce the load current at which

L

Burst Mode operations begins, since it is the peak current

that is being clamped.

Burst Mode Operation and Considerations

The output voltage ripple can increase during Burst

The choice of sense resistor and inductor value also deter-

minestheloadcurrentatwhichtheLTC1871-7entersBurst

Mode operation. When bursting, the controller clamps the

peak inductor current to approximately:

30mV

Mode operation if ΔI is substantially less than I

.

L

BURST

This can occur if the input voltage is very low or if a very

large inductor is chosen. At high duty cycles, a skipped

cycle causes the inductor current to quickly decay to

zero. However, because ΔI is small, it takes multiple

L

I_BURST(PEAK)

=

cycles for the current to ramp back up to I

.

R_SENSE

BURST(PEAK)

18717fc

18

LTC1871-7

APPLICATIONS INFORMATION

Duringthisinductorcharginginterval,theoutputcapacitor

must supply the load current and a signiﬁcant droop in

the output voltage can occur. Generally, it is a good idea

INTV to ground. The resulting dQ/dt is a current that

CC

must be supplied to the INTV capacitor through the

CC

V pin by an external supply. If the IC is operating in

IN

to choose a value of inductor ΔI between 25% and 40%

CCM:

L

of I

. The alternative is to either increase the value

IN(MAX)

I

≈ I = f • Q

Q G

Q(TOT)

of the output capacitor or disable Burst Mode operation

using the MODE/SYNC pin.

P = V • (I + f • Q )

IC

IN

Q

G

2. Power MOSFET switching and conduction losses:

Burst Mode operation can be defeated by connecting the

MODE/SYNC pin to a high logic-level voltage (either with

ꢀ

ꢃ²

ꢅ

I_O(MAX)

P

=

•R_DS(ON)•D_MAX•ꢆ_T

a control input or by connecting this pin to INTV ). In

FET

CC

ꢂ

1–D

ꢁ

_MAXꢄ

this mode, the burst clamp is removed, and the chip can

operateatconstantfrequencyfromcontinuousconduction

mode (CCM) at full load, down into deep discontinuous

conduction mode (DCM) at light load. Prior to skipping

pulsesatverylightload(i.e., <5%offullload), thecontrol-

ler will operate with a minimum switch on-time in DCM.

Pulse skipping prevents a loss of control of the output at

very light loads and reduces output voltage ripple.

I_O(MAX)

2

+ k • V_O

•

•C_RSS• f

1–D_MAX

2

3. The I R losses in the sense resistor can be calculated

almost by inspection.

I_O(MAX)

ꢀ

ꢃ²

ꢅ

P_R(SENSE)

=

•R_SENSE•D_MAX

ꢂ

1–D

ꢁ

_MAXꢄ

Efﬁciency Considerations

4. The losses in the inductor are simply the DC input cur-

rent squared times the winding resistance. Expressing

this loss as a function of the output current yields:

The efﬁciency of a switching regulator is equal to the out-

put power divided by the input power (¥100%). Percent

efﬁciency can be expressed as:

ꢀ

ꢃ²

ꢅ

I_O(MAX)

% Efﬁciency = 100% – (L1 + L2 + L3 + …),

P_R(WINDING)

=

•R_W

ꢂ

1–D

ꢁ

_MAXꢄ

where L1, L2, etc. are the individual loss components as a

percentage of the input power. It is often useful to analyze

individuallossestodeterminewhatislimitingtheefﬁciency

and which change would produce the most improvement.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for the majority

of the losses in LTC1871-7 application circuits:

5. Losses in the boost diode. The power dissipation in the

boost diode is:

P

= I • V

O(MAX) D

DIODE

The boost diode can be a major source of power loss

in a boost converter. For 13.2V input, 42V output at

1.5A example given in Figure 9, a Schottky diode with

a 0.4V forward voltage would dissipate 600mW, which

represents about 1% of the input power. Diode losses

can become signiﬁcant at low output voltages where

the forward voltage is a signiﬁcant percentage of the

output voltage.

1. The supply current into V . The V current is the sum

IN

of the DC supply current I (given in the Electrical Char-

Q

acteristics)andtheMOSFETdriverandcontrolcurrents.

The DC supply current into the V pin is typically about

IN

650μA and represents a small power loss (much less

than 1%) that increases with V . The driver current

IN

resultsfromswitchingthegatecapacitanceofthepower

MOSFET; this current is typically much larger than the

DC current. Each time the MOSFET is switched on and

6. Other losses, including C and C ESR dissipation and

IN

O

inductor core losses, generally account for less than

2% of the total losses.

then off, a packet of gate charge Q is transferred from

G

18717fc

19

LTC1871-7

APPLICATIONS INFORMATION

Checking Transient Response

A second, more severe transient can occur when con-

necting loads with large (>1μF) supply bypass capacitors.

The discharged bypass capacitors are effectively put in

The regulator loop response can be veriﬁed by looking at

the load transient response at minimum and maximum

parallel with C , causing a nearly instantaneous drop in

O

V . Switching regulators generally take several cycles to

IN

V . No regulator can deliver enough current to prevent

O

respond to an instantaneous step in resistive load current.

this problem if the load switch resistance is low and it is

driven quickly. The only solution is to limit the rise time

of the switch drive in order to limit the inrush current

di/dt to the load.

When the load step occurs, V immediately shifts by an

O

amount equal to (ΔI

)(ESR), and then C begins to

LOAD

O

chargeordischarge(dependingonthedirectionoftheload

step) as shown in Figure 14. The regulator feedback loop

acts on the resulting error amp output signal to return V

O

Boost Converter Design Example

to its steady-state value. During this recovery time, V can

O

Thedesignexamplegivenherewillbeforthecircuitshown

in Figure 9. The input voltage is 8V to 28V, and the output

is 42V at a maximum load current of 1.5A.

be monitored for overshoot or ringing that would indicate

a stability problem.

V

= 8V

IN

1. The maximum duty cycle is:

V

OUT

ꢀ

_INꢃ

V_O+ V_D– V

42+ 0.4– 8

42+ 0.4

500mV/DIV

D=

=

= 81.1%

ꢂ

ꢅ

V_O+ V_D

ꢁ

ꢄ

1.5A

2. Pulse-skip operation is chosen so the MODE/SYNC pin

I

OUT

0.5A/DIV

is shorted to INTV .

CC

0.5A

3. The operating frequency is chosen to be 250kHz to

reduce the size of the inductor. From Figure 5, the

resistor from the FREQ pin to ground is 100k.

18717 F14a

250μs/DIV

4. An inductor ripple current of 40% of the maximum load

current is chosen, so the peak input current (which is

also the minimum saturation current) is:

Figure 14a. Load Transient Response for the Circuit in Figure 9

I_O(MAX)

ꢀ

ꢁ

ꢂ

ꢄ

ꢅ

V

= 28V

IN

I

= 1+

•

ꢃ

ꢆ

IN(PEAK)

2

1–D_MAX

V

OUT

1.5

1– 0.81

500mV/DIV

=1.2•

= 9.47A

1.5A

The inductor ripple current is:

I

OUT

I_O(MAX)

1.5

1– 0.81

0.5A/DIV

ꢀI_L= ꢁ •

= 0.4•

= 3.2A

0.5A

1–D_MAX

And so the inductor value is:

V

18717 F14b

IN(MIN)

250μs/DIV

L =

•D_MAX

ꢀI_L• f

Figure 14b. Load Transient Response for the Circuit in Figure 9

8

=

•0.81= 8.1μH

3.2•250k

18717fc

20

LTC1871-7

APPLICATIONS INFORMATION

The component chosen is a 6.8μH inductor made by

Cooper (part number DR127-6R8) which has a satura-

tion current of greater than 13.3A.

T

o satisfy the low ESR, high frequency decoupling

requirements, two 10μF, 50V, X5R ceramic capacitors

are used (TDK part number C5750X5R1H106M). In

parallel with these, two 68μF, 100V electrolytic ca-

pacitors are used (Sanyo part number 100CV68FS).

Check the output ripple with a single oscilloscope

probe connected directly across the output capacitor

terminals, where the HF switching currents ﬂow.

5. Because the duty cycle is 81%, the maximum SENSE

pin threshold voltage is reduced from its low duty cycle

typical value of 150mV to approximately 115mV. In ad-

dition, we need to apply a worst-case derating factor

to this SENSE threshold to account for manufacturing

tolerances within the IC. Finally, the nominal current

limit value should exceed the maximum load current

by some safety margin (in this case 50%). Therefore,

the value of the sense resistor is:

9. The choice of an input capacitor for a boost converter

depends on the impedance of the source supply and

the amount of input ripple the converter will safely

tolerate. For this particular design and lab setup a

560μF, 50V Sanyo electrolytic (50MV560AXL), in

parallel with two 10μF, 100V TDK ceramic capacitors

(C5750X5R1H106M) is required (the input and return

lead lengths are kept to a few inches, but the peak input

current is close to 10A!). As with the output node,

check the input ripple with a single oscilloscope probe

connected across the input capacitor terminals.

1–D_MAX

R

_SENSE= 0.8 • V_SENSE(MAX)•

0.4

2

ꢀ

ꢁ

ꢃ

ꢄ

1+

•1.5•I

O(MAX)

ꢂ

ꢅ

1– 0.81

1.2•1.5•1.5

= 0.8 •0.115•

= 6.5mꢆ

A 1W, 5mꢀ resistor is used in this design.

6. The MOSFET chosen is a Vishay/Siliconix Si7370DP,

which has a BV of greater than 60V and an R

DSS

DS(ON)

V

OUT

of less than 13mꢀ at a V of 6V.

GS

1V/DIV

7. The diode for this design must handle a maximum DC

output current of 1.5A and be rated for a minimum

I

L

2A/DIV

reverse voltage of V , or 42V. A 3A, 60V diode from

OUT

Diodes Inc. (B360B) is chosen.

8. The output capacitor usually consists of a high valued

bulk C connected in parallel with a lower valued, low

ESRceramic.Basedonamaximumoutputripplevoltage

of 1%, or 50mV, the bulk C needs to be greater than:

MOSFET

DRAIN

VOLTAGE

20V/DIV

18717 F15

V

OUT

V

= 8V

1μs/DIV

IN

I_OUT(MAX)

1.5

0.01• V_OUT• f 0.01• 42•250k

I

= 0.5A

= 42V

C_OUTꢀ

=

=14μF

OUT

D = 81%

The RMS ripple current rating for this capacitor needs

to exceed:

Figure 15. Switching Waveforms for the Converter

in Figure 9 at Minimum V_IN(8V)

V_O– V

IN(MIN)

I_RMS(COUT)ꢀI_O(MAX)

•

=

V

IN(MIN)

42– 8

8

1.5•

= 3.09A

18717fc

21

LTC1871-7

APPLICATIONS INFORMATION

100

95

90

85

80

75

V

= 8V

= 12V

= 28V

V

IN

OUT

1V/DIV

I

L

1A/DIV

MOSFET

DRAIN

VOLTAGE

20V/DIV

0.001

0.01

0.1

(mA)

1

10

18717 F16

V

OUT

V

= 28V

1μs/DIV

I

IN

LOAD

I

= 0.5A

= 42V

18717 F17

OUT

D = 27%

Figure 16. Switching Waveforms for the

Converter in Figure 9 at Maximum V_IN(28V)

Figure 17. Efﬁciency vs Load Current and Input Voltage

for the Converter in Figure 9

PC Board Layout Checklist

ringing. Excess inductance can cause increased stress on

the power MOSFET and increase HF noise on the output.

If low ESR ceramic capacitors are used on the output to

reduce output noise, place these capacitors close to the

boost diode in order to keep the series inductance to a

minimum.

1. In order to minimize switching noise and improve out-

put load regulation, the GND pin of the LTC1871-7 should

be connected directly to 1) the negative terminal of the

INTV decoupling capacitor, 2) the negative terminal of

CC

the output decoupling capacitors, 3) the bottom terminal

of the sense resistor, 4) the negative terminal of the input

capacitor and 5) at least one via to the ground plane

immediately adjacent to Pin 6. The ground trace on the

top layer of the PC board should be as wide and short as

possible to minimize series resistance and inductance.

5. Check the stress on the power MOSFET by measur-

ing its drain-to-source voltage directly across the device

terminals (reference the ground of a single scope probe

directly to the source pad on the PC board). Beware of

inductive ringing which can exceed the maximum speci-

ﬁed voltage rating of the MOSFET. If this ringing cannot be

avoided and exceeds the maximum rating of the device,

either choose a higher voltage device or specify an ava-

lanche-rated power MOSFET. Not all MOSFETs are created

equal (some are more equal than others).

2. Beware of ground loops in multiple layer PC boards. Try

to maintain one central ground node on the board and use

the input capacitor to avoid excess input ripple for high

output current power supplies. If the ground plane is to

be used for high DC currents, choose a path away from

the small-signal components.

6. Place the small-signal components away from high fre-

quencyswitchingnodes. InthelayoutshowninFigure 18,

all of the small-signal components have been placed on

one side of the IC and all of the power components have

been placed on the other. This also allows the use of a

pseudo-Kelvin connection for the signal ground, where

high di/dt gate driver currents ﬂow out of the IC ground

3. Place the C

capacitor immediately adjacent to the

VCC

INTV and GND pins on the IC package. This capacitor

CC

carries high di/dt MOSFET gate drive currents. A low ESR

and ESL 4.7μF ceramic capacitor works well here.

4. The high di/dt loop from the bottom terminal of the

output capacitor, through the power MOSFET, through

the boost diode and back through the output capacitors

should be kept as tight as possible to reduce inductive

pin in one direction (to the bottom plate of the INTV

CC

decoupling capacitor) and small-signal currents ﬂow in

the other direction.

18717fc

22

LTC1871-7

APPLICATIONS INFORMATION

7. Minimize the capacitance between the SENSE pin trace

and any high frequency switching nodes. The LTC1871-7

contains an internal leading edge blanking time of ap-

proximately 180ns, which should be adequate for most

applications.

8. For optimum load regulation and true remote sens-

ing, the top of the output resistor divider should connect

independently to the top of the output capacitor (Kelvin

connection), staying away from any high dV/dt traces.

Place the divider resistors near the LTC1871-7 in order

to keep the high impedance FB node short.

V

IN

L1

R3

JUMPER

J1

R4

R

C

PIN 1

LTC1871-7

C

IN

R2

R1

T

C

VCC

SWITCH NODE IS ALSO

THE HEAT SPREADER

FOR L1, M1, D1

M1

R

S

PSEUDO-KELVIN

SIGNAL GROUND

CONNECTION

C

OUT

D1

VIAS TO GROUND

PLANE

V

OUT

TRUE REMOTE

OUTPUT SENSING

1871 F18

Figure 18. LTC1871-7 Boost Converter Suggested Layout

V

IN

R3

R4

L1

J1

1

2

10

9

C

SWITCH

NODE

C

RUN

SENSE

R

C

I

V

IN

TH

LTC1871-7

FB

R1

D1

3

4

5

8

7

6

INTV

CC

R2

FREQ

GATE

GND

M1

R

T

+

MODE/

SYNC

C

VCC

IN

R

S

GND

C

PSEUDO-KELVIN

GROUND CONNECTION

OUT

+

V

OUT

18717 F19

BOLD LINES INDICATE HIGH CURRENT PATHS

Figure 19. LTC1871-7 Boost Converter Layout Diagram

18717fc

23

LTC1871-7

APPLICATIONS INFORMATION

9. Forapplicationswithmultipleswitchingpowerconvert-

ers connected to the same input supply, make sure that

the input ﬁlter capacitor for the LTC1871-7 is not shared

with other converters. AC input current from another

convertercouldcausesubstantialinputvoltageripple,and

this could interfere with the operation of the LTC1871-7.

A few inches of PC trace or wire (L ≈ 100nH) between the

C of the LTC1871-7 and the actual source V should be

and size. All of the SEPIC applications information that

follows assumes L1 = L2 = L.

SEPIC Converter: Duty Cycle Considerations

ForaSEPICconverteroperatinginacontinuousconduction

mode (CCM), the duty cycle of the main switch is:

ꢀ

ꢃ

ꢅ

V_O+ V_D

V + V + V

D=

IN

ꢂ

ꢁ

_Dꢄ

IN

O

sufﬁcient to prevent current sharing problems.

where V is the forward voltage of the diode. For convert-

D

SEPIC Converter Applications

ers where the input voltage is close to the output voltage

The LTC1871-7 is also well suited to SEPIC (single-ended

primaryinductanceconverter)converterapplications. The

SEPIC converter shown in Figure 20 uses two inductors.

The advantage of the SEPIC converter is the input voltage

may be higher or lower than the output voltage, and the

output is short-circuit protected.

the duty cycle is near 50%.

I

IN

I

L1

L2

SW

ON

SW

OFF

21a. Input Inductor Current

The ﬁrst inductor, L1, together with the main switch,

resembles a boost converter. The second inductor, L2,

together with the output diode D1, resembles a ﬂyback or

buck-boost converter. The two inductors L1 and L2 can be

independentbutcanalsobewoundonthesamecoresince

identical voltages are applied to L1 and L2 throughout the

switching cycle. By making L1 = L2 and winding them on

the same core the input ripple is reduced along with cost

O

I

21b. Output Inductor Current

I

IN

O

I

C1

D1

L1

V

OUT

•

+

21c. DC Coupling Capacitor Current

+

R

L

R

L

R

L

V

SW

L2

C

IN

OUT

•

I

D1

20a. SEPIC Topology

V

IN

I

O

V

OUT

•

+

21d. Diode Current

+

•

20b. Current Flow During Switch On-Time

V

OUT

(AC)

V

IN

D1

V

ΔV

COUT

OUT

•

18717 F21

+

ΔV

ESR

+

RINGING DUE TO

TOTAL INDUCTANCE

(BOARD + CAP)

•

18717 F20

21e. Output Ripple Voltage

Figure 21. SEPIC Converter Switching Waveforms

20c. Current Flow During Switch Off-Time

Figure 20. SEPIC Topolgy and Current Flow

18717fc

24

LTC1871-7

APPLICATIONS INFORMATION

The maximum output voltage for a SEPIC converter is:

Like the boost converter, the input current of the SEPIC

converter is calculated at full load current and minimum

inputvoltage.Thepeakinductorcurrentcanbesigniﬁcantly

higher than the output current, especially with smaller in-

ductors and lighter loads. The following formulas assume

CCM operation and calculate the maximum peak inductor

D_MAX

1–D_MAX

1

V_O(MAX)= V + V

– V

^D1–D_MAX

(

)

IN

D

The maximum duty cycle of the LTC1871-7 is typically

92%.

currents at minimum V :

IN

SEPIC Converter: The Peak and Average

Input Currents

V_O+ V_D

ꢀ

ꢁ

ꢂ

ꢄ

ꢅ

I_L1(PEAK)= 1+

•I

•

ꢃ

ꢆ

O(MAX)

2

V

IN(MIN)

ThecontrolcircuitintheLTC1871-7ismeasuringtheinput

current (using a sense resistor in the MOSFET source),

so the output current needs to be reﬂected back to the

input in order to dimension the power MOSFET properly.

Based on the fact that, ideally, the output power is equal

to the input power, the maximum input current for a SEPIC

converter is:

V

_IN(MIN)+ V_D

ꢀ

ꢁ

ꢂ

ꢄ

ꢅ

I_L2(PEAK)= 1+

•I •

O(MAX)

ꢃ

ꢆ

2

V

IN(MIN)

The ripple current in the inductor is typically 20% to 40%

χ

(i.e., a range of ‘ ’ from 0.20 to 0.40) of the maximum

averageinputcurrentoccurringatV

andI

and

IN(MIN)

O(MAX)

ΔI = ΔI . Expressing this ripple current as a function of

L1

L2

D_MAX

1–D_MAX

I_IN(MAX)=I_O(MAX)•

the output current results in the following equations for

calculating the inductor value:

Thepeak input current is:

V

IN(MIN)

L =

•D_MAX

ꢀI_L• f

D_MAX

1–D_MAX

ꢀ

ꢁ

ꢂ

ꢄ

ꢅ

I

= 1+

•I

•

ꢃ

ꢆ

IN(PEAK)

O(MAX)

where

2

D_MAX

1–D_MAX

ꢀI_L= ꢁ •I_O(MAX)

•

The maximum duty cycle, D

, should be calculated at

MAX

minimum V .

IN

χ

By making L1 = L2 and winding them on the same core,

the value of inductance in the equation above is replace

by 2L due to mutual inductance. Doing this maintains the

sameripplecurrentandenergystorageintheinductors.For

example, aCoiltronixCTX10-4isa10μHinductorwithtwo

windings.Withthewindingsinparallel,10μHinductanceis

obtained with a current rating of 4A (the number of turns

hasn’t changed, but the wire diameter has doubled). Split-

ting the two windings creates two 10μH inductors with a

currentratingof2Aeach. Therefore, substituting2Lyields

the following equation for coupled inductors:

Theconstant‘ ’representsthefractionofripplecurrentin

the inductor relative to its maximum value. For example, if

χ

30% ripple current is chosen, then = 0.30 and the peak

current is 15% greater than the average.

It is worth noting here that SEPIC converters that operate

at high duty cycles (i.e., that develop a high output volt-

age from a low input voltage) can have very high input

currents, relative to the output current. Be sure to check

that the maximum load current will not overload the input

supply.

V

SEPIC Converter: Inductor Selection

IN(MIN)

L1=L2=

•D_MAX

2• ꢀI_L• f

For most SEPIC applications the equal inductor values

will fall in the range of 10μH to 100μH. Higher values will

reduce the input ripple voltage and reduce the core loss.

Lower inductor values are chosen to reduce physical size

and improve transient response.

Specify the maximum inductor current to safely handle

I

speciﬁedintheequationabove.Thesaturationcurrent

L(PK)

18717fc

25

LTC1871-7

APPLICATIONS INFORMATION

rating for the inductor should be checked at the minimum

input voltage (which results in the highest inductor cur-

rent) and maximum output current.

92% due to slope compensation, as shown in Figure 11.

χ

The constant ‘ ’ in the denominator represents the ripple

current in the inductors relative to their maximum cur-

rent. For example, if 30% ripple current is chosen, then

χ

SEPIC Converter: Power MOSFET Selection

= 0.30.

Important parameters for the power MOSFET include the

Calculating Power MOSFET Switching and Conduction

Losses and Junction Temperatures

drain-to-sourcebreakdownvoltage(BV ),thethreshold

DSS

DS(ON)

voltage(V

),theon-resistance(R

)versusgate-

GS(TH)

to-source voltage, the gate-to-source and gate-to-drain

In order to calculate the junction temperature of the

power MOSFET, the power dissipated by the device must

be known. This power dissipation is a function of the

duty cycle, the load current and the junction temperature

itself. As a result, some iterative calculation is normally

required to determine a reasonably accurate value. Since

the controller is using the MOSFET as both a switching

and a sensing element, care should be taken to ensure

that the converter is capable of delivering the required

load current over all operating conditions (load, line and

temperature) and for the worst-case speciﬁcations for

charges (Q and Q , respectively), the maximum drain

GS

GD

current (I

) and the MOSFET’s thermal resistances

D(MAX)

and R

(R

).

TH(JA)

TH(JC)

The gate drive voltage is set by the 7V INTV low dropout

CC

regulator. Consequently, 6V rated threshold MOSFETs are

required in most LTC1871-7 applications.

The maximum voltage that the MOSFET switch must

sustain during the off-time in a SEPIC converter is equal

to the sum of the input and output voltages (V + V ).

O

IN

As a result, careful attention must be paid to the BV

V

and the R

of the MOSFET listed in the

DSS

SENSE(MAX)

manufacturer’s data sheet.

DS(ON)

speciﬁcations for the MOSFETs relative to the maximum

actual switch voltage in the application. Many logic-level

devices are limited to 30V or less. Check the switching

waveforms directly across the drain and source terminals

ThepowerdissipatedbytheMOSFETinaSEPICconverter

is:

ꢀ

ꢁ

ꢃ²

ꢄ

D

1–D

of the power MOSFET to ensure the V remains below

DS

P

= I

•

•R_DS(ON)•D•ꢆ_T

ꢂ

ꢅ

FET

O(MAX)

the maximum rating for the device.

D

1–D

+ k • V + V ²•I_O(MAX)

•

•C_RSS• f

Sense Resistor Selection

(

)

IN

O

During the MOSFET’s on-time, the control circuit limits

the maximum voltage drop across the power MOSFET to

about 150mV (at low duty cycle). The peak inductor cur-

2

The ﬁrst term in the equation above represents the I R

losses in the device and the second term, the switching

losses.Theconstantk=1.7isanempiricalfactorinversely

related to the gate drive current and has the dimension

of 1/current.

rentisthereforelimitedto150mV/R

.Therelationship

SENSE

between the maximum load current, duty cycle and the

sense resistor is:

The ρ_Tterm accounts for the temperature coefﬁcient of

V_SENSE(MAX)

1

R

_SENSEꢀ

•

ꢅ ꢂ

ꢇ

the R_DS(ON)of the MOSFET, which is typically 0.4%/°C.

ꢁ

I_O(MAX)

ꢂ

ꢃ

ꢅ

V_O+ V_D

Figure 12 illustrates the variation of normalized R

1+

DS(ON)

ꢄ

+1

ꢄ

ꢇ

ꢆ

2

V

over temperature for a typical power MOSFET.

ꢃ

ꢆ

IN(MIN)

The V_SENSE(MAX)term is typically 150mV at low duty

cycle and is reduced to about 100mV at a duty cycle of

18717fc

26

LTC1871-7

APPLICATIONS INFORMATION

From a known power dissipated in the power MOSFET, its

junction temperature can be obtained using the following

formula:

parameters (ESR, ESL, and bulk C) on the output voltage

ripple waveform are illustrated in Figure 21 for a typical

coupled-inductor SEPIC converter.

T = T + P •R

The choice of component(s) begins with the maximum

acceptable ripple voltage (expressed as a percentage of

the output voltage), and how this ripple should be divided

between the ESR step and the charging/discharging ΔV.

For the purpose of simplicity we will choose 2% for the

maximum output ripple, to be divided equally between the

ESRstepandthecharging/dischargingΔV.Thispercentage

ripple will change, depending on the requirements of the

application, and the equations provided below can easily

be modiﬁed.

J

A

FET TH(JA)

The R

to be used in this equation normally includes

TH(JA)

the R

for the device plus the thermal resistance from

TH(JC)

the board to the ambient temperature in the enclosure.

This value of T can then be used to check the original

J

assumption for the junction temperature in the iterative

calculation process.

SEPIC Converter: Output Diode Selection

To maximize efﬁciency, a fast-switching diode with low

forwarddropandlowreverseleakageisdesired.Theoutput

diode in a SEPIC converter conducts current during the

switch off-time. The peak reverse voltage that the diode

For a 1% contribution to the total ripple voltage, the ESR

of the output capacitor can be determined using the fol-

lowing equation:

0.01• V_O

I_D(PEAK)

must withstand is equal to V

+ V . The average

IN(MAX)

O

ESR_COUTꢀ

forward current in normal operation is equal to the output

current, and the peak current is equal to:

where:

ꢁ

ꢄ

ꢆ

V_O+ V

ꢀ

ꢁ

ꢂ

ꢄ

ꢁ

ꢄ

V_O+ V

ꢀ

I_D(PEAK)= 1+

•I

•

^D+1

ꢁ

ꢂ

ꢄ

ꢅ

ꢃ

I_D(PEAK)= 1+

•I

•

^D+1

ꢃ

ꢆ

O(MAX)

ꢅ

2

V

ꢃ

ꢆ

ꢃ

ꢆ

O(MAX)

ꢂ

ꢅ

IN(MIN)

2

V

ꢂ

ꢅ

IN(MIN)

The power dissipated by the diode is:

P = I • V

For the bulk C component, which also contributes 1% to

the total ripple:

D

O(MAX)

D

I_O(MAX)

and the diode junction temperature is:

C_OUTꢀ

0.01• V_O• f

T = T + P • R

J

A

D

TH(JA)

The R

to be used in this equation normally includes

TH(JA)

Formanydesignsitispossibletochooseasinglecapacitor

type that satisﬁes both the ESR and bulk C requirements

forthedesign.Incertaindemandingapplications,however,

the ripple voltage can be improved signiﬁcantly by con-

necting two or more types of capacitors in parallel. For

example, using a low ESR ceramic capacitor can minimize

the ESR step, while an electrolytic or tantalum capacitor

can be used to supply the required bulk C.

the R

for the device plus the thermal resistance from

TH(JC)

the board to the ambient temperature in the enclosure.

SEPIC Converter: Output Capacitor Selection

Because of the improved performance of today’s electro-

lytic, tantalum and ceramic capacitors, engineers need

to consider the contributions of ESR (equivalent series

resistance), ESL (equivalent series inductance) and the

bulk capacitance when choosing the correct component

for a given output ripple voltage. The effects of these three

Once the output capacitor ESR and bulk capacitance have

been determined, the overall ripple voltage waveform

18717fc

27

LTC1871-7

APPLICATIONS INFORMATION

should be veriﬁed on a dedicated PC board (see Board

Layout section for more information on component place-

ment). Lab breadboards generally suffer from excessive

series inductance (due to inter-component wiring), and

these parasitics can make the switching waveforms look

signiﬁcantly worse than they would be on a properly

designed PC board.

The RMS input capacitor ripple current for a SEPIC con-

verter is:

1

12

I_RMS(CIN)

=

• ꢀI_L

Please note that the input capacitor can see a very high

surge current when a battery is suddenly connected to

the input of the converter and solid tantalum capacitors

can fail catastrophically under these conditions. Be sure

to specify surge-tested capacitors!

The output capacitor in a SEPIC regulator experiences

high RMS ripple currents, as shown in Figure 21. The

RMS output capacitor ripple current is:

SEPIC Converter: Selecting the DC Coupling Capacitor

V_O

I_RMS(COUT)=I_O(MAX)•

V

ThecouplingcapacitorC1inFigure20seesnearlyarectan-

gular current waveform as shown in Figure 21. During the

IN(MIN)

Note that the ripple current ratings from capacitor manu-

facturers are often based on only 2000 hours of life. This

makes it advisable to further derate the capacitor or to

choose a capacitor rated at a higher temperature than

required. Several capacitors may also be placed in parallel

to meet size or height requirements in the design.

switch off-time the current through C1 is I (V /V ) while

O

IN

approximately –I ﬂows during the on-time. This current

O

waveform creates a triangular ripple voltage on C1:

I_O(MAX)

V_O

C1• f V + V_O+ V_D

ꢀV_C1(PꢁP)

=

•

IN

The maximum voltage on C1 is then:

In surface mount applications, multiple capacitors may

have to be placed in parallel in order to meet the ESR or

RMS current handling requirements of the application.

Aluminum electrolytic and dry tantalum capacitors are

both available in surface mount packages. In the case of

tantalum, it is critical that the capacitors have been surge

tested for use in switching power supplies. Also, ceramic

capacitors are now available with extremely low ESR, ESL

and high ripple current ratings.

ꢀV_C1(PꢁP)

V

_C1(MAX)= V +

IN

2

which is typically close to V

through C1 is:

. The ripple current

IN(MAX)

V_O+ V_D

I_RMS(C1)=I_O(MAX)•

V

IN(MIN)

The value chosen for the DC coupling capacitor normally

starts with the minimum value that will satisfy 1) the RMS

current requirement and 2) the peak voltage requirement

SEPIC Converter: Input Capacitor Selection

The input capacitor of a SEPIC converter is less critical

than the output capacitor due to the fact that an inductor

is in series with the input and the input current waveform

istriangularinshape. Theinputvoltagesourceimpedance

determines the size of the input capacitor which is typi-

cally in the range of 10μF to 100μF. A low ESR capacitor

is recommended, although it is not as critical as for the

output capacitor.

(typically close to V ). Low ESR ceramic and tantalum

IN

capacitors work well here.

18717fc

28

LTC1871-7

TYPICAL APPLICATIONS

A 48V Input Flyback Converter Conﬁgurable to 3.3V or 5V Outputs

V

IN

36V TO 72V

UPS840

V

OUT

CTX-002-15242

3.3V

•

100k

10V

3A MAX

100μF

6.3V

×3

T1A

2.2μF

100V

T1B

MMBTA42

9

R1

604k

•

0.1μF

100k

1

RUN

V

IN

2

7

Q1

I

GATE

LTC1871-7

SENSE

MODE/SYNC INTV

TH

FDC2512

26.7k

82.5k

1nF

ALL CAPACITORS

ARE CERAMIC

X5R TYPE

4

5

3

10

8

FREQ

4.7μF

R3

0.1Ω

CC

12.4k

6

V

GND

FB

R2*

21k

18717 TA02a

*R2 = 38.3k FOR V

= 5V

OUT

Output Efﬁciency at 3.3V Output

Output Efﬁciency at 5V Output

90

85

80

75

70

65

60

90

85

80

75

70

65

60

36V

IN

36V

IN

48V

IN

72V

IN

72V

IN

0

2

3

4

5

6

0

2

3

4

5

1

I

(A)

I

(A)

LOAD

18717 TA02b

18717 TA02c

18717fc

29

LTC1871-7

TYPICAL APPLICATIONS

1.2A Automotive LED Headlamp Boost Converter

D3

IRF12CW10

L1

TO

V

IN

LEDS

C5

C7

10μF

100V

+

R7

4.7M

47μF

20V

×2

R6

1M

1%

GND

1

2

10

9

RUN

INPUT

RUN

SENSE

R8

187k

1%

I

TH

V

IN

C8

LTC1871-7

100nF

3

4

5

8

7

6

FB

INTV

CC

Q3

R9

1k

SILICONIX

FREQ

GATE

GND

C9

SUP75N08-9L

R10

300k

MODE/SYNC

4.7μF

X5R

D4

USE 68V

R11

33V

OR 75V

SINGLE

ZENER

0.006Ω

R12

4.02k

D5

33V

R13

17.8k

C10

4.7μF

D6 5V

0V TO 5V

DIMMING

INPUT

R15

0.20Ω

0.5W

R14

1k

FROM

LEDS

18717 TA01

C5: SANYO OS-CON 20SP47M

C7: ITW PAKTRON 106K100CS4

L1: MAGNETICS INC 58206-A2 WITH 29T 18AWG

Dual Output Cell Phone Base Station Flyback Converter

TAB

GND

R2

12.5k

LT1963

SHDN IN GND OUT ADJ

D1

1A 40V

1

2

3

4

5

L1

10μH

T1

VP4-0047

V

5.5V

IN

18V TO 33V

500mA

7

1

12

+

C6

1μF

35V

C5

22μF

50V

C7

3.3μF

50V

R3

43.2k

C3

100μF

R4

6

75Ω

C4

33μF

2

11

C9

D2

R6

1nF

10V

1Ω

R5

150k

3

10

C8

100pF

200V

8

5

3.3V

2A

4

9

C10

330nF

R7

33k

D3

1

2

10

9

UPS840

C12

15nF

RUN

SENSE

R8

20.5k

R9

33k

I

TH

V

IN

LTC1871-7

INTV

LT1431

3

4

5

8

7

6

FB

CC

1

2

3

4

8

7

6

5

+

C13A

COL

REF

R10

64.9k

Q1

C11

100μF

FREQ

GATE

GND

470μF

Si4482DY

SYNC SIGNAL

320kHz

COMP

R

MID

MODE/SYNC

+

V

GNDF

0V TO 2.5V

C13

R11

12.5k

R12

80k

C14

1nF

R13

0.082Ω

C15

4.7μF

470μF

R

GNDS

TOP

18717 TA03

R1

33k

C3, C11: TDK C3225X5R0J107M

C4: SANYO POSCAP 10 TPB33M

C7: TDK C4532X7R1H335M

C13, C13A: SANYO POSCAP 4TPB470M

L1: COILCRAFT DO1608 103

T1: COILTRONICS VP4-0047

C17

R14

1k

C16

10nF 1kV

1μF

D4

BAT54

ISO1

MOC207

18717fc

30

LTC1871-7

TYPICAL APPLICATIONS

Automotive SEPIC Converter

T1

VP5-0155

•

4

9

5

8

6

7

R46

C52

4.7μF

X7R

×2

L7

150Ω 3A

BEAD 1B

47k

CR22

1N4148

Q6

FMMT451

•

1

12

2

11

3

10

(OPTIONAL HF FILTER)

V

CR4

OUT

V

BATT

8V TO 25V

13.5V

3A

BZX84C15V

R37

75k

1%

CR21

9

MBR10100

V

IN

1

2

10

RUN

SENSE

C55

C57

I

TH

R60

124k

1%

4.7μF

16V

X7R

×2

10μF

Q9

Si4486EY

SO-8

X5R

LTC1871-7

INTV

(OPTIONAL

HF FILTER)

R43

13.3k

1%

3

4

5

8

7

C53

22μF

16V

X5R

×2

R45

33.2k

FB

CC

+

C51

150μF

35V

FREQ

R59

R47

133k

1%

C50

4μF

X7R

0.005Ω

1W

C46

100pF

MODE/SYNC GATE

GND

+

R61

12.4k

1%

C49

4.7μF

C47

6800pF

6

18717 TA04

PACKAGE DESCRIPTION

MS Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1661)

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

0.497 ± 0.076

(.0196 ± .003)

REF

10 9

8

7 6

0.889 ± 0.127

(.035 ± .005)

DETAIL “A”

0.254

(.010)

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

0° – 6° TYP

4.90 ± 0.152

(.193 ± .006)

GAUGE PLANE

5.23

3.20 – 3.45

(.206)

0.53 ± 0.152

(.021 ± .006)

(.126 – .136)

MIN

1

2

3

4 5

DETAIL “A”

0.18

(.007)

0.86

(.034)

REF

1.10

(.043)

MAX

0.50

(.0197)

BSC

0.305 ± 0.038

(.0120 ± .0015)

TYP

RECOMMENDED SOLDER PAD LAYOUT

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

NOTE:

0.1016 ± 0.0508

(.004 ± .002)

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

0.50

(.0197)

BSC

MSOP (MS) 0307 REV E

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

18717fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

31

LTC1871-7

TYPICAL APPLICATION

A Small, Nonisolated 12V Flyback Telecom Housekeeping Supply

D3

V

OUT

V

IN

12V

36V

TO 72V

R1

604k

1%

C

0.4A

IN

R5

T1

1, 2, 3

(SERIES)

2.2μF

100V

X7R

C

47μF

X5R

100k

4, 5, 6

(PARALLEL)

OUT

Q1

D1

9.1V

C1

1nF

OPTIONAL

R2

26.7k

1%

R6

10Ω

+

–

UV = 31.8V

UV = 29.5V

C

C2

47pF

RUN

SENSE

D2

I

V

IN

TH

LTC1871-7

FB

INTV

CC

R

C

3.4k

R3

12.4k

1%

M1

FREQ

GATE

GND

MODE/SYNC

f = 200kHz

R4

110k

1%

C

C1

2.2nF

R

T

C2

4.7μF

X5R

C3

0.1μF

X5R

R

S

0.12Ω

120k

18717 TA05

D1: ON SEMICONDUCTOR MMBZ5239BLT1 (9.1V)

D2: ON SEMICONDUCTOR MMSD4148T11

D3: INTERNATIONAL RECTIFIER 10BQ060

T1: COILTRONICS VP1-0076

M1: FAIRCHILD FDC2512 (150V, 0.5Ω)

Q1: ZETEX FMMT625 (120V)

RELATED PARTS

PART NUMBER

LT^®1619

DESCRIPTION

COMMENTS

Current Mode PWM Controller

Current Mode DC/DC Controller

300kHz Fixed Frequency, Boost, SEPIC, Flyback Topology

SO-8; 300kHz Operating Frequency; Buck, Boost, SEPIC Design;

Up to 36V

LTC1624

V

IN

LTC1700

No R

Synchronous Step-Up Controller

Up to 95% Efﬁciency, Operation as Low as 0.9V Input

Operation as Low as 2.5V Input, Boost Flyback,SEPIC

Delivers Up to 5A, 550kHz Fixed Frequency, Current Mode

SENSE

LTC1871

Wide Input Range, No R

Controller

SENSE

LTC1872

SOT-23 Boost Controller

LT1930

1.2MHz, SOT-23 Boost Converter

Inverting 1.2MHz, SOT-23 Converter

1A/2A 3MHz Synchronous Boost Converters

SOT-23 Flyback Controller

Up to 34V Output, 2.6V ≤ V ≤ 16V, Miniature Design

IN

LT1931

Positive-to-Negative DC/DC Conversion, Miniature Design

LTC3401/LTC3402

LTC3803

Up to 97% Efﬁciency, Very Small Solution, 0.5V ≤ V ≤ 5V

IN

Adjustable Slope Compensation, Internal Soft-Start, Current Mode

200kHz Operation

LTC3806

Synchronous Flyback Controller

High Efﬁciency, Improves Cross Regulation in Multiple Output Designs,

Current Mode, 3mm × 4mm 12-Pin DFN Package

18717fc

LT 0108 REV C • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

32

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT1871EMS-7#PBF
厂家：	Linear
描述：	IC SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO10, LEAD FREE, PLASTIC, MSOP-10, Switching Regulator or Controller 稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管
文件：	总32页 (文件大小：456K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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