LT1939EDD [Linear]
Monolithic 2A Step-Down Regulator Plus Linear Regulator/Controller;
| 型号： | LT1939EDD |
| 厂家： | 
Linear |
| 描述： | Monolithic 2A Step-Down Regulator Plus Linear Regulator/Controller |
| 文件： | 总24页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1939
Monolithic 2A Step-Down
Regulator Plus Linear
Regulator/Controller
FEATURES
DESCRIPTION
The LT®1939 is a current mode PWM step-down DC/DC
converter with an internal 2.3A switch. The wide input
range of 3V to 25V makes the LT1939 suitable for regu-
lating power from a wide variety of sources, including
automotive batteries, industrial supplies and unregulated
wall adapters.
n
Wide Input Range: 3V to 25V
n
Short-Circuit Protected Over Full Input Range
n
2A Output Current Capability
n
Adjustable/Synchronizable Fixed Frequency
Operation from 250kHz to 2.2MHz
n
Soft-Start/Tracking Capability
n
Output Adjustable Down to 0.8V
Resistor-programmable 250kHz to 2.2MHz frequency
range and synchronization capability enable optimization
between efficiency and external component size. Cycle-
by-cycle current limit, frequency foldback and thermal
shutdown provide protection against a shorted output.
The soft-start feature controls the ramp rate of the output
voltage, eliminating input current surge during start-up,
and also provides output tracking.
n
Adjustable Linear Regulator/Driver with 13mA
Output Capability
n
Power Good Comparator with Complementary
Outputs
Low Shutdown Current: 12μA
n
n
Thermally Enhanced 3mm × 3mm DFN Package
APPLICATIONS
The LT1939 contains an internal NPN transistor with feed-
back control which can be configured as a linear regulator
or as a linear regulator controller.
n
Automotive Battery Regulation
n
Industrial Control
n
Wall Transformer Regulation
Distributed Power Regulation
n
TheLT1939’slowcurrentshutdownmode(<12μA)enables
easy power management in battery-powered systems.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Dual Step-Down Converters
Switching Converter Efficiency
Output Voltage Ripple
90
BAT54
V
IN
6V TO 25V
2.2μF
V
BST
SW
IN
85
80
75
70
65
60
55
50
0.47μF
6.8μH
LT1939
V
5V
1A
OUT1
V
OUT1
= 5V AT 1A
AC COUPLED
2mV/DIV
B240A
SHDN
SS
42.2k
22μF
0.47μF
FB
PG
PG
8.06k
V
= 3.3V AT 1A
AC COUPLED
2mV/DIV
OUT2
R
V
SYNC LDRV
V
OUT2
= 12V
T/
IN
I
= 0A
53.6k
330pF
C
1k
FREQUENCY = 800kHz
V
24.9k
8.06k
OUT2
3.3V
1A
1939 TA01c
LFB
500ns/DIV
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
40.2k
22μF
LOAD CURRENT (A)
1939 TA01b
1939 TA01a
1939f
1
LT1939
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V , PG, PG Operating.................................... 25V/–0.3V
IN
1
2
3
4
5
6
12 SW
V
IN
SW.............................................................................V
IN
BST
LDRV
LFB
FB
SHDN
SS
11
10
9
BST................................................................ 45V/–0.3V
BST Pin Above SW....................................................25V
LDRV, SHDN..............................................................15V
13
PG
8
V
C
7
PG
R /SYNC
T
FB, LFB, R /SYNC .......................................................5V
T
DD PACKAGE
12-LEAD (3mm × 3mm) PLASTIC DFN
SS, V ......................................................................2.5V
C
θ
= 45°C/W, θ
= 10°C/W
Operating Junction Temperature Range (Notes 2, 6)
LT1939EDD........................................ –40°C to 125°C
LT1939IDD......................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
JA
JC(PAD)
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
12-Lead (3mm × 3mm) Plastic DFN
12-Lead (3mm × 3mm) Plastic DFN
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
LT1939EDD#PBF
LT1939IDD#PBF
LT1939EDD#TRPBF
LT1939IDD#TRPBF
LDJZ
LDJZ
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TJ = 25°C. VVIN = 15V, VRT/SYNC = 2V, unless otherwise specified.
PARAMETER
CONDITIONS
MIN
710
1.5
TYP
760
2.5
2
MAX
780
3.5
UNITS
mV
μA
l
SHDN Threshold
SHDN Source Current
SHDN Current Hysterisis
Minimum Input Voltage (Note 3)
Supply Shutdown Current
Supply Quiescent Current
FB Voltage
1.25
3.25
2.8
μA
l
l
V
V
V
= 0V
2.4
12
V
FB
= 0V
30
μA
SHDN
= 0.9V
= 1V
2.5
3.5
mA
FB
l
l
V
VC
0.784
0.776
0.8
0.8
0.816
0.824
V
V
V
= 0.6V to 1.6V, V = 3V to 25V
IN
VC
FB Bias Current
V
= 0.8V, V = 1V
50
250
16
150
350
20
nA
μmho
μA
FB
VC
Error Amplifier g
V
VC
= 1V, I =
10μA
= 0.6V, V = 1V
150
12
m
VC
Error Amplifier Source Current
Error Amplifier Sink Current
Error Amplifier High Clamp
Error Amplifier Switching Threshold
SS Source Current
V
FB
VC
V
V
V
V
= 1V, V = 1V
14
18
22
μA
FB
VC
= 0.6V
= 0.6V
1.8
0.6
2.25
2.0
0.8
2.75
2.2
1.0
3.75
V
FB
V
FB
= 1V, V = 0.4V, V = 0.9V
μA
SHDN
SS
FB
1939f
2
LT1939
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VVIN = 15V, VRT/SYNC = 2V, unless otherwise specified.
PARAMETER
CONDITIONS
MIN
300
400
50
TYP
600
600
100
100
0.1
MAX
900
800
150
120
1
UNITS
μA
SS Sink Current
V
FB
V
FB
V
FB
= 0V, V = 2V
SS
SS POR Sink Current (Note 4)
SS POR Threshold
= 0V, V = 2V, Cycle SHDN
μA
SS
= 0V
mV
mV
μA
SS to FB Offset (V – V
)
FB
V
VC
= 1V, V = 0.4V
70
SS
SS
PG/PG Leakage
PG/ PG Threshold
PG/ PG Hysteresis
PG Sink Current
PG Sink Current
V
= 0.9V/0.7V, V /V = 25V
FB
PG PG
V
V
V
V
V
= 0.4V
= 0.4V
0.685
20
0.708
30
0.730
40
V
PG
mV
μA
PG
= 0.4V, V = 0.7V
250
500
0.75
500
800
0.850
750
1100
0.975
PG
FB
= 0.4V, V = 0.9V
μA
PG
FB
R /SYNC Reference Voltage
T
= 0.9V, R = 15k
RT/SYNC
V
FB1/2
Switching Frequency
R
R
R
= 90.9k
= 90.9k
= 15k
450
425
2
500
500
2.4
550
625
2.8
kHz
kHz
RT/SYNC
RT/SYNC
RT/SYNC
l
l
MHz
SYNC Frequency Range
Minimum Switch On Time
Minimum Switch Off Time
Switch Leakage Current
Switch Saturation Voltage
Switch Peak Current
250
2500
kHz
ns
V
V
V
= 0.7V, R
= 90.9k
= 90.9k
RT/SYNC
140
120
1
FB
RT/SYNC
= 0.7V, R
ns
FB
= 0V
10
μA
mV
SW
I
SW
= 2A, V
= 18V, V = 0.7V
450
BST
FB
V
BST
= 18V, V = 0.7V
2.3
2.1
2.8
2.8
3.5
3.5
A
A
FB
l
Boost Current
I
I
= 2A, V
= 18V, V = 0.7V
20
30
2.2
0.8
0.8
115
115
1.2
13
45
3
mA
V
SW
BST
FB
Minimum Boost Voltage (Note 5)
LFB Voltage
= 2A, V = 0.7V
FB
SW
l
l
V
= 1.2V
0.784
0.776
90
0.816
0.824
140
300
1.6
V
LDRV
LFB Line/Load Regulation
V
= 3V to 25V, V
= 8V
V
VIN
LDRV
SS to LFB Offset (V – V
)
LFB
V
= 1V, V = 0.8V, V
= V
LFB
mV
nA
V
SS
VC
SS
LDRV
LFB Bias Current
V
V
V
= 0.8V, V = 1V
LFB VC
l
l
LDRV Dropout
= 3V, I
= 5mA
LDRV
0.8
9
LDRV
LDRV
LDRV Maximum Current
= 0V
18
mA
Note 4: An internal power-on reset (POR) latch is set on the positive
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note2: The LT1939EDD is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT1939IDD is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 3: Minimum input voltage is defined as the voltage where internal
bias lines are regulated so that the reference voltage and oscillator remain
constant. Actual minimum input voltage to maintain a regulated output
will depend upon output voltage and load current. See Applications
Information.
transition of the SHDN pin through its threshold. The output of the latch
activates a current source on the SS pin which typically sinks 600μA,
discharging the SS capacitor. The latch is reset when the SS pin is driven
below the soft-start POR threshold or the SHDN pin is taken below its
threshold.
Note 5: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 6: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed the maximum operating junction temperature
when overtemperature protection is active. Continuous operation above
the specified maximum operating junction temperature may impair device
reliability.
1939f
3
LT1939
TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown Threshold and Minimum
Input Voltage vs Temperature
Feedback Voltage vs Temperature
RT/SYNC Voltage vs Temperature
3.0
2.5
2.0
1.5
1.10
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
0.92
0.90
0.820
0.815
0.810
0.805
0.800
0.795
0.790
0.785
0.780
MINIMUM INPUT VOLTAGE
R
= 90.9k
RT/SYNC
FB
LFB
1.0
0.5
0
SHUTDOWN THRESHOLD
R
= 15k
25
RT/SYNC
50
100 125 150
50 75
TEMPERATURE (°C)
–50 –25
0
25
75
–50 –25
0
25
100 125 150
–50
50
100 125
150
–25
0
75
TEMPERATURE (°C)
TEMPERATURE (°C)
1939 G03
1939 G01
1939 G02
Shutdown Pin Currents vs
Temperature
Shutdown Quiescent Current vs
Temperature
Error Amplifier gm vs Temperature
400
350
300
250
200
150
100
15.0
12.5
10.0
7.5
5.0
2.5
0
6
5
4
3
2
1
0
V
V
= 0.9V
= 0.7V
SHDN
SHDN
75 100
125 150
75 100
–50
–25
0
25
50
75 100
–50 –25
0
25 50
125 150
–50 –25
0
25 50
125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1939 G06
1939 G05
1939 G04
Soft-Start Source Current vs
Temperature
Soft-Start Feedback Offset vs
Temperature
VC Switching Threshold vs
Temperature
3.5
3.3
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
150
125
100
75
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
LFB
FB
50
0.50
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
–50
50
100 125
150
–25
0
25
75
–50 –25
0
25
TEMPERATURE (°C)
125 150
50 75 100
TEMPERATURE (°C)
1939 G08
1939 G07
1939 G09
1939f
4
LT1939
TYPICAL PERFORMANCE CHARACTERISTICS
Power Good Thresholds vs
Temperature
Power Good Sink Currents vs
Temperature
Frequency vs Temperature
600
580
560
540
520
500
480
460
440
420
400
0.75
0.74
0.73
0.72
0.71
0.70
0.69
0.68
0.67
0.66
0.65
1000
900
800
700
600
500
400
300
200
100
0
R
= 90.9k
RT/SYNC
PG
RISING EDGE
PG
FALLING EDGE
–50
0
25 50 75 100 125 150
TEMPERATURE (°C)
–25
–50
0
25 50 75 100 125 150
TEMPERATURE (°C)
–50
0
25 50 75 100 125 150
TEMPERATURE (°C)
–25
–25
1939 G12
1939 G10
1939 G11
Peak Switch Current vs
Temperature
LDRV Short-Circuit Current vs
Temperature
External Sync Duty Cycle Range
vs External Sync Frequency
3.5
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
20
19
18
17
16
15
14
13
12
11
10
100
90
80
70
60
50
40
30
20
10
0
MAXIMUM DUTY CYCLE
MINIMUM DUTY CYCLE
–50
0
25 50 75 100 125 150
TEMPERATURE (°C)
50
TEMPERATURE (°C)
125 150
–25
–50
0
25
75 100
250
750
2250
–25
1250
1750
SYNCHRONIZATION FREQUENCY (kHz)
1939 G13
1939 G14
19939 G15
Switch Saturation Voltage vs
Switch Current
Minimum Switching Times
Frequency vs RRT/SYNC
300
275
250
225
200
175
150
125
100
75
600
500
2500
2250
2000
1750
1500
1250
1000
750
400
300
MINIMUM ON TIME
–50°C
200
100
0
25°C
500
MINIMUM OFF TIME
250
150°C
50
0
–50
50
100 125
150
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SWITCH CURRENT (A)
–25
0
25
75
0
20 40 60 80 100 120 140 160 180 200
(kΩ)
TEMPERATURE (°C)
R
RT/SYNC
1939 G16
1939 G18
1939 G17
1939f
5
LT1939
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Boost Voltages vs
Temperature
Boost Current vs Switch Current
Minimum Input Voltage
8
7
6
5
4
3
2
1
0
50
45
40
35
30
25
20
15
10
5
2.7
2.5
2.3
2.1
1.9
1.7
1.5
150°C
–50°C
V
= 5V
OUT1
V
= 3.3V
OUT1
MINIMUM BOOST FOR
SWITCH SATURATION
25°C
F
= 1MHz
SW
L = 3.3μH
0
75 100
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
–50 –25
0
25 50
125 150
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
TEMPERATURE (°C)
SWITCH CURRENT (A)
LOAD CURRENT (A)
1939 G19
1939 G20
1939 G21
Inductor Value for 2A Maximum
Load Current (VOUT = 3.3V,
IRIPPLE = 250mA)
LDRV Dropout Voltage vs
Temperature
Switcher Dropout Operation
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
6
5
4
3
2
1
0
2500
I
= 5mA
I
= 1A
L = 1μH
LDRV
L = 1.5μH
OUT1
2250
2000
1750
1500
1250
1000
750
L = 2.2μH
V
= 5V
OUT1
V
= 3.3V
OUT1
L = 3.3μH
L = 4.7μH
L = 6.8μH
L = 10μH
500
250
2.5
3.5
4.0
4.5
5.0
5.5
–50
50
100 125
150
3.0
–25
0
25
75
5
10
15
INPUT VOLTAGE (V)
20
25
INPUT VOLTAGE (V)
TEMPERATURE (°C)
1939 G23
1939 G22
1939 G24
PIN FUNCTIONS
hysteresiscanbeusedasanundervoltagelockout,prevent-
ingtheregulatorfromoperatinguntiltheinputvoltagehas
reached a predetermined level. Force the SHDN pin above
its threshold or let it float for normal operation.
V (Pin1):TheV pinpowerstheinternalcontrolcircuitry
IN
IN
and is monitored by an undervoltage comparator. The V
IN
pinisalsoconnectedtothecollectorsoftheinternalpower
NPN switch and linear output NPN. The V pin has high
IN
dI/dt edges and must be decoupled to ground close to
SS (Pin 3): The SS pin is used to control the slew rate
of the output of both the switching and linear regulators.
A single capacitor from the SS pin to ground determines
the regulators’ ramp rate. For soft-start details see the
Applications Information section.
the pin of the device.
SHDN (Pin 2): The SHDN pin is used to shut down the
LT1939 and reduce quiescent current to a typical value
of 12μA. The accurate 0.76V threshold and input current
1939f
6
LT1939
PIN FUNCTIONS
PG (Pin 4): The power good pin is an open-collector
PG (Pin 7): The power good bar pin is an open-collector
output that sinks current when the FB or LFB rises above
90% of its nominal regulating voltage.
output that sinks current when the FB or LFB falls below
90% of its nominal regulating voltage. For V above 2V,
IN
its output state remains true, although during SHDN, V
IN
FB (Pin 8): The FB pin is the negative input to the switcher
error amplifier. The output switches to regulate this pin to
0.8V with respect to the exposed ground pad. Bias current
flows out of the FB pin.
undervoltage lockout, or thermal shutdown, its current
sink capability is reduced.
V (Pin 5): The V pin is the output of the error amplifier
C
C
and the input to the peak switch current comparator. It is
normally used for frequency compensation, but can also
be used as a current clamp or control loop override. If
LFB (Pin 9): The LFB pin is the negative input to the linear
error amplifier. The L
pin servo’s to regulate this pin to
DRV
0.8V with respect to the exposed ground pad. Bias current
flows out of the LFB pin.
the error amplifier drives V above the maximum switch
C
current level, a voltage clamp activates. This indicates that
the output is overloaded and current to be pulled from the
SS pin reducing the regulation point.
LDRV (Pin 10): The LDRV pin is the emitter of an inter-
nal NPN that can be configured as an output of a linear
regulator or as the drive for an external NPN high current
regulator. Current flows out of the LDRV pin when the
LFB pin voltage is below 0.8V. The LDRV pin has a typical
maximum current capability of 13mA.
R /SYNC (Pin 6): This R /SYNC pin provides two modes
T
T
of setting the constant switch frequency.
Connecting a resistor from the R /SYNC pin to ground
T
will set the R /SYNC pin to a typical value of 1V. The
T
BST (Pin 11): The BST pin provides a higher than V base
IN
resultant switching frequency will be set by the resistor
value. The minimum value of 15kꢀ and maximum value
of 200kꢀ set the switching frequency to 2.5MHz and
250kHz respectively.
drive to the power NPN to ensure a low switch drop. A
comparator to V imposes a minimum off time on the SW
IN
pin if the BST pin voltage drops too low. Forcing a SW off
time allows the boost capacitor to recharge.
Driving the R /SYNC pin with an external clock signal
T
SW (Pin 12): The SW pin is the emitter of the on-chip
power NPN. At switch off, the inductor will drive this pin
below ground with a high dV/dt. An external catch diode to
will synchronize the switch to the applied frequency.
Synchronization occurs on the rising edge of the clock
signal after the clock signal is detected. Each rising clock
edge initiates an oscillator ramp reset. A gain control loop
servos the oscillator charging current to maintain a con-
stantoscillatoramplitude. Hence, theslopecompensation
remains unchanged. If the clock signal is removed, the
oscillator reverts to resistor mode and reapplies the 1V
ground, closetotheSWpinandrespectiveV decoupling
IN
capacitor’s ground, must be used to prevent this pin from
excessive negative voltages.
Exposed Pad (Pin 13): GND. The Exposed Pad is the
only ground connection for the device. The Exposed Pad
should be soldered to a large copper area to reduce ther-
mal resistance. The GND pin also serves as small-signal
ground. For ideal operation all small-signal ground paths
should connect to the GND pin at a single point, avoiding
any high current ground returns.
biastotheR /SYNCpinafterthesynchronizationdetection
T
circuitry times out. The clock source impedance should
be set such that the current out of the R /SYNC pin in
T
resistor mode generates a frequency roughly equivalent
to the synchronization frequency. Floating or holding the
R /SYNC pin above 1.1V will not damage the device, but
T
will halt oscillation.
1939f
7
LT1939
BLOCK DIAGRAM
1939f
8
LT1939
OPERATION
The LT1939 is a constant frequency, current mode buck
converter with an internal 2.3A switch plus a linear regula-
tor with 13mA output capability. Control of both outputs
is achieved with a common SHDN pin, internal regulator,
oscillator, undervoltage detect, soft-start, thermal shut-
down and power-on reset.
the V pin is driven low disabling switching and the soft-
C
start latch is reset. Once the latch is reset the soft-start
capacitor starts to charge with a typical value of 2.75μA.
As the voltage rises above 100mV on the SS pin, the V
C
pin will be driven high by the error amplifier. When the
voltageontheV pinexceeds0.8V,theclockset-pulsesets
C
If the SHDN pin is taken below its 0.8V threshold, the
LT1939 will be placed in a low quiescent current mode.
In this mode the LT1939 typically draws 12μA from the
the driver flip-flop which turns on the internal power NPN
switch. This causes current from V , through the NPN
IN
switch, inductor and internal sense resistor, to increase.
When the voltage drop across the internal sense resistor
exceeds a predetermined level set by the voltage on the
V pin.
IN
When the SHDN pin is floated or driven above 0.76V, the
internal bias circuits turn on generating an internal regu-
V pin, the flip-flop is reset and the internal NPN switch
C
is turned off. Once the switch is turned off the inductor
will drive the voltage at the SW pin low until the external
Schottky diode starts to conduct, decreasing the current
in the inductor. The cycle is repeated with the start of each
clock cycle. However, if the internal sense resistor voltage
exceedsthepredeterminedlevelatthestartofaclockcycle,
theflip-flopwillnotbesetresultinginafurtherdecreasein
inductor current. Since the output current is controlled by
lated voltage, 0.8(V ) and 1V(R /SYNC) references, and
FB
T
a POR signal which sets the soft-start latch.
As the R /SYNC pin reaches its 1V regulation point, the
T
internal oscillator will start generating a clock signal at a
frequency determined by the resistor from the R /SYNC
T
pin to ground. Alternatively, if a synchronization signal is
detected by the LT1939 at the R /SYNC pin, a clock signal
T
will be generated at the incoming frequency on the rising
edge of the synchronization pulse. In addition, the internal
slope compensation will be automatically adjusted to pre-
vent subharmonic oscillation during synchronization.
the V voltage, output regulation is achieved by the error
C
amplifier continually adjusting the V pin voltage.
C
The error amplifier is a transconductance amplifier that
comparestheFBvoltagetoeithertheSSpinvoltageminus
100mV or an internally regulated 800mV, whichever is
lowest. Compensation of the loop is easily achieved with
a simple capacitor or series resistor/capacitor from the
The LT1939 is a constant frequency, current mode step-
down converter. Current mode regulators are controlled
by an internal clock and two feedback loops that control
the duty cycle of the power switch. In addition to the
normal error amplifier, there is a current sense amplifier
that monitors switch current on a cycle-by-cycle basis.
This technique means that the error amplifier commands
current to be delivered to the output rather than voltage.
V pin to ground.
C
Since the SS pin is driven by a constant current source, a
singlecapacitoronthesoft-startpinwillgeneratecontrolled
linear ramp on the output voltage.
If the current demanded by the output exceeds the maxi-
A voltage fed system will have low phase shift up to the
resonant frequency of the inductor and output capacitor,
thenanabrupt180°shiftwilloccur.Thecurrentfedsystem
will have 90° phase shift at a much lower frequency, but
will not have the additional 90° shift until well beyond
the LC resonant frequency. This makes it much easier to
frequency compensate the feedback loop and also gives
much quicker transient response.
mum current dictated by the V pin clamp, the SS pin
C
will be discharged, lowering the regulation point until the
outputvoltagecanbesupportedbythemaximumcurrent.
When overload is removed, the output will soft-start from
the overload regulation point.
V
undervoltage detection or thermal shutdown will
IN
set the soft-start latch, resulting in a complete soft-start
sequence.
During power up, the POR signal sets the soft-start latch,
which discharges the SS pin to ensure proper start-up
operation. When the SS pin voltage drops below 100mV,
The switch driver operates from either the V or BST volt-
IN
age. An external diode and capacitor are used to generate
1939f
9
LT1939
OPERATION
a drive voltage higher than V to saturate the output NPN
and maintain high efficiency.
A power good comparator with 30mV of hysteresis trips
when both FB and LFB are above 90% of the 0.8V refer-
ence. The PG output is an open collector NPN that is off
when the output is in regulation allowing a resistor to pull
the PG pin to a desired voltage. The PG output is an open-
collector NPN that is on when the output is in regulation
providing either drive for an output disconnect transistor
or inverted power good logic.
IN
In addition to the switching regulator, the LT1939 contains
a NPN linear regulator with a 0.8V reference, and 13mA
current capability. The 0.8 reference will track the SS pin
in the same manner as the switching regulator. The linear
output can also be configured to drive an external NPN to
provide a linear regulator with higher current capability.
APPLICATIONS INFORMATION
Choosing the Output Voltage
maximum recommended frequency can be approximated
by the equation:
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the 1% resis-
tors according to:
VOUT1 + VD
1
Frequency (Hz)=
•
VIN ꢀ VSW + VD tON(MIN)
V
0.8V
ꢀ
ꢁ
ꢃ
ꢄ
R1=R2 OUT1 –1
ꢂ
ꢅ
where
V
D is the forward voltage drop of the catch diode
(D1 Figure 1),
V
SW is the voltage drop of the internal
switch, and t
switch, all at maximum load current.
is the minimum on time of the
ON(MIN)
R2 should be 10.0k or less to avoid bias current errors.
Reference designators refer to the Block Diagram in
Figure 1.
2500
2250
2000
1750
1500
1250
1000
750
Choosing the Switching Frequency
The LT1939 switching frequency is set by resistor R5 in
Figure 1. The R /SYNC pin is internally regulated at 1V.
T
Setting resistor R5 sets the current in the R /SYNC pin
T
which determines the oscillator frequency as illustrated
in Figure 2.
500
250
The switching frequency is typically set as high as pos-
sible to reduce overall solution size. The LT1939 employs
techniques to enhance dropout at high frequencies but
efficiency and maximum input voltage decrease due to
switching losses and minimum switch on times. The
0
0
20 40 60 80 100 120 140 160 180 200
(kΩ)
R
RT/SYNC
1939 G17
Figure 2. Frequency vs RT/SYNC Resistance
1939f
10
LT1939
APPLICATIONS INFORMATION
The following example along with the data in Table 1
illustrates the tradeoffs of switch frequency selection.
where V
and
is the voltage drop of the internal switch,
SW
DC
= 1 – t
• Frequency.
OFF(MIN)
Example.
MAX
Figure 3 shows a typical graph of minimum input voltage
vs load current for 3.3V and 5V applications.
V = 25V, V
= 3.3V, I
= 2A,
OUT1
IN
OUT1
Temperature = 0°C to 85°C
The maximum input voltage is determined by the absolute
t
= 185ns (85°C from Typical Characteris-
tOicNs(MIN)
graph),
VD = 0.6V,
V
SW = 0.4V (85°C)
maximum ratings of the V and BST pins and by the
IN
frequency and minimum duty cycle.
3.3+ 0.6
25ꢀ 0.4+ 0.6 185ns
1
The minimum duty cycle is defined as:
Max Frequency =
•
~835kHz
DC
= t
• Frequency
MIN
ON(MIN)
R /SYNC ~ 49.9k
T
Maximum input voltage as:
Frequency ≅ 820kHz
V
OUT1 + V
DCMIN
V
=
D ꢀ VD + VSW
IN(MAX)
Input Voltage Range
Once the switching frequency has been determined, the
input voltage range of the regulator can be determined.
The minimum input voltage is determined by either the
LT1939’s minimum operating voltage of ~2.8V or by its
maximum duty cycle. The duty cycle is the fraction of time
that the internal switch is on during a clock cycle. The
maximum duty cycle can be determined from the clock
frequency and the minimum off time from the typical
characteristics graph.
8
7
6
5
4
3
2
F
= 1MHz
SW
L = 3.3μH
V
V
V
V
= 5V START-UP
= 5V RUNNING
= 3.3V START-UP
= 3.3V RUNNING
OUT1
OUT1
OUT1
OUT1
This leads to a minimum input voltage of:
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LOAD CURRENT (A)
V
OUT1 + V
DCMAX
V
=
D ꢀ VD + VSW
1939 F03
IN(MIN)
Figure 3. Minimum Input Voltage vs Load Current
Table 1. Efficiency and Size Comparisons for Different RRT/SYNC Values, 3.3V Output
FREQUENCY
R /SYNC
T
EFFICIENCY
V
L
C
C + L AREA
IN(MAX)
2
(mm )
2.5MHz
2.0MHz
1.5MHz
1.0MHz
500kHz
15k
20k
73.6
81.5
84.5
87.3
88.9
12
14
18
25
25
1μ
10μ
10μ
10μ
22μ
47μ
24
24
24
34
40
1.5μ
2.2μ
3.3μ
4.7μ
24.9k
40.2k
90.9k
1939f
11
LT1939
APPLICATIONS INFORMATION
a physically smaller inductor, or one with a lower DCR
resulting in higher efficiency.
Note that the LT1939 will regulate if the input voltage is
taken above the calculated maximum voltage as long as
maximum ratings of the V and BST pins are not violated.
IN
The current in the inductor is a triangle wave with an
average value equal to the load current. The peak switch
current is equal to the output current plus half the peak-to
peak inductor ripple current. The LT1939 limits its switch
current in order to protect itself and the system from
overload faults. Therefore, the maximum output current
that the LT1939 will deliver depends on the current limit,
the inductor value, switch frequency, and the input and
output voltages. The inductor is chosen based on output
currentrequirements, outputvoltageripplerequirements,
size restrictions and efficiency goals.
Howeveroperationinthisregionofinputvoltagewillexhibit
pulse skipping behavior.
Example:
V
= 3.3V, I
= 1A, Frequency = 1MHz,
OUT1
OUT1
Temperature = 25°C,
V
= 0.3V, V = 0.4V, t
= 150ns,
ON(MIN)
SW
D
t
= 110ns
OFF(MIN)
DCMAX =1ꢀ(110ns)1MHz = 89%
3.3+ 0.4
0.89
When the switch is off, the inductor sees the output volt-
age plus the catch diode drop. This gives the peak-to-peak
ripple current in the inductor:
V
=
ꢀ 0.4+ 0.3= 4.06V
IN(MIN)
DCMIN = tON(MIN) •Frequency =15%
1ꢁDC VOUT1 + VD
(
)
(
)
3.3+ 0.4
0.15
ꢀIL =
V
=
ꢀ 0.4+ 0.3 = 24.57V
L • f
IN(MAX)
where f is the switching frequency of the LT1939 and L
is the value of the inductor. The peak inductor and switch
current is:
Inductor Selection and Maximum Output Current
A good first choice for the inductor value is:
ꢀIL
2
(V ꢀ VOUT1)• VOUT1
IN
ISW(PK) =ILPK =IOUT1 +
L =
V • f
IN
To maintain output regulation, this peak current must be
less than the LT1939’s switch current limit, I . I is
guaranteed to be greater than 2.3A over the entire duty
cycle range. The maximum output current is a function
of the chosen inductor value:
where f is frequency in MHz and L is in μH.
LIM LIM
With this value the maximum load current will be ~2A,
independent of input voltage. The inductor’s RMS current
rating must be greater than your maximum load current
and its saturation current should be about 30% higher. To
keep efficiency high, the series resistance (DCR) should
be less than 0.05ꢀ.
ꢁI
2
ꢁIL
2
I
OUT1(MAX) =ILIM ꢀ L =2.3–
If the inductor value is chosen so that the ripple current
is small, then the available output current will be near the
switch current limit.
Forapplicationswithadutycycleofabout50%, theinduc-
tor value should be chosen to obtain an inductor ripple
current less than 40% of peak switch current.
One approach to choosing the inductor is to start with the
simple rule given above, look at the available inductors
and choose one to meet cost or space goals. Then use
these equations to check that the LT1939 will be able to
deliver the required output current. Note again that these
equations assume that the inductor current is continuous.
Ofcourse,suchasimpledesignguidewillnotalwaysresult
intheoptimuminductorforyourapplication.Alargervalue
provides a slightly higher maximum load current, and will
reduce the output voltage ripple. If your load is lower than
1.5A, then you can decrease the value of the inductor and
operate with higher ripple current. This allows you to use
1939f
12
LT1939
APPLICATIONS INFORMATION
Discontinuous operation occurs when I
is less than
capacitor is required to reduce the resulting voltage
ripple at the LT1939 and to force this very high frequency
switching current into a tight local loop, minimizing EMI.
The input capacitor must have low impedance at the
switching frequency to do this effectively, and it must
have an adequate ripple current rating.
OUT
I /2 as calculated above.
L
Figure 4 illustrates the inductance value needed for a 3.3V
output with a maximum load capability of 2A. Referring
to Figure 4, an inductor value between 3.3μH and 4.7μH
will be sufficient for a 15V input voltage and a switch
frequency of 750kHz. There are several graphs in the
Typical Performance Characteristics section of this data
sheet that show inductor selection as a function of input
voltage and switch frequency for several popular output
voltages and output ripple currents. Also, low inductance
may result in discontinuous mode operation, which is
okay, but further reduces maximum load current. For
details of maximum output current and discontinuous
mode operation, see Linear Technology Application Note
A conservative value is the RMS input current is given
by:
ꢁ
ꢃ0.5
IOUT1 VOUT1 • V ꢀ V
(
)
IOUT1
2
IN
OUT1
ꢂ
ꢄ
ICIN(RMS)
=
<
V
IN
and is largest when V = 2V
(50% duty cycle).
IN
OUT1
The frequency, V to V
ratio, and maximum load
OUT
IN
current requirement of the LT1939 along with the input
supply source impedance, determine the energy storage
requirements of the input capacitor. Determine the worst-
case condition for input ripple current and then size the
input capacitor such that it reduces input voltage ripple to
an acceptable level. Typical values for input capacitors run
from10μFatlowfrequenciesto2.2μFathigherfrequencies.
The combination of small size and low impedance (low
equivalentseriesresistanceorESR)ofceramiccapacitors
make them the preferred choice. The low ESR results in
verylowvoltagerippleandthecapacitorscanhandleplenty
of ripple current. They are also comparatively robust and
can be used in this application at their rated voltage. X5R
and X7R types are stable over temperature and applied
voltage,andgivedependableservice.Othertypes(Y5Vand
Z5U) have very large temperature and voltage coefficients
of capacitance, so they may have only a small fraction of
their nominal capacitance in your application. While they
will still handle the RMS ripple current, the input voltage
ripple may become fairly large, and the ripple current may
end up flowing from your input supply or from other by-
pass capacitors in your system, as opposed to being fully
sourced from the local input capacitor. An alternative to a
high value ceramic capacitor is a lower value along with
a larger electrolytic capacitor, for example a 1μF ceramic
capacitor in parallel with a low ESR tantalum capacitor.
For the electrolytic capacitor, a value larger than 10μF will
be required to meet the ESR and ripple current require-
ments. Because the input capacitor is likely to see high
44. Finally, for duty cycles greater than 50% (V /V
OUT IN
> 0.5), there is a minimum inductance required to avoid
subharmonic oscillations. See Application Note 19 for
more information.
2500
2250
L = 1.5μH
L = 1μH
2000
1750
L = 2.2μH
L = 3.3μH
1500
1250
1000
750
L = 4.7μH
L = 6.8μH
500
250
5
10
15
INPUT VOLTAGE (V)
20
25
1939 F04
Figure 4. Inductor Values for 2A Maximum Load Current
(VOUT1 = 3.3V, IRIPPLE = 1A)
Input Capacitor Selection
Bypass the input of the LT1939 circuit with a 4.7μF or
higher ceramic capacitor of X7R or X5R type. A lower
value or a less expensive Y5V type can be used if there
is additional bypassing provided by bulk electrolytic or
tantalum capacitors. The following paragraphs describe
the input capacitor considerations in more detail.
Step-down regulators draw current from the input sup-
ply in pulses with very fast rise and fall times. The input
1939f
13
LT1939
APPLICATIONS INFORMATION
surge currents when the input source is applied, tantalum
capacitors should be surge rated. The manufacturer may
also recommend operation below the rated voltage of the
capacitor. Be sure to place the 1μF ceramic as close as
are free to use ceramic capacitors to achieve very low
output ripple and small circuit size. Estimate output ripple
with the following equations:
ꢀIL
possible to the V and GND pins on the IC for optimal
VRIPPLE
=
IN
8 •Frequency •COUT1
For ceramic capacitors and,
= ΔI • ESR
noise immunity.
A final caution regarding the use of ceramic capacitors for
input bypassing. A ceramic input capacitor can combine
with stray inductance to form a resonant tank circuit. If
power is applied quickly (for example, by plugging the
circuitintoalivepowersource)thistankcanring,doubling
theinputvoltageanddamagingtheLT1939.Thesolutionis
toeitherclamptheinputvoltageordampenthetankcircuit
by adding a lossy capacitor in parallel with the ceramic
capacitor. For details see Application Note 88.
V
RIPPLE
L
For electrolytic (tantalum and aluminum)
where ΔI is the peak-to-peak ripple current in the
L
inductor.
The RMS content of this ripple is very low, and the RMS
current rating of the output capacitor is usually not of
concern.
Output Capacitor Selection
Another constraint on the output capacitor is that it must
havegreaterenergystoragethantheinductor;ifthestored
energy in the inductor is transferred to the output, you
would like the resulting voltage step to be small compared
totheregulationvoltage. Fora5%overshoot, thisrequire-
ment becomes:
Typicallystep-downregulatorsareeasilycompensatedwith
an output crossover frequency that is 1/10 of the switch-
ing frequency. This means that the time that the output
capacitor must supply the output load during a transient
step is ~2 or 3 switching periods. With an allowable 5%
drop in output voltage during the step, a good starting
value for the output capacitor can be expressed by:
ꢀ
ꢃ2
ꢅ
ILIM
COUT1 >10 •L
ꢂ
V
OUT1ꢄ
ꢁ
Max Load Step
Frequency •0.05• VOUT1
CVOUT1
=
Finally,theremustbeenoughcapacitanceforgoodtransient
performance.Thelastequationgivesagoodstartingpoint.
Alternatively, you can start with one of the designs in this
datasheetandexperimenttogetthedesiredperformance.
This topic is covered more thoroughly in the section on
loop compensation.
Example:
V
OUT1
= 3.3V, Frequency = 1MHz, Max Load Step = 2A
2
CVOUT1
=
=12μF
1MHz •0.05•3.3
The high performance (low ESR), small size and robust-
ness of ceramic capacitors make them the preferred type
for LT1939 applications. However, all ceramic capacitors
are not the same. As mentioned above, many of the high
value capacitors use poor dielectrics with high tempera-
ture and voltage coefficients. In particular, Y5V and Z5U
types lose a large fraction of their capacitance with ap-
plied voltage and temperature extremes. Because the loop
stability and transient response depend on the value of
The calculated value is only a suggested starting value.
Increasethevalueiftransientresponseneedsimprovement
or reduce the capacitance if size is a priority. The output
capacitor filters the inductor current to generate an output
with low voltage ripple. It also stores energy in order to
satisfytransientloadsandtostabilizetheLT1939’scontrol
loop. The switching frequency of the LT1939 determines
the value of output capacitance required. Also, the current
mode control loop doesn’t require the presence of output
capacitor series resistance (ESR). For these reasons, you
C
, you may not be able to tolerate this loss. Use X7R
OUT
and X5R types. You can also use electrolytic capacitors.
1939f
14
LT1939
APPLICATIONS INFORMATION
typical value of 3A, determined by the peak switch current
limit of the LT1939. This is safe for short periods of time,
but it would be prudent to check with the diode manu-
facturer if continuous operation under these conditions
can be tolerated.
The ESRs of most aluminum electrolytics are too large to
deliver low output ripple. Tantalum and newer, lower ESR
organic electrolytic capacitors intended for power supply
use, are suitable and the manufacturers will specify the
ESR. The choice of capacitor value will be based on the
ESR required for low ripple. Because the volume of the
capacitor determines its ESR, both the size and the value
will be larger than a ceramic capacitor that would give you
similar ripple performance. One benefit is that the larger
capacitance may give better transient response for large
changes in load current.
BST Pin Considerations
The capacitor and diode tied to the BST pin generate
a voltage that is higher than the input voltage. In most
cases a 0.47μF capacitor and fast switching diode (such
as the CMDSH-3 or FMMD914) will work well. Almost
any type of film or ceramic capacitor is suitable, but the
ESR should be <1ꢀ to ensure it can be fully recharged
during the off time of the switch. The capacitor value can
be approximated by:
Catch Diode
The diode D1 conducts current only during switch off
time. Use a Schottky diode to limit forward voltage drop to
increase efficiency. The Schottky diode must have a peak
reverse voltage that is equal to regulator input voltage and
sized for average forward current in normal operation.
Average forward current can be calculated from:
IOUT1(MAX) •DC
CBST
=
50 • VOUT1 ꢀ VBST(MIN) • f
(
)
where I
BST(MIN)
the switch.
is the maximum load current, and
OUT1(MAX)
I
OUT1 • V ꢀ V
V
is the minimum boost voltage to fully saturate
ID(AVG)
=
(
)
IN
OUT1
VIN
Figure 5 shows four ways to arrange the boost circuit.
The BST pin must be more than 2.2V above the SW pin
for full efficiency.
The only reason to consider a larger diode is the worst-
case condition of a high input voltage and shorted output.
With a shorted condition, diode current will increase to a
V
V
LDRV
BST
SW
V
V
IN
LDRV
BST
SW
IN
IN
IN
D2
LT1939
LT1939
C3
D1
D2
C3
D1
V
V
OUT1
OUT1
V
V
– V = V
V
V
– V = V
BST SW IN
BST(MAX)
BST
SW
OUT1
= V + V
= 2 • V
IN
BST(MAX)
IN
OUT1
(5a)
(5b)
V
V
V
V
LDRV
V
V
LDRV
BST
SW
OUT2
OUT1
IN
IN
IN
IN
D2
D2
LT1939
LT1939
V
> V + 3V
IN
BST
SW
X
C3
D1
V
OUT1
D1
V
– V = V
V
V
– V = V
BST SW X
= V
BST(MAX) X
BST
SW
OUT2
1939 F05
V
= V + V
BST(MAX)
IN
OUT2
V
≥ 2.5V
OUT2
(5c)
(5d)
Figure 5. BST Pin Considerations
1939f
15
LT1939
APPLICATIONS INFORMATION
cases the discharged output capacitor will present a load
to the switcher which will allow it to start. The plots show
Generally, for outputs of 3.3V and higher the standard
circuit (Figure 5a) is the best. For outputs between 2.8V
and 3.3V, replace the D2 with a small Schottky diode such
as the PMEG4005.
theworst-casesituationwhereV isrampingveryslowly.
IN
Use a Schottky diode for the lowest start-up voltage.
For lower output voltages the boost diode can be tied to
the input (Figure 5b). The circuit in Figure 5a is more ef-
ficient because the BST pin current comes from a lower
voltage source.
Frequency Compensation
The LT1939 uses current mode control to regulate the
output.Thissimplifiesloopcompensation.Inparticular,the
LT1939 does not require the ESR of the output capacitor
for stability so you are free to use ceramic capacitors to
achieve low output ripple and small circuit size. Frequency
compensation is provided by the components tied to the
Figure 5c shows the boost voltage source from the linear
output that is set to greater than 2.5V (any available DC
sourcesthataregreaterthan2.5Vissufficient).Thehighest
efficiency is attained by choosing the lowest boost volt-
age above 2.5V. You must also be sure that the maximum
voltage at the BST pin is less than the maximum specified
in the Absolute Maximum Ratings section.
V pin. Generally a capacitor and a resistor in series to
C
ground determine loop gain. In addition, there is a lower
value capacitor in parallel. This capacitor is not part of
the loop compensation but is used to filter noise at the
switching frequency.
The boost circuit can also run directly from a DC voltage
that is higher than the input voltage by more than 2.5V, as
in Figure 5d. The diode is used to prevent damage to the
Loop compensation determines the stability and transient
performance.Designingthecompensationnetworkisabit
complicatedandthebestvaluesdependontheapplication
and in particular the type of output capacitor. A practical
approach is to start with one of the circuits in this data
sheet that is similar to your application and tune the com-
pensation network to optimize the performance. Stability
should then be checked across all operating conditions,
including load current, input voltage and temperature.
LT1939 in case V is held low while V is present. The
X
IN
circuit eliminates a capacitor, but efficiency may be lower
and dissipation in the LT1939 may be higher. Also, if V is
X
absent, the LT1939 will still attempt to regulate the output,
but will do so with very low efficiency and high dissipation
because the switch will not be able to saturate, dropping
1.5V to 2V in conduction.
The minimum input voltage of an LT1939 application is
limited by the minimum operating voltage (<2.8V) and by
the maximum duty cycle as outlined above. For proper
start-up, the minimum input voltage is also limited by
the boost circuit. If the input voltage is ramped slowly, or
the LT1939 is turned on with its SS pin when the output
is already in regulation, then the boost capacitor may not
be fully charged. Because the boost capacitor is charged
with the energy stored in the inductor, the circuit will rely
on some minimum load current to get the boost circuit
running properly. This minimum load will depend on
input and output voltages and on the arrangement of the
boost circuit.
The LT1375 data sheet contains a more thorough discus-
sion of loop compensation and describes how to test the
stability using a transient load.
Figure6showsanequivalentcircuitfortheLT1939control
loop. The error amp is a transconductance amplifier with
finite output impedance. The power section, consisting of
the modulator, power switch, and inductor, is modeled as
a transconductance amplifier generating an output cur-
rent proportional to the voltage at the V pin. Note that
C
the output capacitor integrates this current, and that the
capacitor on the V pin (C ) integrates the error ampli-
C
C
fier output current, resulting in two poles in the loop. In
most cases a zero is required and comes from either the
The Typical Performance Characteristics section shows
plots of the minimum load current to start and to run as a
function of input voltage for 3.3V and 5V outputs. In many
output capacitor ESR or from a resistor in series with C .
C
This simple model works well as long as the value of the
inductor is not too high and the loop crossover frequency
1939f
16
LT1939
APPLICATIONS INFORMATION
LT1939
CURRENT MODE
POWER STAGE
SW
12
8
V
OUT1
g
= 3mho
m
C
R1
R2
PL
ESR
C1
FB
–
+
V
C
5
C1
0.8V
TANTALUM
OR
POLYMER
C
C
F
C
4M
ERROR AMP
m
CERAMIC
g
= 250μmhos
R
C
1939 F06
Figure 6. Model for Loop Response
and 200k until the synchronization circuitry is active for
proper start-up operation.
is much lower than the switching frequency. A phase lead
capacitor (C ) across the feedback divider may improve
PL
the transient response.
Ifthesynchronizationsignalpowersupinanundetermined
state (V , V , Hi-Z), connect the synchronization clock
OL OH
Synchronization
to the LT1939 as shown in Figure 7. The circuit as shown
will isolate the synchronization signal when the output
voltage is below 90% of the regulated output. The LT1939
will start-up with a switching frequency determined by the
The R /SYNC pin can be used to synchronize the LT1939
T
to an external clock source. Driving the R /SYNC resistor
T
with a clock source triggers the synchronization detection
circuitry.Oncesynchronizationisdetected,therisingedge
resistor from the R /SYNC pin to ground.
T
ofSWwillbesynchronizedtotherisingedgeoftheR /SYNC
T
pin signal. An AGC loop will adjust slope compensation
LDRV
LT1939
V
CC
to avoid subharmonic oscillation.
SYNCHRONIZATION
CIRCUITRY
PG
R /SYNC
The synchronizing clock signal input to the LT1939 must
have a frequency between 250kHz and 2.5MHz, a duty
cycle between 20% and 80%, a low state below 0.5V and
a high state above 1.6V. Synchronization signals outside
of these parameters will cause erratic switching behavior.
T
CLK
1939 F07
Figure 7. Synchronous Signal Powered from Regulator’s Output
The R /SYNC resistor should be set such that the free
T
running frequency ((V
– V )/R
SYNCLO
) is
RT/SYNC
RT/SYNC
Ifthesynchronizationsignalpowersupinalowimpedance
approximately equal to the synchronization frequency. If
the synchronization signal is halted, the synchronization
detection circuitry will timeout in typically 10μs at which
time the LT1939 reverts to the free-running frequency
state (V ), connect a resistor between the R /SYNC pin
OL
T
and the synchronizing clock. The equivalent resistance
seen from the R /SYNC pin to ground will set the start-up
T
frequency.
based on the current through R /SYNC. If the R /SYNC
T
T
resistor is held above 1.6V at any time, switching will be
Ifthesynchronizationsignalpowersupinahighimpedance
disabled.
state (Hi-Z), connect a resistor from the R /SYNC pin to
T
ground. The equivalent resistance seen from the R /SYNC
T
If the synchronization signal is not present during regu-
lator start-up (for example, the synchronization circuitry
pin to ground will set the start-up frequency.
is powered from the regulator output) the R /SYNC pin
If the synchronization signal changes between high and
T
must see an equivalent resistance to ground between 15k
lowimpedancestatesduringpowerup(V ,Hi-Z),connect
OL
1939f
17
LT1939
APPLICATIONS INFORMATION
the synchronization circuitry to the LT1939 as shown in
theTypicalApplicationssection. ThiswillallowtheLT1939
to start up with a switching frequency determined by the
0.76
VH ꢀ 0.76
R2=
+ 2.5μA
R1
equivalent resistance from the R /SYNC pin to ground.
T
V = Turn-on threshold
H
Shutdown and Undervoltage Lockout
V = Turn-off threshold
L
Figure8showshowtoaddanundervoltagelockout(UVLO)
to the LT1939. Typically, UVLO is used in situations where
the input supply is current limited, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
loadtothesourceandcancausethesourcetocurrentlimit
or latch low under low source voltage conditions. UVLO
prevents the regulator from operating at source voltages
where these problems might occur.
Example:switchingshouldnotstartuntiltheinputisabove
4.75V and is to stop if the input falls below 3.75V.
V = 4.75V
H
V = 3.75V
L
4.75ꢀ 3.75
R1=
R2=
~499k
2μA
0.76
4.75ꢀ 0.76
~71.5k
+ 2.5μA
499k
V
IN
1
Keep the connections from the resistors to the SHDN
pin short and make sure that the interplane or surface
capacitance to switching nodes is minimized. If high re-
sistor values are used, the SHDN pin should be bypassed
with a 1nF capacitor to prevent coupling problems from
the switch node.
2.5μA
R1
R2
2μA
SHDN
2
+
–
0.76V
1939 F08
C1
Soft-Start
Figure 8. Undervoltage Lockout
The outputs of the LT1939 regulate to either the SS pin
voltage minus 100mV or an internally regulated 800mV,
whicheverislowest. AcapacitorfromtheSSpintoground
is charged by an internal 2.75μA current source resulting
in a linear output ramp from 0V to the regulated output
whose duration is given by:
An internal comparator will force the part into shutdown
below the minimum V of 2.8V. This feature can be
IN
used to prevent excessive discharge of battery-operated
systems.
If an adjustable UVLO threshold is required, the SHDN
pin can be used. The threshold voltage of the SHDN pin
comparator is 0.76V. A 2.5μA internal current source de-
faults the open-pin condition to be operating (see Typical
PerformanceCharacteristics).Currenthysteresisisadded
above the SHDN threshold. This can be used to set voltage
hysteresis of the UVLO using the following:
CSS •0.9V
2.75μA
tRAMP
=
At power-up, a reset signal sets the soft-start latch and
discharges the SS pin to approximately 0V to ensure
proper start-up. When the SS pin is fully discharged the
latch is reset and the internal 2.75μA current source starts
to charge the SS pin.
VH ꢀ VL
R1=
2μA
1939f
18
LT1939
APPLICATIONS INFORMATION
The PG pin has a sink capability of 400μA when the FB and
LFB pins are below the threshold and can withstand 25V
when the outputs are in regulation. The PG pin is typically
connected to the output with a resistor and is used as an
errorflag. Theresistorvalueshouldbechosentoallowthe
PG voltage to drop below 0.4V in an error condition.
When the SS pin voltage is below 100mV, the V pin is
C
pulled low which disables switching. As the SS pin voltage
rises above 100mV, the V pin is released and the outputs
C
are regulated to the SS voltage. When the SS pin voltage
minus 100mV exceeds the internal 0.8V reference, the
outputs are regulated to the reference. The SS pin voltage
will continue to rise until it is clamped at 2V.
Example:
In the event of a V undervoltage lockout, the SHDN pin
IN
V
= 5V, PGSINK
= 200μA
(MIN)
OUT1
drivenbelow0.8V,ortheinternaldietemperatureexceeding
itsmaximumratingduringnormaloperation,thesoft-start
latch is set, triggering a start-up sequence.
R
= (5 – 0.4)/200μA = 23kꢀ
PG
The PG pin has a sink capability of 800μA when the FB
and LFB pins are above the threshold and can withstand
25V when the outputs are not in regulation. The PG pin is
typically used as a drive signal for an output disconnect
device. The PG pull-up resistor should be sized in the
same manner as the PG pull-up resistor.
Inaddition,iftheloadexceedsthemaximumoutputswitch
current (switching regulator only), the output will start to
drop causing the V pin clamp to be activated. As long as
C
the V pin is clamped, the SS pin will be discharged. As
C
a result, the output will be regulated to the highest volt-
age that the maximum output current can support. For
example, if a 6V output is loaded by 1ꢀ the SS pin will
drop to 0.5V, regulating the output at 3V (typical current
limit time load, 3A • 1ꢀ). Once the overload condition is
removed, the output will soft-start from the temporary
voltage level to the normal regulation point.
Linear Regulator
The LT1939 contains an error amplifier and a NPN output
device which can be configured as a linear regulator or as
a linear regulator controller.
With the LFB and LDRV pins configured as shown in
Figure 1, the LDRV pin outputs a regulated voltage with a
typical current limit of 13mA.
Since the SS pin is clamped at 2V and has to discharge to
0.9V before taking control of regulation, momentary over-
loadconditionswillbetoleratedwithoutasoft-startrecov-
ery. The typical time before the SS pin takes control is:
The LDRV voltage is programmed with a resistor divider
between the output and the LFB pin. Choose the 1% resis-
tors according to:
CSS •1.1V
600μA
tSS(CONTROL)
=
V
0.8V
ꢀ
ꢃ
LDRV
R3=R4
–1
ꢅ
ꢂ
ꢁ
ꢄ
Power Good Indicators
R4 should be 10.0k or less to avoid bias current errors.
Reference designators refer to the Block Diagram in
Figure 1.
The PG and PG pins are collector outputs of an internal
comparator. The comparator compares the voltages of
the FB and LFB pins to 90% of the reference voltage with
30mV of hysterisis.
The reference voltage for the linear regulator (LFB pin)
will track the SS pin in the same manner as the FB pin of
the switching regulator.
1939f
19
LT1939
APPLICATIONS INFORMATION
increases the overall efficiency of the system. However,
the minimum V increases to 2V plus the V at full load
of the transistor. Additionally, due to a lack of beta current
limiting, a shorted output can cause the switcher output
of the LT1939 to collapse.
IN
GS
V
OUT
AC COUPLED
20mV/DIV
LOAD STEP
2.5mA TO 7.5mA
5mA/DIV
SincethecollectoroftheLDRVnpnisconnectedinternally
to V , you must consider the impact of LDRV current on
IN
1939 F09
20μs/DIV
efficiencyanddietemperaturewhenconfiguringthelinear
regulator/controller. For example, with V = 25V, LDRV =
IN
Figure 9. Linear Regulator Transient Response
3.3V and I
= 10mA, power dissipation on the die will
LDRV
To compensate the linear regulator, simply add a ceramic
capacitor from the LDRV pin to ground. Typical values
range from 0.01μF to 1μF. Figure 9 illustrates the transient
response with a 0.47μF output capacitor.
be 217mW. For a typical 3.3V/1A switcher application,
this represents an additional 7% efficiency loss and ap-
proximately 10 degrees rise in die temperature.
If the linear output of the LT1939 is not used, the LDRV
pin should be shorted to the LFB Pin.
Linear Controller
By adding an external follower (NPN or NMOS), the LFB
and LDRV pins can be configured as a controller (Fig-
ure 10) for a low dropout regulator with increased output
capability.
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board (PCB) layout. Figure 11
shows the high di/dt paths in the buck regulator circuit.
Notethatlargeswitchedcurrentsflowinthepowerswitch,
the catch diode and the input capacitor. The loop formed
by these components should be as small as possible.
These components, along with the inductor and output
capacitor, should be placed on the same side of the circuit
board and their connections should be made on that layer.
Place a local, unbroken ground plane below these com-
ponents, and tie this ground plane to system ground at
The output current capability of Figure 10’s circuit is a
product of the LDRV current limit and beta of the external
NPN which is normally less than the current capability of
theLT1939. Thedropoutvoltageforthecircuitissetbythe
saturation voltage of the external NPN, which is typically
300mV. The minimum V for the circuit to function prop-
IN
erly is 2V plus the base emitter drop of the external NPN.
Replacing the NPN in Figure 10 with a NMOS transistor
can reduce the dropout voltage down to the R
of the
DS(ON)
NMOS times the output current of the regulator. This also
D2
BAT54
4.5V TO 25V
V
BST
SW
IN
C5
0.47μF
L1
3.3μH
C1
2.2μF
LT1939
V
OUT1
3.5V
D1
B240A
C7
22μF
R1
27.4k
SHDN
SS
R2
8.06k
C2
0.47μF
FB
R
V
SYNC LDRV
Q1
T/
PG
PG
LFB
R3
C
V
3.3V
1A
C6
22μF
OUT2
C3
24.9k
220pF
R6
R5
R4
8.06k
40.2k
49.9k
1939 F10
Figure 10. Linear Controller
1939f
20
LT1939
APPLICATIONS INFORMATION
LT1939
LT1939
GND
LT1939
GND
V
V
V
IN
SW
SW
SW
IN
IN
GND
1939 F11
(11a)
(11b)
(11c)
Figure 11. Subtracting the Current when the Switch is On (11a) from the Current when the Switch is Off (11b) Reveals the Path of the
High Frequency Switching Current (11c). Keep this Loop Small. The Voltage on the SW and BST Traces will Also be Switched; Keep
These Traces as Short as Possible. Finally, Make Sure the Circuit is Shielded with a Local Ground Plane
package must be soldered to a ground plane. This ground
should be tied to other copper layers below with thermal
vias; these layers will spread the heat dissipated by the
LT1939.Placeadditionalviasnearthecatchdiodes.Adding
more copper to the top and bottom layers and tying this
copper to the internal planes with vias can further reduce
thermal resistance. With these steps, the thermal resis-
tance from die (or junction) to ambient can be reduced to
θ
JA
= 45°C/W.
Power dissipation within the LT1939 can be estimated
by calculating the total power loss from an efficiency
measurement and subtracting the catch diode loss. The
die temperature is calculated by multiplying the LT1939
power dissipation by the thermal resistance from junction
to ambient.
The power dissipation in the other power components
such as catch diodes, boost diodes and inductors, cause
additional copper heating and can further increase what
the IC sees as ambient temperature. See the LT1767 data
sheet’s Thermal Considerations section.
Figure 12. LT1939 Demonstration Circuit Board DC1293A
one location, ideally at the ground terminal of the output
capacitor C2. Additionally, the SW and BST traces should
be kept as short as possible. The topside metal from the
DC1069A demonstration board in Figure 12 illustrates
proper component placement and trace routing.
Other Linear Technology Publications
Application notes AN19, AN35 and AN44 contain more
detailed descriptions and design information for buck
regulators and other switching regulators. The LT1376
data sheet has a more extensive discussion of output
ripple, loop compensation and stability testing. Design
noteDN100showshowtogenerateadual(+and–)output
supply using a buck regulator.
Thermal Considerations
The PCB must also provide heat sinking to keep the
LT1939 cool. The exposed metal on the bottom of the
1939f
21
LT1939
TYPICAL APPLICATIONS
High Efficiency Linear Regulator
Efficiency vs Load Current
90
80
70
60
50
D2
BAT54
4.5V TO 25V
V
BST
SW
IN
L1
C1
C5
LT1939
3.3μH
2.2μF
0.47μF
D1
C7
22μF
R1
SHDN
SS
B240A
R2
25.5k
8.06k
C2
0.47μF
FB
M1
R
SYNC LDRV
T/
ZXMN2A03E6
R7
10k
PG
PG
LFB
V
C
R3
C3
220pF
24.9k
V
OUT1
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4
LOAD CURRENT (A)
GND
C8
22μF
R6
R5
49.9k
R4
8.06k
40.2k
1939 TA02b
1939 TA02a
5V/1.5A, 3.3V/0.5A Step-Down with Output Disconnect
D2
BAT54
6V TO 25V
V
BST
SW
IN
L1
4.7μH
C1
2.2μF
C5
0.47μF
LT1939
V
OUT1
5V
1.5A
D1
B240A
C7
22μF
R1
42.2k
R8
100k
SHDN
SS
R2
8.06k
C2
0.47μF
FB
Q1
ZXTCM322
R
SYNC LDRV
T/
V
3.3V
0.5A
OUT2
PG
PG
V
C
C3
220pF
R7
LFB
I89
ZXMP3A17E6
GND
C6
22μF
R6
49.9k
R4
24.9k
R5
8.06k
40.2k
1939 TA03
5V/2A Step-Down with Power Good LED
D2
BAT54
6V TO 25V
V
BST
SW
IN
L1
4.7μH
C1
2.2μF
C5
0.47μF
LT1939
V
5V
2A
OUT1
D1
C7
R1
42.2k
SHDN
SS
B240A
R2
22μF
8.06k
C2
0.47μF
FB
PG
R8
8.06k
R
SYNC LDRV
T/
C8
1μF
R4
8.06k
R3
42.2k
V
C
R5
100k
C3
220pF
R7
LFB
PG
M1
ZXM61N02F
1
GND
R6
49.9k
40.2k
1939 TA04
1939f
22
LT1939
PACKAGE DESCRIPTION
DD Package
12-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1725 Rev A)
0.70 ±0.05
2.38 ±0.05
1.65 ±0.05
3.50 ±0.05
2.10 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.45 BSC
2.25 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.115
0.40 ± 0.10
TYP
7
12
2.38 ±0.10
3.00 ±0.10
(4 SIDES)
1.65 ±0.10
PIN 1 NOTCH
PIN 1
TOP MARK
R = 0.20 OR
0.25 × 45°
CHAMFER
(SEE NOTE 6)
6
1
0.23 ± 0.05
0.45 BSC
0.75 ±0.05
0.200 REF
2.25 REF
(DD12) DFN 0106 REV A
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
1939f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LT1939
TYPICAL APPLICATION
1.8V/2A Step-Down Regulator
V
OUT2
4.5V TO 25V
V
LDRV
LT1939
3.3V
IN
C1
2.2μF
10mA
R3
24.9k
R4
8.06k
C6
1μF
D2
LFB
SHDN
SS
BST
C2
C5
R5 0.47μF
40.2k
0.47μF
D1
L1
V
1.8V
2A
OUT1
SW
FB
PG
PG
R /SYNC
T
R1
V
C
2.2μH
C3
220pF
10k
C7
22μF
R2
8.06k
R6
49.9k
1939 TA05
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
V : 5.5V to 60V, V
LT1766
60V, 1.2A (I ), 200kHz High Efficiency Step-Down DC/DC
= 1.20V, I = 2.5mA, I = 25μA,
OUT(MIN) Q SD
OUT
IN
Converter
16-Lead TSSOPE Package
V : 3.6V to 36V, V = 1.2V, I = 1.6mA, I < 1μA,
OUT(MIN) Q SD
LT1933
LT1936
LT1940
36V, 500mA (I ), 500kHz Step-Down Switching Regulator in
OUT
IN
SOT-23
ThinSOTTM Package
V : 3.6V to 36V, V
36V, 1.4A (I ), 500kHz High Efficiency Step-Down DC/DC
= 1.2V, I = 1.9mA, I < 1μA,
Q SD
OUT
IN
OUT(MIN)
Converter
8-Lead MS8E Package
Dual 25V, 1.4A (I ), 1.1MHz High Efficiency Step-Down DC/DC
Converter
V : 3.6V to 25V, V
= 1.20V, I = 3.8mA, I < 30μA,
Q SD
OUT
IN
OUT(MIN)
16-Lead TSSOPE Package
LTC3407/LTC3407-2 Dual 600mA/800mA, 1.5MHz/2.25MHz Synchronous Step-Down
DC/DC Converter
V : 2.5V to 5.5V, V
= 0.6V, I = 40μA, I < 1μA,
Q SD
IN
OUT(MIN)
3mm × 3mm DFN and 10-Lead MS10E Packages
60V, 2.4A (I ), 200kHz/500kHz High Efficiency Step-Down DC/DC V : 3.3V to 60V, V = 1.20V, I = 100μA, I < 1μA,
OUT IN OUT(MIN)
LT3434/LT3435
Q
SD
Converters with Burst Mode Operation
16-Lead TSSOPE Package
LT3437
60V, 400mA (I ), Micropower Step-Down DC/DC Converter with
V : 3.3V to 60V, V
= 1.25V, I = 100μA, I < 1μA,
Q SD
OUT
IN
OUT(MIN)
Burst Mode Operation
10-Lead 3mm × 3mm DFN, 16-Lead TSSOPE Package
LT3493
36V, 1.4A (I ), 750kHz High Efficiency Step-Down DC/DC
V : 3.6V to 36V, V = 0.8V, I = 1.9mA, I < 1μA,
OUT
IN
OUT(MIN)
Q
SD
Converter
6-Lead 2mm × 3mm DFN Package
LT3501
Dual 25V, 3A (I ), 1.5MHz High Efficiency Step-Down DC/DC
V : 3.3V to 25V, V = 0.8V, I = 3.7mA, I < 10μA,
OUT
IN
OUT(MIN)
Q
SD
Converter
20-Lead TSSOPE Package
LT3502/LT3502A
LT3503
40V, 500mA (I ), 1.1MHz/2.2MHz High Efficiency Step-Down
V : 3V to 40V, V = 0.8V, I = 1.5mA, I < 2μA,
OUT
IN
OUT(MIN)
Q
SD
DC/DC Converter
8-Lead 2mm × 2mm DFN Package
20V, 1A (I ), 2.2MHz High Efficiency Step-Down DC/DC Converter V : 3.6V to 20V, V
= 0.78V, I = 1.9mA, I < 1μA,
OUT
IN
OUT(MIN)
Q
SD
6-Lead 2mm × 3mm DFN Package
LT3505
36V, 1.2A (I ), 3MHz High Efficiency Step-Down DC/DC Converter V : 3.6V to 36V, V = 0.78V, I = 2mA, I < 2μA,
OUT
IN
OUT(MIN)
Q
SD
8-Lead 3mm × 3mm DFN and MSE Packages
LT3506/LT3506A
LT3508
Dual 25V, 1.6A (I ), 575kHz/1.1MHz High Efficiency Step-Down
V : 3.6V to 25V, V = 0.8V, I = 3.8mA, I < 30μA,
OUT
IN
OUT(MIN)
Q
SD
DC/DC Converters
16-Lead 4mm × 5mm DFN and TSSOPE Packages
Dual 36V, 1.4A (I ), 2.5MHz High Efficiency Step-Down DC/DC
V : 3.6V to 36V, V = 0.8V, I = 4.3mA, I < 1μA,
OUT
IN
OUT(MIN)
Q
SD
Converter
24-Lead 4mm × 4mm QFN and 16-Lead TSSOPE Packages
LT3510
Dual 25V, 2A (I ), 1.5MHz High Efficiency Step-Down DC/DC
V : 3.3V to 25V, V = 0.8V, I = 3.7mA, I < 10μA,
OUT
IN
OUT(MIN)
Q
SD
Converter
20-Lead TSSOPE Package
V : 2.5V to 5.5V, V = 0.6V, I = 40μA, I < 1μA,
OUT(MIN) Q SD
LTC3548
LT3680
Dual 400mA/800mA, 2.25MHz Synchronous Step-Down DC/DC
Converter
IN
3mm × 3mm DFN and 10-Lead MSE Packages
36V, 3.5A (I ), 2.4MHz High Efficiency Step-Down DC/DC
V : 3.6V to 36V, V = 0.79V, I = 75μA, I < 1μA,
OUT
IN
OUT(MIN)
Q
SD
Converter
3mm × 3mm DFN and MS10E Packages
LT3500
40V, 2A (I ), 2.2MHz High Efficiency Step-Down DC/DC Converter V : 28V to 36V, V
= 0.8V, I = 75μA, I < 12μA,
OUT(MIN) Q SD
OUT
IN
3mm × 3mm DFN
1939f
LT 0108 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LT1939EDD#PBF
LT1939 - Monolithic 2A Step-Down Regulator Plus Linear Regulator/Controller; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C
Linear
LT1939EDD#TRPBF
LT1939 - Monolithic 2A Step-Down Regulator Plus Linear Regulator/Controller; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C
Linear
LT1939IDD#PBF
LT1939 - Monolithic 2A Step-Down Regulator Plus Linear Regulator/Controller; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C
Linear
LT1939IDD#TRPBF
LT1939 - Monolithic 2A Step-Down Regulator Plus Linear Regulator/Controller; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C
Linear
LT1940EFE#PBF
LT1940 - Dual Monolithic 1.4A, 1.1MHz Step-Down Switching Regulator; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C
Linear
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