LT1956IFE#TRPBF [Linear]
暂无描述;LT1956/LT1956-5
High Voltage, 1.5A,
500kHz Step-Down
Switching Regulators
U
FEATURES
DESCRIPTIO
The LT®1956/LT1956-5 are 500kHz monolithic buck
switching regulators with an input voltage capability up to
60V. Ahighefficiency1.5A, 0.2Ωswitchisincludedonthe
diealongwithallthenecessaryoscillator,controlandlogic
circuitry. A current mode architecture provides fast tran-
sient response and good loop stability.
■
Wide Input Range: 5.5V to 60V
■
1.5A Peak Switch Current
■
Small 16-Pin SSOP or Thermally Enhanced
TSSOP Package
Saturating Switch Design: 0.2Ω
■
■
Peak Switch Current Maintained Over
Full Duty Cycle Range
Special design techniques and a new high voltage process
achieve high efficiency over a wide input range. Efficiency
ismaintainedoverawideoutputcurrentrangebyusingthe
output to bias the circuitry and by utilizing a supply boost
capacitor to saturate the power switch. Patented circuitry
maintains peak switch current over the full duty cycle
range*.Ashutdownpinreducessupplycurrentto25µAand
the device can be externally synchronized from 580kHz to
700kHz with a logic level input.
■
Constant 500kHz Switching Frequency
■
Effective Supply Current: 2.5mA
■
Shutdown Current: 25µA
■
1.2V Feedback Reference (LT1956)
■
5V Fixed Output (LT1956-5)
Easily Synchronizable
■
■
Cycle-by-Cycle CUurrent Limiting
APPLICATIO S
■
The LT1956/LT1956-5 are available in fused-lead 16-pin
SSOP and thermally enhanced TSSOP packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
*U.S. PATENT NO. 6,498,466
High Voltage, Industrial and Automotive
■
Portable Computers
■
Battery-Powered Systems
■
Battery Chargers
■
Distributed Power Systems
U
TYPICAL APPLICATIO
5V Buck Converter
Efficiency vs Load Current
MMSD914TI
100
V
= 12V
IN
L = 18µH
6
V
OUT
= 5V
0.1µF
V
IN
90
80
70
60
50
BOOST
10µH
V
5V
1A
OUT
12V
(TRANSIENTS
TO 60V)
4
2
V
IN
SW
V
OUT
= 3.3V
2.2µF†
100V
CERAMIC
10MQ060N
LT1956-5
22µF
6.3V
CERAMIC
15
14
10
12
SHDN
BIAS
SYNC
GND
FB
V
C
1, 8, 9, 16 11
0
0.25
0.50
0.75
1.00
1.25
220pF
4.7k
LOAD CURRENT (A)
1956 TA02
4700pF
†UNITED CHEMI-CON THCS50EZA225ZT
1956 TA01
1956f
1
LT1956/LT1956-5
W W U W
ABSOLUTE AXI U RATI GS
(Note 1)
Input Voltage (VIN) ................................................. 60V
BOOST Pin Above SW ............................................ 35V
BOOST Pin Voltage ................................................. 68V
SYNC, SENSE Voltage (LT1956-5) ........................... 7V
SHDN Voltage ........................................................... 6V
BIAS Pin Voltage .................................................... 30V
FB Pin Voltage/Current (LT1956)................... 3.5V/2mA
Operating Junction Temperature Range
LT1956EFE/LT1956EFE-5/LT1956EGN/LT1956EGN-5
(Notes 8, 10) ..................................... –40°C to 125°C
LT1956IFE/LT1956IFE-5/LT1956IGN/LT1956IGN-5
(Notes 8, 10) ..................................... –40°C to 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
ORDER PART
NUMBER
ORDER PART
GND
SW
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
NUMBER
GND
SW
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
SHDN
SYNC
NC
SHDN
SYNC
NC
LT1956EGN
LT1956IGN
LT1956EGN-5
LT1956IGN-5
LT1956EFE
LT1956IFE
LT1956EFE-5
LT1956IFE-5
V
IN
V
IN
NC
BOOST
NC
FB/SENSE
NC
BOOST
NC
FB/SENSE
V
C
V
C
BIAS
GND
BIAS
GND
FE PART MARKING
GN PART MARKING
GND
GND
1956EFE
1956IFE
1956EFE-5
1956IFE-5
1956
FE PACKAGE
16-LEAD PLASTIC TSSOP
GN PACKAGE
16-LEAD PLASTIC SSOP
1956I
19565
1956I5
TJMAX = 125°C, θJA = 45°C/ W, θJC (PAD) = 10°C/ W
TJMAX = 125°C, θJA = 85°C/ W, θJC (PIN 8) = 25°C/ W
EXPOSED BACKSIDE MUST BE SOLDERED
TO GROUND PLANE
FOUR CORNER PINS SOLDERED
TO GROUND PLANE
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C.
VIN = 15V, VC = 1.5V, SHDN = 1V, Boost o/c, SW o/c, unless otherwise noted.
PARAMETER
CONDITIONS
5.5V ≤ V ≤ 60V
MIN
TYP
MAX
UNITS
Reference Voltage (LT1956)
1.204 1.219 1.234
1.195
V
V
IN
V
+ 0.2 ≤ V ≤ V – 0.2
●
●
1.243
OL
C
OH
SENSE Voltage (LT1956-5)
5.5V ≤ V ≤ 60V
4.94
4.90
5
5.06
5.10
V
V
IN
V
+ 0.2 ≤ V ≤ V – 0.2
OL
C OH
SENSE Pin Resistance (LT1956-5)
FB Input Bias Current (LT1956)
Error Amp Voltage Gain
9.5
13.8
0.5
19
kΩ
µA
●
●
1.5
(Notes 2, 9)
dl (V ) = ±10µA (Note 9)
200
400
V/V
Error Amp g
1500
1000
2000
3000
3200
µMho
µMho
m
C
V to Switch g
1.7
225
225
0.9
A/V
µA
µA
V
C
m
EA Source Current
EA Sink Current
FB = 1V or V
= 4.1V
●
●
125
100
400
450
SENSE
FB = 1.4V or V
Duty Cycle = 0
SHDN = 1V
= 5.7V
SENSE
V Switching Threshold
C
V High Clamp
C
2.1
V
1956f
2
LT1956/LT1956-5
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C.
VIN = 15V, VC = 1.5V, SHDN = 1V, Boost o/c, SW o/c, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
2
MAX
UNITS
Switch Current Limit
Switch On Resistance
V Open, Boost = V + 5V, FB = 1V or V
C
= 4.1V
●
●
●
1.5
3
A
IN
SENSE
I
= 1.5A, Boost = V + 5V (Note 7)
0.2
0.3
0.4
Ω
Ω
SW
IN
Maximum Switch Duty Cycle
Switch Frequency
FB = 1V or V
= 4.1V
82
75
90
90
%
%
SENSE
V Set to Give DC = 50%
C
460
430
500
540
570
kHz
kHz
●
●
f
f
Line Regulation
5.5V ≤ V ≤ 60V
0.05
0.8
0.15
%/V
V
SW
SW
IN
Shifting Threshold
Df = 10kHz
Minimum Input Voltage
Minimum Boost Voltage
Boost Current (Note 5)
(Note 3)
●
●
4.6
2
5.5
3
V
V
(Note 4) I ≤ 1.5A
SW
Boost = V + 5V, I = 0.5A
Boost = V + 5V, I = 1.5A
●
●
12
42
25
70
mA
mA
IN
SW
IN
SW
Input Supply Current (I
)
(Note 6) V
= 5V
1.4
2.9
25
2.2
4.2
mA
mA
VIN
BIAS
BIAS
Output Supply Current (I
)
(Note 6) V
= 5V
BIAS
Shutdown Supply Current
SHDN = 0V, V ≤ 60V, SW = 0V, V Open
75
200
µA
µA
IN
C
●
●
Lockout Threshold
V Open
C
2.30
2.42
2.53
V
Shutdown Thresholds
V Open, Shutting Down
V Open, Starting Up
C
●
●
0.15
0.25
0.37
0.45
0.6
0.6
V
V
C
Minimum SYNC Amplitude
SYNC Frequency Range
SYNC Input Resistance
●
1.5
2.2
V
kHz
kΩ
580
700
20
Note 1: Absolute Maximum Ratings are those values beyond which the life
Note 7: Switch on resistance is calculated by dividing V to SW voltage by
the forced current (1.5A). See Typical Performance Characteristics for the
graph of switch voltage at other currents.
Note 8: The LT1956EFE/LT1956EFE-5/LT1956EGN/LT1956EGN-5 are
guaranteed to meet performance specifications from 0°C to 125°C
junction temperature. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LT1956IFE/LT1956IFE-5/
LT1956IGN/LT1956IGN-5 are guaranteed over the full –40°C to 125°C
operating junction temperature range.
IN
of a device may be impaired.
Note 2: Gain is measured with a V swing equal to 200mV above the low
C
clamp level to 200mV below the upper clamp level.
Note 3: Minimum input voltage is not measured directly, but is guaranteed
by other tests. It is defined as the voltage where internal bias lines are still
regulated so that the reference voltage and oscillator remain constant.
Actual minimum input voltage to maintain a regulated output will depend
upon output voltage and load current. See Applications Information.
Note 4: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 9: Transconductance and voltage gain refer to the internal amplifier
exclusive of the voltage divider. To calculate gain and transconductance,
refer to the SENSE pin on fixed voltage parts. Divide values shown by the
Note 5: Boost current is the current flowing into the BOOST pin with the
pin held 5V above input voltage. It flows only during switch on time.
ratio V /1.219.
OUT
Note 6: Input supply current is the quiescent current drawn by the input
pin when the BIAS pin is held at 5V with switching disabled. Bias supply
current is the current drawn by the BIAS pin when the BIAS pin is held at
5V. Total input referred supply current is calculated by summing input
Note 10: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
supply current (I ) with a fraction of supply current (I
):
BIAS
VIN
I
= I + (I
)(V /V )
BIAS OUT IN
TOTAL
VIN
with V = 15V, V
= 5V, I = 1.4mA, I
= 2.9mA, I
= 2.4mA.
IN
OUT
VIN
BIAS
TOTAL
1956f
3
LT1956/LT1956-5
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Switch Peak Current Limit
FB Pin Voltage and Current
SHDN Pin Bias Current
2.5
2.0
1.5
1.0
1.234
1.229
1.224
1.219
2.0
1.5
250
200
150
100
12
CURRENT REQUIRED TO FORCE SHUTDOWN
(FLOWS OUT OF PIN). AFTER SHUTDOWN,
CURRENT DROPS TO A FEW µA
TYPICAL
VOLTAGE
CURRENT
1.0
0.5
0
GUARANTEED MINIMUM
1.214
1.209
1.204
AT 2.38V STANDBY THRESHOLD
(CURRENT FLOWS OUT OF PIN)
6
0
0
20
40
60
80
100
50
100 125
–50 –25
0
25
75
50
100 125
–50 –25
0
25
75
DUTY CYCLE (%)
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
1956 G01
1956 G02
1956 G03
Lockout and Shutdown
Thresholds
Shutdown Supply Current
Shutdown Supply Current
300
250
40
35
30
25
20
15
10
5
2.4
2.0
1.6
1.2
0.8
0.4
0
V
= 0V
SHDN
LOCKOUT
V
IN
= 60V
200
150
V
IN
= 15V
100
50
0
START-UP
SHUTDOWN
0
0
0.1
0.2
0.3
0.4
0.5
0
10
20
30
40
50
60
–50
–25
0
25
50
75
100
125
SHUTDOWN VOLTAGE (V)
INPUT VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
1956 G06
1956 G05
1956 G04
Error Amplifier Transconductance
Error Amplifier Transconductance
Frequency Foldback
3000
2500
2000
1500
1000
500
200
150
100
50
625
2500
2000
1500
1000
500
SWITCHING
FREQUENCY
PHASE
GAIN
500
375
250
125
0
V
C
C
OUT
12pF
R
OUT
200k
–3
V
2 • 10
(
)
FB
ERROR AMPLIFIER EQUIVALENT CIRCUIT
= 50Ω
0
FB PIN
CURRENT
R
LOAD
1k
–50
0
100
10k
100k
1M
10M
–25
0
25
50
75
100
125
0
0.2
0.4
0.8
1.0
1.2
–50
0.6
(V)
FREQUENCY (Hz)
JUNCTION TEMPERATURE
V
FB
1956 G08
1956 G07
1956 G09
1956f
4
LT1956/LT1956-5
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Minimum Input Voltage with 5V
Output
Switching Frequency
BOOST Pin Current
575
550
525
500
475
450
425
7.5
7.0
6.5
6.0
5.5
5.0
45
40
35
30
25
20
15
10
5
V
= 5V
OUT
L = 18µH
MINIMUM INPUT
VOLTAGE TO START
MINIMUM INPUT
VOLTAGE TO RUN
0
–50
–25
0
25
50
75
100
125
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
LOAD CURRENT (A)
1
0
0.5
1
1.5
JUNCTION TEMPERATURE (°C)
SWITCH CURRENT (A)
1956 G10
1956 G11
1956 G12
Switch Minimum ON Time
vs Temperature
VC Pin Shutdown Threshold
Switch Voltage Drop
2.1
1.9
450
400
350
300
250
200
150
100
50
600
500
400
300
200
100
0
T
= 125°C
J
1.7
1.5
1.3
1.1
0.9
T
= 25°C
J
T
= –40°C
J
0.7
0
0
0.5
1
1.5
–50
–25
0
25
50
75
100
125
50
100 125
–50 –25
0
25
75
SWITCH CURRENT (A)
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
1766 G14
1956 G15
1956 G13
1956f
5
LT1956/LT1956-5
U
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PI FU CTIO S
VC (Pin 11) The VC pin is the output of the error amplifier
and the input of the peak switch current comparator. It is
normally used for frequency compensation, but can also
serve as a current clamp or control loop override. VC sits
at about 1V for light loads and 2V at maximum load. It can
be driven to ground to shut off the regulator, but if driven
high, current must be limited to 4mA.
GND (Pins 1, 8, 9, 16): The GND pin connections act as
the reference for the regulated output, so load regulation
will suffer if the “ground” end of the load is not at the same
voltage as the GND pins of the IC. This condition will occur
when load current or other currents flow through metal
pathsbetweentheGNDpinsandtheloadground.Keepthe
paths between the GND pins and the load ground short
anduseagroundplanewhenpossible.FortheFEpackage,
the exposed pad should be soldered to the copper GND
plane underneath the device. (See Applications Informa-
tion—Layout Considerations.)
FB/SENSE (Pin 12): The feedback pin is used to set the
output voltage using an external voltage divider that gen-
erates 1.22V at the pin for the desired output voltage. The
5V fixed output voltage parts have the divider included on
the chip and the FB pin is used as a SENSE pin, connected
directly to the 5V output. Three additional functions are
performed by the FB pin. When the pin voltage drops
below 0.6V, switch current limit is reduced and the exter-
nal SYNC function is disabled. Below 0.8V, switching
frequency is also reduced. See Feedback Pin Functions in
Applications Information for details.
SW (Pin 2): The switch pin is the emitter of the on-chip
power NPN switch. This pin is driven up to the input pin
voltage during switch on time. Inductor current drives the
switch pin negative during switch off time. Negative volt-
age is clamped with the external catch diode. Maximum
negative switch voltage allowed is –0.8V.
NC (Pins 3, 5, 7, 13): No Connection.
SYNC (Pin 14): The SYNC pin is used to synchronize the
internal oscillator to an external signal. It is directly logic
compatible and can be driven with any signal between
10% and 90% duty cycle. The synchronizing range is
equal to initial operating frequency up to 700kHz. See
Synchronizing in Applications Information for details. If
unused, this pin should be tied to ground.
VIN (Pin 4): This is the collector of the on-chip power NPN
switch. VIN powers the internal control circuitry when a
voltage on the BIAS pin is not present. High dI/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the VIN pin through the input bypass
capacitor, through the catch diode back to SW. All trace
inductanceonthispathwillcreateavoltagespikeatswitch
off, adding to the VCE voltage across the internal NPN.
SHDN (Pin 15): The SHDN pin is used to turn off the
regulator and to reduce input current to a few microam-
peres. This pin has two thresholds: one at 2.38V to disable
switching and a second at 0.4V to force complete mi-
cropower shutdown. The 2.38V threshold functions as an
accurate undervoltage lockout (UVLO); sometimes used
to prevent the regulator from delivering power until the
input voltage has reached a predetermined level.
BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal
bipolarNPNpowerswitch. Withoutthisaddedvoltage, the
typical switch voltage loss would be about 1.5V. The
additional BOOST voltage allows the switch to saturate
and voltage loss approximates that of a 0.2Ω FET struc-
ture, but with much smaller die area.
If the SHDN pin functions are not required, the pin can
either be left open (to allow an internal bias current to lift
the pin to a default high state) or be forced high to a level
not to exceed 6V.
BIAS (Pin 10): The BIAS pin is used to improve efficiency
when operating at higher input voltages and light load
current. Connecting this pin to the regulated output volt-
age forces most of the internal circuitry to draw its oper-
ating current from the output voltage rather than the input
supply. This architecture increases efficiency especially
when the input voltage is much higher than the output.
Minimumoutputvoltagesettingforthismodeofoperation
is 3V.
1956f
6
LT1956/LT1956-5
W
BLOCK DIAGRA
The LT1956 is a constant frequency, current mode buck
converter. This means that there is an internal clock and
twofeedbackloopsthatcontrolthedutycycleofthepower
switch. In addition to the normal error amplifier, there is a
current sense amplifier that monitors switch current on a
cycle-by-cycle basis. A switch cycle starts with an oscilla-
tor pulse which sets the RS flip-flop to turn the switch on.
When switch current reaches a level set by the inverting
input of the comparator, the flip-flop is reset and the
switch turns off. Output voltage control is obtained by
using the output of the error amplifier to set the switch
current trip point. This technique means that the error
amplifier commands current to be delivered to the output
rather than voltage. A voltage fed system will have low
phase shift up to the resonant frequency of the inductor
and output capacitor, then an abrupt 180° shift will occur.
The current fed system will have 90° phase shift at a much
lower frequency, but will not have the additional 90° shift
until well beyond the LC resonant frequency. This makes
itmucheasiertofrequencycompensatethefeedbackloop
and also gives much quicker transient response.
Most of the circuitry of the LT1956 operates from an
internal 2.9V bias line. The bias regulator normally draws
power from the regulator input pin, but if the BIAS pin is
connected to an external voltage higher than 3V, bias
powerwillbedrawnfromtheexternalsource(typicallythe
regulated output voltage). This will improve efficiency if
the BIAS pin voltage is lower than regulator input voltage.
High switch efficiency is attained by using the BOOST pin
to provide a voltage to the switch driver which is higher
than the input voltage, allowing switch to be saturated.
This boosted voltage is generated with an external capaci-
tor and diode. Two comparators are connected to the
shutdownpin. Onehasa2.38Vthresholdforundervoltage
lockout and the second has a 0.4V threshold for complete
shutdown.
V
4
IN
R
LIMIT
R
SENSE
–
+
2.9V BIAS
REGULATOR
INTERNAL
CC
BIAS
10
V
CURRENT
COMPARATOR
SLOPE COMP
Σ
SYNC 14
BOOST
6
ANTISLOPE COMP
SHUTDOWN
COMPARATOR
500kHz
OSCILLATOR
–
+
S
Q1
POWER
SWITCH
R
DRIVER
CIRCUITRY
S
FLIP-FLOP
R
0.4V
5.5µA
2
SW
SHDN 15
+
–
FREQUENCY
FOLDBACK
LOCKOUT
COMPARATOR
×1
Q2
FOLDBACK
CURRENT
LIMIT
V
C(MAX)
CLAMP
Q3
ERROR
AMPLIFIER
= 2000µMho
CLAMP
–
+
12
FB
g
m
11
1.22V
2.38V
V
C
GND
1, 8, 9, 16
1956 F01
Figure 1. LT1956 Block Diagram
1956f
7
LT1956/LT1956-5
W U U
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APPLICATIO S I FOR ATIO
FEEDBACK PIN FUNCTIONS
current through the diode and inductor is equal to the
short-circuit current limit of the switch (typically 2A for
the LT1956, folding back to less than 1A). Minimum
switch on time limitations would prevent the switcher
from attaining a sufficiently low duty cycle if switching
frequency were maintained at 500kHz, so frequency is
reducedbyabout5:1whenthefeedbackpinvoltagedrops
below 0.8V (see Frequency Foldback graph). This does
not affect operation with normal load conditions; one
simply sees a shift in switching frequency during start-up
as the output voltage rises.
The feedback (FB) pin on the LT1956 is used to set output
voltage and provide several overload protection features.
The first part of this section deals with selecting resistors
to set output voltage and the remaining part talks about
foldback frequency and current limiting created by the FB
pin. Please read both parts before committing to a final
design. The 5V fixed output voltage part (LT1956-5) has
internaldividerresistorsandtheFBpinisrenamedSENSE,
connected directly to the output.
The suggested value for the output divider resistor (see
Figure 2) from FB to ground (R2) is 5k or less, and a
formula for R1 is shown below. The output voltage error
caused by ignoring the input bias current on the FB pin is
less than 0.25% with R2 = 5k. A table of standard 1%
values is shown in Table 1 for common output voltages.
Please read the following section if divider resistors are
increased above the suggested values.
In addition to lower switching frequency, the LT1956 also
operates at lower switch current limit when the feedback
pin voltage drops below 0.6V. Q2 in Figure 2 performs this
function by clamping the VC pin to a voltage less than its
normal 2.1V upper clamp level. This foldback current limit
greatly reduces power dissipation in the IC, diode and in-
ductor during short-circuit conditions. External synchro-
nization is also disabled to prevent interference with fold-
back operation. Again, it is nearly transparent to the user
under normal load conditions. The only loads that may be
affected are current source loads which maintain full load
current with output voltage less than 50% of final value. In
theseraresituationsthefeedbackpincanbeclampedabove
0.6Vwithanexternaldiodetodefeatfoldbackcurrentlimit.
Caution: clamping the feedback pin means that frequency
shifting will also be defeated, so a combination of high in-
putvoltageanddeadshortedoutputmaycausetheLT1956
to lose control of current limit.
R2 V
−1.22
1.22
(
)
OUT
R1=
Table 1
OUTPUT
VOLTAGE
(V)
R1
% ERROR AT OUTPUT
R2
(NEAREST 1%) DUE TO DISCRETE 1%
(kΩ
)
(k
Ω
)
RESISTOR STEPS
+0.32
3
3.3
5
4.99
4.99
4.99
4.75
4.47
4.32
4.12
4.12
7.32
8.45
15.4
18.7
24.9
30.9
36.5
46.4
–0.43
–0.30
6
+0.38
The internal circuitry which forces reduced switching
frequency also causes current to flow out of the feedback
pin when output voltage is low. The equivalent circuitry is
shown in Figure 2. Q1 is completely off during normal
operation. If the FB pin falls below 0.8V, Q1 begins to
conduct current and reduces frequency at the rate of
approximately 3.5kHz/µA. To ensure adequate frequency
foldback (under worst-case short-circuit conditions), the
external divider Thevinin resistance must be low enough
to pull 115µA out of the FB pin with 0.44V on the pin (RDIV
≤ 3.8k). The net result is that reductions in frequency and
current limit are affected by output voltage divider imped-
ance. Although divider impedance is not critical, caution
should be used if resistors are increased beyond the
8
+0.20
10
12
15
–0.54
+0.24
–0.27
More Than Just Voltage Feedback
Thefeedbackpinisusedformorethanjustoutputvoltage
sensing. It also reduces switching frequency and current
limit when output voltage is very low (see the Frequency
Foldback graph in Typical Performance Characteristics).
This is done to control power dissipation in both the IC
andintheexternaldiodeandinductorduringshort-circuit
conditions. A shorted output requires the switching regu-
lator to operate at very low duty cycles, and the average
suggested values and short-circuit conditions will occur
1956f
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U
V
SW
LT1956
L1
TO FREQUENCY
SHIFTING
OUTPUT
5V
1.4V
Q1
ERROR
AMPLIFIER
1.2V
+
–
R1
R4
2k
R3
1k
FB
+
C1
BUFFER
R2
Q2
TO SYNC CIRCUIT
V
GND
C
1956 F02
Figure 2. Frequency and Current Limit Foldback
with high input voltage. High frequency pickup will in-
crease and the protection accorded by frequency and
current foldback will decrease.
V
USING
OUT
22µF CERAMIC
OUTPUT
10mV/DIV
CAPACITOR
V
USING
OUT
CHOOSING THE INDUCTOR
100µF, 0.08Ω
TANTALUM
OUTPUT
10mV/DIV
For most applications, the output inductor will fall into the
range of 5µH to 30µH. Lower values are chosen to reduce
physical size of the inductor. Higher values allow more
output current because they reduce peak current seen by
the LT1956 switch, which has a 1.5A limit. Higher values
also reduce output ripple voltage.
CAPACITOR
V
V
= 12V
OUT
L = 15µH
1µs/DIV
1956 F03
IN
= 5V
Figure 3. LT1956 Output Ripple Voltage Waveforms.
Ceramic vs Tantalum Output Capacitors
Output ripple voltage is determined by ripple current
(ILP-P) through the inductor and the high frequency
impedance of the output capacitor. At high frequencies,
the impedance of the tantalum capacitor is dominated by
its effective series resistance (ESR).
When choosing an inductor you will need to consider
output ripple voltage, maximum load current, peak induc-
tor current and fault current in the inductor. In addition,
other factors such as core and copper losses, allowable
component height, EMI, saturation and cost should also
be considered. The following procedure is suggested as a
way of handling these somewhat complicated and con-
flicting requirements.
Tantalum Output Capacitor
The typical method for reducing output ripple voltage
when using a tantalum output capacitor is to increase the
inductor value (to reduce the ripple current in the induc-
tor). The following equations will help in choosing the
requiredinductorvaluetoachieveadesirableoutputripple
voltage level. If output ripple voltage is of less importance,
the subsequent suggestions in Peak Inductor and Fault
Current and EMI will additionally help in the selection of
the inductor value.
Output Ripple Voltage
Figure 3 shows a comparison of output ripple voltage for
the LT1956 using either a tantalum or ceramic output
capacitor. It can be seen from Figure 3 that output ripple
voltagecanbesignificantlyreducedbyusingtheceramic
outputcapacitor;thesignificantdecreaseinoutputripple
voltage is due to the very low ESR of ceramic capacitors.
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Peak-to-peak output ripple voltage is the sum of a triwave
(created by peak-to-peak ripple current (ILP-P) times ESR)
and a square wave (created by parasitic inductance (ESL)
and ripple current slew rate). Capacitive reactance is
assumed to be small compared to ESR or ESL.
ceramic capacitor. Although this reduction of ESR re-
moves a useful zero in the overall loop response, this zero
can be replaced by inserting a resistor (RC) in series with
the VC pin and the compensation capacitor CC. (See
Ceramic Capacitors in Applications Information.)
Peak Inductor Current and Fault Current
dI
dt
VRIPPLE = I
LP-P)(
ESR + ESL Σ
) (
(
)
To ensure that the inductor will not saturate, the peak in-
ductorcurrentshouldbecalculatedknowingthemaximum
load current. An appropriate inductor should then be cho-
sen. In addition, a decision should be made whether or not
the inductor must withstand continuous fault conditions.
where:
ESR = equivalent series resistance of the output
capacitor
ESL = equivalent series inductance of the output
capacitor
If maximum load current is 0.5A, for instance, a 0.5A
inductor may not survive a continuous 2A overload condi-
tion. Dead shorts will actually be more gentle on the
inductor because the LT1956 has frequency and current
limit foldback.
dI/dt = slew rate of inductor ripple current = VIN/L
Peak-to-peak ripple current (ILP-P) through the inductor
and into the output capacitor is typically chosen to be
between 20% and 40% of the maximum load current. It is
approximated by:
Peak inductor and switch current can be significantly
higher than output current, especially with smaller induc-
tors and lighter loads, so don’t omit this step. Powdered
V
V – V
IN OUT
(
=
OUT )(
)
ILP-P
Table 2
V
f L
IN)( )( )
(
VENDOR/
PART NO.
VALUE
H)
I
DCR
(Ohms)
HEIGHT
(mm)
DC(MAX)
(
µ
(Amps)
Example: with VIN = 12V, VOUT = 5V, L = 15µH, ESR =
0.080Ω and ESL = 10nH, output ripple voltage can be
approximated as follows:
Coiltronics
UP1B-100
10
22
22
33
15
1.9
1.2
2.0
1.7
1.5
0.111
0.254
0.062
0.092
0.175
5.0
5.0
6.0
6.0
5.0
UP1B-220
UP2B-220
5 12 − 5
( )(
)
ILP-P
=
= 0.389A
UP2B-330
12 15 •10–6 500 •10–6
( )
(
)(
)
UP1B-150
dI
Σ
12
Coilcraft
=
= 106 • 0.8
15 •10−6
D01813P-153HC
D01813P-103HC
D53316P-223
D53316P-333
LP025060B-682
Sumida
15
10
22
33
1.5
1.9
1.6
1.4
1.3
0.170
0.111
0.207
0.334
0.165
5.0
5.0
dt
VRIPPLE = 0.389 0.08 + 10 •10−9 106 0.8
(
)(
)
(
)
(
)(
)
5.1
= 0.031+ 0.008 = 39mVP-P
5.1
6.8
1.65
To reduce output ripple voltage further requires an in-
crease in the inductor value with the trade-off being a
physically larger inductor with the possibility of increased
component height and cost.
CDRH4D28-4R7
CDRH5D28-100
CDRH6D28-150
CDRH6D28-180
CDRH6D28-220
CDRH6D38-220
4.7
10
15
18
22
22
1.32
1.30
1.40
1.32
1.20
1.30
0.072
0.065
0.084
0.095
0.128
0.096
3.0
3.0
3.0
3.0
3.0
4.0
Ceramic Output Capacitor
An alternative way to further reduce output ripple voltage
is to reduce the ESR of the output capacitor by using a
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APPLICATIO S I FOR ATIO
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current without affecting the frequency compensation it
provides.
iron cores are forgiving because they saturate softly,
whereas ferrite cores saturate abruptly. Other core mate-
rials fall somewhere in between. The following formula
assumes continuous mode of operation, but errs only
slightly on the high side for discontinuous mode, so it can
be used for all conditions.
Maximum load current would be equal to maximum
switch current for an infinitely large inductor, but with
finite inductor size, maximum load current is reduced by
one half of peak-to-peak inductor current (ILP-P). The
following formula assumes continuous mode operation,
implying that the term on the right is less than one half
of IP.
VOUT V – V
ILP-P
2
(
)
IN
OUT
IPEAK = IOUT
EMI
+
= IOUT +
2•V • f •L
IN
IOUT(MAX) Continuous Mode
Decide if the design can tolerate an “open” core geometry
like a rod or barrel, which have high magnetic field
radiation, or whether it needs a closed core like a toroid to
prevent EMI problems. This is a tough decision because
the rods or barrels are temptingly cheap and small and
there are no helpful guidelines to calculate when the
magnetic field radiation will be a problem.
V
+ V V – V
2 V f L
( )( IN)( )( )
– V
ILP-P
2
(
F)(
)
OUT
IN
OUT F
= IP –
= IP –
For VOUT = 5V, VIN(MAX) = 8V, VF(DI) = 0.63V, f = 500kHz
and L = 10µH:
5 + 0.63 8 – 5 – 0.63
(
)(
)
IOUT(MAX) = 1.5 –
2 8 500•103 10•10–6
( )( )
Additional Considerations
(
)(
)
After making an initial choice, consider additional factors
such as core losses and second sourcing, etc. Use the
experts in Linear Technology’s Applications department if
you feel uncertain about the final choice. They have
experience with a wide range of inductor types and can tell
you about the latest developments in low profile, surface
mounting, etc.
= 1.5 – 0.17 = 1.33A
Note that there is less load current available at the higher
inputvoltagebecauseinductorripplecurrentincreases.At
VIN = 15V and using the same set of conditions:
5 + 0.63 15 – 5 – 0.63
(
)(
)
IOUT(MAX) = 1.5 –
2 15 500•103 10•10–6
( )( )
(
)(
)
MAXIMUM OUTPUT LOAD CURRENT
= 1.5 – 0.35 = 1.15A
Maximum load current for a buck converter is limited by
themaximumswitchcurrentrating(IP).Thecurrentrating
fortheLT1956is1.5A. Unlikemostcurrentmodeconvert-
ers, the LT1956 maximum switch current limit does not
fall off at high duty cycles. Most current mode converters
suffer a drop off of peak switch current for duty cycles
above 50%. This is due to the effects of slope compensa-
tion required to prevent subharmonic oscillations in cur-
rent mode converters. (For detailed analysis, see Applica-
tion Note 19.)
To calculate peak switch current with a given set of
conditions, use:
ILP-P
2
ISW(PEAK) = IOUT
= IOUT
+
+
V
OUT
+ V V – V
2 V f L
( )( IN)( )( )
– V
OUT F
(
F)(
)
IN
Reduced Inductor Value and Discontinuous Mode
The LT1956 is able to maintain peak switch current limit
over the full duty cycle range by using patented circuitry to
cancel the effects of slope compensation on peak switch
If the smallest inductor value is of the most importance to
a converter design, in order to reduce inductor size/cost,
discontinuous mode may yield the smallest inductor
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solution. The maximum output load current in discontinu-
ous mode, however, must be calculated and is defined
later in this section.
load current is required, the inductor value must be
increased. If IOUT(MAX) no longer meets the discontinuous
mode criteria, use the IOUT(MAX) equation for continuous
mode; the LT1956 is designed to operate well in both
modes of operation, allowing a large range of inductor
values to be used.
Discontinuous mode is entered when the output load
current is less than one-half of the inductor ripple current
(ILP-P). In this mode, inductor current falls to zero before
the next switch turn-on (see Figure 8). Buck converters
will be in discontinuous mode for output load current
given by:
SHORT-CIRCUIT CONSIDERATIONS
For a ground short-circuit fault on the regulated output,
the maximum input voltage for the LT1956 is typically
limited to 25V. If a greater input voltage is required,
increasing the resistance in series with the inductor may
suffice (see short-circuit calculations at the end of this
section). Alternatively, the 1.5A LT1766 can be used since
it is identical to the LT1956 but runs at a lower frequency
of 200kHz, allowing higher sustained input voltage capa-
bility during output short circuit.
IOUT Discontinous Mode
(VOUT + V )(V – VOUT – V )
F
IN
F
<
(2)(V )(f)(L)
IN
The inductor value in a buck converter is usually chosen
large enough to keep inductor ripple current (ILP-P) low;
this is done to minimize output ripple voltage and maxi-
mize output load current. In the case of large inductor
values, as seen in the equation above, discontinuous
mode will be associated with “light loads.”
The LT1956 is a current mode controller. It uses the VC
node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
peak switch current is reached. The internal clamp on the
VC node, nominally 2V, then acts as an output switch peak
current limit. This action becomes the switch current limit
specification. The maximum available output power is
then determined by the switch current limit.
When choosing small inductor values, however, discon-
tinuous mode will occur at much higher output load
currents. The limit to the smallest inductor value that can
be chosen is set by the LT1956 peak switch current (IP)
and the maximum output load current required given by:
A potential controllability problem could occur under
short-circuit conditions. If the power supply output is
short circuited, the feedback amplifier responds to the low
output voltage by raising the control voltage, VC, to its
peak current limit value. Ideally, the output switch would
be turned on, and then turned off as its current exceeded
thevalueindicatedbyVC.However,thereisfiniteresponse
time involved in both the current comparator and turnoff
of the output switch. These result in a minimum on time
tON(MIN). When combined with the large ratio of VIN to
(VF + I • R), the diode forward voltage plus inductor I • R
voltage drop, the potential exists for a loss of control.
Expressed mathematically the requirement to maintain
control is:
IOUT(MAX) DiscontinuousMode
2
2
IP
IP (f)(L)(V )
IN
=
=
2(ILP-P) 2(VOUT + V )(V – VOUT − V )
F
IN
F
Example: For VIN = 15V, VOUT = 5V, VF = 0.63V, f = 500kHz
and L = 4µH
IOUT(MAX) Discontinuous Mode
1.52(500•103)(4 •10−6)(15)
2(5 + 0.63)(15 – 5 – 0.63)
=
IOUT(MAX) Discontinuous Mode = 0.639A
What has been shown here is that if high inductor ripple
current and discontinuous mode operation can be toler-
ated, small inductor values can be used. If a higher output
VF +I•R
f • tON
≤
V
IN
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capacitor may potentially be starting from 0V. This re-
quires that the part obey the overall duty cycle demanded
by the loop, related to VIN and VOUT, as the output voltage
rises to its target value. It is recommended that for [VIN/
(VOUT + VF)] ratios > 4, a soft-start circuit should be used
tocontroltheoutputcapacitorchargerateduringstart-up
or during recovery from an output short circuit, thereby
adding additional control over peak inductor current. See
Buck Converter with Adjustable Soft-Start later in this
data sheet.
where:
f = switching frequency
tON = switch minimum on time
VF = diode forward voltage
VIN = input voltage
I • R = inductor I • R voltage drop
If this condition is not observed, the current will not be
limited at IPK, but will cycle-by-cycle ratchet up to some
higher value. Using the nominal LT1956 clock frequency
of 500KHz, a VIN of 12V and a (VF + I • R) of say 0.7V, the
maximum tON to maintain control would be approximately
116ns, an unacceptably short time.
OUTPUT CAPACITOR
The LT1956 will operate with either ceramic or tantalum
output capacitors. The output capacitor is normally cho-
sen by its effective series resistance (ESR), because this
is what determines output ripple voltage. The ESR range
for typical LT1956 applications using a tantalum output
capacitoris0.05Ωto0.2Ω. Atypicaloutputcapacitorisan
AVX type TPS, 100µF at 10V, with a guaranteed ESR less
than 0.1Ω. This is a “D” size surface mount solid tantalum
capacitor. TPS capacitors are specially constructed and
tested for low ESR, so they give the lowest ESR for a given
volume. The value in microfarads is not particularly criti-
cal, and values from 22µF to greater than 500µF work well,
but you cannot cheat mother nature on ESR. If you find a
tiny 22µF solid tantalum capacitor, it will have high ESR,
and output ripple voltage will be terrible. Table 3 shows
some typical solid tantalum surface mount capacitors.
The solution to this dilemma is to slow down the oscillator
when the FB pin voltage is abnormally low thereby indicat-
ing some sort of short-circuit condition. Oscillator fre-
quency is unaffected until FB voltage drops to about 2/3 of
its normal value. Below this point the oscillator frequency
decreasesroughlylinearlydowntoalimitofabout100kHz.
Thisloweroscillatorfrequencyduringshort-circuitcondi-
tions can then maintain control with the effective mini-
mum on time. Even with frequency foldback, however, the
LT1956 will not survive a permanent output short at the
absolute maximum voltage rating of VIN = 60V; this is
defined solely by internal semiconductor junction break-
down effects.
For the maximum input voltage allowed during an output
short to ground, the previous equation defining minimum
on-time can be used. Assuming VF (D1 catch diode) =
0.63V at 1A (short-circuit current is folded back to typical
switch current limit • 0.5), I (inductor) • DCR = 1A • 0.128
= 0.128V (L = CDRH6D28-22), typical f = 100kHz (folded
back) and typical minimum on-time = 300ns, the maxi-
mum allowable input voltage during an output short to
ground is typically:
Table 3. Surface Mount Solid Tantalum Capacitor ESR
and Ripple Current
E CASE SIZE
ESR (MAX,
Ω
)
RIPPLE CURRENT (A)
AVX TPS, Sprague 593D
D CASE SIZE
0.1 to 0.3
0.1 to 0.3
0.2 (typ)
0.7 to 1.1
AVX TPS, Sprague 593D
C CASE SIZE
0.7 to 1.1
0.5 (typ)
AVX TPS
VIN = (0.63V + 0.128V)/(100kHz • 300ns)
VIN(MAX) = 25V
Unlike the input capacitor, RMS ripple current in the
output capacitor is normally low enough that ripple cur-
rent rating is not an issue. The current waveform is
triangular with a typical value of 125mARMS. The formula
to calculate this is:
Increasing the DCR of the inductor will increase the maxi-
mumVIN allowedduringanoutputshorttogroundbutwill
also drop overall efficiency during normal operation.
Every time the converter wakes up from shutdown or
undervoltage lockout to begin switching, the output
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is to prevent excessive ripple causing dips below the mini-
mum operating voltage resulting in erratic operation.
Output capacitor ripple current (RMS):
0.29 V
OUT )(
=
V – V
IN OUT
(
)
Depending on how the LT1956 circuit is powered up you
may need to check for input voltage transients.
IRIPPLE(RMS)
L f V
( )( )(
)
IN
The input voltage transients may be caused by input
voltage steps or by connecting the LT1956 converter to an
already powered up source such as a wall adapter. The
sudden application of input voltage will cause a large
surge of current in the input leads that will store energy in
the parasitic inductance of the leads. This energy will
causetheinputvoltagetoswingabovetheDClevelofinput
power source and it may exceed the maximum voltage
rating of input capacitor and LT1956.
Ceramic Capacitors
Ceramic capacitors are generally chosen for their good
high frequency operation, small size and very low ESR
(effective series resistance). Their low ESR reduces
outputripplevoltagebutalsoremovesausefulzerointhe
loop frequency response, common to tantalum capaci-
tors. To compensate for this, a resistor RC can be placed
in series with the VC compensation capacitor CC. Care
must be taken however, since this resistor sets the high
frequency gain of the error amplifier, including the gain
at the switching frequency. If the gain of the error
amplifier is high enough at the switching frequency,
output ripple voltage (although smaller for a ceramic
output capacitor) may still affect the proper operation of
the regulator. A filter capacitor CF in parallel with the
RC/CC network is suggested to control possible ripple at
the VC pin. The LT1956 can be stabilized for VOUT = 5V at
1A using a 22µF ceramic output capacitor and VC com-
ponent values of CC = 4700pF, RC = 4.7k and CF = 220pF.
The easiest way to suppress input voltage transients is to
addasmallaluminumelectrolyticcapacitorinparallelwith
the low ESR input capacitor. The selected capacitor needs
to have the right amount of ESR in order to critically
dampen the resonant circuit formed by the input lead
inductance and the input capacitor. The typical values of
ESRwillfallintherangeof0.5Ωto2Ωandcapacitancewill
fall in the range of 5µF to 50µF.
If tantalum capacitors are used, values in the 22µF to
470µF range are generally needed to minimize ESR and
meet ripple current and surge ratings. Care should be
taken to ensure the ripple and surge ratings are not
exceeded. The AVX TPS and Kemet T495 series are surge
rated. AVX recommends derating capacitor operating
voltage by 2 for high surge applications.
INPUT CAPACITOR
Step-down regulators draw current from the input supply
in pulses. The rise and fall times of these pulses are very
fast. The input capacitor is required to reduce the voltage
ripple this causes at the input of LT1956 and force the
switching current into a tight local loop, thereby minimiz-
ing EMI. The RMS ripple current can be calculated from:
CATCH DIODE
HighestefficiencyoperationrequirestheuseofaSchottky
type diode. DC switching losses are minimized due to its
low forward voltage drop, and AC behavior is benign due
to its lack of a significant reverse recovery time. Schottky
diodes are generally available with reverse voltage ratings
ofupto60Vandeven100V, andarepricecompetitivewith
other types.
VOUT V – V
(
)
IN
OUT
IRIPPLE(RMS)CIN = IOUT
2
V
IN
Ceramiccapacitorsareidealforinputbypassing.At500kHz
switching frequency, the energy storage requirement of
the input capacitor suggests that values in the range of
2.2µF to 10µF are suitable for most applications. If opera-
tionisrequiredclosetotheminimuminputrequiredbythe
output of the LT1956, a larger value may be required. This
The use of so-called “ultrafast” recovery diodes is gener-
ally not recommended. When operating in continuous
mode, the reverse recovery time exhibited by “ultrafast”
diodes will result in a slingshot type effect. The power
1956f
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internalswitchwillrampupVIN currentintothediodeinan
attempt to get it to recover. Then, when the diode has
finallyturnedoff,sometensofnanosecondslater,theVSW
node voltage ramps up at an extremely high dV/dt, per-
haps 5 to even 10V/ns! With real world lead inductances,
the VSW node can easily overshoot the VIN rail. This can
result in poor RFI behavior and if the overshoot is severe
enough, damage the IC itself.
A 0.1µF boost capacitor is recommended for most appli-
cations. Almost any type of film or ceramic capacitor is
suitable, but the ESR should be <1Ω to ensure it can be
fully recharged during the off time of the switch. The
capacitor value is derived from worst-case conditions of
1800ns on time, 42mA boost current and 0.7V discharge
ripple. The boost capacitor value could be reduced under
less demanding conditions, but this will not improve
circuitoperationorefficiency.Underlowinputvoltageand
low load conditions, a higher value capacitor will reduce
discharge ripple and improve start-up operation.
The suggested catch diode (D1) is an International Recti-
fier 10MQ060N Schottky. It is rated at 1.5A average
forward current and 60V reverse voltage. Typical forward
voltage is 0.63V at 1A. The diode conducts current only
during switch off time. Peak reverse voltage is equal to
regulatorinputvoltage.Averageforwardcurrentinnormal
operation can be calculated from:
SHUTDOWN FUNCTION AND UNDERVOLTAGE
LOCKOUT
Figure 4 shows how to add undervoltage lockout (UVLO)
to the LT1956. Typically, UVLO is used in situations where
the input supply is current limited, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
loadtothesourceandcancausethesourcetocurrentlimit
or latch low under low source voltage conditions. UVLO
prevents the regulator from operating at source voltages
where these problems might occur.
ID(AVG) = IOUT (1 – DC)
This formula will not yield values higher than 1.5A with
maximum load current of 1.5A. The only reason to
consider a larger diode is the worst-case condition of a
high input voltage and shorted output. With a shorted
condition, diode current will increase to a typical value of
2A, determined by peak switch current limit. This is safe
forshortperiodsoftime, butitwouldbeprudenttocheck
with the diode manufacturer if continuous operation
under these conditions must be tolerated.
Threshold voltage for lockout is about 2.38V. A 5.5µA bias
currentflowsout ofthepinatthisthreshold. Theinternally
generated current is used to force a default high state on
the shutdown pin if the pin is left open. When low shut-
down current is not an issue, the error due to this current
can be minimized by making RLO 10k or less. If shutdown
currentisanissue, RLO canberaisedto100k, buttheerror
due to initial bias current and changes with temperature
should be considered.
BOOST PIN
For most applications, the boost components are a 0.1µF
capacitor and an MMSD914TI diode. The anode is typi-
callyconnectedtotheregulatedoutputvoltagetogenerate
avoltageapproximatelyVOUT aboveVIN todrivetheoutput
stage. However, the output stage discharges the boost
capacitor during the on time of the switch. The output
driver requires at least 3V of headroom throughout this
period to keep the switch fully saturated. If the output
voltageislessthan3V,itisrecommendedthatanalternate
boostsupplyisused. Theboostdiodecanbeconnectedto
the input, although, care must be taken to prevent the 2×
VIN boost voltage from exceeding the BOOST pin absolute
maximum rating. The additional voltage across the switch
driver also increases power loss, reducing efficiency. If
available, an independent supply can be used with a local
bypass capacitor.
RLO = 10k to 100k 25k suggested
(
)
RLO V − 2.38V
(
)
IN
RHI =
2.38V −RLO 5.5µA
(
)
VIN = minimum input voltage
Keep the connections from the resistors to the shutdown
pin short and make sure that interplane or surface capaci-
tance to the switching nodes are minimized. If high
resistor values are used, the shutdown pin should be
1956f
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LT1956/LT1956-5
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APPLICATIO S I FOR ATIO
R
FB
L1
LT1956
OUTPUT
V
SW
2.38V
+
–
IN
INPUT
STANDBY
R
HI
5.5µA
+
SHDN
C1
+
–
TOTAL
SHUTDOWN
R
C2
LO
0.4V
GND
1956 F04
Figure 4. Undervoltage Lockout
bypassed with a 1000pF capacitor to prevent coupling
problems from the switch node. If hysteresis is desired in
the undervoltage lockout point, a resistor RFB can be
added to the output node. Resistor values can be calcu-
lated from:
SYNCHRONIZING
The SYNC input must pass from a logic level low, through
the maximum synchronization threshold with a duty cycle
between 10% and 90%. The input can be driven directly
from a logic level output. The synchronizing range is equal
to initial operating frequency up to 700kHz. This means
that minimum practical sync frequency is equal to the
worst-case high self-oscillating frequency (570kHz), not
the typical operating frequency of 500kHz. Caution should
be used when synchronizing above 662kHz because at
highersyncfrequenciestheamplitudeoftheinternalslope
compensation used to prevent subharmonic switching is
reduced. This type of subharmonic switching only occurs
at input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insufficient slope compensa-
tion. Application Note 19 has more details on the theory
of slope compensation.
RLO V − 2.38 ∆V/V
+1 + ∆V
(
)
[
IN
OUT
]
RHI =
2.38 −RLO 5.5µA
(
)
R = R
V
/
∆V
(
)
(
)
FB
HI
OUT
25k suggested for RLO
VIN = Input voltage at which switching stops as input
voltage descends to trip level
∆V = Hysteresis in input voltage level
Example: output voltage is 5V, switching is to stop if input
voltage drops below 12V and should not restart unless
input rises back to 13.5V. ∆V is therefore 1.5V and
VIN = 12V. Let RLO = 25k.
25k 12 − 2.38 1.5/5 +1 + 1.5
(
)
)
[
]
RHI =
At power-up, when VC is being clamped by the FB pin (see
Figure2,Q2),thesyncfunctionisdisabled.Thisallowsthe
frequency foldback to operate in the shorted output con-
dition. During normal operation, switching frequency is
controlledbytheinternaloscillatoruntiltheFBpinreaches
0.8V, after which the SYNC pin becomes operational. If no
synchronization is required, this pin should be connected
2.38 – 25k 5.5µA
(
25k 10.41
(
)
=
= 116k
2.24
RFB = 116k 5/1.5 = 387k
(
)
to ground.
1956f
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LAYOUT CONSIDERATIONS
LT1956
HIGH
FREQUENCY
CIRCULATING
PATH
L1
5V
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency, switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
in Figure 5, must be kept as short as possible. This is
implementedinthesuggestedlayoutofFigure6. Shorten-
ingthispathwillalsoreducetheparasitictraceinductance
of approximately 25nH/inch. At switch off, this parasitic
inductance produces a flyback spike across the LT1956
switch. When operating at higher currents and input
voltages, with poor layout, this spike can generate volt-
ages across the LT1956 that may exceed its absolute
maximum rating. A ground plane should always be used
under the switcher circuitry to prevent interplane coupling
and overall noise.
V
IN
C3
D1 C1
LOAD
1956 F05
Figure 5. High Speed Switching Path
The VC and FB components should be kept as far away as
possible from the switch and boost nodes. The LT1956
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic like oscillation.
CONNECT TO
GROUND PLANE
GND
L1
FOR THE FE PACKAGE,
SOLDER THE EXPOSED
C1
PAD TO THE COPPER
GROUND PLANE
MINIMIZE LT1956
C3-D1 LOOP
D2
UNDERNEATH THE DEVICE
V
OUT
D1
C3
C2
GND
GND
SW
GND
SHDN
SYNC
KELVIN SENSE
V
OUT
V
IN
LT1956
FB
R2
V
C
BOOST
GND
R1
C
FB
BIAS
GND
C
F
V
IN
R
C
KEEP FB AND V COMPONENTS
C
AWAY FROM HIGH FREQUENCY,
HIGH CURRENT COMPONENTS
C
C
PLACE FEEDTHROUGH AROUND
GROUND PINS (4 CORNERS) FOR
GOOD THERMAL CONDUCTIVITY
1956 F06
Figure 6. Suggested Layout
1956f
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APPLICATIO S I FOR ATIO
a >100MHz oscilloscope must be used, and waveforms
should be observed on the leads of the package. This
switch off spike will also cause the SW node to go below
ground. The LT1956 has special circuitry inside which
mitigates this problem, but negative voltages over 0.8V
lasting longer than 10ns should be avoided. Note that
100MHz oscilloscopes are barely fast enough to see the
details of the falling edge overshoot in Figure 7.
Board layout also has a significant effect on thermal resis-
tance. For the GN package, Pins 1, 8, 9 and 16, GND, are
a continuous copper plate that runs under the LT1956 die.
This is the best thermal path for heat out of the package.
Reducing the thermal resistance from Pins 1, 8, 9 and 16
onto the board will reduce die temperature and increase
the power capability of the LT1956. This is achieved by
providing as much copper area as possible around these
pins. Addingmultiplesolderfilledfeedthroughsunderand
around these four corner pins to the ground plane will also
help. Similar treatment to the catch diode and coil termi-
nations will reduce any additional heating effects. For the
FE package, the exposed pad should be soldered to the
copper ground plane underneath the device.
A second, much lower frequency ringing is seen during
switch off time if load current is low enough to allow the
inductor current to fall to zero during part of the switch off
time(seeFigure8).Switchanddiodecapacitanceresonate
with the inductor to form damped ringing at 1MHz to 10
MHz. This ringing is not harmful to the regulator and it has
not been shown to contribute significantly to EMI. Any
attempt to damp it with a resistive snubber will degrade
efficiency.
PARASITIC RESONANCE
Resonance or “ringing” may sometimes be seen on the
switch node (see Figure 7). Very high frequency ringing
following switch rise time is caused by switch/diode/input
capacitor lead inductance and diode capacitance. Schot-
tky diodes have very high “Q” junction capacitance that
can ring for many cycles when excited at high frequency.
Iftotalleadlengthfortheinputcapacitor, diodeandswitch
path is 1 inch, the inductance will be approximately 25nH.
At switch off, this will produce a spike across the NPN
output device in addition to the input voltage. At higher
currents this spike can be in the order of 10V to 20V or
higher with a poor layout, potentially exceeding the abso-
lute max switch voltage. The path around switch, catch
diode and input capacitor must be kept as short as
possibletoensurereliableoperation.Whenlookingatthis,
THERMAL CALCULATIONS
Power dissipation in the LT1956 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current,andinputquiescentcurrent.Thefollowingformu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
Switch loss:
2
RSW OUT
I
V
OUT
(
) (
)
PSW
=
+ tEFF(1/2) I
V
f
(
OUT)( IN)( )
V
IN
SWITCH NODE
VOLTAGE
SW RISE
SW FALL
10V/DIV
0.2A/DIV
2V/DIV
INDUCTOR
CURRENT AT
IOUT = 0.1A
V
IN = 25V
500ns/DIV
1956 F08
VOUT = 5V
50ns/DIV
1956 F07
L = 15µH
Figure 8. Discontinuous Mode Ringing
Figure 7. Switch Node Resonance
1956f
18
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Boost current loss:
(V )(V – VOUT)(ILOAD
)
F
IN
PDIODE
=
2
V
IN
VOUT
I
/36
OUT
(
)
PBOOST
=
VF = Forward voltage of diode (assume 0.63V at 1A)
V
IN
Quiescent current loss:
(0.63)(12 –5)(1)
PDIODE
=
= 0.37W
12
P = V 0.0015 + V 0.003
OUT
(
)
(
)
Q
IN
Notice that the catch diode’s forward voltage contributes
a significant loss in the overall system efficiency. A larger,
low VF diode can improve efficiency by several percent.
RSW = switch resistance (≈0.3) hot
tEFF = effective switch current/voltage overlap time
= (tr + tf + tIr + tIf)
tr = (VIN/1.2)ns
tf = (VIN/1.7)ns
tIr = tIf = (IOUT/0.05)ns
f = switch frequency
PINDUCTOR = (ILOAD)(LDCR
)
L
DCR = inductor DC resistance (assume 0.1Ω)
PINDUCTOR = (1)(0.1) = 0.1W
Typical thermal resistance of the board is 10°C/W. Taking
the catch diode and inductor power dissipation into ac-
count and using the example calculations for LT1956 dis-
sipation, the LT1956 die temperature will be estimated as:
Example: with VIN = 12V, VOUT = 5V and IOUT = 1A:
0.3 1 2 5
(
)( ) ( )
PSW
=
+ 57•10−9 1/2 1 12 500 •103
(
)
)
( )( )
(
(
)
12
TJ = TA + (θJA • PTOT) + (10 • [PDIODE + PINDUCTOR])
= 0.125 + 0.171= 0.296W
With the GN16 package (θJA = 85°C/W), at an ambient
temperature of 70°C:
2
5 1/36
( )
(
)
PBOOST
=
= 0.058W
TJ = 70 + (85 • 0.39) + (10 • 0.47) = 108°C
12
P =12 0.0015 +5 0.003 = 0.033W
(
)
(
)
Q
With the TSSOP package (θJA = 45°C/W) at an ambient
temperature of 70°C:
Total power dissipation in the IC is given by:
PTOT = PSW + PBOOST + PQ
TJ = 70 + (45 • 0.37) + (10 • 0.47) = 91°C
Die temperature can peak for certain combinations of
VIN,VOUT andloadcurrent.WhilehigherVIN givesgreater
switch AC losses, quiescent and catch diode losses, a
lower VIN may generate greater losses due to switch DC
losses. Ingeneral, themaximumandminimumVIN levels
shouldbecheckedwithmaximumtypicalloadcurrentfor
calculation of the LT1956 die temperature. If a more
accurate die temperature is required, a measurement of
theSYNCpinresistance(toGND)canbeused. TheSYNC
pin resistance can be measured by forcing a voltage no
greater than 0.5V at the pin and monitoring the pin
current over temperature in a oven. This should be done
with minimal device power (low VIN and no switching
[VC = 0V]) in order to calibrate SYNC pin resistance with
ambient (oven) temperature.
= 0.296W + 0.058W + 0.033W = 0.39W
Thermal resistance for the LT1956 packages is influenced
by the presence of internal or backside planes.
SSOP (GN16) Package: With a full plane under the GN16
package, thermal resistance will be about 85°C/W.
TSSOP(ExposedPad)Package:Withafullplaneunderthe
TSSOP package, thermal resistance (θJA) will be about
45°C/W.
To calculate die temperature, use the proper thermal
resistance (θJA) number for the desired package an add in
worst-case ambient temperature:
TJ = TA + (θJA • PTOT
)
When estimating ambient, remember the nearby catch
diode and inductor will also be dissipating power.
1956f
19
LT1956/LT1956-5
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APPLICATIO S I FOR ATIO
Note: Some of the internal power dissipation in the IC, due
to BOOST pin voltage, can be transferred outside of the IC
to reduce junction temperature by increasing the voltage
drop in the path of the boost diode D2 (see Figure 9). This
reduction of junction temperature inside the IC will allow
higher ambient temperature operation for a given set of
conditions.BOOSTpincircuitrydissipatespowergivenby:
A zener, D4, placed in series with D2 (see Figure 9), drops
voltage to C2.
Example:
The BOOST pin power dissipation for a 20V input to 12V
output conversion at 1A is given by:
12• 1/36 •12
(
)
P
=
= 0.2W
BOOST
VOUT • I /36 •V
(
)
20
SW
C2
PDISS (BOOST Pin)=
V
IN
If a 7V zener is placed in series with D2, then power
dissipation becomes:
Typically, VC2 (the boost voltage across the capacitor C2)
equals VOUT. This is because diodes D1 and D2 can be
considered almost equal, where:
12• 1/36 •5
(
)
P
=
= 0.084W
BOOST
20
VC2 = VOUT – VF(D2) – [–VF(D1)] = VOUT
.
For an FE package with thermal resistance of 45°C/W,
ambient temperature savings would be:
Hence, the equation for boost circuitry power dissipation
given in the previous Thermal Calculations section, is
stated as:
T (ambient) savings = 0.116W • 45°C/W = 5°C
For a GN package with thermal resistance of 85°C/W,
VOUT • I /36 •V
(
)
SW
OUT
ambient temperature savings would be:
PDISS(BOOST)
=
V
IN
T (ambient) savings = 0.116W • 85°C/W = 10°C
Here it can be seen that boost power dissipation increases
as the square of VOUT. It is possible, however, to reduce
VC2 below VOUT to save power dissipation by increasing
the voltage drop in the path of D2. Care should be taken
that VC2 does not fall below the minimum 3.3V boost
voltage required for full saturation of the internal power
switch.Foroutputvoltagesof5V,VC2 isapproximately5V.
During switch turn on, VC2 will fall as the boost capacitor
C2isdischargedbytheBOOSTpin.InthepreviousBOOST
Pin section, the value of C2 was designed for a 0.7V droop
in VC2 (= VDROOP). Hence, an output voltage as low as 4V
would still allow the minimum 3.3V for the boost function
using the C2 capacitor calculated.
The 7V zener should be sized for excess of 0.116W
operation. The tolerances of the zener should be consid-
ered to ensure minimum VBOOST exceeds 3.3V + VDROOP
.
D2
D2
D4
BOOST
LT1956
C2
L1
V
V
OUT
V
SW
IN
IN
C3
SHDN
BIAS
+
R1
C1
SYNC
GND
FB
R2
If a target output voltage of 12V is required, however, an
excess of 8V is placed across the boost capacitor which is
not required for the boost function but still dissipates
additional power.
V
C
D1
R
C
C
F
C
C
What is required is a voltage drop in the path of D2 to
achieve minimal power dissipation while still maintaining
minimum boost voltage across C2.
1956 F09
Figure 9. BOOST Pin, Diode Selection
1956f
20
LT1956/LT1956-5
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APPLICATIO S I FOR ATIO
U
Input Voltage vs Operating Frequency Considerations
circuits, read the Layout Considerations section first.
Common layout errors that appear as stability problems
are distant placement of input decoupling capacitor and/
or catch diode, and connecting the VC compensation to a
ground track carrying significant switch current. In addi-
tion, the theoretical analysis considers only first order
non-ideal component behavior. For these reasons, it is
important that a final stability check is made with produc-
tion layout and components.
TheabsolutemaximuminputsupplyvoltagefortheLT1956
is specified at 60V. This is based on internal semiconduc-
tor junction breakdown effects. The practical maximum
input supply voltage for the LT1956 may be less than 60V
due to internal power dissipation or switch minimum on
time considerations.
For the extreme case of an output short-circuit fault to
ground, see the section Short-Circuit Considerations.
The LT1956 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 10.
The LT1956 can be considered as two gm blocks, the error
amplifier and the power stage.
A detailed theoretical basis for estimating internal power
dissipation is given in the Thermal Calculations section.
Thiswillallowafirstpasscheckofwhetheranapplication’s
maximum input voltage requirement is suitable for the
LT1956. Be aware that these calculations are for DC input
voltages and that input voltage transients as high as 60V
are possible if the resulting increase in internal power
dissipation is of insufficient time duration to raise die
temperature significantly. For the FE package, this means
high voltage transients on the order of hundreds of milli-
seconds are possible. If LT1956 (FE package) thermal
calculations show power dissipation is not suitable for the
given application, the LT1766 (FE package) is a recom-
mended alternative since it is identical to the LT1956 but
runs cooler at 200kHz.
Figure 11 shows the overall loop response. At the VC pin,
the frequency compensation components used are:
RC = 2.2k, CC = 0.022µF and CF = 220pF. The output
capacitor used is a 100µF, 10V tantalum capacitor with
typical ESR of 100mΩ.
TheESRofthetantalumoutputcapacitorprovidesauseful
zerointheloopfrequencyresponseformaintainingstabil-
ity. This ESR, however, contributes significantly to the
ripple voltage at the output (see Output Ripple Voltage in
the Applications Information section). It is possible to
reduce capacitor size and output ripple voltage by replac-
ing the tantalum output capacitor with a ceramic output
capacitor because of its very low ESR. The zero provided
by the tantalum output capacitor must now be reinserted
back into the loop. Alternatively, there may be cases
where, even with the tantalum output capacitor, an addi-
tional zero is required in the loop to increase phase margin
for improved transient response.
Switch minimum on time is the other factor that may limit
the maximum operational input voltage for the LT1956 if
pulse-skipping behavior is not allowed. For the LT1956,
pulse-skipping may occur for VIN/(VOUT + VF) ratios > 4.
(VF = Schottky diode D1 forward voltage drop, Figure 5.)
If the LT1766 is used, the ratio increases to 10. Pulse-
skippingistheregulator’swayofmissingswitchpulsesto
maintain output voltage regulation. Although an increase
in output ripple voltage can occur during pulse-skipping,
a ceramic output capacitor can be used to keep ripple
voltage to a minimum (see output ripple voltage compari-
son for tantalum vs ceramic output capacitors, Figure 3).
Azerocanbeaddedintotheloopbyplacingaresistor(RC)
attheVC pininserieswiththecompensationcapacitor,CC,
or by placing a capacitor (CFB) between the output and the
FB pin.
When using RC, the maximum value has two limitations.
First, thecombinationofoutputcapacitorESRandRC may
stopthelooprollingoffaltogether. Second, iftheloopgain
is not rolled off sufficiently at the switching frequency,
output ripple will perturb the VC pin enough to cause
unstable duty cycle switching similar to subharmonic
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response,thefollowingshouldberemembered—theworse
the board layout, the more difficult the circuit will be to
stabilize. This is true of almost all high frequency analog
1956f
21
LT1956/LT1956-5
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APPLICATIO S I FOR ATIO
80
60
180
150
120
90
LT1956
CURRENT MODE
POWER STAGE
SW
GAIN
OUTPUT
ERROR
g
m
= 2mho
40
AMPLIFIER
C
FB
R1
R
FB
–
TANTALUM CERAMIC
20
g
=
m
2000µmho
PHASE
ESR
ESL
+
R
200k
1.22V
O
0
60
LOAD
+
C1
C1
GND
V
C
–20
–40
30
R2
0
R
C
10
100
1k
10k
100k
1M
C
F
FREQUENCY (Hz)
1956 F11
C
C
V
= 12V
R
C
C
= 2.2k
= 22nF
= 220pF
IN
C
C
F
1956 F10
V
= 5V
OUT
LOAD
I
= 500mA
= 100µF, 10V, 0.1Ω
C
OUT
Figure 10. Model for Loop Response
Figure 11. Overall Loop Response
oscillations. If needed, an additional capacitor (CF) can be
addedacrosstheRC/CC networkfromtheVC pintoground
to further suppress VC ripple voltage.
CONVERTER WITH BACKUP OUTPUT REGULATOR
In systems with a primary and backup supply, for ex-
ample, a battery powered device with a wall adapter input,
the output of the LT1956 can be held up by the backup
supply with the LT1956 input disconnected. In this condi-
tion, the SW pin will source current into the VIN pin. If the
SHDN pin is held at ground, only the shut down current of
25µAwillbepulledviatheSWpinfromthesecondsupply.
With the SHDN pin floating, the LT1956 will consume its
quiescentoperatingcurrentof1.5mA. TheVIN pinwillalso
source current to any other components connected to the
input line. If this load is greater than 10mA or the input
could be shorted to ground, a series Schottky diode must
be added, as shown in Figure 12. With these safeguards,
the output can be held at voltages up to the VIN absolute
maximum rating.
With a tantalum output capacitor, the LT1956 already
includes a resistor (RC) and filter capacitor (CF) at the VC
pin (see Figures 10 and 11) to compensate the loop over
the entire VIN range (to allow for stable pulse skipping for
high VIN-to-VOUT ratios ≥ 4). A ceramic output capacitor
can still be used with a simple adjustment to the resistor
RC for stable operation (see Ceramic Capacitors section
for stabilizing LT1956). If additional phase margin is
required, a capacitor (CFB) can be inserted between the
output and FB pin but care must be taken for high output
voltage applications. Sudden shorts to the output can
create unacceptably large negative transients on the FB
pin.
For VIN-to-VOUT ratios < 4, higher loop bandwidths are
possiblebyreadjustingthefrequencycompensationcom-
ponents at the VC pin.
BUCK CONVERTER WITH ADJUSTABLE SOFT-START
Large capacitive loads or high input voltages can cause
high input currents at start-up. Figure 13 shows a circuit
that limits the dv/dt of the output at start-up, controlling
the capacitor charge rate. The buck converter is a typical
configuration with the addition of R3, R4, CSS and Q1.
As the output starts to rise, Q1 turns on, regulating switch
When checking loop stability, the circuit should be oper-
ated over the application’s full voltage, current and tem-
peraturerange.Properloopcompensationmaybeobtained
byempiricalmethodsasdescribedinApplicationNotes19
and 76.
1956f
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APPLICATIO S I FOR ATIO
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MMSD914TI
C2
0.1µF
D3
L1
18µH
10MQ060N
BOOST
LT1956
REMOVABLE
INPUT
V
SW
IN
5V, 1A
R3
ALTERNATE
SUPPLY
BIAS
54k
R1
SHDN
SYNC
GND
15.4k
FB
C1
100µF
10V
+
D1
10MQ060N
R2
4.99k
V
C
R4
25k
C3
2.2µF
C
R
C
2.2k
F
220pF
C
C
0.022µF
1956 F12
Figure 12. Dual Source Supply with 25µA Reverse Leakage
D2
MMSD914TI
C2
0.1µF
L1
18µH
BOOST
BIAS
SW
OUTPUT
5V
1A
INPUT
12V
V
IN
C3
2.2µF
CERAMIC
+
R1
15.4k
C1
100µF
D1
LT1956
SHDN
FB
R2
4.99k
SYNC GND
V
C
C
SS
R3
2k
15nF
Q1
C
R
C
2.2k
F
1766 F13
220pF
C
R4
47k
C
0.022µF
Figure 13. Buck Converter with Adjustable Soft-Start
current via the VC pin to maintain a constant dv/dt at the
output. Output rise time is controlled by the current
through CSS defined by R4 and Q1’s VBE. Once the output
is in regulation, Q1 turns off and the circuit operates
normally. R3 is transient protection for the base of Q1.
The ramp is linear and rise times in the order of 100ms are
possible. Since the circuit is voltage controlled, the ramp
rate is unaffected by load characteristics and maximum
outputcurrentisunchanged. Variantsofthiscircuitcanbe
used for sequencing multiple regulator outputs.
R4 CSS VOUT
( )( )(
)
DUAL POLARITY OUTPUT CONVERTER
RiseTime =
VBE
The circuit in Figure 14a generates both positive and
negative 5V outputs with all components under 3mm
height. The topology for the 5V output is a standard buck
converter. The –5V output uses a second inductor L2,
diode D3 and output capacitor C6. The capacitor C4
1956f
Using the values shown in Figure 10,
47 •103 15•10–9
5
( )
(
)(
)
Rise Time =
= 5ms
0.7
23
LT1956/LT1956-5
APPLICATIO S I FOR ATIO
W U U
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D2
MMSD914TI
C2
0.1µF
L1*
V
BOOST
LT1956
IN
15µH
9V TO 12V
(TRANSIENTS
TO 36V)
V
**
OUT1
5V
V
SW
FB
IN
R1
15.4k
SHDN
C5
C3
+
10µF
6.3V
CER
2.2µF
50V
SYNC
GND
R2
4.99k
V
C
CERAMIC
D1
R
C
F
220pF
C
B0540W
2.2k
C
C
3300pF
GND
C4
+
+
C6
10µF
6.3V CER
10µF
6.3V
CER
L2*
*SUMIDA CDRH4D28-150
**SEE FIGURE 14c FOR V
, V
OUT1 OUT2
**†
LOAD CURRENT RELATIONSHIP
V
OUT2
†IF LOAD CAN GO TO ZERO, AN OPTIONAL
PRELOAD OF 500Ω CAN BE
–5V
D3
B0540W
1956 F14a
USED TO IMPROVE REGULATION
Figure 14a. Dual Polarity Output Converter
5.30
5.25
500
450
400
350
300
250
200
150
100
50
100
90
80
70
60
50
40
30
20
10
V
LOAD CURRENT
750mA
OUT1
V
LOAD CURRENT
OUT1
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
4.75
750mA
V
LOAD CURRENT
250mA
OUT1
V
LOAD CURRENT
OUT1
500mA
V
LOAD CURRENT
OUT1
250mA
0
0
0
0
400
600
0
100
V
200
300
400
500
600
200
800
100
200
300
400
500
LOAD CURRENT (mA)
V
OUT1
LOAD CURRENT (mA)
OUT2
V
LOAD CURRENT (mA)
OUT2
1956 F15b
1956 F14c
1956 F14d
Figure 14b. VOUT2 (–5V) Maximum
Allowable Load Current vs VOUT1
(5V) Load Current
Figure 14c. VOUT2 (–5V) Output
Voltage vs Load Current
Figure 14d. Dual Polarity Output
Converter Efficiency
transformer becomes available to provide a better height/
cost solution, refer to the dual output SEPIC circuit de-
scription in Design Note 100 for correct transformer
connection.
couples energy to L2 and ensures equal voltages across
L2 and L1 during steady state. Instead of using a trans-
former for L1 and L2, uncoupled inductors were used
becausetheyrequirelessheightthanasingletransformer,
can be placed separately in the circuit layout for optimized
space savings and reduce overall cost. This is true even
whentheuncoupledinductorsaresized(twicethevalueof
inductance of the transformer) in order to keep ripple
current comparable to the transformer solution. If a single
During switch on-time, in steady state, the voltage across
both L1 and L2 is positive and equal; with energy (and
current) ramping up in each inductor. The current in L2 is
provided by the coupling capacitor C4. During switch off-
time, current ramps downward in each inductor. The
1956f
24
LT1956/LT1956-5
W U U
APPLICATIO S I FOR ATIO
U
currentinL2andC4flowsviathecatchdiodeD3, charging
the negative output capacitor C6. If the negative output is
not loaded enough, it can go severely unregulated (be-
come more negative). Figure 14b shows the maximum
allowable –5V output load current (vs load current on the
5V output) that will maintain the –5V output within 3%
tolerance. Figure 14c shows the –5V output voltage regu-
lation vs its own load current when plotted for three
separate load currents on the 5V output. The efficiency of
the dual output converter circuit shown in Figure 14a is
given in Figure 14d.
(V )(VOUT
)
IN
IP –
(VOUT )(V – 0.3)
IN
2(VOUT + V )(f)(L)
IN
IMAX
=
(VOUT + V – 0.3)(VOUT + VF)
IN
IP = maximum rated switch current
VIN = minimum input voltage
OUT = output voltage
VF = catch diode forward voltage
0.3 = switch voltage drop at 1.5A
V
Example: with VIN(MIN) = 5.5V, VOUT = 12V, L = 15µH,
VF = 0.63V, IP = 1.5A: IMAX = 0.36A.
POSITIVE-TO-NEGATIVE CONVERTER
INDUCTOR VALUE
The circuit in Figure 15 is a positive-to-negative topology
using a grounded inductor. It differs from the standard
approach in the way the IC chip derives its feedback signal
because the LT1956 accepts only positive feedback sig-
nals. Thegroundpinmustbetiedtotheregulatednegative
output. A resistor divider to the FB pin, then provides the
proper feedback voltage for the chip.
The criteria for choosing the inductor is typically based on
ensuring that peak switch current rating is not exceeded.
This gives the lowest value of inductance that can be used,
but in some cases (lower output load currents) it may give
a value that creates unnecessarily high output ripple
voltage.
The difficulty in calculating the minimum inductor size
needed is that you must first decide whether the switcher
will be in continuous or discontinuous mode at the critical
point where switch current reaches 1.5A. The first step is
to use the following formula to calculate the load current
above which the switcher must use continuous mode. If
your load current is less than this, use the discontinuous
mode formula to calculate minimum inductor needed. If
load current is higher, use the continuous mode formula.
Thefollowingequationcanbeusedtocalculatemaximum
load current for the positive-to-negative converter:
D2
MMSD914TI
C2
0.1µF
L1*
7µH
BOOST
V
IN
SW
FB
V
IN
12V
R1
36.5k
LT1956
C3
2.2µF
25V
GND
V
C
Output current where continuous mode is needed:
+
C1
100µF
20V TANT
D1
C
C
10MQO60N
C
F
(V )2(IP)2
R2
IN
4.12k
R
C
ICONT >
OUTPUT**
–12V, 0.25A
1956 F15
4(V + VOUT)(V + VOUT + V )
IN
IN
F
* INCREASE L1 TO 10µH OR 18µH FOR HIGHER CURRENT APPLICATIONS.
Minimum inductor discontinuous mode:
SEE APPLICATIONS INFORMATION
** MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE
AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION
2(VOUT)(IOUT
(f)(IP)2
)
LMIN
=
Figure 15. Positive-to-Negative Converter
1956f
25
LT1956/LT1956-5
U
PACKAGE DESCRIPTIO
Minimum inductor continuous mode:
The output capacitor ripple current for the positive-to-
negative converter is similar to that for a typical buck
regulator—it is a triangular waveform with peak-to-peak
valueequaltothepeak-to-peaktriangularwaveformofthe
inductor. The low output ripple design in Figure 14 places
theinputcapacitorbetweenVIN andtheregulatednegative
output. This placement of the input capacitor significantly
reduces the size required for the output capacitor (versus
placing the input capacitor between VIN and ground).
(V )(VOUT
)
IN
LMIN
=
(VOUT + VF)
2(f)(V + VOUT ) IP – IOUT 1+
IN
V
IN
For a 12V to –12V converter using the LT1956 with peak
switch current of 1.5A and a catch diode of 0.63V:
(12)2(1.5)2
4(12 +12)(12 +12 + 0.63)
ICONT
>
= 0.370A
The peak-to-peak ripple current in both the inductor and
output capacitor (assuming continuous mode) is:
For a load current of 0.25A, this says that discontinuous
mode can be used and the minimum inductor needed is
found from:
DC • V
IN
IP-P
=
f •L
V
OUT + V
F
DC = Duty Cycle =
2(12)(0.25)
(500 •103)(1.5)2
LMIN
=
= 5.3µH
V
OUT + V + V
IN F
IP-P
ICOUT (RMS) =
In practice, the inductor should be increased by about
30% over the calculated minimum to handle losses and
variations in value. This suggests a minimum inductor of
7µH for this application.
12
Theoutputripplevoltageforthisconfigurationisaslowas
the typical buck regulator based predominantly on the
inductor’s triangular peak-to-peak ripple current and the
ESR of the chosen capacitor (see Output Ripple Voltage in
Applications Information).
Ripple Current in the Input and Output Capacitors
Positive-to-negative converters have high ripple current
in the input capacitor. For long capacitor lifetime, the
RMS value of this current must be less than the high
frequency ripple current rating of the capacitor. The
followingformulawillgiveanapproximatevalueforRMS
ripple current. This formula assumes continuous mode
and large inductor value. Small inductors will give some-
what higher ripple current, especially in discontinuous
mode. The exact formulas are very complex and appear
in Application Note 44, pages 29 and 30. For our pur-
poses here I have simply added a fudge factor (ff). The
value for ff is about 1.2 for higher load currents and L
≥15µH. It increases to about 2.0 for smaller inductors at
lower load currents.
Diode Current
Average diodecurrentisequaltoloadcurrent. Peak diode
current will be considerably higher.
Peak diode current:
ContinuousMode =
(V + VOUT
)
(V )(VOUT)
IN
IN
IOUT
+
V
IN
2(L)(f)(V + VOUT)
IN
2(IOUT)(VOUT
(L)(f)
)
DiscontinuousMode =
Keep in mind that during start-up and output overloads,
average diode current may be much higher than with
normalloads.Careshouldbeusedifdiodesratedlessthan
1A are used, especially if continuous overload conditions
must be tolerated.
VOUT
V
IN
Capacitor IRMS = (ff)(IOUT
)
ff = 1.2 to 2.0
1956f
26
LT1956/LT1956-5
U
PACKAGE DESCRIPTIO
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BB
4.90 – 5.10*
(.193 – .201)
3.58
(.141)
3.58
(.141)
16 1514 13 12 1110
9
6.60 ±0.10
4.50 ±0.10
2.94
(.116)
SEE NOTE 4
2.94
(.116)
6.40
BSC
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.0433)
MAX
4.30 – 4.50*
(.169 – .177)
0° – 8°
0.65
(.0256)
BSC
0.45 – 0.75
0.09 – 0.20
0.05 – 0.15
(.018 – .030)
(.0036 – .0079)
(.002 – .006)
0.195 – 0.30
(.0077 – .0118)
FE16 (BB) TSSOP 0203
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
1956f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LT1956/LT1956-5
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.053 – .068
(1.351 – 1.727)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
(0.203 – 0.305)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
GN16 (SSOP) 0502
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LT1074/LT1076/ Step-Down Switching Regulators
LT1076HV
Up to 64V Input, 100kHz, 5A and 2A
LT1082
LT1370
LT1371
1A High Voltage/Efficiency Switching Voltage Regulator
Up to 75V Input, 60kHz Operation
Up to 42V, 6A, 500kHz Switch
Up to 35V, 3A, 500kHz Switch
High Efficiency DC/DC Converter
High Efficiency DC/DC Converter
LT1375/LT1376 1.5A, 500kHz Step-Down Switching Regulators
Operation Up to 25V Input, Synchronizable (LT1375),
N8, S8, S16
LT1616
LT1676
LT1765
600mA, 1.4MHz Step-Down Switching Regulator
3.6V to 25V V , 6-Lead ThinSOTTM
IN
Wide Input Range, High Efficiency, Step-Down Switching Regulator 7.4V to 60V V , 100kHz Operation, 700mA Internal Switch, S8
IN
Monolithic 3A, 1.25MHz Step-Down Regulator
V : 3V to 25V; V = 1.2V; S8, TSSOP-16E
IN
REF
Exposed Pad
LT1766
Wide Input Range, High Efficiency, Step-Down Switching Regulator 5.5V to 60V Input, 200kHz Operation, 1.5A Internal Switch,
TSSOP-16E
LT1767
LT1776
Monolithic 1.5A, 1.25MHz Step-Down Regulator
V : 3V to 25V; V = 1.2V; MS8
IN REF
Wide Input Range, High Efficiency, Step-Down Switching Regulator Up to 7.4V to 60V, 200kHz Operation, 700mA Internal Switch,
TSSOP-16E
LT1777
Low Noise Buck Regulator
Operation Up to 48V, Controlled Voltage
and Current Slew Rates, S16
ThinSOT is a trademark of Linear Technology Corporation.
1956f
LT/TP 0303 2K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2001
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