LT1964ES5-SD#TRM [Linear]
LT1964 - 200mA, Low Noise, Low Dropout Negative Micropower Regulator; Package: SOT; Pins: 5; Temperature Range: -40°C to 85°C;型号: | LT1964ES5-SD#TRM |
厂家: | Linear |
描述: | LT1964 - 200mA, Low Noise, Low Dropout Negative Micropower Regulator; Package: SOT; Pins: 5; Temperature Range: -40°C to 85°C 线性稳压器IC 调节器 电源电路 光电二极管 输出元件 PC |
文件: | 总16页 (文件大小:222K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LT1964
200mA, Low Noise,
Low Dropout Negative
Micropower Regulator
FEATURES
DESCRIPTION
TheLT®1964isamicropowerlownoise,lowdropoutnega-
tive regulator. The device is capable of supplying 200mA
of output current with a dropout voltage of 340mV. Low
quiescent current (30μA operating and 3μA shutdown)
makes the LT1964 an excellent choice for battery-pow-
ered applications. Quiescent current is well controlled in
dropout.
n
Low Noise: 30μV
(10Hz to 100kHz)
RMS
n
Low Quiescent Current: 30μA
Low Dropout Voltage: 340mV
Output Current: 200mA
n
n
n
n
n
n
n
n
Fixed Output Voltage: –5V
Adjustable Output from –1.22V to –20V
Positive or Negative Shutdown Logic
3μA Quiescent Current in Shutdown
Stable with 1μF Output Capacitor
Stable with Aluminum, Tantalum, or Ceramic
Capacitors
Thermal Limiting
Low Profile (1mm) ThinSOT™ and (0.75mm) 8-Pin
3mm × 3mm DFN Packages
Other features of the LT1964 include low output noise.
With the addition of an external 0.01μF bypass capacitor,
outputnoiseisreducedto30μV
overa10Hzto100kHz
RMS
bandwidth. The LT1964 is capable of operating with small
capacitors and is stable with output capacitors as low
as 1μF. Small ceramic capacitors can be used without
the necessary addition of ESR as is common with other
regulators. Internal protection circuitry includes reverse
output protection, current limiting, and thermal limiting.
The device is available with a fixed output voltage of –5V
and as an adjustable device with a –1.22V reference volt-
age. The LT1964 regulators are available in a low profile
(1mm) ThinSOT and the low profile (0.75mm) 8-pin
(3mm × 3mm) DFN packages.
n
n
APPLICATIONS
n
Battery-Powered Instruments
n
Low Noise Regulator for Noise-Sensitive
Instrumentation
n
Negative Complement to LT1761 Family of
Positive LDOs
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. ThinSOT is
a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
TYPICAL APPLICATION
10Hz to 100kHz Output Noise
–5V Low Noise Regulator
1μF
10μF
GND
V
OUT
30μV
RMS
SHDN
BYP
OUT
V
100μV/DIV
IN
–5.4V
0.01μF
LT1964-5
TO –20V
IN
–5V AT 200mA
30μV
NOISE
RMS
1964 TA01a
1964 TA01b
1ms/DIV
1964fb
1
LT1964
ABSOLUTE MAXIMUM RATINGS
(Note 1)
SHDN Pin Voltage
IN Pin Voltage ........................................................ 20V
OUT Pin Voltage (Note 11)...................................... 20V
OUT to IN Differential Voltage (Note 11) ........ –0.5V, 20V
ADJ Pin Voltage
(with Respect to IN Pin) (Note 11)............. –0.5V, 20V
BYP Pin Voltage
(with Respect to GND Pin)..........................–20V, 15V
Output Short-Circuit Duration .......................... Indefinite
Operating Junction Temperature (E, I Grade)
Range (Note 10) ............................... – 40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
(with Respect to IN Pin)..................................... 20V
SHDN Pin Voltage
SOT-23 Package................................................ 300°C
(with Respect to IN Pin) (Note 11)............. –0.5V, 35V
PIN CONFIGURATION
LT1964
LT1964-SD
TOP VIEW
TOP VIEW
OUT
OUT
1
2
3
4
8
7
6
5
IN
GND 1
IN 2
5 OUT
4 ADJ
IN
9
ADJ
GND
BYP
SHDN 3
SHDN
S5 PACKAGE
5-LEAD PLASTIC SOT-23
DD PACKAGE
T
JMAX
= 150°C, θ ≈125°C/W to 250°C/W
JA
8-LEAD (3mm s 3mm) PLASTIC DFN
(NOTE 13)
T
= 125°C, θ = 40°C/W, θ = 16°C/W
JMAX
JA
JC
SEE THE APPLICATIONS INFORMATION SECTION
(NOTE 13)
EXPOSED PAD (PIN 9) IS IN, MUST BE SOLDERED TO PCB
LT1964-BYP
LT1964-5
TOP VIEW
TOP VIEW
GND 1
IN 2
5 OUT
4 ADJ
GND 1
IN 2
5 OUT
BYP 3
BYP 3
4 SHDN
S5 PACKAGE
5-LEAD PLASTIC SOT-23
S5 PACKAGE
5-LEAD PLASTIC SOT-23
T
= 150°C, θ ≈125°C/W to 250°C/W
T
= 150°C, θ ≈125°C/W to 250°C/W
JMAX
JA
JMAX
JA
(NOTE 13)
(NOTE 13)
SEE THE APPLICATIONS INFORMATION SECTION
SEE THE APPLICATIONS INFORMATION SECTION
ORDER INFORMATION
LEAD FREE FINISH
LT1964ES5-SD#PBF
LT1964ES5-BYP#PBF
LT1964ES5-5#PBF
LT1964EDD#PBF
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
LT1964ES5-SD#TRPBF
LTVX
5-Lead Plastic SOT-23
LT1964ES5-BYP#TRPBF LTVY
5-Lead Plastic SOT-23
LT1964ES5-5#TRPBF
LT1964EDD#TRPBF
LT1964IS5-SD#TRPBF
LT1964IS5-BYP#TRPBF
LT1964IS5-5#TRPBF
LT1964IDD#TRPBF
LTVZ
5-Lead Plastic SOT-23
LDVM
LTVX
LTVY
8-Lead (3mm × 3mm) Plastic DFN
5-Lead Plastic SOT-23
LT1964IS5-SD#PBF
LT1964IS5-BYP#PBF
LT1964IS5-5#PBF
LT1964IDD#PBF
5-Lead Plastic SOT-23
LTVZ
5-Lead Plastic SOT-23
LDVM
8-Lead (3mm × 3mm) Plastic DFN
1964fb
2
LT1964
ORDER INFORMATION
LEAD BASED FINISH
LT1964ES5-SD
LT1964ES5-BYP
LT1964ES5-5
LT1964EDD
TAPE AND REEL
LT1964ES5-SD#TR
LT1964ES5-BYP#TR
LT1964ES5-5#TR
LT1964EDD#TR
PART MARKING*
LTVX
PACKAGE DESCRIPTION
5-Lead Plastic SOT-23
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
LTVY
5-Lead Plastic SOT-23
LTVZ
5-Lead Plastic SOT-23
LDVM
LTVX
8-Lead (3mm × 3mm) Plastic DFN
5-Lead Plastic SOT-23
LT1964IS5-SD
LT1964IS5-BYP
LT1964IS5-5
LT1964IS5-SD#TR
LT1964IS5-BYP#TR
LT1964IS5-5#TR
LT1964IDD#TR
LTVY
5-Lead Plastic SOT-23
LTVZ
5-Lead Plastic SOT-23
LT1964IDD
LDVM
8-Lead (3mm × 3mm) Plastic DFN
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Regulated Output Voltage
(Notes 3, 9)
LT1964-5
V
= –5.5V, I
= –1mA
LOAD
–4.925
–4.850
–5
–5
–5.075
–5.150
V
V
IN
l
l
–20V < V < –6V, –200mA < I
< –1mA
IN
LOAD
ADJ Pin Voltage
(Notes 2, 3, 9)
LT1964
V
= –2V, I
= –1mA
–1.202
–1.184
–1.22
–1.22
–1.238
–1.256
V
V
IN
LOAD
–20V < V < –2.8V, –200mA < I
< –1mA
IN
LOAD
l
l
Line Regulation
LT1964-5
ΔV = –5.5V to –20V, I
IN
= –1mA
= –1mA
15
1
50
12
mV
mV
IN
LOAD
LOAD
LT1964 (Note 2) ΔV = –2.8V to –20V, I
Load Regulation
LT1964-5
LT1964
V
V
= –6V, ΔI
= –6V, ΔI
= –1mA to –200mA
= –1mA to –200mA
15
35
50
mV
mV
IN
IN
LOAD
LOAD
l
l
l
l
l
l
V
V
= –2.8V, ΔI
= –2.8V, ΔI
= –1mA to –200mA
= –1mA to –200mA
2
7
15
mV
mV
IN
IN
LOAD
LOAD
Dropout Voltage
I
I
= –1mA
= –1mA
0.1
0.15
0.19
V
V
LOAD
LOAD
V
= V
OUT(NOMINAL)
IN
(Notes 4, 5)
I
I
= –10mA
= –10mA
0.15
0.26
0.34
0.20
0.25
V
V
LOAD
LOAD
I
I
= –100mA
= –100mA
0.33
0.39
V
V
LOAD
LOAD
I
I
= –200mA
= –200mA
0.42
0.49
V
V
LOAD
LOAD
l
l
l
l
l
GND Pin Current
I
I
I
I
I
= 0mA
30
85
300
1.3
2.5
70
180
600
3
μA
μA
LOAD
LOAD
LOAD
LOAD
LOAD
V
= V
= –1mA
IN
OUT(NOMINAL)
(Notes 4, 6)
= –10mA
= –100mA
= –200mA
μA
mA
mA
6
1964fb
3
LT1964
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
Output Voltage Noise
C
= 10μF, C
= 0.01μF, I
= –200mA, BW = 10Hz to 100kHz
30
30
μV
RMS
OUT
BYP
LOAD
ADJ Pin Bias Current
(Notes 2, 7)
100
nA
l
l
Minimum Input Voltage (Note 12)
LOAD
LT1964-BYP
LT1964-SD
–1.9
–1.6
–2.8
–2.2
V
V
I
= –200mA
l
l
l
l
Shutdown Threshold
V
OUT
V
OUT
V
OUT
V
OUT
= Off to On (Positive)
= Off to On (Negative)
= On to Off (Positive)
= On to Off (Negative)
1.6
–1.9
0.8
2.1
–2.8
V
V
V
V
0.25
–0.25
–0.8
SHDN Pin Current (Note 8)
V
SHDN
V
SHDN
V
SHDN
= 0V
= 15V
= –15V
–1
0.1
6
–3
1
15
–9
μA
μA
μA
l
Quiescent Current in Shutdown
Ripple Rejection
V
V
= –6V, V
= 0V
SHDN
3
10
μA
dB
IN
– V
= –1.5V(Avg), V
= 0.5V ,
P-P
46
54
IN
OUT
RIPPLE
f
= 120Hz, I
= –200mA
LOAD
RIPPLE
Current Limit
V
V
= –6V, V
= 0V
350
mA
mA
IN
IN
OUT
l
l
220
= V
–1.5V, ΔV
OUT
= 0.1V
OUT(NOMINAL)
Input Reverse Leakage Current
V
IN
= 20V, V , V , V
= Open Circuit
1
mA
OUT ADJ SHDN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime
Note 2: The LT1964 (adjustable version) is tested and specified for these
conditions with the ADJ pin connected to the OUT pin.
Note 3: Operating conditions are limited by maximum junction
temperature. The regulated output voltage specification will not apply
for all possible combinations of input voltage and output current. When
operating at maximum input voltage, the output current range must be
limited. When operating at maximum output current, the input voltage
range must be limited.
Note 4: To satisfy requirements for minimum input voltage, the LT1964
(adjustable version) is tested and specified for these conditions with an
external resistor divider (two 249k resistors) for an output voltage of
–2.44V. The external resistor divider will add a 5μA DC load on the output.
Note 5: Dropout voltage is the minimum input to output voltage differential
needed to maintain regulation at a specified output current. In dropout, the
Note 7: ADJ pin bias current flows out of the ADJ pin.
Note 8: Positive SHDN pin current flows into the SHDN pin. SHDN pin
current is included in the GND pin current specification.
Note 9: For input-to-output differential voltages greater than 7V, a 50μA
load is needed to maintain regulation.
Note 10: The LT1964 is tested and specified under pulse load conditions
such that T ≅ T . The LT1964E is tested at T = 25°C. Performance at
J
A
A
–40°C to 125°C is assured by design, characterization and correlation with
statistical process controls. The LT1964I is guaranteed over the full –40°C
to 125°C operating junction temperature range.
Note 11: A parasitic diode exists internally on the LT1964 between the
OUT, ADJ and SHDN pins and the IN pin. The OUT, ADJ and SHDN pins
cannot be pulled more than 0.5V more negative than the IN pin during
fault conditions, and must remain at a voltage more positive than the IN
pin during operation.
Note 12: For the LT1964-BYP, this specification accounts for the operating
threshold of the SHDN pin, which is tied to the IN pin internally. For the
LT1964-SD, the SHDN threshold must be met to ensure device operation.
output voltage will be equal to: (V + V
Note 6: GND pin current is tested with V = V
source load. This means the device is tested while operating in its dropout
region. This is the worst-case GND pin current. The GND pin current will
decrease slightly at higher input voltages.
).
Note 13: Actual thermal resistance (θ ) junction to ambient will be a
function of board layout. See the Thermal Considerations section in the
Applications Information.
IN
DROPOUT
JA
and a current
IN
OUT(NOMINAL)
1964fb
4
LT1964
TYPICAL PERFORMANCE CHARACTERISTICS
Typical Dropout Voltage
Guaranteed Dropout Voltage
Dropout Voltage
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
= TEST POINT
T
T
= 125°C
= 25°C
J
J
T
T
≤ 125°C
≤ 25°C
J
J
I
L
= –200mA
I
I
= –100mA
= –50mA
L
L
I
I
= –10mA
= –1mA
L
L
0
0
0
0
–40
–80
–120
–160
–200
–50 –25
0
25
50
75 100 125
0
–40
–80
–120
–160
–200
OUTPUT CURRENT (mA)
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
1964 G02
1964 G03
1964 G01
LT1964-5
Output Voltage
Quiescent Current
LT1964 ADJ Pin Voltage
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
–5.12
–5.09
–5.06
–5.03
–5.00
–4.97
–4.94
–4.91
–4.88
–1.240
–1.235
–1.230
–1.225
–1.220
–1.215
–1.210
–1.205
–1.200
V
= –6V
I
= –1mA
I = –1mA
L
IN
L
L
R
= 250k (∞ FOR LT1964-5)
I
= –5μA (0 FOR LT1964-5)
L
V
SHDN
= V
IN
V
SHDN
= 0V
0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1964 G05
1964 G06
1964 G04
LT1964-5
Quiescent Current
LT1964-5
GND Pin Current
LT1964 Quiescent Current
–40
–35
–30
–25
–20
–15
–10
–5
–40
–35
–30
–25
–20
–15
–10
–5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
R
L
= 25
L
T
= 25°C
= ∞
T
= 25°C
= 250k
L
T
= 25°C
= V
J
L
J
J
I
= –200mA*
R
R
V
SHDN
IN
V
= V
IN
V
= V
IN
SHDN
SHDN
I
= –5μA
*FOR V
= –5V
L
OUT
R
L
= 50
= –100mA*
L
I
R
L
= 100
= –50mA*
L
I
R
L
= 500
= –10mA*
L
V
SHDN
= 0V
V
SHDN
= 0V
I
–0
–0
0
–1 –2 –3 –4 –5 –6 –7 –8 –9 –10
0
–1 –2 –3 –4 –5 –6 –7 –8 –9 –10
0
–1 –2 –3 –4 –5 –6 –7 –8 –9 –10
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
1964 G08
1964 G09
1964 G07
1964fb
5
LT1964
TYPICAL PERFORMANCE CHARACTERISTICS
LT1964 GND Pin Current
GND Pin Current vs ILOAD
SHDN Pin Thresholds
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
2.5
2.0
T
= 25°C; V
= V ; *FOR V
IN
= –1.22V
V
IN
= V
– 1V
OUT(NOMINAL)
J
SHDN
OUT
ON
1.5
R
L
= 6.1Ω
T
= –50°C
L
J
I
= –200mA*
1.0
R
L
= 12.2Ω
0.5
L
T
= 25°C
J
I
= –100mA*
0
OFF
T
= 125°C
J
–0.5
–1.0
–1.5
–2.0
–2.5
R
L
= 24.4Ω
L
I
= –50mA*
R
L
= 122Ω
L
I
= –10mA*
ON
0
–1 –2 –3 –4 –5 –6 –7 –8 –9 –10
0
–40
–80
–120
–160
–200
–50 –25
0
25
50
75 100 125
INPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
TEMPERATURE (°C)
1964 G10
1964 G11
1964 G12
SHDN Pin Input Current
SHDN Pin Input Current
ADJ Pin Bias Current
12
9
–70
–60
–50
–40
–30
–20
–10
0
10
8
V
IN
= –15V
T
= 25°C
J
POSITIVE CURRENT
FLOWS INTO THE PIN
POSITIVE CURRENT
FLOWS INTO THE PIN
6
6
4
V
V
= 15V
SHDN
SHDN
2
3
0
0
–2
–4
–6
–8
–10
= –15V
–3
–6
–9
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–10 –8 –6 –4 –2
0
2
4
6
8
10
TEMPERATURE (°C)
TEMPERATURE (°C)
SHDN PIN VOLTAGE (V)
1964 G14
1964 G15
1964 G13
1964fb
6
LT1964
TYPICAL PERFORMANCE CHARACTERISTICS
Current Limit
Current Limit
Input Ripple Rejection
–600
–500
–400
–300
–200
–100
0
–600
–500
–400
–300
–200
–100
0
80
70
60
50
40
30
20
10
0
I
= –200mA
L
ΔV
OUT
= 100mV
V
V
= –7V
OUT
IN
V
= V
– 1V +
IN
OUT(NOMINAL)
50mV
= 0
= 0V
RIPPLE
RMS
C
BYP
C
OUT
= 10μF
C
OUT
= 1μF
0
–4
–8
–12
–16
–20
–50 –25
0
25
50
75 100 125
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
INPUT/OUTPUT DIFFERENTIAL (V)
TEMPERATURE (°C)
1964 G18
1964 G16
1964 G17
LT1964-BYP
Minimum Input Voltage
LT1964, LT1964-SD
Minimum Input Voltage
Input Ripple Rejection
60
58
56
54
52
50
48
46
44
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
V
= V
– 1V +
IN
OUT(NOMINAL)
0.5V RIPPLE AT f = 120Hz
P-P
I
L
= –200mA
I
I
= –200mA
= –1mA
I
I
= –200mA
= –1mA
L
L
L
L
NOTE: THE MINIMUM INPUT VOLTAGE
ACCOUNTS FOR THE OPERATING
THRESHOLD OF THE SHDN PIN WHICH
IS TIED TO THE IN PIN INTERNALLY
NOTE: THE SHDN PIN THRESHOLD
MUST BE MET TO ENSURE
DEVICE OPERATION
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1964 G19
1964 G20
1964 G21
1964fb
7
LT1964
TYPICAL PERFORMANCE CHARACTERISTICS
RMS Output Noise vs Bypass
Capacitor
Load Regulation
Output Noise Spectral Density
30
25
20
15
10
5
10
140
120
100
80
C
L
= 10μF
OUT
I
L
= –1mA TO –200mA
I
= –200mA
f = 10Hz TO 100kHz
C
BYP
= 1000pF
C
BYP
= 100pF
LT1964-5
1
LT1964-5
C
BYP
= 0
60
0.1
0.01
40
C
= 0.01μF
= 10μF
BYP
OUT
LT1964
100
20
LT1964
C
I
LT1964-5
LT1964
= 200mA
L
0
0
–50 –25
0
25
50
75 100 125
10
1k
10k
10
100
1k
FREQUENCY (Hz)
10k
100k
C
BYP
(pF)
TEMPERATURE (°C)
1964 G23
1964 G22
1964 G24
RMS Output Noise vs Load
Current
LT1964-5, 10Hz to 100kHz Output
Noise, CBYP = 0
LT1964-5, 10Hz to 100kHz Output
Noise, CBYP = 100pF
140
120
100
80
C
OUT
= 10μF
LT1964-5
V
V
OUT
100μV/DIV
OUT
200μV/DIV
C
= 0
BYP
LT1964
60
40
LT1964-5
LT1964
20
1964 G26
1964 G27
C
I
= 10μF
= –200mA
1ms/DIV
C
I
= 10μF
OUT
LOAD
1ms/DIV
OUT
LOAD
= –200mA
C
BYP
= 0.01μF
0
–0.01
–0.1
–1
–10
–100
–1k
LOAD CURRENT (mA)
1964 G25
1964fb
8
LT1964
LT1964-5, 10Hz to 100kHz Output
Noise, CBYP = 1000pF
LT1964-5, 10Hz to 100kHz Output
Noise, CBYP = 0.01μF
V
V
OUT
OUT
100μV/DIV
100μV/DIV
1964 G29
1964 G28
C
I
= 10μF
= –200mA
1ms/DIV
C
I
= 10μF
= –200mA
1ms/DIV
OUT
LOAD
OUT
LOAD
LT1964-5, Transient Response,
CBYP = 0
LT1964-5, Transient Response,
CBYP = 0.01μF
V
C
C
= –6V
V
C
C
= –6V
IN
IN
IN
IN
0.2
0.1
0.04
0.02
0
= 10μF
= 10μF
= 10μF
= 10μF
OUT
OUT
0
–0.1
–0.2
–0.02
–0.04
0
–100
–200
0
–100
–200
0
400
800
1200
1600
2000
0
20 40 60 80 100 120 140 160 180 200
TIME (μs)
TIME (μs)
1964 G30
1964 G31
1964fb
9
LT1964
PIN FUNCTIONS
ADJ(AdjustableDevicesonly):FortheAdjustableLT1964,
this is the Input to the Error Amplifier. The ADJ pin has a
bias current of 30nA that flows out of the pin. The ADJ pin
voltage is –1.22V referenced to ground, and the output
voltage range is –1.22V to –20V. A parasitic diode exists
between the ADJ pin and the input of the LT1964. The ADJ
pin cannot be pulled more negative than the input during
normal operation, or more than 0.5V more negative than
the input during a fault condition.
OUT: The Output Supplies Power to the Load. A minimum
output capacitor of 1μF is required to prevent oscillations.
Larger output capacitors will be required for applications
with large transient loads to limit peak voltage transients.
A parasitic diode exists between the output and the input.
The output cannot be pulled more negative than the input
duringnormaloperation,ormorethan0.5Vbelowtheinput
during a fault condition. See the Applications Information
section for more information on output capacitance and
reverse output characteristics.
BYP: The BYP Pin is used to Bypass the Reference of
the LT1964 to Achieve Low Noise Performance from the
Regulator. A small capacitor from the output to this pin
willbypassthereferencetolowertheoutputvoltagenoise.
A maximum value of 0.01μF can be used for reducing
output voltage noise to a typical 30μV
to 100kHz bandwidth. If not used, this pin must be left
unconnected.
SHDN: The SHDN Pin is used to put the LT1964 into a Low
Power Shutdown State. The SHDN pin is referenced to
the GND pin for regulator control, allowing the LT1964 to
be driven by either positive or negative logic. The output
of the LT1964 will be off when the SHDN pin is pulled
within 0.8V of GND. Pulling the SHDN pin more than
–1.9V or +1.6V will turn the LT1964 on. The SHDN pin
can be driven by 5V logic or open collector logic with a
pull-up resistor. The pull-up resistor is required to supply
the pull-up current of the open collector gate, normally
several microamperes, and the SHDN pin current, typi-
cally 3μA out of the pin (for negative logic) or 6μA into
the pin (for positive logic). If unused, the SHDN pin must
over a 10Hz
RMS
Exposed Pad (DFN Package Only): IN. Connect to IN
(Pins 7, 8) at the PCB.
GND: Ground.
IN: Power is Supplied to the Device Through the Input Pin.
A bypass capacitor is required on this pin if the device
is more than six inches away from the main input filter
capacitor. In general, the output impedance of a battery
rises with frequency, so it is advisable to include a bypass
capacitor in battery-powered circuits. A bypass capacitor
in the range of 1μF to 10μF is sufficient.
be connected to V . The device will be shut down if the
IN
SHDN pin is open circuit. For the LT1964-BYP, the SHDN
pin is internally connected to V . A parasitic diode exists
IN
between the SHDN pin and the input of the LT1964. The
SHDN pin cannot be pulled more negative than the input
during normal operation, or more than 0.5V below the
input during a fault condition.
1964fb
10
LT1964
APPLICATIONS INFORMATION
TheLT1964isa200mAnegativelowdropoutregulatorwith
micropower quiescent current and shutdown. The device
is capable of supplying 200mA at a dropout voltage of
the formula in Figure 1. The value of R1 should be less
than 250k to minimize errors in the output voltage caused
by the ADJ pin bias current. Note that in shutdown the
output is turned off and the divider current will be zero.
CurvesofADJPinVoltagevsTemperatureandADJPinBias
CurrentvsTemperatureappearintheTypicalPerformance
Characteristics section.
340mV. Output voltage noise can be lowered to 30μV
RMS
over a 10Hz to 100kHz bandwidth with the addition of a
0.01μF reference bypass capacitor. Additionally, the refer-
ence bypass capacitor will improve transient response of
the regulator, lowering the settling time for transient load
conditions. The low operating quiescent current (30μA)
drops to 3μA in shutdown. In addition to the low quies-
cent current, the LT1964 incorporates several protection
features which make it ideal for use in battery-powered
systems. In dual supply applications where the regulator
load is returned to a positive supply, the output can be
pulled above ground by as much as 20V and still allow
the device to start and operate.
The adjustable device is tested and specified with the ADJ
pintiedtotheOUTpinanda5μADCload(unlessotherwise
specified) for an output voltage of –1.22V. Specifications
for output voltages greater than –1.22V will be propor-
tional to the ratio of the desired output voltage to –1.22V;
(V /–1.22V). For example, load regulation for an output
OUT
current change of 1mA to 200mA is 2mV typical at V
–1.22V. At V
=
OUT
= –12V, load regulation is:
OUT
(–12V/–1.22V) • (2mV) = 19.6mV
Adjustable Operation
Bypass Capacitance and Low Noise Performance
The adjustable version of the LT1964 has an output volt-
age range of –1.22V to –20V. The output voltage is set by
the ratio of two external resistors as shown in Figure 1.
The device servos the output to maintain the voltage at
the ADJ pin at –1.22V referenced to ground. The current
in R1 is then equal to –1.22V/R1 and the current in R2 is
the current in R1 plus the ADJ pin bias current. The ADJ
pin bias current, 30nA at 25°C, flows through R2 out of
the ADJ pin. The output voltage can be calculated using
The LT1964 may be used with the addition of a bypass
capacitorfromV totheBYPpintoloweroutputvoltage
OUT
noise. A good quality low leakage capacitor is recom-
mended. This capacitor will bypass the reference of the
LT1964, providing a low frequency noise pole. The noise
pole provided by this bypass capacitor will lower the out-
put voltage noise to as low as 30μV
with the addition
RMS
of a 0.01μF bypass capacitor. Using a bypass capacitor
has the added benefit of improving transient response.
With no bypass capacitor and a 10μF output capacitor, a
–10mA to –200mA load step will settle to within 1% of
its final value in less than 100μs. With the addition of a
0.01μF bypass capacitor, the output will stay within 1%
for the same –10mA to –200mA load step (see LT1964-5
TransientResponseintheTypicalCharacteristicssection).
However, regulatorstart-uptimeisproportionaltothesize
of the bypass capacitor.
R1
+
GND
V
IN
ADJ
LT1964
R2
IN
V
OUT
OUT
1964 F01
R2
R1
V
V
= –1.22V(1 +
= –1.22V
) – (I )(R2)
ADJ
OUT
ADJ
Higher values of output voltage noise may be measured
if care is not exercised with regard to circuit layout and
testing.Crosstalkfromnearbytracescaninduceunwanted
noise onto the output of the LT1964-X.
I
= 30nA AT 25°C
ADJ
OUTPUT RANGE = –1.22V TO –20V
Figure 1. Adjustable Operation
1964fb
11
LT1964
APPLICATIONS INFORMATION
Output Capacitance and Transient Response
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or micro-
phone works. For a ceramic capacitor the stress can be
induced by vibrations in the system or thermal transients.
The resulting voltages produced can cause appreciable
The LT1964 is designed to be stable with a wide range
of output capacitors. The ESR of the output capacitor
affects stability, most notably with small capacitors. A
minimum output capacitor of 1μF with an ESR of 3Ω or
less is recommended to prevent oscillations. The LT1964
is a micropower device and output transient response
will be a function of output capacitance. Larger values
of output capacitance decrease the peak deviations and
provideimprovedtransientresponseforlargerloadcurrent
changes. Bypass capacitors, used to decouple individual
components powered by the LT1964, will increase the
effective output capacitor value.
20
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
0
X5R
–20
–40
Extra consideration must be given to the use of ceramic
capacitors. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior across
temperature and applied voltage. The most common
dielectrics used are specified with EIA temperature char-
acteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and
Y5V dielectrics are good for providing high capacitances
in a small package, but they tend to have strong voltage
and temperature coefficients as shown in Figures 2 and 3.
When used with a 5V regulator, a 16V 10μF Y5V capacitor
can exhibit an effective value as low as 1μF to 2μF for the
DC bias voltage applied and over the operating tempera-
ture range. The X5R and X7R dielectrics result in more
stable characteristics and are more suitable for use as the
output capacitor. The X7R type has better stability across
temperature, while the X5R is less expensive and is avail-
able in higher values. Care still must be exercised when
using X5R and X7R capacitors; the X5R and X7R codes
only specify operating temperature range and maximum
capacitancechangeovertemperature.Capacitancechange
due to DC bias with X5R and X7R capacitors is better than
Y5VandZ5Ucapacitors,butcanstillbesignificantenough
to drop capacitor values below appropriate levels. Capaci-
tor DC bias characteristics tend to improve as component
casesizeincreases, butexpectedcapacitanceatoperating
voltage should be verified.
–60
Y5V
–80
–100
0
8
12 14
2
4
6
10
16
DC BIAS VOLTAGE (V)
1964 F02
Figure 2. Ceramic Capacitor DC Bias Characteristics
40
20
X5R
0
–20
–40
Y5V
–60
–80
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
–100
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
1964 F03
Figure 3. Ceramic Capacitor Temperature Characteristics
1964fb
12
LT1964
APPLICATIONS INFORMATION
amounts of noise, especially when a ceramic capacitor is
used for noise bypassing. A ceramic capacitor produced
Figure 4’s trace in response to light tapping from a pencil.
Similar vibration induced behavior can masquerade as
increased output voltage noise.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat gener-
ated by power devices.
The following tables list thermal resistance for several
different board sizes and copper areas. All measurements
were taken in still air on 3/32" FR-4 board with one ounce
copper.
V
OUT
Table 1. SOT-23 Thermal Resistance
1mV/DIV
COPPER AREA
THERMAL RESISTANCE
TOPSIDE* BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2
2
2
2
2
2
2
2
2
2
2
2500mm
1000mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
125°C/W
125°C/W
130°C/W
135°C/W
150°C/W
2
1964 F04
LT1964-5
100ms/DIV
2
225mm
100mm
C
C
= 10μF
OUT
BYP
= 0.01μF
= –200mA
2
I
LOAD
2
50mm
Figure 4. Noise Resulting from Tapping on a Ceramic Capacitor
*Device is mounted on topside.
Thermal Considerations
Table 2. DFN Thermal Resistance
COPPER AREA
The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C). The
power dissipated by the device will be made up of two
components:
THERMAL RESISTANCE
TOPSIDE* BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2
2
2
2
2
2
2
2
2
2500mm
1000mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
40°C/W
45°C/W
50°C/W
62°C/W
2
2
225mm
100mm
1. Output current multiplied by the input/output voltage
2
differential: I
• (V – V ), and
OUT
IN OUT
*Device is mounted on topside.
2. Ground pin current multiplied by the input voltage:
• V
The thermal resistance junction-to-case (θ ), measured
JC
I
GND
IN
at Pin 2, is 60°C/W. for the SOT-23 package and is 16°C/W
measured at the backside of the exposed pad on the DFN
package
The GND pin current can be found by examining the GND
Pin Current curves in the Typical Performance Character-
istics. Power dissipation will be equal to the sum of the
two components listed above.
Calculating Junction Temperature
TheLT1964seriesregulatorshaveinternalthermallimiting
designedtoprotectthedeviceduringoverloadconditions.
For continuous normal conditions the maximum junction
temperature rating of 125°C must not be exceeded. It is
important to give careful consideration to all sources of
thermal resistance from junction to ambient. Additional
heat sources mounted nearby must also be considered.
Example: Given an output voltage of –5V, an input voltage
range of –6V to –8V, an output current range of 0mA to
–100mA, and a maximum ambient temperature of 50°C,
what will the maximum junction temperature be?
The power dissipated by the device will be equal to:
1964fb
13
LT1964
APPLICATIONS INFORMATION
I
• (V
– V ) + (I
• V )
act like an open circuit, no current will flow into the pin.
If the input is powered by a voltage source, the output
will sink the short-circuit current of the device and will
protect itself by thermal limiting. In this case, grounding
the SHDN pin will turn off the device and stop the output
from sinking the short-circuit current.
OUT(MAX)
IN(MAX)
OUT
GND
IN(MAX)
where,
I
= –100mA
= –8V
OUT(MAX)
V
IN(MAX)
I
at (I = –100mA, V = –8V) = –2mA
OUT IN
GND
Like many IC power regulators, the LT1964 series have
safe operating area protection. The safe area protection
activates at input-to-output differential voltages greater
than –7V. The safe area protection decreases the current
limit as the input-to-output differential voltage increases
and keeps the power transistor inside a safe operating
region for all values of forward input to-output voltage.
Theprotectionisdesignedtoprovidesomeoutputcurrent
at all values of input-to-output voltage up to the device
breakdown. A 50μA load is required at input-to-output
differential voltages greater than –7V.
so,
P = –100mA • (–8V + 5V) + (–2mA • –8V) = 0.32W
The thermal resistance (junction to ambient) will be in the
range of 125°C/W to 150°C/W for the SOT-23 package
dependingonthecopperarea.Sothejunctiontemperature
rise above ambient will be approximately equal to:
0.32W • 140°C/W = 44.2°C
The maximum junction temperature will then be equal to
the maximum junction temperature rise above ambient
plus the maximum ambient temperature or:
When power is first turned on, as the input voltage rises,
the output follows the input, allowing the regulator to start
up into very heavy loads. During start-up, as the input
voltage is rising, the input-to-output voltage differential
is small, allowing the regulator to supply large output
currents. With a high input voltage, a problem can occur
wherein removal of an output short will not allow the
output voltage to fully recover. Other regulators, such as
the LT1175, also exhibit this phenomenon, so it is not
unique to the LT1964 series.
T
= 50°C + 44.2°C = 94.2°C
JMAX
Protection Features
The LT1964 incorporates several protection features
which make it ideal for use in battery-powered circuits.
In addition to the normal protection features associated
with monolithic regulators, such as current limiting and
thermal limiting, the device is protected against reverse
input voltages and reverse output voltages.
The problem occurs with a heavy output load when
the input voltage is high and the output voltage is low.
Common situations are immediately after the removal of
a short-circuit or when the SHDN pin is pulled high after
the input voltage has already been turned on. The load line
for such a load may intersect the output current curve at
two points. If this happens, there are two stable operat-
ing points for the regulator. With this double intersection,
the input supply may need to be cycled down to zero and
brought up again to make the output recover.
Current limit protection and thermal overload protection
areintendedtoprotectthedeviceagainstcurrentoverload
conditionsattheoutputofthedevice.Fornormaloperation,
the junction temperature should not exceed 125°C.
The output of the LT1964 can be pulled above ground
withoutdamagingthedevice.Iftheinputisleftopencircuit
or grounded, the output can be pulled above ground by
20V. For fixed voltage versions, the output will act like a
largeresistor,typically500korhigher,limitingcurrentflow
to less than 40μA. For adjustable versions, the output will
1964fb
14
LT1964
PACKAGE DESCRIPTION
S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635)
0.62
MAX
0.95
REF
2.90 BSC
(NOTE 4)
1.22 REF
1.50 – 1.75
(NOTE 4)
2.80 BSC
1.4 MIN
3.85 MAX 2.62 REF
PIN ONE
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
NOTE:
S5 TSOT-23 0302 REV B
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
0.38 0.10
TYP
5
8
0.675 0.05
3.5 0.05
2.15 0.05 (2 SIDES)
1.65 0.05
3.00 0.10
(4 SIDES)
1.65 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PACKAGE
OUTLINE
(DD) DFN 1203
4
1
0.25 0.05
0.75 0.05
0.200 REF
0.25 0.05
0.50 BSC
0.50
BSC
2.38 0.05
(2 SIDES)
2.38 0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
1964fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT1964
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1120
125mA Micropower Low Dropout Regulator with Comparator Includes 2.5V Reference and Comparator, V : 3.5V to 36V, I = 40μA,
IN Q
and Shutdown
N8 Package
LT1121
LT1129
LT1175
150mA Micropower Low Dropout Regulator
700mA Micropower Low Dropout Regulator
800mA Negative Low Dropout Micropower Regulator
V : 4.2V to 30V, I = 30μA; ThinSOT, S8 and MS8 Packages
IN
Q
V : 4.5V to 30V, I = 50μA; DD and S8 Packages
IN
Q
V : 4.5V to 20V, I = 45μA, 0.26V Dropout Voltage, S8 and
IN
Q
ThinSOT Packages
LT1611
Inverting 1.4MHz Switching Regulator
–5V at 150mA from 5V Input, ThinSOT Package
LT1761 Series
LT1762 Series
LT1763 Series
LT1764A
100mA, Low Noise, Low Dropout Micropower Regulators
150mA, Low Noise, LDO Micropower Regulators
500mA, Low Noise, LDO Micropower Regulators
3A, Low Noise, Fast Transient Response LDO
V : 1.5V to 20V, I = 20μA, 20μV
Noise, ThinSOT Package
Noise, MS8 Package
Noise, S8 Package
IN
Q
RMS
RMS
RMS
V : 1.5V to 20V, I = 25μA, 20μV
IN
Q
V : 1.5V to 20V, I = 30μA, 20μV
IN
Q
V : 1.5V to 20V, 40μV
Noise; DD and T5 Packages
IN
RMS
LT1931/LT1931A Inverting 1.2MHz/2.2MHz Switching Regulators
–5V at 350mA from 5V Input, ThinSOT Package
V : 1.5V to 20V, I = 30μA, 20μV Noise, MS8 Package
LT1962
300mA, Low Noise, LDO Micropower Regulator
1.5A, Low Noise, Fast Transient Response LDO
IN
Q
RMS
LT1963A
V : 1.5V to 20V, 40μV
Noise; DD, T5, S8 and ThinSOT Packages
IN
RMS
1964fb
LT 0708 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
© LINEAR TECHNOLOGY CORPORATION 2001
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号:
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