LT1965EQ#PBF_技术文档

LT3030

Dual 750mA/250mA

Low Dropout, Low Noise,

Micropower Linear Regulator

FeaTures

DescripTion

n

Output Current: 750mA/250mA

TheLT^®3030isadual,micropower,lownoise,lowdropout

linear regulator. The device operates with either common

or independent input supplies for each channel, over a

1.8V to 20V input voltage range. Output 1/Output 2 supply

750mA/250mArespectivelywithatypicaldropoutvoltage

of 300mV. With an external 10nF bypass capacitor, output

n

Low Dropout Voltage: 300mV

Low Noise: 20μV

n

(10Hz to 100kHz)

RMS

n

Low Quiescent Current: 120μA/75μA

Wide Input Voltage Range: 1.8V to 20V

Adjustable Output: 1.220V Reference Voltage

Shutdown Quiescent Current: <1μA

Stable with 10µF/3.3µF Minimum Output Capacitor

Stable with Ceramic, Tantalum or Aluminum

Electrolytic Capacitors

noise is only 20μV

over a 10Hz to 100kHz bandwidth.

RMS

Designed for use in battery-powered systems, the low

120μA/75μA quiescent current makes it an ideal choice.

In shutdown, quiescent current drops to less than 1μA.

n

Precision Threshold for Shutdown Logic or UVLO Function Shutdown control is independent for each channel and

PWRGD Flag for each Output

Reverse Battery and Reverse Output-to-Input

Protection

Current Limit with Foldback and Thermal Shutdown

Thermally Enhanced 20-Lead TSSOP and

28-Lead (4mm × 5mm) QFN Packages

its precision logic threshold allows for voltage lockout

functionality. The LT3030 includes a PWRGD flag for each

channel to indicate output regulation.

n

TheLT3030optimizesstabilityandtransientresponsewith

low ESR ceramic output capacitors, requiring a minimum

of only 10μF/3.3μF.

applicaTions

Internal circuitry provides reverse-battery protection,

reverse-current protection, current limiting with foldback

and thermal shutdown with hysteresis. The adjustable

output voltage device has a 1.220V reference voltage.

The LT3030 is offered in the thermally enhanced 20-lead

TSSOP and 28-lead, low profile (4mm × 5mm × 0.75mm)

QFN packages.

n

General Purpose Linear Regulator

n

Battery-Powered Systems

n

Microprocessor Core/Logic Supplies

n

Post Regulator for Switching Supplies

Tracking/Sequencing Power Supplies

n

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners.

Typical applicaTion

2.5V_INto 1.8V/1.5V Application

Dropout Voltage vs Load Current

500

V

IN

2.5V

V

OUT1

T

= 25°C

IN1

OUT1

J

1.8V

450

400

350

300

250

200

150

100

50

10nF

10µF

750mA

3.3µF

IN2

LT3030

113k

1%

SHDN1

SHDN2

BYP1

ADJ1

237k

1%

OUT2

1M

PWRGD1

PWRGD2

OUT1

V

OUT2

1.5V

10nF

3.3µF

250mA

54.9k

1%

BYP2

ADJ2

0

GND

0

75 150 225 300 375 450 525 600 675 750

237k

1%

3030 TA01a

OUTPUT CURRENT (mA)

3030 TA01b

3030f

1

For more information www.linear.com/3030

LT3030

absoluTe MaxiMuM raTings

(Note 1)

IN1, IN2 Pin Voltage................................................±22V

OUT1, OUT2 Pin Voltage .........................................±22V

Input-to-Output Differential Voltage........................±22V

ADJ1, ADJ2 Pin Voltage............................................±±V

BYP1, BYP2 Pin Voltage ........................................±0.6V

SHDN1, SHDN2 Pin Voltage....................................±22V

PWRGD1, PWRGD2 Pin Voltage ....................22V, –0.3V

Output Short-Circuit Duration.......................... Indefinite

Operating Junction Temperature (Notes 2, 12)

E-/I-Grade.......................................... –40°C to 125°C

H-Grade ............................................. –40°C to 150°C

MP-Grade .......................................... –55°C to 150°C

Storage Temperature Range

QFN/TSSOP Package............................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

(TSSOP Only)........................................................300°C

pin conFiguraTion

TOP VIEW

ADJ1

BYP1

OUT1

GND

1

2

3

4

5

6

7

8

9

20

19

18

17

16

15

14

SHDN1

PWRGD1

IN1

28 27 26 25 24 23

OUT1

GND

1

2

3

4

5

6

7

8

22

21

20

19

18

17

16

15

PWRGD1

IN1

GND

21

GND

29

GND

OUT2

BYP2

IN2

GND

IN2

OUT2

IN2

13 IN2

PWRGD2

12

11

PWRGD2

SHDN2

9

10 11 12 13 14

UFD PACKAGE

ADJ2 10

FE PACKAGE

20-LEAD PLASTIC TSSOP

T

= 150°C, θ = 28°C/W, , θ = 10°C/W

JA JC

EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB

JMAX

28-LEAD (4mm × 5mm) PLASTIC QFN

T

= 125°C, θ = 33°C/W, , θ = 3.4°C/W

JMAX

JA

JC

EXPOSED PAD (PIN 2±) IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH

LT3030EUFD#PBF

LT3030IUFD#PBF

LT3030EFE#PBF

LT3030IFE#PBF

TAPE AND REEL

PART MARKING*

3030

PACKAGE DESCRIPTION

28-Lead (4mm × 5mm) Plastic QFN

TEMPERATURE RANGE

–40°C to 125°C

LT3030EUFD#TRPBF

LT3030IUFD#TRPBF

LT3030EFE#TRPBF

LT3030IFE#TRPBF

LT3030HFE#TRPBF

LT3030MPFE#TRPBF

3030

28-Lead (4mm × 5mm) Plastic QFN

20-Lead Plastic TSSOP

–40°C to 125°C

–40°C to 150°C

–55°C to 150°C

LT3030FE

20-Lead Plastic TSSOP

LT3030HFE#PBF

LT3030MPFE#PBF

20-Lead Plastic TSSOP

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

3030f

2

For more information www.linear.com/3030

LT3030

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C (Note 2).

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

Minimum Input Voltage (Notes 3, 11)

Output 1, I

Output 2, I

= 750mA

= 250mA

1.7

2.2

V

LOAD

ADJ1, ADJ2 Pin Voltage (Notes 3, 4)

V

= 2V, I

= 1mA

IN1

IN2

1.208

1.1±6

1.220

1.232

1.244

V

IN

LOAD

l

Output 1, 2.2V < V < 20V, 1mA < I

< 750mA

< 250mA

LOAD

Output 2, 2.2V < V < 20V, 1mA < I

l

Line Regulation (Note 3)

Load Regulation (Note 3)

∆V = 2V to 20V, I

= 1mA

0.5

2

5

mV

IN

LOAD

Output 1, V = 2.2V, ∆I

= 1mA to 750mA

6

10

mV

IN1

LOAD

V

= 2.2V, ∆I

Output 2, V = 2.2V, ∆I

= 1mA to 250mA

2

6

10

mV

IN2

LOAD

V

= 2.2V, ∆I

Dropout Voltage (Output 1)

I

= 10mA

0.13

0.17

0.27

0.3

0.20

0.28

V

LOAD

V

= V

OUT1(NOMINAL)

IN1

(Notes 5, 6, 11)

I

= 100mA

0.23

0.33

V

LOAD

I

= 500mA

0.32

0.43

V

LOAD

I

= 750mA

0.36

0.48

V

LOAD

Dropout Voltage (Output 2)

I

= 10mA

0.14

0.18

0.22

0.3

0.20

0.28

V

LOAD

V

= V

OUT2(NOMINAL)

IN2

(Notes 5, 6, 11)

I

= 50mA

0.24

0.32

V

LOAD

I

= 100mA

0.28

0.38

V

LOAD

I

= 250mA

0.36

0.48

V

LOAD

l

GND Pin Current (Output 1)

I

= 0mA

120

420

2

300

800

3.8

17

μA

mA

LOAD

V

= V

= 10mA

= 100mA

= 500mA

= 750mA

IN1

OUT1(NOMINAL)

(Notes 5, 7)

±

15

27

l

GND Pin Current (Output 2)

I

= 0mA

75

330

1

1.8

5

200

600

1.8

3.4

±

μA

mA

LOAD

V

= V

= 10mA

= 50mA

= 100mA

= 250mA

IN2

OUT2(NOMINAL)

(Notes 5, 7)

Output Voltage Noise

C

= 10μF, C

= 10nF, I

= Full Current (Note 13)

20

μV

RMS

OUT

BYP

LOAD

BW = 10Hz to 100kHz

ADJ1/ADJ2 Pin Bias Current (Notes 3, 8)

Shutdown Threshold

30

100

nA

l

V

= Off to On

= On to Off

1.0±

0.5

1.21

0.83

0.38

1.33

V

OUT

Hysteresis (Note 2)

l

SHDN1/SHDN2 Pin Current (Note 10)

V

, V

= 0V

= 20V

0

0.85

0.5

3

μA

SHDN1 SHDN2

, V

SHDN1 SHDN2

Quiescent Current in Shutdown (per Channel)

PWRGD Trip Point

V

= 20V, V

= 0V, V = 0V

SHDN2

0.3

±0

2

μA

%

IN

SHDN1

l

% of Nominal Output Voltage, Output Rising

% of Nominal Output Voltage, Output Falling

86

±4

PWRGD Trip Point Hysteresis (Note 2)

PWRGD Output Low Voltage

PWRGD Leakage Current

1.6

15

%

l

I

= 100μA

150

1

mV

μA

PWRGD

V

SHDN

= 0V, V

= 20V

PWRGD

3030f

3

For more information www.linear.com/3030

LT3030

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C (Note 2).

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Ripple Rejection

V

= 2.72V (Avg), V

= 0.5V ,

P-P

50

60

dB

IN

RIPPLE

f

= 120Hz, I

= Full Current (Note 13)

RIPPLE

LOAD

V

= V

+ 1V, V

LOAD

= 50mV

RMS

50

1.4

420

dB

IN

OUT(NOMINAL)

RIPPLE

f

= 1MHz, I

= Full Current (Note 13)

RIPPLE

l

Current Limit (Note ±)

Output 1, V = 6V, V

= 0V

OUT1

1.1

1.7

A

mA

IN1

OUT1

V

= 2.2V, ∆V

= –0.1V

800

l

Output 2, V = 6V, V

= 0V

= –0.1V

350

270

4±0

mA

IN2

OUT2

V

= 2.2V, ∆V

OUT2

l

Input Reverse Leakage Current

Reverse Output Current

V

= –20V, V

= 0V

OUT

1

mA

μA

IN

= 1.220V, V = 0V

0.5

10

OUT

IN

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 6: Dropout voltage is the minimum input to output voltage differential

needed to maintain regulation at a specified output current. In dropout, the

output voltage equals: V – V

.

IN

DROPOUT

Note 7: GND pin current is tested with V = 2.447V and a current source

IN

Note 2: The LT3030 is tested and specified under pulse load conditions

load. This means the device is tested while operating in its dropout region

or at the minimum input voltage specification. This is the worst-case

GND pin current. The GND pin current decreases slightly at higher input

voltages. Total GND pin current equals the sum of output 1 and output 2

GND pin currents.

Note 8: ADJ1/ADJ2 pin bias current flows into the pin.

Note 9: The LT3030 contains current limit foldback circuitry. See the

such that T ≈ T . The LT3030E is 100% tested at T = 25°C and

J

A

performance is guaranteed from 0°C to 125°C. Performance of the

LT3030E over the full –40°C to 125°C operating junction temperature

range is assured by design, characterization and correlation with statistical

process controls. The LT3030I is guaranteed over the full –40°C to 125°C

operating junction temperature range. The LT3030MP is 100% tested and

guaranteed over the –55°C to 150°C operating junction temperature range.

The LT3030H is tested at 150°C operating junction temperature. High

junction temperatures degrade operating lifetimes. Operating lifetime is

derated at junction temperatures greater than 125°C.

Typical Performance Characteristics section for current limit as a function

of the V – V

differential voltage.

IN

OUT

Note 10: SHDN1 and SHDN2 pin current flows into the pin.

Note 11: The LT3030 minimum input voltage specification limits dropout

voltage under some output voltage/load conditions. See the curve of

Minimum Input Voltage in the Typical Performance Characteristics section.

Note 12: The LT3030 includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature exceeds the maximum operating junction temperature when

overtemperature protection is active. Continuous operation above the

specified maximum operating junction temperature may impair device

reliability.

Note 3: The LT3030 is tested and specified for these conditions with the

ADJ1/ADJ2 pin connected to the corresponding OUT1/OUT2 pin.

Note 4: Maximum junction temperature limits operating conditions. The

regulated output voltage specification does not apply for all possible

combinations of input voltage and output current. When operating at

maximum input voltage, limit the output current range. When operating at

maximum output current, limit the input voltage range.

Note 5: To satisfy minimum input voltage requirements, the LT3030 is

tested and specified for these conditions with an external resistor divider

(two 243k resistors) for an output voltage of 2.447V. The external resistor

divider adds 5μA of DC load on the output.

Note 13: The Full Current for I

is 750mA and 250mA for Output 1 and

LOAD

Output 2 respectively.

3030f

4

For more information www.linear.com/3030

LT3030

T_J= 25°C, unless otherwise noted.

Typical perForMance characTerisTics

OUT1 Dropout Voltage

vs Temperature

OUT1 Guaranteed Dropout

OUT1 Typical Dropout Voltage

Voltage

500

450

400

350

300

250

200

150

100

50

500

450

400

350

300

250

200

150

100

50

500

450

400

350

300

250

200

150

100

50

= TEST POINTS

I

L

I

L

I

L

I

L

I

L

I

L

= 750mA

= 500mA

= 300mA

= 100mA

= 10mA

= 1mA

T = 150°C

J

T = 150°C

J

T = 125°C

J

T = 25°C

J

T = 25°C

J

T = –55°C

J

0

75 150 225 300 375 450 525 600 675 750

0

75 150 225 300 375 450 525 600 675 750

–75 –50 –25

0

25 50 75 100 125 150 175

OUTPUT CURRENT (mA)

TEMPERATURE (°C)

3030 G01

3030 G02

3030 G03

OUT2 Guaranteed Dropout

Voltage

OUT2 Dropout Voltage

vs Temperature

OUT2 Typical Dropout Voltage

500

450

400

350

300

250

200

150

100

50

500

450

400

350

300

250

200

150

100

50

500

450

400

350

300

250

200

150

100

50

= TEST POINTS

I

L

I

L

I

L

I

L

I

L

I

L

= 250mA

= 175mA

= 100mA

= 50mA

= 10mA

= 1mA

T = 150°C

J

T = 150°C

J

T = 125°C

J

T = 25°C

J

T = 25°C

J

T = –55°C

J

0

25 50 75 100 125 150 175 200 225 250

0

25 50 75 100 125 150 175 200 225 250

–75 –50 –25

0

25 50 75 100 125 150 175

OUTPUT CURRENT (mA)

TEMPERATURE (°C)

3030 G04

3030 G05

3030 G06

Quiescent Current

ADJ1/ADJ2 Pin Voltage

Quiescent Current

300

250

200

150

100

50

1.244

1.238

1.232

1.226

1.220

1.214

1.208

1.202

1.196

300

250

200

150

100

50

V

R

= V = 6V

IN2

L2

I

= I = 1mA

L1 L2

T

= 25°C

J

IN1

L1

= R = 243k; I = I = 5µA

R

= R = 243k; I = I = 5µA

L1 L2

L1

L2

= V

L1 L2

V

= 1.220V

OUT2

OUT1

ADJ2

ADJ1

OUTPUT 1

= V

V

SHDN1

IN1

OUTPUT 1, V

OUTPUT 2, V

= V

SHDN1

IN1

SHDN2

IN2

OUTPUT 2

= V

V

SHDN2

IN2

OUTPUT 1; V

OUTPUT 2; V

= 0V

SHDN1

SHDN2

0

–75 –50 –25

0

25 50 75 100 125 150 175

–75 –50 –25

0

25 50 75 100 125 150 175

0

2

4

6

8

10 12 14 16 18 20

TEMPERATURE (°C)

INPUT VOLTAGE (V)

3030 G07

3030 G08

3030 G09

3030f

5

For more information www.linear.com/3030

LT3030

T_J= 25°C, unless otherwise noted.

Typical perForMance characTerisTics

Quiescent Current in Shutdown

(per Output)

OUT1 GND Pin Current

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

0

27

T = 25°C

J

T = 25°C

J

T = 25°C

J

24

R

= R = 243k; I = I = 5µA

FOR V

= 1.220V

OUT1

FOR V

= 1.220V

L1

L2

L1 L2

OUT1

V

= V

= 1.220V

OUT2

OUT1

SHDN1

21

18

15

12

9

= V

= 0V

SHDN2

I

L1

= 100mA

I

= 750mA

L1

I

= 500mA

= 250mA

L1

I

= 1mA

8

6

L1

I

= 10mA

4

L1

3

0

2

4

6

8

10 12 14 16 18 20

0

1

2

3

5

6

7

9

0

1

2

3

4

5

6

7

8

9

INPUT VOLTAGE (V)

3030 G10

3030 G11

3030 G12

OUT1 GND Pin Current

OUT2 GND Pin Current

9

8

7

6

5

4

3

2

1

0

27

24

21

18

15

12

9

1.2

1.0

0.8

0.6

0.4

0.2

0

T = 25°C

J

T = 25°C

J

T = 25°C

J

FOR V

= 1.220V

V

= V

+ 1V

FOR V

= 1.220V

OUT2

IN1

OUT1(NOMINAL)

I

= 250mA

L2

I

= 25mA

L1

I

= 10mA

= 1mA

L1

I

= 50mA

L2

6

I

L2

= 100mA

3

0

1

2

3

4

5

6

7

8

9

0

75 150 225 300 375 450 525 600 675 750

0

1

2

3

4

5

6

7

8

9

INPUT VOLTAGE (V)

OUTPUT CURRENT (mA)

INPUT VOLTAGE (V)

3030 G15

3030 G13

3030 G14

SHDN1 or SHDN2 Pin Input

Current

OUT2 GND Pin Current

SHDN1 or SHDN2 Pin Threshold

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

9

8

7

6

5

4

3

2

1

0

T = 25°C

J

T = 25°C

J

IN2

OFF TO ON

V

= V

+ 1V

OUT2(NOMINAL)

ON TO OFF

V

= 2.2V

= 20V

IN

V

= 2.2V

IN

–75 –50 –25

0

25 50 75 100 125 150 175

0

2

4

6

8

10 12 14 16 18 20

0

25 50 75 100 125 150 175 200 225 250

TEMPERATURE (°C)

SHDN PIN VOLTAGE (V)

OUTPUT CURRENT (mA)

3030 G17

3030 G18

3030 G16

3030f

6

For more information www.linear.com/3030

LT3030

T_J= 25°C, unless otherwise noted.

Typical perForMance characTerisTics

SHDN1 or SHDN2 Pin Input

Current

ADJ1 or ADJ2 Pin Bias Current

PWRGD1 or PWRGD2 Trip Point

94

93

92

91

90

89

88

87

86

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

150

135

120

105

90

OUTPUT RISING

V

= 2.2V,

IN

SHDN

75

= 20V

60

45

OUTPUT FALLING

30

V

= 20V

= 2.2V

IN

SHDN

15

0

–75 –50 –25

0

25 50 75 100 125 150 175

–75 –50 –25

0

25 50 75 100 125 150 175

–75 –50 –25

0

25 50 75 100 125 150 175

TEMPERATURE (°C)

3030 G21

3030 G19

3030 G20

PWRGD1 or PWRGD2 Output Low

Voltage

OUT1 Current Limit

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

150

135

120

105

90

I

= 100µA

V

= 0V

OUT

V

= 0V

PWRGD

OUT

V

= 6V

IN

T = –55°C

J

T = 25°C

J

75

T = 125°C

J

60

T = 150°C

J

45

V

= 18V

30

IN

15

0

2

4

6

8

10 12 14 16 18 20

–75 –50 –25

0

25 50 75 100 125 150 175

–75 –50 –25

0

25 50 75 100 125 150 175

INPUT VOLTAGE (V)

TEMPERATURE (°C)

3030 G23

3030 G24

3030 G22

OUT2 Current Limit

Reverse Current

0.60

0.54

0.48

0.42

0.36

0.30

0.24

0.18

0.12

0.06

0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

0.60

0.54

0.48

0.42

0.36

0.30

0.24

0.18

0.12

0.06

0

V

= 0V

V

= 0V

T = 25°C

J

OUT

V

= V = 0V

IN1

IN2

= V

ADJ1

ADJ2

OUT1

OUT2

V

= 6V

IN

T = –55°C

J

T = 25°C

J

I

OR I

ADJ2

ADJ1

T = 125°C

J

V

= 18V

IN

T = 150°C

J

I

OR I

7

OUT1

6

OUT2

0

2

4

6

8

10 12 14 16 18 20

0

1

2

3

4

5

8

9

–75 –50 –25

0

25 50 75 100 125 150 175

INPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

TEMPERATURE (°C)

3030 G25

3030 G27

3030 G26

I

= FLOWS INTO ADJ PIN TO GND PIN

= FLOWS INTO OUT PIN TO IN PIN

ADJ

OUT

3030f

7

For more information www.linear.com/3030

LT3030

T_J= 25°C, unless otherwise noted.

Typical perForMance characTerisTics

Reverse Current

OUT1 Input Ripple Rejection

500

450

400

350

300

250

200

150

100

50

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V

= V = 0V

IN1

IN2

= V

= 1.220V

ADJ1

ADJ2

OUT1

OUT2

C

= 10nF

BYP1

C

= 47µF

C

= 1000pF

OUT1

BYP1

C

= 22µF

OUT1

C

= 100pF

BYP1

I

OR I

ADJ2

ADJ1

C

= 10µF

OUT1

I

OUT1

T = 25°C

J

I

= 750mA, C

= V

= 0

I

= 750mA, C

V = V

IN1

= 22µF

+ 1V

OUT1(NOMINAL)

L1

V

BYP1

L1

OUT1

I

+ 1V

OUT2

IN1

OUT1(NOMINAL)

+ 50mV

RIPPLE

+ 50mV

RIPPLE

RMS

0

10

100

1k

10k 100k

1M

10M

10

100

1k

10k 100k

1M

10M

–75 –25

0

25 50 75 100 125 150 175

TEMPERATURE (°C)

FREQUENCY (Hz)

3030 G28

3030 G29

3030 G30

I

= FLOWS INTO ADJ PIN TO GND PIN

= FLOWS INTO OUT PIN TO IN PIN

ADJ

OUT

OUT1 Input Ripple Rejection

OUT2 Input Ripple Rejection

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

C

= 10µF

OUT2

C

BYP2

= 10nF

C

= 1000pF

BYP2

C

= 22µF

OUT2

C

= 100pF

BYP2

C

= 3.3µF

OUT2

V

= V

+ 1.5V

T = 25°C

J

IN1

OUT1(NOMINAL)

J

+ 500mV RIPPLE

I

= 250mA, C

= 0

I

= 250mA, C

= 10µF

OUT2

P-P

L2

IN2

BYP2

L2

f = 120Hz

= 750mA

V

= V

+ 1V

V

= V

+ 1V

OUT2(NOMINAL)

IN2

I

+ 50mV

RIPPLE

+ 50mV

RIPPLE

L1

RMS

–75 –50 –25

0

25 50 75 100 125 150 175

10

100

1k

10k 100k

1M

10M

10

100

1k

10k 100k

1M

10M

TEMPERATURE (°C)

FREQUENCY (Hz)

3030 G31

3030 G32

3030 G33

OUT2 Input Ripple Rejection

Channel-to-Channel Isolation

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

CHANNEL 1

CHANNEL 2

V

OUT1

100mV/DIV

V

OUT2

100mV/DIV

GIVEN CHANNEL IS TESTED WITH

50mV

SIGNAL ON OPPOSING

V

= V

+ 1.5V

OUT2(NOMINAL)

RMS

IN2

CHANNEL, BOTH CHANNELS

DELIVERING FULL CURRENT

+ 500mV RIPPLE

P-P

3030 G36

50µs/DIV

f = 120Hz

= 250mA

C

OUT1

C

OUT2

C

BYP1

= 10µF

= 3.3µF

BYP2

∆I = 50mA TO 750mA

T = 25°C

J

I

L1

L2

∆I = 50mA TO 250mA

L2

10

100

1k

10k 100k

1M

10M

–75 –50 –25

0

25 50 75 100 125 150 175

= C

= 0.01µF

V

IN

= 6V, V

= V

= 5V

OUT1

OUT2

FREQUENCY (Hz)

TEMPERATURE (°C)

3030 G35

3030 G34

3030f

8

For more information www.linear.com/3030

LT3030

T_J= 25°C, unless otherwise noted.

Typical perForMance characTerisTics

OUT1 or OUT2 Load Regulation

OUT1 or OUT2 Line Regulation

Output Noise Spectral Density

10

8

5

4

10

1

T = 25°C

∆I = 1mA TO FULL LOAD

L

∆V = 2V TO 20V

IN

J

OUT

BYP

C

= 10µF

= 0

6

3

I

= FULL LOAD

L

V

= 5V

OUT

4

2

1

V

OUT

= V

ADJ

0

–2

–4

–6

–8

–10

–1

–2

–3

–4

–5

0.1

0.01

–75 –50 –25

0

25 50 75 100 125 150 175

–75 –50 –25

0

25 50 75 100 125 150 175

0.01

0.1

1

FREQUENCY (kHz)

10

100

TEMPERATURE (°C)

3030 G37

3030 G38

3030 G39

RMS Output Noise vs Bypass

Capacitor

OUT1 RMS Output Noise

Output Noise Spectral Density

vs Output Current (10Hz to 100kHz)

160

140

120

100

80

10

1

160

140

120

100

80

T = 25°C

J

T = 25°C

J

T = 25°C

J

OUT

L

BW

C

= 10µF

C

L

= 10µF

OUT

C

I

f

= 10µF

V

= 5V

OUT

I

= FULL LOAD

= 10Hz TO 100kHz

V

C

= 5V

= 0

V

= 5V

OUT1

BYP1

OUT

OUTPUT2

OUTPUT1

C

= 100pF

BYP

V

C

= V

ADJ1

= 0

OUT1

BYP1

V

= 1.220V

OUT

60

V

= V

60

OUT

ADJ

0.1

40

V

= V

ADJ1

C

= 0.01µF

OUT1

BYP

OUTPUT1

20

OUTPUT2

V

= 5V

1

OUT1

C

= 1000pF

BYP

C

= 10nF

BYP1

0

0.01

0

0.01

0.1

10

100

1000

0.01

0.1

1

10

100

10

100

1000

10000

OUTPUT CURRENT (mA)

FREQUENCY (Hz)

C

(pF)

BYP

3030 G42

3030 G40

3030 G41

Start-Up Time from Shutdown

C_BYP= 0pF

Start-Up Time from Shutdown

C_BYP= 0.01µF

OUT2 RMS Output Noise

vs Output Current (10Hz to 100kHz)

160

140

120

100

80

T = 25°C

OUT

J

C

= 10µF

V

OUT

V

C

= 5V

= 0

OUT

OUT2

BYP2

1V/DIV

V

C

= V

= 0

OUT2

BYP2

ADJ2

SHDN

VOLTAGE

2V/DIV

SHDN

VOLTAGE

2V/DIV

60

40

3030 G45

3030 G44

C

= 10nF

BYP2

1ms/DIV

20

V

= 5V

OUT2

V

C

= 2.5V

= 10µF

OUT

I = FULL LOAD

V

= 2.5V

= 10µF

I = FULL LOAD

IN

L

J

IN

L

V

= V

ADJ2

OUT2

T = 25°C

V

C

T = 25°C

J

V

0

IN

OUT

0.01

0.1

1

10

100

1000

= 10µF

= 1.5V

OUT

= 10µF

= 1.5V

OUT

OUTPUT CURRENT (mA)

3030 G43

3030f

9

For more information www.linear.com/3030

LT3030

T_J= 25°C, unless otherwise noted.

Typical perForMance characTerisTics

OUT1 or OUT2 Minimum Input

Voltage

10Hz to 100kHz Output Noise,

C_BYP= 100pF

C_BYP= 0pF

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

V

= V

= 1.220V

OUT2

OUT1

I

= FULL LOAD

L

V

OUT

100µV/DIV

OUT

I

= 1mA

L

100µV/DIV

3030 G47

3030 G48

1ms/DIV

C

L

V

= 10µF

C

= 10µF

OUT

I

= FULL LOAD

I = FULL LOAD

L

= 5V

V

= 5V

OUT

–75 –50 –25

0

25 50 75 100 125 150 175

TEMPERATURE (°C)

3030 G46

10Hz to 100kHz Output Noise,

C_BYP= 0.01µF

OUT1 Transient Response

C_BYP= 0pF

C

_BYP= 1000pF

V

DEVIATION

OUT

200mV/DIV

500mA/DIV

V

OUT

100µV/DIV

LOAD CURRENT DEVIATION

3030 G50

3030 G51

3030 G49

1ms/DIV

200µs/DIV

1ms/DIV

C

I

= 10µF

= FULL LOAD

= 5V

C

L

V

= 10µF

= FULL LOAD

= 5V

OUT

L

OUT

V

C

= 6V

I

= 100mA TO 750mA

IN

L

I

= 22µF

T = 25°C

J

V

OUT

= 22µF

V

= 5V

OUT

OUT1 Transient Response

C_BYP= 0.01µF

OUT2 Transient Response

C_BYP= 0pF

OUT2 Transient Response

C_BYP= 0.01µF

V

DEVIATION

V

DEVIATION

OUT

V

DEVIATION

OUT

50mV/DIV

200mV/DIV

100mA/DIV

50mV/DIV

LOAD CURRENT DEVIATION

500mA/DIV

100mA/DIV

3030 G52

3030 G53

3030 G54

20µs/DIV

200µs/DIV

= 100mA TO 250mA

20µs/DIV

V

C

= 6V

I

= 100mA TO 750mA

V

C

= 6V

I

V

C

= 6V

I = 100mA TO 250mA

IN

L

IN

L

IN

L

= 22µF

T = 25°C

= 10µF

T = 25°C

= 10µF

T = 25°C

J

= 22µF

V

= 5V

= 10µF

V

= 5V

= 10µF

V

= 5V

OUT

3030f

10

For more information www.linear.com/3030

LT3030

pin FuncTions ^(QFN/TSSOP)

OUT1, OUT2 (Pins 1, 2, 7, 8/Pins 3, 4, 7, 8): Output. The

OUT1/OUT2 pins supply power to the loads. A minimum

10μF/3.3μF output capacitor prevents oscillations on

OUT1/OUT2.Applicationswithlargeoutputloadtransients

require larger values of output capacitance to limit peak

voltage transients. See the Applications Information sec-

tion for more on output capacitance and on reverse output

characteristics.

changes state from an open-collector pull-down to high

impedance after the output increases above ±0% of the

nominal voltage. The maximum pull-down current of the

PWRGD pin in the low state is 100μA.

SHDN1, SHDN2 (Pins 23, 14/Pins 20, 11): Shutdown.

Pulling the SHDN1 or SHDN2 pin low puts its correspond-

ing LT3030 channel into a low power state and turns its

output off. The SHDN1 and SHDN2 pins are completely

independentofeachother,andeachSHDNpinonlyaffects

operation on its corresponding channel. Drive the SHDN1

andSHDN2pinswitheitherlogicoranopencollector/drain

with pull-up resistors. The resistors supply the pull-up

current to the open collectors/drains and the SHDN1 or

SHDN2 current, typically less than 1μA. If unused, con-

nect SHDN1 and SHDN2 to their corresponding IN pins.

Each channel will be in its low power shutdown state if its

corresponding SHDN pin is not connected.

GND (Pins 3, 4, 5, 6, 11, 12, 13, 18, 19, 24, 25, 26,

Exposed Pad Pin 29/Pins 5, 6, 15, 16, Exposed Pad Pin

21): Ground. The exposed pad (backside) of the QFN and

TSSOP packages is an electrical connection to GND. To

ensure proper electrical and thermal performance, sol-

der the exposed pad to the PCB ground and tie directly

to GND pins. Connect the bottom of the output voltage

setting resistor divider directly to GND for optimum load

regulation performance.

IN1, IN2 (Pins 20, 21, 16, 17/Pins 17, 18, 13, 14): In-

put. The IN1/IN2 pins supply power to each channel. The

LT3030 requires a bypass capacitor at the IN1/IN2 pins

if located more than six inches away from the main input

filter capacitor. Include a bypass capacitor in battery-

powered circuits, as a battery’s output impedance rises

with frequency. A bypass capacitor in the range of 1μF to

10μF suffices. The LT3030’s design withstands reverse

voltages on the IN pins with respect to ground and the

OUT pins. In the case of a reversed input, which occurs

if a battery is plugged in backwards, the LT3030 acts as

if a diode is in series with its input. No reverse current

flows into the LT3030 and no reverse voltage appears at

the load. The device protects itself and the load.

ADJ1, ADJ2 (Pins 27, 10/Pins 1, 10): Adjust Pin. These

are the error amplifier inputs. These pins are internally

clamped to ±±V. A typical input bias current of 30nA flows

into the pins (see curve of ADJ1/ADJ2 Pin Bias Current vs

Temperature in the Typical Performance Characteristics

section). The ADJ1 and ADJ2 pin voltages are 1.220V

referenced to ground and the output voltage range is

1.220V to 1±.5V.

BYP1, BYP2 (Pins 28, 9/Pins 2, 9): Bypass. Connecting

a capacitor between OUT and BYP of a respective chan-

nel bypasses the LT3030 reference to achieve low noise

performance, improve transient response and soft-start

the output. Internal circuitry clamps the BYP1/BYP2 pins

to ±0.6V (one V ) from ground. A small capacitor from

BE

PWRGD1, PWRGD2 (Pins 22, 15/Pins 19, 12): Power

Good.ThePWRGDflagisanopen-collectorflagtoindicate

that the output voltage has increased above ±0% of the

nominal output voltage. There is no internal pull-up on

this pin; a pull-up resistor must be used. The PWRGD pin

the corresponding output to this pin bypasses the refer-

ence to lower the output voltage noise. Using a maximum

value of 10nF reduces the output voltage noise to a typical

20μV

over a 10Hz to 100kHz bandwidth. If not used,

RMS

this pin must be left unconnected.

3030f

11

For more information www.linear.com/3030

LT3030

applicaTions inForMaTion

LT3030

TheLT3030isadual750mA/250mAlowdropoutregulator

with independent inputs, micropower quiescent current

and shutdown. The device supplies up to 750mA/250mA

fromtheoutputsofchannel1/channel2atatypicaldropout

voltageof300mV.ThetworegulatorssharecommonGND

pins and are thermally coupled. However, the two inputs

and outputs of the LT3030 operate independently. Each

channel can be shut down independently, but a thermal

shutdown fault on either channel shuts off the output on

bothchannels.Theadditionofa10nFreferencebypassca-

⎛

⎞

R2

R1⎠

OUT1/OUT2

V

OUT

V_OUT= 1.220V 1+

+ I

(

R2

_ADJ)( )

⎜

⎟

⎝

V

IN1/IN2

IN

R2

R1

C

OUT

V

_ADJ= 1.220V

_ADJ= 30nA AT 25°C

OUTPUT RANGE = 1.220V TO 19.5V

ADJ1/ADJ2

I

GND

3030 F01

Figure 1. Adjustable Operation

For example, load regulation on OUT2 for an output cur-

rent change of 1mA to full load current is typically –2mV

pacitorlowersoutputvoltagenoiseto20μV

overa10Hz

at V

= 1.220V. At V

= 2.5V, load regulation is:

RMS

OUT2

to 100kHz bandwidth. Additionally, the reference bypass

capacitor improves transient response of the regulator,

loweringthesettlingtimefortransientloadconditions.The

low operating quiescent current (120μA/75μA for channel

1/2) drops to typically less than 1μA in shutdown. In ad-

dition to the low quiescent current, the LT3030 regulator

incorporates several protection features that make it ideal

for use in battery powered systems. Most importantly,

the device protects itself against reverse input voltages.

(2.5V/1.220V) • (–2mV) = –4.1mV

Table 1 shows 1% resistor divider values for some com-

mon output voltages with a resistor divider current of

approximately 5μA.

Table 1. Output Voltage Resistor Divider Values

V

OUT

(V)

R1 (k)

237

243

232

210

200

R2 (k)

54.±

113

255

340

1.5

1.8

2.5

3

3.3

5

Adjustable Operation

357

61±

EachoftheLT3030’schannelshasanoutputvoltagerange

of 1.220V to 1±.5V. Figure 1 illustrates that the output

voltage is set by the ratio of two external resistors. The

device regulates the output to maintain the corresponding

ADJ pin voltage at 1.220V referenced to ground. R1’s cur-

rent equals 1.220V/R1. R2’s current equals R1’s current

plus the ADJ pin bias current. The ADJ pin bias current,

30nA at 25°C, flows through R2 into the ADJ pin. Use

the formula in Figure 1 to calculate output voltage. Linear

Technology recommends that the value of R1 be less than

243k to minimize errors in the output voltage due to the

ADJ pin bias current. In shutdown, the output turns off

and the divider current is zero. Curves of ADJ Pin Voltage

vs Temperature and ADJ Pin Bias Current vs Temperature

appearintheTypicalPerformanceCharacteristicssection.

Bypass Capacitance and Low Noise Performance

Using a bypass capacitor connected between a channel’s

BYP pin and its corresponding OUT pin significantly low-

ers LT3030 output voltage noise, but is not required in

all applications. Linear Technology recommends a good

quality low leakage capacitor. This capacitor bypasses

the regulator’s reference, providing a low frequency noise

pole. A 10nF bypass capacitor introduces a noise pole that

decreasesoutputvoltagenoisetoaslowas20μV

.Using

RMS

a bypass capacitor provides the added benefit of improv-

ing transient response. With no bypass capacitor and a

10μF output capacitor, a 100mA to full load step settles to

within 1% of its final value in approximately 400μs. With

the addition of a 10nF bypass capacitor and evaluating

the same load step, output voltage excursion stays within

2% (see Transient Response in the Typical Performance

Characteristics section). Using a bypass capacitor makes

regulator start-up time proportional to the value of the

bypass capacitor. For example, a 10nF bypass capacitor

LinearTechnologytestsandspecifieseachLT3030channel

with its ADJ pin tied to the corresponding OUT pin for a

1.220V output voltage. Specifications for output voltages

greaterthan1.220Vareproportionaltotheratioofdesired

output voltage to 1.220V:

V

/1.220V

OUT

and 10μF output capacitor slow start-up time to 15ms.

3030f

12

For more information www.linear.com/3030

LT3030

applicaTions inForMaTion

Input Capacitance and Stability

LT3030’s output also helps. However, this requires an

order of magnitude more capacitance in comparison with

additional LT3030 input bypassing. Series resistance be-

tween the supply and the LT3030 input also helps stabilize

the application; as little as 0.1Ω to 0.5Ω suffices. This

impedance dampens the LC tank circuit at the expense of

dropout voltage. A better alternative is to use higher ESR

tantalum or electrolytic capacitors at the LT3030 input in

place of ceramic capacitors.

Each LT3030 channel is stable with an input capacitor

typically between 1µF and 10µF. Applications operating

with smaller V to V

differential voltages and that ex-

IN

OUT

perience large load transients may require a higher input

capacitor value to prevent input voltage droop and letting

the regulator enter dropout.

Very low ESR ceramic capacitors may be used. However,

in cases where long wires connect the power supply to the

LT3030’s input and ground, use of low value input capaci-

tors combined with an output load current of greater than

20mAmayresultininstability.TheresonantLCtankcircuit

formed by the wire inductance and the input capacitor is

the cause and not a result of LT3030 instability.

Output Capacitance and Transient Response

TheLT3030isstablewithawiderangeofoutputcapacitors.

TheESRoftheoutputcapacitoraffectsstability,mostnota-

blywithsmallcapacitors.LinearTechnologyrecommends

a minimum output capacitor of 10μF/3.3μF (channel 1

/channel 2) with an ESR of 3Ω, or less, to prevent oscil-

lations. The LT3030 is a micropower device, and output

transient response is a function of output capacitance.

Larger values of output capacitance decrease the peak

deviations and provide improved transient response for

larger load current changes.

The self-inductance, or isolated inductance, of a wire

is directly proportional to its length. However, the wire

diameter has less influence on its self inductance. For

example, the self-inductance of a 2-AWG isolated wire

with a diameter of 0.26" is about half the inductance of a

30-AWG wirewithadiameterof0.01". Onefootof30-AWG

wire has 465nH of self-inductance.

Ceramic capacitors require extra consideration. Manufac-

turersmakeceramiccapacitorswithavarietyofdielectrics,

eachwithdifferentbehavioracrosstemperatureandapplied

voltage. The most common dielectrics specify the EIA

temperature characteristic codes of Z5U, Y5V, X5R and

X7R. Z5U and Y5V dielectrics provide high C-V products

in a small package at low cost, but exhibit strong voltage

and temperature coefficients, as shown in Figure 2 and

Figure 3. When used with a 5V regulator, a 16V 10μF Y5V

capacitor can exhibit an effective value as low as 1μF to

2μF for the applied DC bias voltage and over the operat-

ing temperature range. X5R and X7R dielectrics result in

more stable characteristics and are more suitable for use

as the output capacitor. The X7R type has better stability

across temperature, while the X5R is less expensive and

is available in higher values.

Several methods exist to reduce a wire’s self-inductance.

OnemethoddividesthecurrentflowingtowardstheLT3030

between two parallel conductors. In this case, placing the

wires further apart reduces the inductance; up to a 50%

reduction when placed only a few inches apart. Splitting

the wires connects two equal inductors in parallel. How-

ever, when placed in close proximity to each other, mutual

inductance adds to the overall self inductance of the wires.

Themosteffectivetechniquetoreducingoverallinductance

is to place the forward and return current conductors (the

input wire and the ground wire) in close proximity. Two

30-AWG wires separated by 0.02" reduce the overall self

inductance to about one-fifth of a single wire.

Ifabattery,mountedincloseproximity,powerstheLT3030,

a 1μF input capacitor suffices for stability. However, if a

distantly located supply powers the LT3030, use a larger

value input capacitor. Use a rough guideline of 1μF (in

addition to the 1μF minimum) per 8 inches of wire length.

The minimum input capacitance needed to stabilize the

application also varies with power supply output imped-

ance variations. Placing additional capacitance on the

Exercise care even when using X5R and X7R capacitors;

theX5RandX7Rcodesonlyspecifyoperatingtemperature

rangeandmaximumcapacitancechangeovertemperature.

Capacitance change due to DC bias (voltage coefficient)

with X5R and X7R capacitors is better than with Y5V and

Z5U capacitors, but can still be significant enough to drop

3030f

13

For more information www.linear.com/3030

LT3030

applicaTions inForMaTion

capacitor values below appropriate levels. Capacitor DC

biascharacteristicstendtoimproveascasesizeincreases.

LinearTechnologyrecommendsverifyingexpectedversus

actual capacitance values at operating voltage in situ for

an application.

Voltage and temperature coefficients are not the only

sources of problems. Some ceramic capacitors have a

piezoelectric response. A piezoelectric device generates

voltage across its terminals due to mechanical stress,

similar to the way a piezoelectric accelerometer or micro-

phone works. For a ceramic capacitor, the stress can be

induced by vibrations in the system or thermal transients.

The resulting voltages produced can cause appreciable

amounts of noise, especially when a ceramic capacitor is

used for noise bypassing. A ceramic capacitor produced

the trace's response to light tapping from a pencil, as

shown in Figure 4. Similar vibration induced behavior can

masquerade as increased output voltage noise.

20

BOTH CAPACITORS ARE 16V,

1210 CASE SIZE, 10µF

0

X5R

–20

–40

–60

Y5V

–80

Shutdown/UVLO

–100

TheSHDNpinisusedtoputtheLT3030intoamicropower

shutdown state. The LT3030 has an accurate 1.21V

threshold(duringturn-on)ontheSHDNpin.Thisthreshold

can be used in conjunction with a resistor divider from the

system input supply to define an accurate undervoltage

lockout (UVLO) threshold for the regulator. The SHDN pin

current (at the threshold) needs to be considered when

determining the resistor divider network.

0

8

12 14

2

4

6

10

16

DC BIAS VOLTAGE (V)

3030 F02

Figure 2. Ceramic Capacitor

DC Bias Characteristics

40

20

X5R

0

–20

–40

–60

–80

–100

PWRGD Flag

Y5V

The PWRGD flag indicates that the ADJ pin voltage is

within 10% of the regulated voltage. The PWRGD pin is an

open-collectoroutput,capableofsinking100μAofcurrent

when the ADJ pin voltage is below ±0% of the regulated

voltage. There is no internal pull-up on the PWRGD pin;

an external pull-up resistor must be used. As the ADJ

pin voltage rises above ±0% of its regulated voltage, the

PWRGD pin switches to a high impedance state and the

external pull-up resistor pulls the PWRGD pin voltage up.

During normal operation, an internal glitch filter prevents

the PWRGD pin from switching to a low voltage state if

the ADJ pin voltage falls below the regulated voltage by

more than 10% in a short transient (<40μs typical) event.

BOTH CAPACITORS ARE 16V,

1210 CASE SIZE, 10µF

–50 –25

0

25

50

TEMPERATURE (°C)

75

100 125

3030 F03

Figure 3. Ceramic Capacitor

Temperature Characteristics

C

I

= 10µF

OUT

= 0.01µF

= 750mA

BYP

LOAD

V

OUT

500µV/DIV

Thermal Considerations

The LT3030’s power handling capability limits the maxi-

mumratedjunctiontemperature(125°C,LT3030E/LT3030I

or 150°C, LT3030H/LT3030MP). Two components com-

3030 F04

100ms/DIV

Figure 4. Noise Resulting from Tapping on a Ceramic Capacitor

prise the power dissipated by each channel:

3030f

14

For more information www.linear.com/3030

LT3030

applicaTions inForMaTion

Table 3. FE Package, 20-Lead TSSOP

COPPER AREA

1. Output current multiplied by the input/output voltage

differential: (I )(V – V ), and

OUT

IN

OUT

THERMAL RESISTANCE

TOPSIDE*

BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)

2.GND pin current multiplied by the input voltage:

(I )(V ).

2

2500mm

25°C/W

27°C/W

28°C/W

32°C/W

GND

IN

2

1000mm

2

225mm

Ground pin current is found by examining the GND Pin

Current curves in the Typical Performance Characteristics

section.

2

100mm

*Device is mounted on topside.

Power dissipation for each channel equals the sum of the

two components listed above. Total power dissipation for

the LT3030 equals the sum of the power dissipated by

each channel.

The junction-to-case thermal resistance (θ ), measured

JC

at the exposed pad on the back of the die, is 3.4°C/W for

the QFN package, and 10°C/W for the TSSOP package.

The LT3030’s internal thermal shutdown circuitry

protects both channels of the device if either channel

experiences an overload or fault condition. Activation

of the thermal shutdown circuitry turns both channels

off. If the overload or fault condition is removed, both

outputs are allowed to turn back on. For continu-

ous normal conditions, do not exceed the maximum

junctiontemperatureratingof125°C(LT3030E/LT3030I)

or 150°C (LT3030H/LT3030MP).

Calculating Junction Temperature

Example: Channel 1’s output voltage is set to 1.8V.

Channel 2’s output voltage is set to 1.5V. Each channel’s

input voltage is 2.5V. Channel 1’s output current range

is 0mA to 750mA. Channel 2’s output current range is

0mA to 250mA. The application has a maximum ambient

temperature of 50°C. What is the LT3030’s maximum

junction temperature?

The power dissipated by each channel equals:

Carefully consider all sources of thermal resistance from

junction-to-ambient, including additional heat sources

mounted in proximity to the LT3030. For surface mount

devices,usetheheatspreadingcapabilitiesofthePCboard

and its copper traces to accomplish heat sinking. Copper

board stiffeners and platedthrough-holes can also spread

the heat generated by power devices.

I

(V – V ) + I

(V )

GND IN

OUT(MAX) IN

OUT

where for output 1:

I

= 750mA

OUT(MAX)

V = 2.5V

IN

I

at (I

= 750mA, V = 2.5V) = 13mA

OUT IN

GND

For output 2:

= 250mA

The following tables list thermal resistance as a function of

copper area in a fixed board size. All measurements were

taken in still air on a four-layer FR-4 board with 1oz solid

internal planes, and 2oz external trace planes with a total

board thickness of 1.6mm. For further information on ther-

malresistanceandusingthermalinformation,refertoJEDEC

standard JESD51, notably JESD 51-7 and JESD 51-12.

I

OUT(MAX)

V = 2.5V

IN

GND

I

at (I = 250mA, V = 2.5V) = 4.5mA

OUT IN

So, for output 1:

P = 750mA (2.5V – 1.8V) + 13mA (2.5V) = 0.56W

For output 2:

Table 2. UFD Package, 28-Lead QFN

COPPER AREA

THERMAL RESISTANCE

P = 250mA (2.5V – 1.5V) + 4.5mA (2.5V) = 0.26W

TOPSIDE*

BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)

2

Thethermalresistanceisintherangeof25°C/Wto35°C/W,

dependingonthecopperarea.So,thejunctiontemperature

rise above ambient temperature approximately equals:

2500mm

30°C/W

32°C/W

33°C/W

35°C/W

2

1000mm

2

225mm

2

100mm

(0.56W + 0.26W) 30°C/W = 24.6°C

*Device is mounted on topside.

3030f

15

For more information www.linear.com/3030

LT3030

applicaTions inForMaTion

The maximum junction temperature then equals the maxi-

mum ambient temperature plus the maximum junction

temperature rise above ambient temperature, or:

The LT3030 incurs no damage if either ADJ pin is pulled

above or below ground by ±V. If the input is left open

circuit or grounded, the ADJ pins perform like an open

circuit down to –1.5V, and then like a 1.2k resistor down

to –±V when pulled below ground. When pulled above

ground, the ADJ pins perform like an open circuit up to

0.5V, then like a 5.7k resistor up to 3V, then like a 1.8k

resistor up to ±V.

T

JMAX

= 50°C + 24.6°C = 74.6°C

Protection Features

The LT3030 regulator incorporates several protection fea-

tures that make it ideal for use in battery-powered circuits.

Inadditiontothenormalprotectionfeaturesassociatedwith

monolithicregulators,suchascurrentlimitingandthermal

limiting,thedeviceprotectsitselfagainstreverseinputvolt-

ages and reverse voltages from output to input. The two

regulators have independent inputs, a common GND pin

and are thermally coupled. However, the two channels of

the LT3030 operate independently. Each channel’s output

can be shut down independently, and a fault condition on

one output does not affect the other output electrically,

unless the thermal shutdown circuitry is activated.

InsituationswhereanADJpinconnectstoaresistordivider

that would pull the pin above its ±V clamp voltage if the

output is pulled high, the ADJ pin input current must be

limited to less than 5mA. For example, assume a resistor

divider sets the regulated output voltage to 1.5V, and the

output is forced to 20V. The top resistor of the resistor

divider must be chosen to limit the current into the ADJ

pin to less than 5mA when the ADJ pin is at ±V. The 11V

difference between the OUT and ADJ pins divided by the

5mA maximum current into the ADJ pin yields a minimum

top resistor value of 2.2k.

Current limit protection and thermal overload protection

protect the device against current overload conditions at

each output of the LT3030. For normal operation, do not

allowthejunctiontemperaturetoexceed125°C(LT3030E/

LT3030I) or 150°C (LT3030H/LT3030MP). The typical

thermal shutdown temperature threshold is 165°C and

thecircuitryincorporatesapproximately5°Cofhysteresis.

In circuits where a backup battery is required, several

different input/output conditions can occur. The output

voltage may be held up while the input is either pulled

to ground, pulled to some intermediate voltage or is left

open-circuit. Current flow back into the output follows the

curve shown in Figure 5.

If either of the LT3030’s IN pins is forced below its cor-

responding OUT pin, or the OUT pin is pulled above its

correspondingINpin,inputcurrentforthatchanneltypically

Each channel’s input withstands reverse voltages of 22V.

Current flow into the device is limited to less than 1mA

(typicallylessthan100μA)andnonegativevoltageappears

at the respective channel’s output. The device protects

both itself and the load against batteries that are plugged

in backwards.

5.0

T = 25°C

J

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

V

= V = 0V

IN1

IN2

= V

ADJ1

ADJ2

OUT1

OUT2

= V

The LT3030 incurs no damage if either channel’s output

is pulled below ground. If the input is left open-circuit,

or grounded, the output can be pulled below ground by

22V. The output acts like an open circuit, and no current

flows from the output. However, current flows in (but is

limitedby)theexternalresistordividerthatsetstheoutput

voltage. If the input is powered by a voltage source, the

output sources current equal to its current limit capabil-

ity and the LT3030 protects itself by its thermal limiting

circuitry. In this case, grounding the relevant SHDN1 or

SHDN2 pin turns off its channel’s output and stops that

output from sourcing current.

I

OR I

ADJ2

ADJ1

I

OR I

7

OUT1

6

OUT2

8

0

1

2

3

4

5

9

OUTPUT VOLTAGE (V)

3030 F05

I

= FLOWS INTO ADJ PIN TO GND PIN

= FLOWS INTO OUT PIN TO IN PIN

ADJ

OUT

Figure 5. Reverse Output Current

3030f

16

For more information www.linear.com/3030

LT3030

applicaTions inForMaTion

drops to less than 2μA. This occurs if the IN pin is con-

nected to a discharged (low voltage) battery, and either

a backup battery or a second regulator circuit holds up

the output. The state of that channel’s SHDN pin has no

effect on the reverse output current if the output is pulled

above the input.

When power is first applied, as input voltage rises, the

output follows the input, allowing the regulator to start-up

into heavy loads. During start-up, as the input voltage is

rising, the input-to-output voltage differential is small, al-

lowing the regulator to supply large output currents. With

a high input voltage, an event can occur wherein removal

of an output short will not allow the output to recover. The

eventoccurswithaheavyoutputloadwhentheinputvoltage

is high and the output voltage is low. Common situations

occur immediately after the removal of a short-circuit or if

the shutdown pin is pulled high after the input voltage has

already been turned on. The load line intersects the output

current curve at two points creating two stable output oper-

ating points for the regulator. With this double intersection,

the input power supply may need to be cycled down to zero

and brought up again to make the output recover.

Overload Recovery

Like many IC power regulators, the LT3030 has safe

operating area (SOA) protection. The safe area protec-

tion decreases current limit as input-to-output voltage

increases and keeps the power transistor inside a safe

operating region for all values of input-to-output voltage.

The protective design provides some output current at

all values of input-to-output voltage up to the specified

maximum operational input voltage of 20V.

Typical applicaTions

Coincident Tracking Supply Application

3.3V

C

GATE

V

OUT1

0.1µF

V

GATE

LTC2923

1.8V

CC

IN1

OUT1

750mA

LT3030

10nF

10µF

113k

1%

3.3µF

1M

ON

OFF ON

RAMP

PWRGD1

BYP1

ADJ1

RAMPBUF FB1

SHDN1

113k

237k

1%

TRACK1

SDO

90.9k

1%

54.9k

1%

2.5V

V

IN2

OUT2

1.5V

3.3µF

10nF

3.3µF

TRACK2

FB2

250mA

54.9k

1%

63.4k

1%

PWRGD2

BYP2

ADJ2

GND

SHDN2

237k

1%

GND

3030 TA02a

V

OUT1

OUT2

500mV/DIV

3030 TA02b

20ms/DIV

3030f

17

For more information www.linear.com/3030

LT3030

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UFD Package

28-Lead (4mm × 5mm) Plastic QFN

(Reference LTC DWG # 05-08-1712 Rev B)

0.70 0.05

4.50 0.05

3.10 0.05

2.50 REF

2.65 0.05

3.65 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

3.50 REF

4.10 0.05

5.50 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH

R = 0.20 OR 0.35

× 45° CHAMFER

2.50 REF

R = 0.115

TYP

R = 0.05

TYP

0.75 0.05

4.00 0.10

(2 SIDES)

27

28

0.40 0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

5.00 0.10

(2 SIDES)

3.50 REF

3.65 0.10

2.65 0.10

(UFD28) QFN 0506 REV B

0.25 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3030f

18

For more information www.linear.com/3030

LT3030

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

FE Package

20-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663 Rev J)

Exposed Pad Variation CB

6.40 – 6.60*

3.86

(.152)

(.252 – .260)

3.86

(.152)

20 1918 17 16 15 14 1312 11

6.60 ±0.10

2.74

(.108)

4.50 ±0.10

6.40

(.252)

BSC

2.74

(.108)

SEE NOTE 4

0.45 ±0.05

1.05 ±0.10

0.65 BSC

5

7

8

1

2

3

4

6

9 10

RECOMMENDED SOLDER PAD LAYOUT

1.20

(.047)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

0.195 – 0.30

FE20 (CB) TSSOP REV J 1012

(.0077 – .0118)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

MILLIMETERS

(INCHES)

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

3030f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

19

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/3030

LT3030

Typical applicaTion

Sequencing Supply Application

V

OUT1

V

IN1

1.8V

IN1

OUT1

3.3V

750mA

LT3030

10nF

22µF

1µF

113k

1%

1M

SHDN1

BYP1

ADJ1

V

OUT2

1V/DIV

PWRGD1

IN2

237k

1%

V

1.5V

250mA

OUT2

V

OUT1

V

IN2

OUT2

1V/DIV

2.5V

10nF

10µF

1M

54.9k

1%

V

SHDN1

PWRGD2

BYP2

ADJ2

5V/DIV

3030 TA03b

SHDN2

10ms/DIV

237k

1%

GND

3030 TA03a

relaTeD parTs

PART NUMBER DESCRIPTION

COMMENTS

V : 1.8V to 20V, V

LT1761

100mA, Low Noise Micropower LDO

= 1.22V, V = 0.3V, I = 20μA, I <1μA, Low Noise < 20μV

,

IN

OUT

DO

Q

SD

RMS

Stable with 1μF Ceramic Capacitors, ThinSOT™ Package

LT1763

500mA, Low Noise Micropower LDO

V : 1.8V to 20V, V

= 1.22V, V = 0.3V, I = 30μA, I <1μA, Low Noise < 20μV

DO Q SD

IN

OUT

RMS

S8 Package

LT1 63/

LT1 63A

1.5A, Low Noise, Fast Transient Response V : 2.1V to 20V, V

= 1.21V, V = 0.34V, I = 1mA, I < 1μA,

IN

OUT(MIN) DO Q SD

LDOs

Low Noise: < 40μV

, “A” Version Stable with Ceramic Capacitors, DD, TO220-5, SOT223,

RMS

S8 Packages

LT1 64

LT1 65

200mA, Low Noise Micropower, Negative V : –2.2V to –20V, V

= 1.21V, V = 0.34V, I = 30μA, I = 3μA,

IN

OUT(MIN) DO Q SD

LDO

Low Noise: <30μV

, Stable with Ceramic Capacitors, ThinSOT Package

RMS

1.1A, Low Noise, Fast Transient Response V : 1.8V to 20V, V

= 1.20V, V = 0.3V, I = 0.5mA, I < 1μA,

DO Q SD

, Stable with Ceramic Capacitors, 3mm × 3mm DFN,

IN

OUT(MIN)

LDO

Low Noise: < 40μV

RMS

MS8E, DD-Pak, TO-220 Packages

LT3023

LT3024

LT3027

LT3028

LT302

Dual 100mA, Low Noise, Micropower

LDO

V : 1.8V to 20V, V

= 1.22V, V = 0.30V, I = 40μA, I <1μA, DFN,

DO Q SD

IN

OUT(MIN)

MS10 Packages

Dual 100mA/500mA, Low Noise,

Micropower LDO

V : 1.8V to 20V, V

= 1.22V, V = 0.30V, I = 60μA, I <1μA, DFN,

DO Q SD

IN

OUT(MIN)

TSSOP-16E Packages

Dual 100mA, Low Noise, Micropower

LDO with Independent Inputs

V : 1.8V to 20V, V

= 1.22V, V = 0.30V, I = 40μA, I <1μA, DFN,

DO Q SD

IN

OUT(MIN)

MS10E Packages

Dual 100mA/500mA, Low Noise,

Micropower LDO with Independent Inputs TSSOP-16E Packages

V : 1.8V to 20V, V

= 1.22V, V = 0.30V, I = 60μA, I <1μA, DFN,

DO Q SD

IN

OUT(MIN)

Dual 500mA/500mA, Low Noise,

Micropower LDO with Independent Inputs MSOP-16E Packages

V : 1.8V to 20V, V

= 1.215V, V = 0.30V, I = 55μA, I <1μA, DFN,

IN

OUT(MIN) DO Q SD

LT3032

Dual 150mA Positive/Negative Low

Noise, Low Dropout Linear Regulator

V : ±2.3V to ±20V, V

= ±1.22V, V = 0.30V, I = 30μA, I <1μA,

OUT(MIN) DO Q SD

IN

14-Lead DFN Package

LT3080/

LT3080-1

1.1A, Parallelable, Low Noise LDO

300mV Dropout Voltage (2-Supply Operation), Low Noise 40µV

, V = 1.2V to 36V,

RMS IN

V

: 0V to 35.7V, Current-Based Reference with 1-Resistor V

Set, Directly Parallelable

OUT

(No Op Amp Required), Stable with Ceramic Capacitors, TO-220, SOT-223, MSOP and

3mm × 3mm DFN

3030f

LT 0213 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 5035-7417

20

For more information www.linear.com/3030

●

 LINEAR TECHNOLOGY CORPORATION 2013

(408)432-1 00 FAX: (408) 434-0507 www.linear.com/3030


型号：	LT1965EQ#PBF
厂家：	Linear
描述：	LT1965 - 1.1A, Low Noise, Low Dropout Linear Regulator; Package: DD PAK; Pins: 5; Temperature Range: -40°C to 85°C 稳压器
文件：	总20页 (文件大小：584K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT1965EQ#PBF [Linear]

相关型号：

LT1965EQ-1.5#TRPBF

LT1965EQ-2.5#TRPBF

LT1965EQ-3.3#PBF

LT1965EQ-3.3#TRPBF

LT1965EQPBF

LT1965EQTRPBF

LT1965ET#PBF

LT1965ET-2.5#PBF

LT1965ETPBF

LT1965ETTRPBF

LT1965IDD

LT1965IDD#PBF