LT1976B_技术文档

LT1976/LT1976B

High Voltage 1.5A, 200kHz

Step-Down Switching Regulator

with 100μA Quiescent Current

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FEATURES

DESCRIPTIO

The LT^®1976/LT1976B are 200kHz monolithic step-down

switching regulators that accept input voltages up to 60V.

A high efficiency 1.5A, 0.2Ω switch is included on the die

along with all the necessary oscillator, control and logic

circuitry. Current mode topology is used for fast transient

■

Wide Input Range: 3.3V to 60V

1.5A Peak Switch Current (LT1976)

100μA Quiescent Current (LT1976)**

1.6mA Quiescent Current (LT1976B)

Low Shutdown Current: I_Q< 1μA

Power Good Flag with Programmable Threshold

Load Dump Protection to 60V

200kHz Switching Frequency

■

response and good loop stability.

■

Innovative design techniques along with a new high volt-

age process achieve high efficiency over a wide input

range. Efficiency is maintained over a wide output current

rangebyemployingBurstModeoperationatlowcurrents,

utilizing the output to bias the internal circuitry, and by

using a supply boost capacitor to fully saturate the power

switch. The LT1976B does not shift into Burst Mode

operation at low currents, eliminating low frequency out-

put ripple at the expense of efficiency. Patented circuitry

maintains peak switch current over the full duty cycle

range.* Shutdown reduces input supply current to less

than 1μA. External synchronization can be implemented

by driving the SYNC pin with logic-level inputs. A single

capacitor from the C_SSpin to the output provides a

controlled output voltage ramp (soft-start). The devices

also have a power good flag with a programmable thresh-

old and time-out and thermal shutdown protection.

■

Saturating Switch Design: 0.2Ω On-Resistance

Peak Switch Current Maintained Over

■

Full Duty Cycle Range*

1.25V Feedback Reference Voltage

Easily Synchronizable

Soft-Start Capability

■

Small 16-Pin Thermally Enhanced TSSOP Package

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APPLICATIO S

■

High Voltage Power Conversion

14V and 42V Automotive Systems

Industrial Power Systems

Distributed Power Systems

■

Battery-Powered Systems

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

Burst Mode is a registered trademark of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

*Protected by U.S. Patents, including 6498466

The LT1976/LT1976B are available in a 16-pin TSSOP

package with Exposed Pad leadframe for low thermal

resistance.

**See Burst Mode Operation section for conditions

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TYPICAL APPLICATIO

LT1976 Supply Current vs

Input Voltage

LT1976 Efficiency and Power

Loss vs Load Current

14V to 3.3V Step-Down Converter with

100μA No Load Quiescent Current

150

100

75

50

25

0

10

V

= 3.3V

= 25°C

OUT

A

T

EFFICIENCY

V

3.3V

1A

OUT

125

100

75

50

25

0

V

IN

V

BOOST

SW

IN

3.3V TO 60V

1

4.7μF

100V

CER

33μH

0.33μF

4148

SHDN

5V

0.1μF

LT1976

3.3V

10MQ60N

0.1

C

SS

V

C

330pF

1500pF

10k

TYPICAL

POWER LOSS

V

BIAS

165k

47pF

FB

1%

100μF

6.3V

TANT

0.01

0.001

C

T

PGFB

PG

1μF

SYNC

GND

100k

1%

1976 TA01

0

10

20

30

40

50

60

0.1

1

10

100

1000 10000

INPUT VOLTAGE (V)

1976 F05

LOAD CURRENT (mA)

1976 TA02

1976bfg

1

LT1976/LT1976B

W W U W

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ABSOLUTE AXI U RATI GS

(Note 1)

PACKAGE/ORDER I FOR ATIO

V_IN, SHDN, PG, BIAS .............................................. 60V

BOOST Pin Above SW ............................................ 35V

BOOST Pin Voltage ................................................. 68V

SYNC, C_SS, PGFB, FB................................................ 6V

Operating JunctionTemperature Range

LT1976EFE/LT1976BEFE (Note 2) ... –40°C to 125°C

LT1976IFE/LT1976BIFE (Note 2) ..... –40°C to 125°C

LT1976HFE (Note 2)........................ –40°C to 140°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

ORDER PART

NUMBER

TOP VIEW

NC

SW

NC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

PG

LT1976EFE

LT1976IFE

LT1976HFE

LT1976BEFE

LT1976BIFE

SHDN

SYNC

PGFB

FB

V

IN

17

NC

BOOST

V

C

T

BIAS

FE PART MARKING

GND

C

SS

1976EFE

1976IFE

1976HFE

1976BEFE

1976BIFE

FE PACKAGE

16-LEAD PLASTIC TSSOP

_JA= 45°C/W, θ_JC(PAD)= 10°C/W

θ

EXPOSED PAD IS GND (PIN 17)

MUST BE SOLDERED TO GND (PIN 8)

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full –40°C to 125°C

operating temperature range, otherwise specifications are at T_J= 25°C. V_IN= 12V, SHDN = 12V, BOOST = 15.3V, BIAS = 5V,

FB/PGFB = 1.25V, C_SS/SYNC = 0V unless otherwise noted.

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

1.3

5

MAX

1.4

20

3

UNITS

V

I

SHDN Threshold

●

1.2

SHDN

SHDN Input Current

SHDN = 12V

μA

V

SHDN

VINS

Minimum Input Voltage (Note 3)

Supply Shutdown Current

Supply Sleep Current (Note 4) (LT1976)

2.4

0.1

I

SHDN = 0V, BOOST = 0V, FB/PGFB = 0V

2

μA

mA

BIAS = 0V, FB = 1.35V

FB = 1.35V

●

170

45

230

75

Supply Quiescent Current

BIAS = 0V, FB = 1.15V, V = 0.8V (V = 0V LT1976B)

BIAS = 5V, FB = 1.15V, V = 0.8V (V = 0V LT1976B)

3.2

2.6

4.10

3.25

VIN

C

Minimum BIAS Voltage (Note 5)

BIAS Sleep Current (Note 4) (LT1976)

BIAS Quiescent Current

●

2.7

110

700

1.8

40

3

180

800

2.5

V

μA

I

BIASS

BIAS

SYNC = 3.3V

Minimum Boost Voltage (Note 6)

Input Boost Current (Note 7)

I

= 1.5A

V

SW

50

mA

V

Reference Voltage (V

)

REF

3.3V < V < 60V

●

1.225

1.25

75

1.275

200

REF

VIN

I

FB Input Bias Current

nA

FB

EA Voltage Gain (Note 8)

900

650

40

V/V

μMho

μA

EA Voltage g

dI(V )= 10μA

FB = 1.15V

FB = 1.35V

400

20

800

55

C

m

EA Source Current

EA Sink Current

15

30

40

μA

V to SW g

3

A/V

V

C

m

V High Clamp

C

2.1

0.1

2.2

0.4

2.4

0.8

V Switching Threshold (LT1976B)

C

●

V

1976bfg

2

LT1976/LT1976B

ELECTRICAL CHARACTERISTICS

FB/PGFB = 1.25V, C_SS/SYNC = 0V unless otherwise noted.

The ● denotes the specifications which apply over the full –40°C to 125°C

operating temperature range, otherwise specifications are at T_J= 25°C. V_IN= 12V, SHDN = 12V, BOOST = 15.3V, BIAS = 5V,

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I

SW Current Limit

LT1976

LT1976B

●

1.5

1.2

2.4

2.5

3.5

4

A

PK

Switch On Resistance (Note 9)

Switching Frequency

●

0.2

200

92

0.4

Ω

kHz

%

BOOST = OPEN

180

90

230

Maximum Duty Cycle

Minimum SYNC Amplitude

SYNC Frequency Range

SYNC Input Impedance

1.5

600

100

13

2.0

V

230

7

kHz

kΩ

μA

nA

%

SYNC = 0.5V

FB = 0V

I

C

Current Threshold (Note 10)

SS

20

100

92

CSS

PGFB Input Current

25

PGFB

V

I

PGFB Voltage Threshold (Note 11)

●

88

2

90

PGFB

C Source Current (Note 11)

T

3.6

2

5.5

μA

mA

V

CT

C Sink Current (Note 11)

T

1

V

C Voltage Threshold (Note 11)

T

1.16

1.2

0.1

200

1.26

1

CT

PG Leakage (Note 11)

PG = 12V

μA

PG Sink Current (Note 11)

PGFB = 1V, PG = 400mV

120

The ● denotes the specifications which apply over the full –40°C to 140°C operating temperature range, otherwise specifications are

at T_J= 25°C. V_IN= 12V, SHDN = 12V, BOOST = 15.3V, BIAS = 5V, FB/PGFB = 1.25V, C_SS/SYNC = 0V unless otherwise noted.

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

1.3

5

MAX

1.4

20

3

UNITS

V

I

SHDN Threshold

●

1.2

SHDN

SHDN Input Current

SHDN = 12V

μA

V

SHDN

VINS

Minimum Input Voltage (Note 3)

Supply Shutdown Current

Supply Sleep Current (Note 4) (LT1976)

2.4

0.1

I

SHDN = 0V, BOOST = 0V, FB/PGFB = 0V

2

μA

BIAS = 0V, FB = 1.35V

FB = 1.35V

●

170

45

300

100

μA

Supply Quiescent Current

BIAS = 0V, FB = 1.15V, V = 0.8V

BIAS = 5V, FB = 1.15V, V = 0.8V

3.2

2.6

4.10

3.25

mA

VIN

C

Minimum BIAS Voltage (Note 5)

BIAS Sleep Current (Note 4)

BIAS Quiescent Current

●

2.7

110

700

1.8

40

3

180

800

2.5

V

μA

I

BIASS

BIAS

SYNC = 3.3V

μA

Minimum Boost Voltage (Note 6)

Input Boost Current (Note 7)

I

= 1.5A

V

SW

50

mA

V

Reference Voltage (V

)

REF

3.3V < V < 60V

●

1.212

1.25

75

1.288

200

REF

VIN

I

FB Input Bias Current

nA

FB

EA Voltage Gain (Note 8)

900

650

40

V/V

μMho

μA

EA Voltage g

dI(V )= 10μA

400

20

800

55

C

m

EA Source Current

EA Sink Current

FB = 1.15V

FB = 1.35V

15

30

40

μA

V to SW g

3

A/V

V

C

m

V High Clamp

C

2.1

2.2

2.4

1976bfg

3

LT1976/LT1976B

ELECTRICAL CHARACTERISTICS

FB/PGFB = 1.25V, C_SS/SYNC = 0V unless otherwise noted.

The ● denotes the specifications which apply over the full –40°C to 140°C

operating temperature range, otherwise specifications are at T_J= 25°C. V_IN= 12V, SHDN = 12V, BOOST = 15.3V, BIAS = 5V,

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

2.4

0.2

200

92

MAX

UNITS

A

I

SW Current Limit

PK

Switch On Resistance (Note 9)

Switching Frequency

●

0.6

Ω

BOOST = OPEN

150

90

260

kHz

%

Maximum Duty Cycle

Minimum SYNC Amplitude

SYNC Frequency Range

SYNC Input Impedance

1.5

600

85

2.0

V

230

7

kHz

kΩ

μA

nA

%

SYNC = 0.5V

I

C

Current Threshold (Note 10)

SS

13

20

100

93

CSS

PGFB Input Current

25

PGFB

V

I

PGFB Voltage Threshold (Note 11)

●

87

1.5

1

90

PGFB

C Source Current (Note 11)

T

3.6

2

5.5

μA

mA

V

CT

C Sink Current (Note 11)

T

V

C Voltage Threshold (Note 11)

T

1.16

1.2

0.1

200

1.26

1

CT

PG Leakage (Note 11)

PG = 12V

μA

PG Sink Current (Note 11)

PGFB = 1V, PG = 400mV

120

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 5: Minimum BIAS voltage is the voltage on the BIAS pin when I

sourced into the pin.

is

BIAS

Note 6: This is the minimum voltage across the boost capacitor needed to

guarantee full saturation of the internal power switch.

Note 2: The LT1976EFE/LT1976BEFE are guaranteed to meet performance

specifications from 0°C to 125°C junction temperature. Specifications over

the –40°C to 125°C operating junction temperature range are assured by

design, characterization and correlation with statistical process controls.

The LT1976IFE/LT1976BIFE/LT1976HFE are guaranteed and tested over

the full –40°C to 125°C operating junction temperature range. The

LT1976HFE is also tested to the LT1976HFE electrical characteristics table

at 140°C operating junction temperature. High junction temperatures

degrade operating lifetimes.

Note 7: Boost current is the current flowing into the BOOST pin with the

pin held 3.3V above input voltage. It flows only during switch on time.

Note 8: Gain is measured with a V swing from 1.15V to 750mV.

C

Note 9: Switch on resistance is calculated by dividing V to SW voltage by

IN

the forced current (1.5A LT1976, 1.2A LT1976B). See Typical Performance

Characteristics for the graph of switch voltage at other currents.

Note 10: The C threshold is defined as the value of current sourced into

SS

the C pin which results in an increase in sink current from the V pin.

SS

C

See the Soft-Start section in Applications Information.

Note 3: Minimum input voltage is defined as the voltage where switching

starts. Actual minimum input voltage to maintain a regulated output will

depend upon output voltage and load current. See Applications

Information.

Note 4: Supply input current is the quiescent current drawn by the input

pin. Its typical value depends on the voltage on the BIAS pin and operating

state of the LT1976. With the BIAS pin at 0V, all of the quiescent current

Note 11: The PGFB threshold is defined as the percentage of V voltage

REF

which causes the current source output of the C pin to change from

T

sinking (below threshold) to sourcing current (above threshold). When

sourcing current, the voltage on the C pin rises until it is clamped

T

internally. When the clamp is activated, the output of the PG pin will be set

to a high impedance state. When the C clamp is inactive the PG pin will

T

be set active low with a current sink capability of 200μA.

required to operate the LT1976 will be provided by the V pin. With the

IN

BIAS voltage above its minimum input voltage, a portion of the total

quiescent current will be supplied by the BIAS pin. Supply sleep current

for the LT1976 is defined as the quiescent current during the “sleep”

portion of Burst Mode operation. See Applications Information for

determining application supply currents.

1976bfg

4

LT1976/LT1976B

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TYPICAL PERFOR A CE CHARACTERISTICS

LT1976B Efficiency and Power

Loss vs Load Current

LT1976 Efficiency and Power Loss

vs Load Current

FB Voltage

100

75

50

25

0

10

1.30

100

75

50

25

0

10

1.29

1.28

1.27

1.26

1.25

1.24

1.23

1.22

1.21

1.20

EFFICIENCY

1

5V

3.3V

0.1

0.01

0.001

0.1

0.01

0.001

TYPICAL

POWER LOSS

0.1

1

10

100

1000 10000

–50

–25

0

25 50 75 100 125 150

0.1

1

10

100

1000 10000

LOAD CURRENT (mA)

TEMPERATURE (°C)

LOAD CURRENT (mA)

1976 TA02

1976 G25

1976 G01

Oscillator Frequency

SHDN Threshold

SHDN Pin Current

250

240

230

220

210

200

190

180

170

160

150

1.40

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0

T

= 25°C

J

1.35

1.30

1.25

1.20

0.15

1.10

1.05

1.00

–50

0

25 50 75 100 125 150

–25

0

10

30

40

50

60

–50 –25

0

25 50 75 100 125 150

20

TEMPERATURE (°C)

SHDN VOLTAGE (V)

TEMPERATURE (°C)

1976 G02

1976 G03

1976 G04

LT1976 Sleep Mode Supply

Current

LT1976 Bias Sleep Current

Shutdown Supply Current

200

180

160

140

120

100

80

240

220

200

180

160

140

120

100

80

25

20

15

10

5

V

BIAS

= 0V

V

= 60V

IN

V

BIAS

= 5V

60

40

V

= 42V

V

= 12V

IN

0

20

0

–50

0

25 50 75 100 125 150

TEMPERATURE (°C)

1976 G07

–25

–50

25 50 75 100 125 150

–50

0

25 50 75

125 150

100

–25

TEMPERATURE (°C)

1976 G05

1976 G06

1976bfg

5

LT1976/LT1976B

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TYPICAL PERFOR A CE CHARACTERISTICS

Switch Peak Current Limit

PGFB Threshold

PG Sink Current

1.20

1.18

1.16

1.14

1.12

1.10

1.08

1.06

1.04

1.02

1.00

3.5

3.0

2.5

2.0

250

200

150

100

50

1.5

0

–50

–50 –25 –0 25 50 75 100 125 150

–50

0

25 50 75 100 125 150

TEMPERATURE (°C)

50

TEMPERATURE (°C)

–25

0

25

75 100

125 150

–25

TEMPERATURE (°C)

1976 G10

1976 G08

Soft-Start Current Threshold

vs FB Voltage

Oscillator Frequency

vs FB Voltage

Switch On Voltage (V_CESAT

)

500

450

400

350

300

250

200

150

100

50

45

40

35

30

25

20

15

10

5

250

200

150

100

50

T

= 25°C

T

= 25°C

J

SOFT-START

DEFEATED

T = 125°C

J

T = 25°C

J

T = –50°C

J

0

0.5

0

0.2

0.6

0.8

1.0

1.2

0.7

1.1

LOAD CURRENT (A)

1.3

0.4

0

0.2

0.6

0.8

1.0

1.2

0.9

1.5

0.4

FB VOLTAGE (V)

1976 G11

1976 G13

1976 G12

LT1976 Supply Current

vs Input Voltage

LT1976 Burst Mode Threshold

vs Input Voltage

Minimum Input Voltage

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

200

180

160

140

120

100

80

150

125

100

75

V

= 3.3V

V

= 3.3V

OUT

T

A

OUT

= 25°C

L = 33μH

= 100μF

C

OUT

5V START

5V RUNNING

3.3V START

50

60

40

25

3.3V RUNNING

20

0

800 1000

1200 1400 1600

0

200 400 600

5

7

9

11 13 15 17 19 21 23 25

INPUT VOLTAGE (V)

1975 G20

0

10

30

40

50

60

20

LOAD CURRENT (mA)

INPUT VOLTAGE (V)

1976 F05

1976 G19

1976bfg

6

LT1976/LT1976B

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TYPICAL PERFOR A CE CHARACTERISTICS

LT1976B V_CSwitching Threshold

vs Temperature

Minimum On Time

Boost Current vs Load Current

500

450

400

350

300

250

200

150

100

50

700

600

45

40

35

30

25

20

15

10

5

500

400

300

200

100

LOAD CURRENT = 0.5A

LOAD CURRENT = 1A

0

–50 –30 –10 10 30 50 70 90 110

0

200 400 600 800 1000 1200 1400

LOAD CURRENT (mA)

–30 –10 10 30 50

–50

70 90 110

TEMPERATURE (°C)

TEMPERATURE (˚C)

1976 G21

1976 G22

1976 G26

Dropout Operation

LT1976 Burst Mode Operation

4.0

3.5

3.0

2.5

6

5

4

3

2

1

0

V

= 3.3V

V

= 5V

OUT

V_OUT

BOOST DIODE = DIODES INC. B1100

50mV/DIV

LOAD CURRENT = 250mA

I_SW

100mA/DIV

2.0

1.5

LOAD CURRENT = 1.25A

LOAD CURRENT = 250mA

LOAD CURRENT = 1.25A

1.0

0.5

0

0A

V_IN= 12V

TIME (5ms/DIV)

1976 G14

V_OUT= 3.3V

I_Q= 100μA

2.5

3

4

2

4.5

INPUT VOLTAGE (V)

5

3.5

2

2.5

3

3.5

4

5.5

6

INPUT VOLTAGE (V)

1976 G23

1976 G24

LT1976B No Load Operation

(Pulse-Skipping Mode)

LT1976 No Load 1A

Step Response

LT1976 Burst Mode Operation

V_OUT

50mV/DIV

AC

V_OUT

50mV/

DIV

V_OUT

100mV/DIV

COUPLED

I_SW

100mA/DIV

1A

I_OUT

I_SW

100mA/

DIV

500mA/DIV

0A

V

_IN= 12V

TIME (10μs/DIV)

1976 G27

V_IN= 12V

V_OUT= 3.3V

I_Q= 100μA

TIME (10μs/DIV)

1976 G15

V_IN= 12V

V_OUT= 3.3V

C_OUT= 47μF

TIME (1ms/DIV)

1976 G17

V_OUT= 3.3V

I_Q= 1.6mA

1976bfg

7

LT1976/LT1976B

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TYPICAL PERFOR A CE CHARACTERISTICS

LT1976 Step Response

V_OUT

100mV/DIV

1A

I_OUT

500mA/DIV

0A

V_IN= 12V

TIME (1ms/DIV)

1976 G18

V_OUT= 3.3V

C

_OUT= 47μF

I_DC= 250mA

U

PI FU CTIO S

NC (Pins 1, 3, 5): No Connection. Pins 1, 3, 5 are

electrically isolated from the LT1976. They may be con-

nected to PCB traces to aid in PCB layout.

C_T(Pin7):AcapacitorontheC_Tpindeterminestheamount

of delay time between the PGFB pin exceeding its thresh-

old (V_PGFB) and the PG pin set to a high impedance state.

When the PGFB pin rises above V_PGFB, current is sourced

from the C_Tpin into the external capacitor. When the volt-

age on the external capacitor reaches an internal clamp

(V_CT), the PG pin becomes a high impedance node. The

resultant PG delay time is given by t = C_CT• V_CT/I_CT. If the

voltage on the PGFB pin drops below V_PGFB, C_CTwill be

discharged rapidly to 0V and PG will be active low with a

200μAsinkcapability.IftheC_Tpinisclamped(PowerGood

condition)duringnormaloperationandSHDNistakenlow,

the C_Tpin will be discharged and a delay period will occur

when SHDN is returned high. See the Power Good section

in Applications Information for details.

SW(Pin2):TheSWpinistheemitteroftheon-chippower

NPN switch. This pin is driven up to the input pin voltage

during switch on time. Inductor current drives the SW pin

negativeduringswitchofftime.Negativevoltageisclamped

with the external Schottky catch diode to prevent exces-

sive negative voltages.

V_IN(Pin 4): This is the collector of the on-chip power NPN

switch. V_INpowers the internal control circuitry when a

voltage on the BIAS pin is not present. High di/dt edges

occur on this pin during switch turn on and off. Keep the

path short from the V_INpin through the input bypass

capacitor, through the catch diode back to SW. All trace

inductanceonthispathwillcreateavoltagespikeatswitch

off, adding to the V_CEvoltage across the internal NPN.

GND (Pins 8, 17): The GND pin connection acts as the

reference for the regulated output, so load regulation will

suffer if the “ground” end of the load is not at the same

voltage as the GND pin of the IC. This condition will occur

when load current or other currents flow through metal

paths between the GND pin and the load ground. Keep the

path between the GND pin and the load ground short and

use a ground plane when possible. The GND pin also acts

as a heat sink and should be soldered (along with the

exposed leadframe) to the copper ground plane to reduce

thermal resistance (see Applications Information).

BOOST (Pin 6): The BOOST pin is used to provide a drive

voltage, higher than the input voltage, to the internal

bipolarNPNpowerswitch. Withoutthisaddedvoltage, the

typical switch voltage loss would be about 1.5V. The

additional BOOST voltage allows the switch to saturate

and its voltage loss approximates that of a 0.2Ω FET

structure, but with much smaller die area.

1976bfg

8

LT1976/LT1976B

U

PI FU CTIO S

C_SS(Pin 9): A capacitor from the C_SSpin to the regulated

output voltage determines the output voltage ramp rate

during start-up. When the current through the C_SScapaci-

tor exceeds the C_SSthreshold (I_CSS), the voltage ramp of

the output is limited. The C_SSthreshold is proportional to

the FB voltage (see Typical Performance Characteristics)

and is defeated for FB voltage greater than 0.9V (typical).

See Soft-Start section in Applications Information for

details.

PGFB (PIN 13): The PGFB pin is the positive input to a

comparator whose negative input is set at V_PGFB. When

PGFB is taken above V_PGFB, current (I_CSS) is sourced into

the C_Tpin starting the PG delay period. When the voltage

on the PGFB pin drops below V_PGFB, the C_Tpin is rapidly

discharged resetting the PG delay period. The PGFB volt-

age is typically generated by a resistive divider from the

regulated output or input supply. See Power Good section

in Applications Information for details.

BIAS (Pin 10): The BIAS pin is used to improve efficiency

when operating at higher input voltages and light load

current. Connecting this pin to the regulated output volt-

age forces most of the internal circuitry to draw its

operating current from the output voltage rather than the

input supply. This architecture increases efficiency espe-

cially when the input voltage is much higher than the

output. Minimum output voltage setting for this mode of

operation is 3V.

SYNC (Pin 14): The SYNC pin is used to synchronize the

internal oscillator to an external signal. It is directly logic

compatible and can be driven with any signal between

20% and 80% duty cycle. The synchronizing range is

equaltomaximuminitialoperatingfrequencyupto700kHz.

When the voltage on the FB pin is below 0.9V the SYNC

function is disabled. See the Synchronizing section in

Applications Information for details.

SHDN (Pin 15): The SHDN pin is used to turn off the

regulator and to reduce input current to less than 1μA. The

SHDN pin requires a voltage above 1.3V with a typical

source current of 5μA to take the IC out of the shutdown

state.

V_C(Pin 11): The V_Cpin is the output of the error amplifier

and the input of the peak switch current comparator. It is

normally used for frequency compensation, but can also

serve as a current clamp or control loop override. The V_C

pin sits about 0.45V for light loads and 2.2V at current

limit. The LT1976 clamps the V_Cpin slightly below the

burst threshold during sleep periods for better transient

response. Driving the V_Cpin to ground will disable switch-

ing and also place the LT1976 into sleep mode.

PG (Pin 16): The PG pin is functional only when the SHDN

pin is above its threshold, and is active low when the

internal clamp on the C_Tpin is below its clamp level and

high impedance when the clamp is active. The PG pin has

a typical sink capability of 200μA. See the Power Good

section in Applications Information for details.

FB (Pin 12): The feedback pin is used to determine the

output voltage using an external voltage divider from the

outputthatgenerates1.25VattheFBpin. WhentheFBpin

drops below 0.9V, switching frequency is reduced, the

SYNC function is disabled and output ramp rate control is

enabled via the C_SSpin. See the Feedback section in

Applications Information for details.

1976bfg

9

LT1976/LT1976B

W

BLOCK DIAGRA

V

IN

INTERNAL REF

SLOPE

COMP

4

2.4V

UNDERVOLTAGE

LOCKOUT

Σ

+

–

BIAS

THERMAL

SHUTDOWN

200kHz

10

CURRENT

COMP

OSCILLATOR

SYNC

SHDN

14

15

BOOST

SW

6

2

ANTISLOPE

COMP

+

–

R

SHDN

COMP

SWITCH

LATCH

DRIVER

CIRCUITRY

Q

S

1.3V

BURST MODE

DETECT

LT1976 ONLY

C

SS

SOFT-START

9

V

C

CLAMP

FOLDBACK

DETECT

FB

12

–

ERROR

AMP

1.25V

+

V

C

11

13

PG

16

PGFB

+

PG

COMP

1.2V C

T

CLAMP

1.12V

–

GND 17

PGND

C

8

T

7

1976 BD

Figure 1. LT1976/LT1976B Block Diagram

The LT1976 is a constant frequency, current mode buck

converter.Thismeansthatthereisaninternalclockandtwo

feedback loops that control the duty cycle of the power

switch. In addition to the normal error amplifier, there is a

current sense amplifier that monitors switch current on a

cycle-by-cycle basis. A switch cycle starts with an oscilla-

torpulsewhichsetstheRSlatchtoturntheswitchon.When

switch current reaches a level set by the current compara-

tor the latch is reset and the switch turns off. Output volt-

age control is obtained by using the output of the error

amplifiertosettheswitchcurrenttrippoint.Thistechnique

means that the error amplifier commands current to be

delivered to the output rather than voltage. A voltage fed

system will have low phase shift up to the resonant fre-

quencyoftheinductorandoutputcapacitor,thenanabrupt

180° shift will occur. The current fed system will have 90°

phaseshiftatamuchlowerfrequency,butwillnothavethe

additional 90° shift until well beyond the LC resonant fre-

quency. This makes it much easier to frequency compen-

sate the feedback loop and also gives much quicker tran-

sient response.

Most of the circuitry of the LT1976 operates from an

internal 2.4V bias line. The bias regulator normally draws

1976bfg

10

LT1976/LT1976B

W

BLOCK DIAGRA

power from the V_INpin, but if the BIAS pin is connected to

an external voltage higher than 3V bias power will be

drawn from the external source (typically the regulated

output voltage). This improves efficiency.

In Burst Mode operation, all circuitry associated with

controlling the output switch is shut down reducing the

input supply current to 45μA.

The only difference between the LT1976 and the LT1976B

is that the LT1976B does not shift into burst mode in light

load situations, eliminating low frequency output ripple at

the expense of light load efficiency.

High switch efficiency is attained by using the BOOST pin

to provide a voltage to the switch driver which is higher

than the input voltage, allowing switch to be saturated.

This boosted voltage is generated with an external capaci-

tor and diode.

The LT1976 contains a power good flag with a program-

mable threshold and delay time. A logic-level low on the

SHDN pin disables the IC and reduces input suppy current

to less than 1μA.

To further optimize efficiency, the LT1976 automatically

switches to Burst Mode operation in light load situations.

W U U

U

APPLICATIO S I FOR ATIO

CHOOSING THE LT1976 OR LT1977

INPUT VOLTAGE RANGE

The LT1976/LT1976B and LT1977 are high voltage 1.5A

step-down switching regulators. The LT1976 and LT1977

containcircuitrywhichshiftsintoburstmodeatlightloads

reducingquiescentcurrenttotypically100μA.TheLT1976B

pulse skips in light load situations, eliminating low fre-

quency burst mode output ripple at the expense of light

load efficiency. The difference between the LT1976/

LT1976BandLT1977isthatthefixedswitchingfrequency

of the LT1976/LT1976B is 200kHz versus 500kHz for the

LT1977. The switching frequency affects: inductor size,

input voltage range in continuous mode operation, effi-

ciency, thermal loss and EMI.

The minimum on and off times for all versions of the ic are

equivalent. This results in a narrower range of continuous

mode operation for the LT1977. Typical minimum and

maximum duty cycles are 6% to 92% for the LT1976/

LT1976B and 15% to 90% for the LT1977. Both parts will

regulate up to an input voltage of 60V but the LT1977 will

transistionintopulse-skipping/BurstModeoperationwhen

the input voltage is above 30V for a 5V output. At outputs

above 10V the LT1977’s input range will be similar to the

LT1976/LT1976B. Lowering the input voltage below the

maximum duty cycle limitation will cause a dropout in

regulation.

Table 1. LT1976/LT1976B/LT1977 Comparison

OUTPUT RIPPLE AND INDUCTOR SIZE

PARAMETER

Minimum Duty Cycle

Maximum Duty Cycle

Inductor Size

ADVANTAGE

LT1976/LT1976B

LT1977

Output ripple current is determined by the input to output

voltage ratio, inductor value and switch frequency. Since

the switch frequency of the LT1977 is 2.5 times greater

than that of the LT1976/LT1976B, the inductance used in

the LT1977 application can be 2.5 times lower than the

LT1976/LT1976Bwhilemaintainingthesameoutputripple

current. The lower value used in the LT1977 application

allows the use of a physically smaller inductor.

Output Capacitor Size

Efficiency

LT1977

LT1976

EMI

LT1976B

Input Range

LT1976/LT1976B

LT1977

Output Ripple

Light Load Output Ripple

LT1976B

1976bfg

11

LT1976/LT1976B

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APPLICATIO S I FOR ATIO

FEEDBACK PIN FUNCTIONS

More Than Just Voltage Feedback

The feedback (FB) pin on the LT1976 is used to set output

voltage and provide several overload protection features.

The first part of this section deals with selecting resistors

to set output voltage and the remaining part talks about

frequency foldback and soft-start features. Please read

both parts before committing to a final design.

The FB pin is used for more than just output voltage

sensing. It also reduces switching frequency and con-

trolsthesoft-startvoltagerampratewhenoutputvoltage

is below the regulated level (see the Frequency Foldback

and Soft-Start Current graphs in Typical Performance

Characteristics).

Referring to Figure 2, the output voltage is determined by

a voltage divider from V_OUTto ground which generates

1.25VattheFBpin.Sincetheoutputdividerisaloadonthe

output care must be taken when choosing the resistor

divider values. For light load applications the resistor

values should be as large as possible to achieve peak

efficiencyinBurstModeoperation. Extremelylargevalues

forresistorR1willcauseanoutputvoltageerrorduetothe

50nA FB pin input current. The suggested value for the

output divider resistor (see Figure 2) from FB to ground

(R2) is 100k or less. A formula for R1 is shown below. A

table of standard 1% values is shown in Table 2 for

common output voltages.

Frequencyfoldbackisdonetocontrolpowerdissipationin

both the IC and in the external diode and inductor during

short-circuit conditions. A shorted output requires the

switching regulator to operate at very low duty cycles. As

a result the average current through the diode and induc-

tor is equal to the short-circuit current limit of the switch

(typically 2.4A for the LT1976). Minimum switch on time

limitations would prevent the switcher from attaining a

sufficiently low duty cycle if switching frequency were

maintained at 200kHz, so frequency is reduced by about

4:1 when the FB pin voltage drops below 0.4V (see

Frequency Foldback graph). In addition, if the current in

the switch exceeds 1.5 times the current limitations speci-

fied by the V_Cpin, due to minimum switch on time, the

LT1976 will skip the next switch cycle. As the feedback

voltagerises,theswitchingfrequencyincreasesto200kHz

with 0.95V on the FB pin. During frequency foldback,

external syncronization is disabled to prevent interference

with foldback operation. Frequency foldback does not

affect operation during normal load conditions.

V_OUT– 1.25

R1= R2 •

1.25 +R2 • 50nA

ForLT1976Baplications,thesuggestedvalueforR2is10k

or less, eliminating output voltage errors due to feedback

pin current and reducing noise susceptibility.

In addition to lowering switching frequency the soft-start

ramp rate is also affected by the feedback voltage. Large

V

OUT

LT1976

SW

2

9

C1

C

SS

SOFT-START

Table 2

OUTPUT

VOLTAGE

(V)

R1

NEAREST (1%)

(kΩ)

OUTPUT

ERROR

(%)

R2

(kΩ, 1%)

200kHz

OSCILLATOR

FOLDBACK

DETECT

R1

2.5

3

100

140

165

300

383

536

698

866

0

FB

12

11

–

+

ERROR

AMP

3.3

5

0.38

0

R2

1.25V

6

0.63

–0.63

–0.25

0.63

V

C

8

10

12

1976 F02

Figure 2. Feedback Network

1976bfg

12

LT1976/LT1976B

W U U

APPLICATIO S I FOR ATIO

U

capacitive loads or high input voltages can cause a high

input current surge during start-up. The soft-start func-

tion reduces input current surge by regulating switch

current via the V_Cpin to maintain a constant voltage ramp

rate(dV/dt)attheoutput. Acapacitor(C1inFigure2)from

the C_SSpin to the output determines the maximum output

dV/dt. Whenthefeedbackvoltageisbelow0.4V, theV_Cpin

will rise, resulting in an increase in switch current and

outputvoltage.IfthedV/dtoftheoutputcausesthecurrent

through the C_SScapacitor to exceed I_CSSthe V_Cvoltage is

reduced resulting in a constant dV/dt at the output. As the

feedback voltage increases I_CSSincreases, resulting in an

increased dV/dt until the soft-start function is defeated

with 0.9V present at the FB pin. The soft-start function

does not affect operation during normal load conditions.

However, if a momentary short (brown out condition) is

present at the output which causes the FB voltage to drop

below 0.9V, the soft-start circuitry will become active.

the parasitic inductance of the leads. This energy will

causetheinputvoltagetoswingabovetheDClevelofinput

power source and it may exceed the maximum voltage

rating of the input capacitor and LT1976. All input voltage

transient sequences should be observed at the V_INpin of

the LT1976 to ensure that absolute maximum voltage

ratings are not violated.

The easiest way to suppress input voltage transients is to

addasmallaluminumelectrolyticcapacitorinparallelwith

the low ESR input capacitor. The selected capacitor needs

to have the right amount of ESR to critically damp the

resonant circuit formed by the input lead inductance and

theinputcapacitor. ThetypicalvaluesofESRwillfallinthe

range of 0.5Ω to 2Ω and capacitance will fall in the range

of 5μF to 50μF.

If tantalum capacitors are used, values in the 22μF to

470μF range are generally needed to minimize ESR and

meet ripple current and surge ratings. Care should be

taken to ensure the ripple and surge ratings are not

exceeded. The AVX TPS and Kemet T495 series are surge

rated AVX recommends derating capacitor operating volt-

age by 2:1 for high surge applications.

INPUT CAPACITOR

Step-down regulators draw current from the input supply

in pulses. The rise and fall times of these pulses are very

fast. The input capacitor is required to reduce the voltage

ripple this causes at the input of LT1976 and force the

switching current into a tight local loop, thereby minimiz-

ing EMI. The RMS ripple current can be calculated from:

OUTPUT CAPACITOR

The output capacitor is normally chosen by its effective

series resistance (ESR) because this is what determines

output ripple voltage. To get low ESR takes volume, so

physically smaller capacitors have higher ESR. The ESR

range for typical LT1976 applications is 0.05Ω to 0.2Ω. A

typical output capacitor is an AVX type TPS, 100μF at 10V,

with a guaranteed ESR less than 0.1Ω. This is a “D” size

surface mount solid tantalum capacitor. TPS capacitors

are specially constructed and tested for low ESR, so they

give the lowest ESR for a given volume. The value in

microfarads is not particularly critical and values from

22μF to greater than 500μF work well, but you cannot

cheat Mother Nature on ESR. If you find a tiny 22μF solid

tantalum capacitor, it will have high ESR and output ripple

voltage could be unacceptable. Table 3 shows some

typical solid tantalum surface mount capacitors.

I_OUT

V

IN

I_RIPPLE(RMS)

=

V_OUTV – V

IN OUT

(

)

Ceramiccapacitorsareidealforinputbypassing.At200kHz

switching frequency input capacitor values in the range of

4.7μF to 20μF are suitable for most applications. If opera-

tionisrequiredclosetotheminimuminputrequiredbythe

LT1976 a larger value may be required. This is to prevent

excessive ripple causing dips below the minimum operat-

ing voltage resulting in erratic operation.

Input voltage transients caused by input voltage steps or

by hot plugging the LT1976 to a pre-powered source such

as a wall adapter can exceed maximum V_INratings. The

sudden application of input voltage will cause a large

surge of current in the input leads that will store energy in

1976bfg

13

LT1976/LT1976B

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APPLICATIO S I FOR ATIO

Table 3. Surface Mount Solid Tantalum Capacitor ESR

and Ripple Current

filter capacitor C_Fin parallel with the R_C/C_Cnetwork, along

with a small feedforward capacitor C_FB, is suggested to

control possible ripple at the V_Cpin. The LT1976 can be

stabilized using a 47μF ceramic output capacitor and V_C

componentvaluesofC_C=0.047μF, R_C=12.5k, C_F=100pF

and C_FB= 27pF.

E CASE SIZE

AVX TPS

ESR MAX (Ω)

RIPPLE CURRENT (A)

0.1 to 0.3

0.7 to 1.1

D CASE SIZE

AVX TPS

0.1 to 0.3

0.2

0.7 to 1.1

0.5

C CASE SIZE

AVX TPS

OUTPUT RIPPLE VOLTAGE

Figure 3 shows a typical output ripple voltage waveform

for the LT1976. Ripple voltage is determined by the

impedance of the output capacitor and ripple current

through the inductor. Peak-to-peak ripple current through

the inductor into the output capacitor is:

Many engineers have heard that solid tantalum capacitors

are prone to failure if they undergo high surge currents.

This is historically true and type TPS capacitors are

specially tested for surge capability but surge ruggedness

is not a critical issue with the output capacitor. Solid

tantalum capacitors fail during very high turn-on surges

which do not occur at the output of regulators. High

discharge surges, such as when the regulator output is

dead shorted, do not harm the capacitors.

V_OUTV – V

(

)

IN

OUT

I_P-P

=

V

L f

(

_IN

)( )( )

For high frequency switchers the ripple current slew rate

is also relevant and can be calculated from:

Unlike the input capacitor RMS, ripple current in the

output capacitor is normally low enough that ripple cur-

rent rating is not an issue. The current waveform is

triangular with a typical value of 200mA_RMS. The formula

to calculate this is:

di

dt

V

IN

L

=

Peak-to-peak output ripple voltage is the sum of a triwave

created by peak-to-peak ripple current times ESR and a

square wave created by parasitic inductance (ESL) and

ripple current slew rate. Capacitive reactance is assumed

to be small compared to ESR or ESL.

Output capacitor ripple current (RMS)

0.29 V

_OUT)(

V – V

IN OUT

(

)

=

I_P-P

12

I_RIPPLE(RMS)

=

L f V

( )( )(

)

IN

CERAMIC CAPACITORS

di

dt

V_RIPPLE= I

ESR + ESL

(

_P-P)(

) (

)

Higher value, lower cost ceramic capacitors are now

becoming available. They are generally chosen for their

good high frequency operation, small size and very low

ESR(effectiveseriesresistance).LowESRreducesoutput

ripple voltage but also removes a useful zero in the loop

frequency response, common to tantalum capacitors. To

compensate for this a resistor R_Ccan be placed in series

with the V_Ccompensation capacitor C_C(Figure 10). Care

must be taken however since this resistor sets the high

frequency gain of the error amplifier including the gain at

the switching frequency. If the gain of the error amplifier

is high enough at the switching frequency output ripple

voltage (although smaller for a ceramic output capacitor)

may still affect the proper operation of the regulator. A

V_OUT

20mV/DIV

47μF TANTALUM

ESR 100mΩ

V_OUT

20mV/DIV

47μF CERAMIC

V_SW

5V/DIV

V

_IN= 12V

V_OUT= 3.3V

_LOAD= 1A

L = 33μH

1μs/DIV

1976 F03

I

Figure 3. LT1976 Ripple Voltage Waveform

1976bfg

14

LT1976/LT1976B

W U U

APPLICATIO S I FOR ATIO

U

Example: with V_IN= 12V, V_OUT= 3.3V, L = 33μH, ESR =

For V_OUT= 5V, V_IN= 8V and L = 20μH:

0.08Ω, ESL = 10nH:

5 8 – 5

( )(

)

I_OUT(MAX)= 1.5 –

3.3 12 – 3.3

(

)(

)

2 20e – 6 200e3 8

)( )( )

(

I_P-P

di

=

= 0.362A

12 33e − 6 200e3

( )(

)(

)

= 1.5 – 0.24 = 1.26A

12

=

= 3.63e5

Note that there is less load current available at the higher

inputvoltagebecauseinductorripplecurrentincreases.At

V_IN= 15V, duty cycle is 33% and for the same set of

conditions:

dt 3.3e – 5

V_RIPPLE= (0.362A)(0.08) + (10e – 9)(363e3)

= 0.0289 + 0.003 = 32mV_P-P

5 15 – 5

( )(

)

I_OUT(MAX)= 1.5 –

MAXIMUM OUTPUT LOAD CURRENT

2 20e – 6 200e3 15

)( )( )

(

Maximum load current for a buck converter is limited by

the maximum switch current rating (I_PK). The current

rating for the LT1976 is 1.5A. Unlike most current mode

converters, the LT1976 maximum switch current limit

does not fall off at high duty cycles. Most current mode

converters suffer a drop off of peak switch current for duty

cycles above 50%. This is due to the effects of slope

compensation required to prevent subharmonic oscilla-

tions in current mode converters. (For detailed analysis,

see Application Note 19.)

= 1.5 – 0.42 = 1.08A

To calculate actual peak switch current in continuous

mode with a given set of conditions, use:

V_OUTV – V_OUT

(

IN

)

I_SW(PK)= I_OUT

+

2 L f V

( )( )( ^IN

)

If a small inductor is chosen which results in discontinous

mode operation over the entire load range, the maximum

load current is equal to:

The LT1976 is able to maintain peak switch current limit

over the full duty cycle range by using patented circuitry to

cancel the effects of slope compensation on peak switch

current without affecting the frequency compensation it

provides.

I_PK²2 f L V

( )( )(

)

IN

I_OUT(MAX)

=

2 V

( _OUT)(

V – V

IN OUT

)

Maximum load current would be equal to maximum

switch current for an infinitely large inductor, but with

finite inductor size, maximum load current is reduced by

one-half peak-to-peak inductor current. The following

formula assumes continuous mode operation, implying

CHOOSING THE INDUCTOR

For most applications the output inductor will fall in the

range of 15μH to 100μH. Lower values are chosen to

reduce physical size of the inductor. Higher values allow

more output current because they reduce peak current

seen by the LT1976 switch, which has a 1.5A limit. Higher

values also reduce output ripple voltage and reduce core

loss.

that the term on the right (I_P-P/2) is less than I_OUT

.

V

V – V

IN OUT

(

_OUT)(

)

= I_PK–

I_P-P

2

I_OUT(MAX)= I_PK

–

2 L f V

( )( )(

)

IN

When choosing an inductor you might have to consider

maximum load current, core and copper losses, allow-

able component height, output voltage ripple, EMI, fault

current in the inductor, saturation and of course cost.

The following procedure is suggested as a way of han-

dling these somewhat complicated and conflicting

Discontinuous operation occurs when:

V_OUTV – V

(

)

IN

OUT

I_OUT(DIS)

≤

2(L)(f)(V )

IN

requirements.

1976bfg

15

LT1976/LT1976B

W U U

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APPLICATIO S I FOR ATIO

1. Choose a value in microhenries from the graph of

maximum load current. Choosing a small inductor with

lighter loads may result in discontinuous mode of

operation, but the LT1976 is designed to work well in

either mode.

Assume that the average inductor current is equal to

load current and decide whether or not the inductor

must withstand continuous fault conditions. If maxi-

mum load current is 0.5A, for instance, a 0.5A inductor

may not survive a continuous 2A overload condition.

For applications with a duty cycle above 50%, the

inductor value should be chosen to obtain an inductor

ripple current of less than 40% of the peak switch

current.

Table 4. Inductor Selection Criteria

VENDOR/

PART NUMBER

VALUE (μH)

I

(A) DCR (Ω) HEIGHT (mm)

RMS

Coiltronics

2. Calculate peak inductor current at full load current to

ensure that the inductor will not saturate. Peak current

canbesignificantlyhigherthanoutputcurrent,especially

with smaller inductors and lighter loads, so don’t omit

thisstep.Powderedironcoresareforgivingbecausethey

saturate softly, whereas ferrite cores saturate abruptly.

Other core materials fall somewhere in between. The

following formula assumes continuous mode of opera-

tion, but it errs only slightly on the high side for discon-

tinuous mode, so it can be used for all conditions.

UP2B-150

15

33

2.4

1.7

1.4

1.2

0.95

3.9

2.4

1.9

1.6

1.4

0.041

0.062

0.139

0.179

0.271

0.032

0.069

0.101

0.156

0.205

6

UP2B-330

UP2B-470

47

6

UP2B-680

68

6

UP2B-101

100

15

6

UP3B-150

6.8

UP3B-330

33

UP3B-470

47

UP3B-680

68

UP3B-101

100

Sumida

V_OUTV – V

(

)

IN

OUT

I_PEAK= I_OUT

+

CDRH8D28-150M

CDRH124-150M

CDRH127-150M

CDRH8D28-330M

CDRH124-330M

CDRH127-330M

CDRH8D28-470M

CDRH125-470M

CDRH127-470M

CDRH124-680M

CDRH127-680M

CDRH124-101M

CDRH127-101M

Coilcraft

15

33

47

68

100

2.2

3.2

4.5

1.4

2.7

3.0

1.25

1.8

2.5

1.5

2.1

1.2

1.7

0.053

0.05

3

4.5

8

2 f L V

( )( )(

)

IN

0.02

V_IN= maximum input voltage

0.122

0.97

3

f = switching frequency, 200kHz

4.5

8

3. Decide if the design can tolerate an “open” core geom-

etry like a rod or barrel, which have high magnetic field

radiation, or whether it needs a closed core like a toroid

to prevent EMI problems. This is a tough decision

because the rods or barrels are temptingly cheap and

small and there are no helpful guidelines to calculate

when the magnetic field radiation will be a problem.

0.048

0.150

0.058

0.076

0.228

0.1

3

6

8

4.5

8

0.30

4.5

8

4. After making an initial choice, consider the secondary

things like output voltage ripple, second sourcing, etc.

Use the experts in the Linear Technology’s applications

department if you feel uncertain about the final choice.

They have experience with a wide range of inductor

types and can tell you about the latest developments in

low profile, surface mounting, etc.

0.17

DT3308P-153

DT3308P-333

DT3308P-473

15

33

47

2.0

1.4

1

0.1

0.3

3

0.47

1976bfg

16

LT1976/LT1976B

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APPLICATIO S I FOR ATIO

U

Short-Circuit Considerations

The solution to this dilemma is to slow down the oscillator

to allow the current in the inductor to drop to a sufficiently

low value such that the current doesn’t continue to ratchet

higher. When the FB pin voltage is abnormally low thereby

indicating some sort of short-circuit condition, the oscil-

lator frequency will be reduced. Oscillator frequency is

reduced by a factor of 4 when the FB pin voltage is below

0.4V and increases linearly to its typical value of 200kHz at

aFBvoltageof0.95V(seeTypicalPerformanceCharacter-

istics). In addition, if the current in the switch exceeds 1.5

• I_PKcurrent demanded by the V_Cpin, the LT1976 will skip

the next on cycle effectively reducing the oscillator fre-

quency by a factor of 2. These oscillator frequency reduc-

tions during short-circuit conditions allow the LT1976 to

maintain current control.

The LT1976 is a current mode controller. It uses the V_C

node voltage as an input to a current comparator which

turns off the output switch on a cycle-by-cycle basis as

this peak current is reached. The internal clamp on the V_C

node, nominally 2.2V, then acts as an output switch peak

current limit. This action becomes the switch current limit

specification. The maximum available output power is

then determined by the switch current limit.

Apotentialcontrollabilityprod}mcouldoccurundershort-

circuit conditions. If the power supply output is short

circuited, the feedback amplifier responds to the low

output voltage by raising the control voltage, V_C, to its

peak current limit value. Ideally, the output switch would

be turned on, and then turned off as its current exceeded

thevalueindicatedbyV_C.However,thereisfiniteresponse

time involved in both the current comparator and turn-off

of the output switch. These result in a minimum on time

t_ON(MIN).When combined with the large ratio of V_INto

(V_F+ I • R), the diode forward voltage plus inductor I • R

voltage drop, the potential exists for a loss of control.

Expressed mathematically the requirement to maintain

control is:

SOFT-START

For applications where [V_IN/(V_OUT+ V_F)] ratios > 10 or

large input surge currents can’t be tolerated, the LT1976

soft-start feature should be used to control the output

capacitor charge rate during start-up, or during recovery

from an output short circuit thereby adding additional

control over peak inductor current. The soft-start function

limits the switch current via the V_Cpin to maintain a

constantvoltage ramp rate (dV/dt)atthe outputcapacitor.

A capacitor (C1 in Figure 2) from the C_SSpin to the

regulated output voltage determines the output voltage

ramp rate. When the current through the C_SScapacitor

exceeds the C_SSthreshold (I_CSS), the voltage ramp of the

output capacitor is limited by reducing the V_Cpin voltage.

The C_SSthreshold is proportional to the FB voltage (see

Typical Performance Characteristics) and is defeated for

FB voltages greater than 0.9V (typical). The output dV/dt

can be approximated by:

V +I•R

F

f • t_ON

≤

V

IN

where:

f = switching frequency

t_ON= switch on time

V_F= diode forward voltage

V_IN= Input voltage

I • R = inductor I • R voltage drop

If this condition is not observed, the current will not be

limited at I_PKbut will cycle-by-cycle ratchet up to some

higher value. Using the nominal LT1976 clock frequency

of 200kHz, a V_INof 40V and a (V_F+ I • R) of say 0.7V, the

maximum t_ONto maintain control would be approximately

90ns, an unacceptably short time.

dV I_CSS

=

dt C_SS

but actual values will vary due to start-up load conditions,

compensation values and output capacitor selection.

1976bfg

17

LT1976/LT1976B

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APPLICATIO S I FOR ATIO

Example: For V_OUT= 3.3V, V_IN= 12V

C

_SS= GND

V_OUT

0.5V/DIV

125μA + 12.5μA + 0.5μA

3.3

12

(

)

⎛

⎞

C

_SS= 0.1μF

C_SS= 0.1μF

I

= 45μA + 5μA +

⎜

⎝

⎟

⎠

IN(AVG)

0.8

(

)

= 45μA + 5μA + 47μA = 97μA

During the sleep portion of the Burst Mode cycle, the V_C

pin voltage is held just below the level needed for normal

operation to improve transient response. See the Typical

Performance Characteristics section for burst and tran-

sient response waveforms.

C_OUT= 47μF

I_LOAD= 200mA

V_IN= 12V

TIME (1ms/DIV)

1976 F04

Figure 4. V_OUTdV/dt

Ifanoloadconditioncanbeanticipated,thesupplycurrent

can be further reduced by cycling the SHDN pin at a rate

higher than the natural no load burst frequency. Figure 6

shows Burst Mode operation with the SHDN pin. V_OUT

burstrippleismaintainedwhiletheaveragesupplycurrent

Burst Mode OPERATION (LT1976 ONLY)

To enhance efficiency at light loads, the LT1976 automati-

cally switches to Burst Mode operation which keeps the

output capacitor charged to the proper voltage while mini-

mizing the input quiescent current. During Burst Mode

operation, the LT1976 delivers short bursts of current to

the output capacitor followed by sleep periods where the

output power is delivered to the load by the output capaci-

tor. In addition, V_INand BIAS quiescent currents are re-

duced to typically 45μA and 125μA respectively during the

sleep time. As the load current decreases towards a no

load condition, the percentage of time that the LT1976

operates in sleep mode increases and the average input

current is greatly reduced resulting in higher efficiency.

150

V

= 3.3V

= 25°C

OUT

A

T

125

100

75

50

25

0

10

30

40

50

60

20

The minimum average input current depends on the V_INto

V_OUTratio, V_Cfrequency compensation, feedback divider

network and Schottky diode leakage. It can be approxi-

mated by the following equation:

INPUT VOLTAGE (V)

1976 F05

Figure 5. I_Qvs V_IN

I

_BIASS+I_FB+I_S

⎛ V_OUT

⎞

⎟

(

)

V_OUT

50mV/DIV

I

_IN(AVG)≅ I_VINS+I_SHDN+

⎜

⎝ V ⎠

η

( )

IN

where

I_VINS= input pin current in sleep mode

V_OUT= output voltage

V_SHDN

2V/DIV

V_IN= input voltage

I_BIASS= BIAS pin current in sleep mode

I_FB= feedback network current

I_S= catch diode reverse leakage at V_OUT

I_SW

500mA/DIV

V

_IN= 12V

TIME (50ms/DIV)

1976 G16

V_OUT= 3.3V

I_Q= 15μA

Figure 6. Burst Mode with Shutdown Pin

η = low current efficiency (non Burst Mode operation)

1976bfg

18

LT1976/LT1976B

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APPLICATIO S I FOR ATIO

U

drops to 15μA. The PG pin will be active low during the

“on” portion of the SHDN waveform due to the C_Tcapaci-

tor discharge when SHDN is taken low. See the Power

Good section for further information.

The effect of reverse leakage and forward drop on effi-

ciency for various Schottky diodes is shown in Table 4. As

can be seen these are conflicting parameters and the user

mustweightheimportanceofeachspecificationinchoos-

ing the best diode for the application.

CATCH DIODE

The use of so-called “ultrafast” recovery diodes is gener-

ally not recommended. When operating in continuous

mode, the reverse recovery time exhibited by “ultrafast”

diodes will result in a slingshot type effect. The power

internalswitchwillrampupV_INcurrentintothediodeinan

attempt to get it to recover. Then, when the diode has

finallyturnedoff,sometensofnanosecondslater,theV_SW

node voltage ramps up at an extremely high dV/dt, per-

haps 5V to even 10V/ns! With real world lead inductances

the V_SWnode can easily overshoot the V_INrail. This can

result in poor RFI behavior and, if the overshoot is severe

enough, damage the IC itself.

The catch diode carries load current during the SW off

time. The average diode current is therefore dependent on

theswitchdutycycle. Athighinputtooutputvoltageratios

the diode conducts most of the time. As the ratio ap-

proaches unity the diode conducts only a small fraction of

the time. The most stressful condition for the diode is

whentheoutputisshortcircuited.Underthisconditionthe

diode must safely handle I_PEAKat maximum duty cycle.

To maximize high and low load current efficiency a fast

switching diode with low forward drop and low reverse

leakage should be used. Low reverse leakage is critical to

maximize low current efficiency since its value over tem-

perature can potentially exceed the magnitude of the

LT1976 supply current. Low forward drop is critical for

high current efficiency since the loss is proportional to

forward drop.

BOOST PIN

For most applications the boost components are a 0.33μF

capacitor and a MMSD914 diode. The anode is typically

connected to the regulated output voltage to generate a

voltage approximately V_OUTabove V_INto drive the output

stage (Figure 7a). However, the output stage discharges

the boost capacitor during the on time of the switch. The

output driver requires at least 2.5V of headroom through-

out this period to keep the switch fully saturated. If the

output voltage is less than 3.3V it is recommended that an

alternate boost supply is used. The boost diode can be

connected to the input (Figure 7b) but care must be taken

to prevent the boost voltage (V_BOOST= V_IN• 2) from

exceeding the BOOST pin absolute maximum rating. The

additional voltage across the switch driver also increases

power loss and reduces efficiency. If available, an inde-

pendent supply can be used to generate the required

BOOST voltage (Figure 7c). Tying BOOST to V_INor an

independent supply may reduce efficiency but it will re-

duce the minimum V_INrequired to start-up with light

loads. If the generated BOOST voltage dissipates too

much power at maximum load, the BOOST voltage the

LT1976 sees can be reduced by placing a Zener diode in

series with the BOOST diode (Figure 7a option).

These requirements result in the use of a Schottky type

diode. DC switching losses are minimized due to its low

forward voltage drop and AC behavior is benign due to its

lackofasignificantreverserecoverytime.Schottkydiodes

are generally available with reverse voltage ratings of 60V

and even 100V and are price competitive with other types.

Table 5. Catch Diode Selection Criteria

I at 125°C EFFICIENCY

Q

V

LEAKAGE

= 3.3V

=12V

V

=12V

IN

V

V AT 1A

F

V

= 3.3 V = 3.3V

OUT

DIODE

25°C 125°C 25°C 125°C

I = 0A

L

I = 1A

L

IR 10BQ100 0.0μA 59μA 0.72V 0.58V

125μA

215μA

74.1%

82.8%

Diodes Inc. 0.1μA 242μA 0.48V 0.41V

B260SMA

Diodes Inc. 0.2μA 440μA 0.45V 0.36V

B360SMB

270μA

821μA

1088μA

83.6%

83.7%

84.5%

IR

1μA 1.81mA 0.42V 0.34V

MBRS360TR

IR 30BQ100 1.7μA 2.64mA 0.40V 0.32V

1976bfg

19

LT1976/LT1976B

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APPLICATIO S I FOR ATIO

OPTIONAL

SHUTDOWN FUNCTION AND UNDERVOLTAGE

LOCKOUT

The SHDN pin on the LT1976 controls the operation of the

IC. When the voltage on the SHDN pin is below the 1.2V

shutdown threshold the LT1976 is placed in a “zero”

supply current state. Driving the SHDN pin above the

shutdown threshold enables normal operation. The SHDN

pin has an internal sink current of 3μA.

V

BOOST

SW

V

OUT

IN

LT1976

GND

V

– V = V

SW OUT

= V + V

IN OUT

BOOST

BOOST(MAX)

V

(7a)

In addition to the shutdown feature, the LT1976 has an

undervoltage lockout function. When the input voltage is

below 2.4V, switching will be disabled. The undervoltage

lockout threshold doesn’t have any hysteresis and is

mainly used to insure that all internal voltages are at the

correct level before switching is enabled. If an undervolt-

age lockout function with hysteresis is needed to limit

input current at low V_INto V_OUTratios refer to Figure 8 and

the following:

V

BOOST

SW

IN

LT1976

V

GND

OUT

V

– V = V

SW IN

BOOST

BOOST(MAX)

= 2V

IN

(7b)

V

BOOST

V

IN

DC

V

⎛

⎞

⎠

LT1976

SHDN

V_UVLO= R1

+

^SHDN+I_SHDN+ V

⎟

SHDN

⎜

GND

SW

OUT

⎝ R3

R2

D

SS

V_OUTR1

( )

1976 F07

V_HYST

=

V

– V = V

SW DC

BOOST

R3

V

= V + V

DC IN

BOOST(MAX)

(7c)

Figure 7. BOOST Pin Configurations

R1shouldbechosentominimizequiescentcurrentduring

normal operation by the following equation:

V – 2V

IN

A 0.33μF boost capacitor is recommended for most appli-

cations. Almost any type of film or ceramic capacitor is

suitablebuttheESRshouldbe<1Ωtoensureitcanbefully

recharged during the off time of the switch. The capacitor

value is derived from worst-case conditions of 4700ns on

time, 42mA boost current and 0.7V discharge ripple. The

boost capacitor value could be reduced under less de-

mandingconditionsbutthiswillnotimprovecircuitopera-

tion or efficiency. Under low input voltage and low load

conditions a higher value capacitor and Schottky boost

diode will reduce discharge ripple and improve start-up

and dropout operation.

R1=

1.5 I

(

)

(

)

SHDN(MAX)

Example:

12 – 2

1.5 5μA

R1=

= 1.3MΩ

(

)

5 1.3MΩ

(

)

= 6.5MΩ (Nearest 1% 6.49MΩ)

R3 =

1

1.3

R2 =

7 – 1.3

1.3MΩ

1.3

– 1μA –

6.49MΩ

= 408k (Nearest 1% 412k)

1976bfg

20

LT1976/LT1976B

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APPLICATIO S I FOR ATIO

U

LT1976

V

IN

4

+

–

V

IN

COMP

2.4V

1.3V

ENABLE

R1

R2

R3

SHDN

V

OUT

15

+

–

SHDN

COMP

3μA

1976 F08

Figure 8. Undervoltage Lockout

See the Typical Performance Characteristics section for

graphs of SHDN and V_INcurrents verses input voltage.

If the synchronization signal is present during Burst Mode

operation, synchronization will occur during the burst

portionoftheoutputwaveform.SynchronizingtheLT1976

during Burst Mode operation may alter the natural burst

frequency which can lead to jitter and increased ripple in

the burst waveform. Synchronizing the LT1976B during

pulse skip operation may also increase output ripple.

SYNCHRONIZING

Oscillatorsynchronizationtoanexternalinputisachieved

by connecting a TTL logic-compatible square wave with a

duty cycle between 20% and 80% to the LT1976 SYNC

pin. The synchronizing range is equal to initial operating

frequency up to 700kHz. This means that minimum

practical sync frequency is equal to the worst-case high

self-oscillating frequency (230kHz), not the typical oper-

ating frequency of 200kHz. Caution should be used when

synchronizing above 230kHz because at higher sync

frequencies the amplitude of the internal slope compen-

sation used to prevent subharmonic switching is re-

duced. Thistypeofsubharmonicswitchingonlyoccursat

input voltages less than twice output voltage. Higher

inductor values will tend to eliminate this problem. See

Frequency Compensation section for a discussion of an

entirely different cause of subharmonic switching before

assuming that the cause is insufficient slope compensa-

tion. Application Note 19 has more details on the theory

of slope compensation.

If no synchronization is required this pin should be con-

nected to ground.

POWER GOOD

The LT1976 contains a power good block which consists

ofacomparator, delaytimerandactivelowflagthatallows

the user to generate a delayed signal after the power good

threshold is exceeded.

Referring to Figure 2, the PGFB pin is the positive input to

a comparator whose negative input is set at V_PGFB. When

PGFB is taken above V_PGFB, current (I_CSS) is sourced into

the C_Tpin starting the delay period. When the voltage on

the PGFB pin drops below V_PGFBthe C_Tpin is rapidly

discharged resetting the delay period. The PGFB voltage is

typically generated by a resistive divider from the regu-

lated output or input supply.

If the FB pin voltage is below 0.9V (power-up or output

short-circuit conditions) the sync function is disabled.

This allows the frequency foldback to operate to avoid and

hazardous conditions for the SW pin.

The capacitor on the C_Tpin determines the amount of

delay time between the PGFB pin exceeding its threshold

(V_PGFB) and the PG pin set to a high impedance state.

When the PGFB pin rises above V_PGFBcurrent is sourced

1976bfg

21

LT1976/LT1976B

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APPLICATIO S I FOR ATIO

(I_CT) from the C_Tpin into the external capacitor. When the

voltageontheexternalcapacitorreachesaninternalclamp

(V_CT), the PG pin becomes a high impedance node. The

resultant PG delay time is given by t = C_CT• (V_CT)/(I_CT). If

thevoltageonthePGFBpindropsbelowitsV_PGFB, C_CTwill

be discharged rapidly and PG will be active low with a

200μA sink capability. If the SHDN pin is taken below its

threshold during normal operation, the C_Tpin will be

dischargedandPGinactive,resultinginanonPowerGood

cycle when SHDN is taken above its threshold. Figure 9

shows the power good operation with PGFB connected to

FB and the capacitance on C_T= 0.1μF. The PGOOD pin has

a limited amount of drive capability and is susceptible to

noise during start-up and Burst Mode operation. If erratic

operation occurs during these conditions a small filter

capacitor from the PGOOD pin to ground will ensure

proper operation. Figure 10 shows several different con-

figurations for the LT1976 Power Good circuitry.

V_OUT

500mV/DIV

PG

100k TO V_IN

V_CT

500mV/DIV

V_SHDN

2V/DIV

TIME (10ms/DIV)

1976 F09

Figure 9. Power Good

PG at 80% V

with 100ms Delay

PG at V > 4V with 100ms Delay

IN

OUT

V

IN

V

IN

200k

PG

LT1976

PG

LT1976

V

= 3.3V

OUT

511k

200k

C

153k

12k

OUT

PGFB

V

= 3.3V

OUT

165k

100k

C

OUT

FB

100k

C

T

0.27μF

V

Disconnect at 80% V

with 100ms Delay

V Disconnect 3.3V Logic Signal

OUT

with 100μs Delay

V

IN

PG

LT1976

PGFB

IN

PG

LT1976

200k

V

= 3.3V

V

= 12V

OUT

153k

12k

C

OUT

PGFB

866k

100k

FB

100k

C

T

0.27μF

270pF

1976 F10

Figure 10. Power Good Circuits

1976bfg

22

LT1976/LT1976B

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U

LAYOUT CONSIDERATIONS

LT1976 switch. When operating at higher currents and

input voltages, with poor layout, this spike can generate

voltages across the LT1976 that may exceed its absolute

maximum rating. A ground plane should always be used

under the switcher circuitry to prevent interplane coupling

and overall noise.

As with all high frequency switchers, when considering

layout, care must be taken in order to achieve optimal

electrical, thermal and noise performance. For maximum

efficiency switch rise and fall times are typically in the

nanosecond range. To prevent noise both radiated and

conducted the high speed switching current path, shown

in Figure 11, must be kept as short as possible. This is

implemented in the suggested layout of Figure 12. Short-

ening this path will also reduce the parasitic trace induc-

tance of approximately 25nH/inch. At switch off, this

parasitic inductance produces a flyback spike across the

The V_Cand FB components should be kept as far away as

possible from the switch and boost nodes. The LT1976

pinout has been designed to aid in this. The ground for

these components should be separated from the switch

current path. Failure to do so will result in poor stability or

subharmonic like oscillation.

LT1976

L1

V

OUT

V

4

2

SW

IN

V

IN

+

HIGH

C2

FREQUENCY

CIRCULATION

PATH

D1

C1 LOAD

1976 F11

Figure 11. High Speed Switching Path

C2

D2

CONNECT PIN 8 GND TO THE

PIN 17 EXPOSED PAD GND

V

OUT

L1

C1

PLACE VIA's UNDER EXPOSED

PAD TO A BOTTOM PLANE TO

ENHANCE THERMAL

KELVIN SENSE

FEEDBACK

TRACE AND

D1

CONDUCTIVITY

KEEP SEPARATE

FROM BIAS TRACE

MINIMIZE

D1-C3

GND

1

2

3

4

5

6

7

8

NC

SW

NC

PG 16

SHDN 15

SYNC 14

PGFB 13

FB 12

LOOP

R3

LT1976

C3

V

R1

R2

C2

IN

V

IN

NC

BOOST

V

11

C

BIAS 10

T

C4

C5

GND

C

9

SS

GND

1976 F12

Figure 12. Suggested Layout

1976bfg

23

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APPLICATIO S I FOR ATIO

Board layout also has a significant effect on thermal

resistance. Pin 8 and the exposed die pad, Pin 17, are a

continuous copper plate that runs under the LT1976 die.

This is the best thermal path for heat out of the package.

Reducing the thermal resistance from Pin 8 and exposed

pad onto the board will reduce die temperature and in-

creasethepowercapabilityoftheLT1976.Thisisachieved

by providing as much copper area as possible around the

exposed pad. Adding multiple solder filled feedthroughs

under and around this pad to an internal ground plane will

also help. Similar treatment to the catch diode and coil

terminations will reduce any additional heating effects.

Example: with V_IN= 40V, V_OUT= 5V and I_OUT= 1A:

0.3 1 ²5

(

)( ) ( )

P_SW

=

+ 97e – 9 1/2 1 40 200e3

(

)

(

)

( )( )(

)

40

0.04 + 0.388 = 0.43W

2

5

( )

1/36

(

)

P

=

= 0.02W

BOOST

40

P = 40 0.0015 + 5 0.003 = 0.08W

(

)

(

)

Q

Total power dissipation is:

P

_TOT= 0.43 + 0.02 + 0.08 = 0.53W

THERMAL CALCULATIONS

Thermal resistance for the LT1976 package is influenced

by the presence of internal or backside planes. With a full

plane under the FE16 package, thermal resistance will be

about 45°C/W. No plane will increase resistance to about

150°C/W. To calculate die temperature, use the proper

thermal resistance number for the desired package and

add in worst-case ambient temperature:

Power dissipation in the LT1976 chip comes from four

sources: switch DC loss, switch AC loss, boost circuit

current,andinputquiescentcurrent.Thefollowingformu-

las show how to calculate each of these losses. These

formulas assume continuous mode operation, so they

should not be used for calculating efficiency at light load

currents.

T_J= T_A+ Q_JA(P_TOT

)

Switch loss:

With the FE16 package (Q_JA= 45°C/W) at an ambient

temperature of 70°C:

2

R_{SW OUT}

I

(

V

OUT

) (

)

P_SW

=

+ t_EFF1/2 I

V

f

T_J= 70 + 45(0.53) = 94°C

(

)

(

_OUT)( _IN)( )

V

IN

If a more accurate die temperature is required, a measure-

ment of the SYNC pin resistance to ground can be used.

The SYNC pin resistance can be measured by forcing a

voltagenogreaterthan0.25Vatthepinandmonitoringthe

pincurrentversustemperatureinacontrolledtemperature

environment. The measurement should be done with

minimal device power dissipation (pull the V_Cpin to

ground for sleep mode) in order to calibrate the SYNC pin

resistance with the ambient temperature.

Boost current loss:

2

V

(

I

/36

)

(

)

OUT

P

=

BOOST

V

IN

Quiescent current loss: (LT1976)

P_Q= V_IN(0.0015) + V_OUT(0.003)

R_SW= switch resistance (≈0.3 when hot )

t_EFF= effective switch current/voltage overlap time

(t_r+ t_f+ t_IR+ t_IF)

t_r= (V_IN/1.7)ns

t_f= (V_IN/1.2)ns

t_IR= t_IF= (I_OUT/0.05)ns

f = switch frequency

1976bfg

24

LT1976/LT1976B

W U U

APPLICATIO S I FOR ATIO

U

HIGH TEMPERATURE OPERATION

where:

Extreme care must be taken when designing LT1976

applications to operate at high ambient temperatures. The

LT1976H grade is designed to work at elevated tempera-

tures but erratic operation can occur due to external

components. Eachpassivecomponentshouldbechecked

for absolute value and voltage ratings to ensure loop

stability at temperature. Boost and Catch diode leakages,

as well as increased series resistance (Table 5), will

adversely affect efficiency and low quiescent current op-

eration. Junction temperature increase in the diodes due

to self heating (leakage) and power dissipation should be

measured to ensure their maximum temperature specifi-

cations are not violated.

V_IN= input voltage

V_OUT= output voltage

V_F= Schottky diode forward drop

f_OSC= switching frequency

A potential controllability problem arises if the LT1976 is

called upon to produce an on time shorter than it is able to

produce. Feedback loop action will lower then reduce the

V_Ccontrol voltage to the point where some sort of cycle-

skipping or Burst Mode behavior is exhibited.

In summary:

1. Be aware that the simultaneous requirements of high

V_IN, high I_OUTand high f_OSCmay not be achievable in

practice due to internal dissipation. The Thermal Con-

siderations section offers a basis to estimate internal

power.Inquestionablecasesaprototypesupplyshould

be built and exercised to verify acceptable operation.

Input Voltage vs Operating Frequency Considerations

TheabsolutemaximuminputsupplyvoltagefortheLT1976

is specified at 60V. This is based solely on internal semi-

conductor junction breakdown effects. Due to internal

power dissipation the actual maximum V_INachievable in a

particular application may be less than this.

2. The simultaneous requirements of high V_IN, low V_OUT

and high f_OSCcan result in an unacceptably short

minimum switch on time. Cycle-skipping and/or Burst

Mode behavior will result although correct output volt-

age is usually maintained.

A detailed theoretical basis for estimating internal power

loss is given in the section Thermal Considerations. Note

that AC switching loss is proportional to both operating

frequency and output current. The majority of AC switch-

ing loss is also proportional to the square of input voltage.

FREQUENCY COMPENSATION

For example, while the combination of V_IN= 40V, V_OUT

=

Before starting on the theoretical analysis of frequency

responsethefollowingshouldberemembered—theworse

the board layout, the more difficult the circuit will be to

stabilize. This is true of almost all high frequency analog

circuits. Read the Layout Considerations section first.

Common layout errors that appear as stability problems

aredistantplacementofinputdecouplingcapacitorand/or

catch diode and connecting the V_Ccompensation to a

ground track carrying significant switch current. In addi-

tionthetheoreticalanalysisconsidersonlyfirstordernon-

idealcomponentbehavior.Forthesereasons,itisimportant

that a final stability check is made with production layout

and components.

5V at 1A and f_OSC= 200kHz may be easily achievable,

simultaneously raising V_INto 60V and f_OSCto 700kHz is

not possible. Nevertheless, input voltage transients up to

60V can usually be accommodated, assuming the result-

ing increase in internal dissipation is of insufficient time

duration to raise die temperature significantly.

A second consideration is controllability. A potential limi-

tation occurs with a high step-down ratio of V_INto V_OUT

asthisrequiresacorrespondinglynarrowminimumswitch

on time. An approximate expression for this (assuming

continuous mode operation) is given as follows:

,

t_ON(MIN)= V_OUT+ V_F/V_IN(f_OSC

)

1976bfg

25

LT1976/LT1976B

W U U

U

APPLICATIO S I FOR ATIO

The LT1976 uses current mode control. This alleviates

many of the phase shift problems associated with the

inductor. The basic regulator loop is shown in Figure 12.

The LT1976 can be considered as two g_mblocks, the error

amplifier and the power stage.

Tantalum output capacitor zero is set by C_OUTand C_OUT

ESR

Output Capacitor Zero = 1/(2π • 100μF • 0.1) = 15.9kHz

The zero produced by the ESR of the tantalum output

capacitor is very useful in maintaining stability. If better

transient response is required, a zero can be added to the

loop using a resistor (R_C) in series with the compensation

capacitor. As the value of R_Cis increased, transient

response will generally improve but two effects limit its

value. First, the combination of output capacitor ESR and

a large R_Cmay stop loop gain rolling off altogether.

Second, if the loop gain is not rolled off sufficiently at the

switching frequency output ripple will perturb the V_Cpin

enough to cause unstable duty cycle switching similar to

subharmonic oscillation. This may not be apparent at the

output. Small-signal analysis will not show this since a

continuous time system is assumed. If needed, an addi-

tional capacitor (C_F) can be added to form a pole at

typically one-fifth the switching frequency (if R_C= 10k,

C_E= 1500pF, C_F= 330pF)

Figure13showstheoverallloopresponsewitha330pFV_C

capacitor and a typical 100μF tantalum output capacitor.

The response is set by the following terms:

Error amplifier: DC gain is set by g_mand R_O:

Ω

EA Gain = 650μ • 1.5M = 975

The pole set by C_Fand R_L:

EA Pole = 1/(2π • 1.5M • 330pF) = 322Hz

Unity gain frequency is set by C_Fand g_m:

EA Unity Gain Frequency = 650μF/(2π • 330pF)

= 313kHz

Powerstage: DC gain is set by g_mand R_L(assume 10Ω):

PS DC Gain = 3 • 10 = 30

When checking loop stability the circuit should be oper-

ated over the application’s full voltage, current and tem-

perature range. Any transient loads should be applied and

the output voltage monitored for a well-damped behavior.

Pole set by C_OUTand R_L:

PS Pole = 1/(2π • 100μF • 10) = 159Hz

Unity gain set by C_OUTand g_m:

PS Unity Gain Freq = 3/(2π • 100μF) = 4.7kHz.

LT1976

100

50

0

100

135

90

V

C

= 3.3V

OUT

F

CURRENT MODE

SW

= 100μF, 0.1Ω

OUTPUT

POWER STAGE

2

Ω

C = 330pF

g

m

= 3

R /C = NC

C

FB

L

R1

12

R2

Ω

I

= 330mA

LOAD

g

m

= 650μ

FB

–

+

V

C

ERROR

AMP

11

ESR

R

C

1.6M

C

1.26V

C

OUT

F

45

C

1976 F13

–50

0

1M

10

100

1k

10k

100k

Figure 13. Model for Loop Response

FREQUENCY (Hz)

1976 F14

Figure 14. Overall Loop Response

1976bfg

26

LT1976/LT1976B

U

TYPICAL APPLICATIO

V

3.3V

1A

LT1976B Efficiency and Power

OUT

V

IN

V

BOOST

IN

3.3V TO 60V

Loss vs Load Current

4.7μF

100V

CER

33μH

0.33μF

4148

SHDN

100

75

50

25

0

10

SW

LT1976B

0.1μF

EFFICIENCY

10MQ60N

C

V

C

SS

1

100pF

4700pF

8.06k

V

BIAS

FB

16.5k

1%

5V

100μF

6.3V

TANT

3.3V

C

T

PGFB

PG

0.1

0.01

0.001

1μF

SYNC

GND

10k

1%

TYPICAL

POWER LOSS

1976 TA03

14V to 3.3V Non Burst Mode Step-Down Converter

0.1

1

10

100

1000 10000

LOAD CURRENT (mA)

1976 G25

U

PACKAGE DESCRIPTIO

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation BC

4.90 – 5.10*

(.193 – .201)

3.58

(.141)

3.58

(.141)

16 1514 13 12 1110

9

6.60 0.10

4.50 0.10

2.94

(.116)

6.40

(.252)

BSC

SEE NOTE 4

2.94

(.116)

0.45 0.05

1.05 0.10

0.65 BSC

5

7

8

1

2

3

4

6

RECOMMENDED SOLDER PAD LAYOUT

1.10

(.0433)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

0.195 – 0.30

FE16 (BC) TSSOP 0204

(.0077 – .0118)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

MILLIMETERS

(INCHES)

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

1976bfg

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

27

LT1976/LT1976B

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

V : 7.3V to 45V/64V, V

LT1074/LT1074HV

4.4A (I ), 100kHz, High Efficiency Step-Down DC/DC Converters

: 2.21V, I : 8.5mA,

OUT(MIN) Q

OUT

IN

I

: 10μA, DD5/7, TO220-5/7

SD

LT1076/LT1076HV

LT1676

1.6A (I ), 100kHz, High Efficiency Step-Down DC/DC Converters

V : 7.3V to 45V/64V, V

: 2.21V, I : 8.5mA,

Q

OUT

IN

OUT(MIN)

I

: 10μA, DD5/7, TO220-5/7

SD

60V, 440mA (I ), 100kHz, High Efficiency Step-Down DC/DC

V : 7.4V to 60V, V

S8

: 1.24V, I : 3.2mA, I : 2.5μA,

OUT(MIN) Q SD

OUT

IN

Converter

LT1765

25V, 3A (I ), 1.25MHz, High Efficiency Step-Down DC/DC

Converter

V : 3V to 25V, V

SO-8, TSSOP16E

: 1.20V, I : 1mA, I : 15μA,

OUT(MIN) Q SD

OUT

IN

LT1766

60V, 1.2A (I ), 200kHz, High Efficiency Step-Down DC/DC

Converter

V : 5.5V to 60V, V

TSSOP16/E

: 1.20V, I : 2.5mA, I : 25μA,

OUT(MIN) Q SD

OUT

IN

LT1767

25V, 1.5A (I ), 1.25MHz, High Efficiency Step-Down DC/DC

Converter

V : 3V to 25V, V

MS8/E

: 1.20V, I : 1mA, I : 6μA,

OUT(MIN) Q SD

OUT

IN

LT1776

40V, 550mA (I ), 200kHz, High Efficiency Step-Down DC/DC

Converter

V : 7.4V to 40V, V

N8, S8

: 1.24V, I : 3.2mA, I : 30μA,

OUT(MIN) Q SD

OUT

IN

LTC^®1875

LT1940

1.5A (I ), 550kHz, Synchronous Step-Down DC/DC Converter

V : 2.7V to 6V, V

TSSOP16

: 0.8V, I : 15μA, I : <1μA,

OUT

IN

OUT(MIN) Q SD

Dual 1.2A (I ), 1.1MHz, High Efficiency Step-Down DC/DC

V : 3V to 25V, V

: 1.2V, I : 3.8mA, MS10

OUT

IN

OUT(MIN)

Q

Converter

LT1956

60V, 1.2A (I ), 500kHz, High Efficiency Step-Down DC/DC

Converter

V : 5.5V to 60V, V

TSSOP16/E

: 1.20V, I : 2.5mA, I : 25μA,

OUT

IN

OUT(MIN)

Q

SD

LT3010

80V, 50mA, Low Noise Linear Regulator

V : 1.5V to 80V, V

: 1.28V, I : 30μA, I : <1μA,

Q SD

IN

MS8E

LTC3407

LTC3412

LTC3414

LT3430

Dual 600mA (I ), 1.5MHz, High Efficiency Step-Down DC/DC

Converter

V : 2.5V to 5.5V, V

: 0.6V, I : 40μA MS10

OUT

IN

OUT(MIN)

Q

2.5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter

V : 2.5V to 5.5V, V

: 0.8V, I : 60μA, I : <1μA,

OUT

IN

Q

SD

TSSOP16E

4A (I ), 4MHz, Synchronous Step-Down DC/DC Converter

V : 2.25V to 5.5V, V

: 0.8V, I : 64μA, I : <1μA,

OUT(MIN) Q SD

OUT

IN

TSSOP20E

60V, 2.5A (I ), 200kHz, High Efficiency Step-Down DC/DC

V : 5.5V to 60V, V

TSSOP16E

: 1.20V, I : 2.5mA, I : 30μA,

OUT(MIN) Q SD

OUT

IN

Converter

LT3431

60V, 2.5A (I ), 500kHz, High Efficiency Step-Down DC/DC

Converter

V : 5.5V to 60V, V

TSSOP16E

: 1.20V, I : 2.5mA, I : 30μA,

OUT(MIN) Q SD

OUT

IN

LT3433

LT3434

60V, 400mA (I ), 200kHz, Buck-Boost DC/DC Converter

V : 5V to 60V, V : 3.3V to 20V, I : 100μA, TSSOP-16E

OUT

IN

OUT

Q

60V, 3A, 200kHz Step-Down Switching Regulator with 100μA

Quiescent Current

V : 3.3V to 60V, V

: 1.25V, I : 100μA, I : <1μA,

IN

OUT(MIN)

Q

SD

TSSOP-16E

LTC3727/LTC3727-1 36V, 500kHz, High Efficiency Step-Down DC/DC Controllers

V : 4V to 36V, V

QFN-32, SSOP-28

: 0.8V, I : 670μA, I : 20μA,

OUT(MIN) Q SD

IN

1976bfg

LT/CGRAFX 0407 REV G PRINTED IN USA

28 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT1976B
厂家：	Linear
描述：	High Voltage 1.5A, 200kHz Step-Down Switching Regulator with 100μA Quiescent Current 高电压1.5A ， 200kHz的降压型开关稳压器具有100μA静态电流稳压器开关
文件：	总28页 (文件大小：302K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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