LT1995CDD_技术文档

LT1995

32MHz, 1000V/µs

Gain Selectable Amplifier

U

FEATURES

DESCRIPTIO

■

Internal Gain Setting Resistors

The LT^®1995 is a high speed, high slew rate, gain select-

able amplifier with excellent DC performance. Gains from

–7to8withagainaccuracyof0.2%canbeachievedusing

no external components. The device is particularly well

suitedforuseasadifferenceamplifier, wheretheexcellent

resistor matching results in a typical common mode

rejection ratio of 79dB.

■

Pin Configurable as a Difference Amplifier,

Inverting and Noninverting Amplifier

Difference Amplifier:

■

Gain Range 1 to 7

CMRR > 65dB

■

Noninverting Amplifier:

Gain Range 1 to 8

The amplifier is a single gain stage design similar to the

LT1363 and features superb slewing and settling charac-

teristics. Input offset of the internal operational amplifier

is less than 2.5mV and the slew rate is 1000V/µs. The

output can drive a 150Ω load to ±2.5V on ±5V supplies,

making it useful in cable driver applications.

■

Inverting Amplifier:

Gain Range –1 to –7

■

Gain Error: <0.2%

■

Slew Rate: 1000V/µs

■

Bandwidth: 32MHz (Gain = 1)

■

Op Amp Input Offset Voltage: 2.5mV Max

■

The resistors have excellent matching, 0.2% maximum at

room temperature and 0.3% from –40°C to 85°C. The

temperature coefficient of the resistors is typically

–30ppm/°C. The resistors are extremely linear with volt-

age, resulting in a gain nonlinearity of 10ppm.

Quiescent Current: 9mA Max

Wide Supply Range: ±2.5V to ±15V

Available in 10-Lead MSOP and

10-Lead (3mm × 3mm) DFN Packages

U

The LT1995 is fully specified at ±2.5V, ±5V and ±15V sup-

plies and from –40°C to 85°C. The device is available in

space saving 10-lead MSOP and 10-Lead (3mm × 3mm)

DFN packages. For a micropower precision amplifier with

precision resistors, see the LT1991 and LT1996.

APPLICATIO S

■

Instrumentation Amplifier

■

Current Sense Amplifier

■

Video Difference Amplifier

Automatic Test Equipment

■

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

U

TYPICAL APPLICATIO

High Slew Rate Differential Gain of 1

Large-Signal Transient (G = 1)

M1 M2 M4

15V

OUT

1k

2k

4k

–

+

–

INPUT

RANGE

4k

2k

1k

–15V TO 15V

+

LT1995

4k

1995 TA01b

REF

P1 P2 P4

–15V

1995 TA01a

1995fb

1

LT1995

ABSOLUTE MAXIMUM RATINGS

W W

U W

(Note 1)

Total Supply Voltage (V⁺to V^–) .............................. 36V

Input Current (Note 2) ....................................... ±10mA

Output Short-Circuit Duration (Note 3)........... Indefinite

Operating Temperature Range (Note 4) .. – 40°C to 85°C

Specified Temperature Range (Note 5)... – 40°C to 85°C

Storage Temperature Range

MS Package .................................... –65°C to 150°C

DD Package ..................................... –65°C to 125°C

Maximum Junction Temperature

MS Package ..................................................... 150°C

DD Package ..................................................... 125°C

Lead Temperature (Soldering, 10 sec).................. 300°C

U

W U

PACKAGE/ORDER INFORMATION

ORDER PART

NUMBER

ORDER PART

NUMBER

TOP VIEW

P1

P2

1

2

3

4

5

10 M1

P1

P2

1

2

3

4

5

10 M1

9

8

7

6

M2

LT1995CDD

LT1995IDD

LT1995CMS

LT1995IMS

9

8

7

6

M2

M4

S

OUT

–

+

P4

–

M4

–

+

P4

+

–

+

V

S

V

S

V

S

V

REF

OUT

DD PART

MARKING*

MS PART

MARKING*

MS PACKAGE

10-LEAD PLASTIC MSOP

DD PACKAGE

10-LEAD (3mm × 3mm) PLASTIC DFN

T_JMAX= 150°C, θ_JA= 160°C/W (NOTE 6)

LBJF

LTBJD

T_JMAX= 125°C, θ_JA= 160°C/W (NOTE 6)

EXPOSED PAD INTERNALLY CONNECTED TO V_S

PCB CONNECTION OPTIONAL

–

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grades are identified by a label on the shipping container.

ELECTRICAL CHARACTERISTICS

Difference Amplifier Configuration. T = 25°C, V

= V = 0V and unused gain pins are unconnected, unless otherwise noted.

CM

A

REF

SYMBOL PARAMETER

CONDITIONS

V

MIN

TYP

MAX

UNITS

SUPPLY

GE

Gain Error

V

= ±12V, R = 1k, G = 1

±15V

±5V

0.05

0.2

0.25

0.2

%

OUT

L

= ±12V, R = 1k, G = 2

L

= ±12V, R = 1k, G = 4

L

= ±5V, R = 150Ω, G = 1

L

= ±2.5V, R = 500Ω, G = 1

L

= ±2.5V, R = 150Ω, G = 1

±5V

0.25

L

GNL

Gain Nonlinearity

V

= ±12V, R = 1k, G = 1

±15V

10

ppm

OUT

L

V

Input Offset Voltage

Referred to Input (Note 7)

G = 1 (MS10)

G = 1 (DD10)

G = 2 (MS10)

G = 2 (DD10)

G = 4 (MS10)

G = 4 (DD10)

G = 1 (MS10)

G = 1 (DD10)

G = 1 (MS10)

G = 1 (DD10)

±15V

±5V

1

5

9

4

6.8

3.75

5.6

5

9

5

9

mV

OS

1.5

0.7

1.2

0.6

0.9

1

1.4

1

1.3

±5V

±2.5V

1995fb

2

LT1995

ELECTRICAL CHARACTERISTICS

Difference Amplifier Configuration. T = 25°C, V

= V = 0V and unused gain pins are unconnected, unless otherwise noted.

CM

A

REF

SYMBOL PARAMETER

CONDITIONS

V

MIN

TYP

MAX

UNITS

SUPPLY

V

Op Amp Input Offset Voltage

(Note 10)

G = 1 (MS10)

G = 1 (DD10)

±2.5V, ±5V, ±15V

0.5

0.75

2.5

4.5

mV

OS_OA

e

n

Input Noise Voltage

G = 1, f = 10kHz

G = 2, f = 10kHz

G = 4, f = 10kHz

±2.5V to ±15V

27

18

14

nV/√Hz

R

Common Mode Input Resistance

Input Capacitance

V

CM

= ±15V, G = 1

±15V

4

kΩ

IN

C

IN

2.5

pF

Input Voltage Range

G = 1

±15V

±5V

±2.5V

±15

±5

±1

±15.5

±5.5

±1.5

V

CMRR

Common Mode Rejection Ratio

Referred to Input

G = 1, V = ±15V

±15V

±5V

65

71

75

65

61

79

84

87

73

68

dB

CM

G = 2, V = ±15V

CM

G = 4, V = ±15V

CM

G = 1, V = ±5V

CM

G = 1, V = ±1V

±2.5V

CM

PSRR

Power Supply Rejection Ratio

Output Voltage Swing

P1 = M1 = 0V, G = 1, V = ±2.5V to ±15V

78

87

dB

S

V

OUT

R = 1k

±15V

±5V

±13.5

±13

±3.5

±1.3

±14

±13.5

±4

V

L

R = 500Ω

L

R = 500Ω

L

R = 500Ω

±2.5V

±2

L

I

Short-Circuit Current

Slew Rate

G = 1

±15V

±70

±120

mA

SC

SR

G = –2, V

Measured at V

G = –2, V

Measured at V

= ±12V, P2 = 0V

OUT

750

1000

V/µs

OUT

= ±10V

= ±3.5V, P2 = 0V

±5V

450

V/µs

OUT

= ±2V

OUT

FPBW

HD

Full Power Bandwidth

10V Peak, G = –2 (Note 8)

3V Peak, G = –2 (Note 8)

±15V

±5V

16

24

MHz

Total Harmonic Distortion

–3dB Bandwidth

G = 1, f = 1MHz, R = 1k, V

= 2V

P-P

±15V

–81

dB

L

OUT

G = 1

±15V

±5V

±2.5V

32

25

21

MHz

t , t

Rise Time, Fall Time

Overshoot

10% to 90%, 0.1V, G = 1

±15V

±5V

10

15

ns

r

f

OS

0.1V, G = 1, C = 10pF

±15V

±5V

30

%

L

t

Propagation Delay

Settling Time

50% V to 50% V , 0.1V, G = 1

±15V

±5V

9

11

ns

pd

s

IN

OUT

10V Step, 0.1%, G = 1

5V Step, 0.1%, G = 1

±15V

±5V

100

110

ns

∆G

Differential Gain

Differential Phase

Output Resistance

Supply Current

G = 2, R = 150Ω

±15V

0.06

0.15

1.5

%

Deg

Ω

L

∆θ

G = 2, R = 150Ω

L

R

OUT

f = 1MHz, G = 1

G = 1

I

±15V

±5V

7.1

6.7

9.0

8.5

mA

S

1995fb

3

LT1995

ELECTRICAL CHARACTERISTICS

The

●

denotes the specifications which apply over the 0°C ≤ T ≤ 70°C.

A

Difference Amplifier Configuration. V

= V = 0V and unused gain pins are unconnected, unless otherwise noted.

CM

REF

SYMBOL PARAMETER

CONDITIONS

V

MIN

TYP

MAX

UNITS

SUPPLY

GE

Gain Error

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

= ±12V, R = 1k, G = 1

±15V

±5V

●

0.05

0.25

0.35

%

L

= ±12V, R = 1k, G = 2

L

= ±12V, R = 1k, G = 4

L

= ±2.5V, R = 500Ω, G = 1

L

= ±2.5V, R = 150Ω, G = 1

±5V

L

V

OS

Input Offset Voltage

Referred to Input (Note 7)

G = 1 (MS10)

G = 1 (DD10)

G = 2 (MS10)

G = 2 (DD10)

G = 4 (MS10)

G = 4 (DD10)

G = 1 (MS10)

G = 1 (DD10)

G = 1 (MS10)

G = 1 (DD10)

±15V

±5V

●

1.1

1.5

0.8

1.2

0.7

0.9

1

1.4

1

1.3

6.5

11.5

5.5

9

mV

5

7.5

6.5

11.5

6.5

11.5

±5V

±2.5V

V

TC

Input Offset Voltage Drift

Referred to Input (Note 9)

G = 1 (MS10)

G = 1 (DD10)

±15V

●

10

26

35

µV/°C

OS

Op Amp Input Offset Voltage

(Note 10)

G = 1 (MS10)

G = 1 (DD10)

±2.5V, ±5V, ±15V

●

0.55

0.75

3.25

5.75

mV

OS_OA

Input Voltage Range

G = 1

±15V

±5V

±2.5V

●

±15

±5

±1

±15.5

±5.5

±1.5

V

CMRR

PSRR

Common Mode Rejection Ratio

Referred to Input

V

= ±15V, G = 1

= ±15V, G = 2

= ±15V, G = 4

= ±5V, G = 1

= ±1V, G = 1

±15V

±5V

●

63

69

73

62

59

77

83

86

72

66

dB

CM

±2.5V

Power Supply Rejection Ratio

Output Voltage Swing

P1 = M1 = 0V, G = 1, V = ±2.5V to ±15V

●

76

86

dB

S

V

OUT

R = 1k

±15V

±5V

●

±13.1

±12.6

±3.4

±14

±13.5

±4

V

L

R = 500Ω

L

R = 500Ω

L

R = 500Ω

±2.5V

±1.2

±2

L

I

Short-Circuit Current

Slew Rate

G = 1

±15V

●

±55

±115

mA

SC

SR

G = –2, V

Measured at V

= ±12V, P2 = 0V

OUT

600

900

V/µs

OUT

= ±10V

I

Supply Current

G = 1

±15V

±5V

●

7.9

7.4

10.5

9.9

mA

S

The

●

denotes the specifications which apply over the –40°C ≤ T ≤ 85°C.

A

Difference Amplifier Configuration. V

= V = 0V and unused gain pins are unconnected, unless otherwise noted.

CM

REF

SYMBOL PARAMETER

CONDITIONS

V

MIN

TYP

MAX

UNITS

SUPPLY

GE

Gain Error

V

= ±12V, R = 1k, G = 1

±15V

±5V

●

0.05

0.3

0.35

0.3

%

OUT

L

= ±12V, R = 1k, G = 2

L

= ±12V, R = 1k, G = 4

L

= ±2.5V, R = 500Ω, G = 1

L

= ±2.5V R = 150Ω, G = 1

±5V

0.5

L

1995fb

4

LT1995

ELECTRICAL CHARACTERISTICS

The

●

denotes the specifications which apply over the –40°C ≤ T ≤ 85°C.

A

Difference Amplifier Configuration. V

SYMBOL PARAMETER

= V = 0V and unused gain pins are unconnected, unless otherwise noted.

REF

CM

CONDITIONS

V

MIN

TYP

MAX

UNITS

SUPPLY

V

OS

Input Offset Voltage

Referred to Input (Note 7)

G = 1 (MS10)

G = 1 (DD10)

G = 2 (MS10)

G = 2 (DD10)

G = 4 (MS10)

G = 4 (DD10)

G = 1 (MS10)

G = 1 (DD10)

G = 1 (MS10)

G = 1 (DD10)

±15V

±5V

●

1.2

1.6

0.9

1.2

0.7

0.9

1.1

1.4

1.1

1.5

7.5

13

6

10

5.5

8.5

7.5

13

7.5

13

mV

±5V

±2.5V

V

TC

Input Offset Voltage Drift

Referred to Input (Note 9)

G = 1 (MS10)

G = 1 (DD10)

±15V

●

10

26

35

µV/°C

OS

Op Amp Input Offset Voltage

(Note 10)

G = 1 (MS10)

G = 1 (DD10)

±2.5V, ±5V, ±15V

●

0.6

0.8

3.75

6.5

mV

OS_OA

Input Voltage Range

G = 1

±15V

±5V

±2.5V

●

±15

±5

±1

±15.5

±5.5

±1.5

V

CMRR

PSRR

Common Mode Rejection Ratio

Referred to Input

V

= ±15V, G = 1

= ±15V, G = 2

= ±15V, G = 4

= ±5V, G = 1

= ±1V, G = 1

±15V

±5V

●

62

68

72

61

57

77

83

86

72

66

dB

CM

±2.5V

Power Supply Rejection Ratio

Output Voltage Swing

P1 = M1 = 0V, G = 1, V = ±2.5V to ±15V

●

74

86

dB

S

V

OUT

R = 1k

±15V

±5V

●

±13

±12.5

±3.3

±1.1

±14

±13.5

±4

V

L

R = 500Ω

L

R = 500Ω

L

R = 500Ω

±2.5V

±2

L

I

Short-Circuit Current

Slew Rate

G = 1

±15V

●

±50

±105

mA

SC

SR

G = –2, V

Measured at V

= ±12V, P2 = 0V

OUT

550

900

V/µs

OUT

= ±10V

I

Supply Current

G = 1

±15V

±5V

●

8.0

7.6

11.0

10.4

mA

S

Note 1: Absolute Maximum Ratings are those values beyond which the life

Note 6: Thermal resistance (θ ) varies with the amount of PC board metal

JA

of a device may be impaired.

Note 2: The inputs are protected by diodes connected to V and V

connected to the leads. The specified values are for short traces connected

to the leads. If desired, the thermal resistance can be reduced slightly in

the MS package to about 130°C/W by connecting the used leads to a

larger metal area. A substantial reduction in thermal resistance down to

about 50°C/W can be achieved by connecting the Exposed Pad on the

+

–

.

S

If an input goes beyond the supply range, the input current should be

limited to 10mA.

Note 3: A heat sink may be required to keep the junction temperature

below absolute maximum.

bottom of the DD package to a large PC board metal area which is either

–

open-circuited or connected to V

.

S

Note 4: The LT1995C and LT1995I are guaranteed functional over the

operating temperature range of –40°C to 85°C.

Note 5: The LT1995C is guaranteed to meet specified performance from

0°C to 70°C. The LT1995C is designed, characterized and expected to

meet specified performance from –40°C to 85°C but is not tested or QA

sampled at these temperatures. The LT1995I is guaranteed to meet

specified performance from –40°C to 85°C.

Note 7: Input offset voltage is pulse tested and is exclusive of warm-up

drift. V and V TC refer to the input offset of the difference amplifier

OS

configuration. The equivalent input offset of the internal op amp can be

calculated from V = V • G/(G +1).

OS_OA

OS

Note 8: Full Power bandwidth is calculated from the slew rate measure-

ment: FPBW = SR/2πV .

P

Note 9: This parameter is not 100% tested.

Note 10: The input offset of the internal op amp is calculated from the

input offset voltage: V

= V • G/(G +1).

OS_OA

OS

1995fb

5

LT1995

U W

TYPICAL PERFOR A CE CHARACTERISTICS ^{(Difference Amplifier Configuration)}

Supply Current vs Supply Voltage

and Temperature

V

Distribution

Input Noise Spectral Density

OS

25

20

15

10

5

1000

100

10

8

V

= ±15V

CM

V

T

= ±15V

= 25°C

S

A

V

= 0V

G = 1

MS PACKAGE

T

= 125°C

= 25°C

A

T

A

6

G = 1

G = 4

G = 2

T

= –55°C

A

4

G = 7

2

0

1

0.01

0

–3.5

–1.5 –0.5 0.5

INPUT OFFSET VOLTAGE (mV)

1.5 2.5 3.5

–2.5

0

5

10

15

20

0.1

1

10

100

FREQUENCY (kHz)

SUPPLY VOLTAGE (±V)

1995 G01

1995 G03

1995 G02

Change in Gain Error

vs Resistive Load

Output Voltage Swing vs Supply

Voltage

Output Voltage Swing vs Load

Current

+

0.05

0.04

0.03

0.02

0.01

0

V

T

= ±15V

S

A

T

A

= 25°C

V = ±5V

S

= 25°C

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

V

= ±12V

OUT

R

L

= 1k

25°C

G = 7

G = 4

–40°C

R

L

= 500Ω

3.0

2.5

2.0

1.5

1.0

0.5

85°C

25°C

G = 2

G = 1

–0.01

–0.02

–0.03

–0.04

–0.05

R

L

= 500Ω

1.5

1.0

0.5

–40°C

R

L

= 1k

15

–

V

0

1

2

3

4

5

6

7

8

9

10

–50

–25

OUTPUT CURRENT (mA)

0

25

50

0

5

20

RESISTIVE LOAD (kΩ)

SUPPLY VOLTAGE (±V)

1995 G04

1995 G05

1995 G06

Output Short-Circuit Current

vs Temperature

Warm-Up Drift vs Time

Output Impedance vs Frequency

120

100

80

1000

100

10

300

V

= ±15V

= 25°C

V = ±5V

S

A

V

= ±15V

= 25°C

S

A

T

250

MS PACKAGE

200

150

G = 7

SOURCE

G = 1

G = 7

60

SINK

G = 1

40

20

0

100

50

0

1

0.1

50

TEMPERATURE (°C)

100 125

10k

100k

1M

FREQUENCY (Hz)

10M

100M

–50 –25

0

25

75

0

1

2

3

4

5

TIME AFTER POWER ON (MINUTES)

1995 G09

1995 G08

1995 G07

1995fb

6

LT1995

U W

TYPICAL PERFOR A CE CHARACTERISTICS ^{(Difference Amplifier Configuration)}

Settling Time vs Output Step

(Non-Inverting)

Settling Time vs Output Step

(Inverting)

Gain vs Frequency

20

18

16

14

12

10

8

6

4

2

0

–2

–4

–6

–8

–10

10

8

10

8

V

T

= ±15V

= 25°C

= 1k

V

T

= ±15V

= 25°C

= 1k

S

G = 7

A

R

L

R

L

6

G = –1

G = 4

G = 2

G = 1

4

10mV

1mV

10mV

1mV

2

0

–2

–4

–6

–8

–10

–2

–4

–6

–8

–10

1mV

10mV

V

= ±15V

= 25°C

= 1k

S

A

L

T

R

10k

100k

1M

10M

100M

0

20 40 60 80 100 120 140 160

0

20 40 60 80 100 120 140 160 180

FREQUENCY (Hz)

SETTLING TIME (ns)

1995 G10

1995 G12

1995 G11

Settling Time vs Gain

(Non-Inverting)

–3dB Bandwidth and Overshoot

vs Supply Voltage

–3dB Bandwidth and Overshoot

vs Temperature

35

30

25

20

40

35

30

25

20

140

120

G = –1

T

= 25°C

A

G = –1

V

= ±15V

S

–3dB BANDWIDTH

V

= ±5V

S

100

–3dB BANDWIDTH

80

60

40

20

42

41

40

50

45

40

OVERSHOOT

C

= 15pF

L

C

L

= 15pF

V

= ±15V

= 25°C

OUT

= 1k

S

A

V

S

= ±15V

= ±5V

T

∆V

R

L

= 10V

V

S

0.1% SETTLING

35

0

50

0

TEMPERATURE (°C)

100 125

–50 –25

25

75

8

10

0

2

4

6

12 14 16 18

1

3

4

5

6

7

8

2

GAIN (V/V)

SUPPLY VOLTAGE (±V)

1995 G15

1995 G14

1995 G13

Frequency Response vs Supply

Voltage (G = 1, G = –1)

Frequency Response

vs Capacitive Load

Common Mode Rejection Ratio

vs Frequency

20

15

10

5

100

90

80

70

60

50

40

30

20

10

0

10

8

V

T

= ±15V

= 25°C

V

T

= ±15V

= 25°C

= ∞

T

= 25°C

= 1k

S

A

G = 1

S

A

L

C = 200pF

R

A

R

L

6

G = –1

4

C = 100pF

C = 50pF

±2.5V

±15V

±5V

2

0

–2

–4

–5

–10

–15

C = 0pF

–6

–8

–10

1

100

1k

10k

1M

10M

100M

10

100k

1M

10M

100M

FREQUENCY (MHz)

FREQUENCY (Hz)

1995 G16

1995 G17

1995 G18

1995fb

7

LT1995

U W

TYPICAL PERFOR A CE CHARACTERISTICS ^{(Difference Amplifier Configuration)}

Power Supply Rejection Ratio

vs Frequency

Slew Rate vs Supply Voltage

Slew Rate vs Temperature

1800

1600

1400

1200

1000

800

90

80

70

60

50

40

30

20

10

0

1600

1400

1200

1000

G = –2

V

T

= ±15V

= 25°C

T

= 25°C

S

A

G = 1

A

G = –1

= V – V – 3V

P-P

+

–

V

OUT

S

+PSRR

V

= ±15V

OUT

S

= 27V

P-P

–PSRR

800

600

V

= ±5V

OUT

S

600

= 7V

400

200

0

400

200

0

–10

1k

10k

100k

1M

10M

100M

0

5

10

15

–50 –25

0

25

125

50

75 100

TEMPERATURE (°C)

FREQUENCY (Hz)

SUPPLY VOLTAGE (±V)

1995 G19

1995 G20

1995 G21

Total Harmonic Distortion vs

Frequency

Undistorted Output Swing vs

Slew Rate vs Input Level

Frequency (±15V)

0.01

0.001

30

25

20

15

10

5

1400

1200

T

= 25°C

= ±15V

T = 25°C

A

S

V

= 3V

o RMS

G = –1

R = 500Ω

L

G = 1

1000

800

600

400

200

G = –1

G = 1

G = –1

V

= ±15V

= 25°C

S

A

T

HD <2%

0

0.0001

0

6

10 12 14 16 18 20

0.1

1

10

2

4

8

0.01

0.1

1

10

100

FREQUENCY (MHz)

INPUT LEVEL (V

)

P-P

FREQUENCY (kHz)

1995 G24

1995 G23

1995 G22

Undistorted Output Swing vs

Frequency (±5V)

2nd and 3rd Harmonic Distortion

vs Frequency

Differential Gain and Phase

vs Supply Voltage

10

9

8

7

6

5

4

3

2

1

0

0.5

0.4

0.3

0.2

0.1

0

–40

–50

–60

–70

–80

–90

–100

V

T

= ±5V

T

A

= 25°C

V

= ±15V

S

A

S

= 25°C

R

L

= 150Ω

= 2V

OUT

P-P

HD <2%

G = 2

R

= 500Ω

L

G = 2

DIFFERENTIAL

GAIN

G = 1

1.0

0.8

0.6

0.4

0.2

2ND HARMONIC

G = –1

DIFFERENTIAL

PHASE

3RD HARMONIC

0

0.1

1

10

0.1

1

10

0

30

5

10

15

20

25

FREQUENCY (MHz)

SUPPLY VOLTAGE (V)

1995 G25

1995 G26

1995 G27

1995fb

8

LT1995

U W

TYPICAL PERFOR A CE CHARACTERISTICS ^{(Difference Amplifier Configuration)}

Capacitive Load Handling

100

90

100

90

V

T

= ±5V

= 25°C

= ∞

V

T

= ±15V

= 25°C

= ∞

S

A

G = 4

G = 7

G = 4

G = 2

R

L

R

L

80

G = 1

70

G = 7

G = 1

60

50

60

50

40

30

20

10

0

40

30

20

10

0

10pF

100pF 1000pF 0.01µF 0.1µF

1µF

10pF

100pF 1000pF 0.01µF 0.1µF

1µF

CAPACITIVE LOAD

1995 G29

1995 G28

Small-Signal Transient

(Noninverting, G = 1, C = 100pF)

Small-Signal Transient (G = 1)

Small-Signal Transient (G = –1)

L

V_S= ±15V

R_L= 1k

100ns/DIV

1995 G30

V

_S= ±15V

100ns/DIV

1995 G31

V

_S= ±15V

100ns/DIV

1995 G32

R_L= 1k

Large-Signal Transient

(Noninverting, G = 1, C = 100pF)

Large-Signal Transient (G = 1)

Large-Signal Transient (G = –1)

L

V

_S= ±15V

100ns/DIV

1995 G34

V_S= ±15V

R_L= 1k

100ns/DIV

1995 G33

V_S= ±15V

R_L= 1k

100ns/DIV

1995 G35

R_L= 1k

1995fb

9

LT1995

U

PI FU CTIO S ^{(Difference Amplifier Configuration)}

OUT (Pin 6): Output Voltage. V_OUT= V_REF+ 1 • (V_P1– V_M1

+ 2 • (V_P2– V_M2) + 4 • (V_P4– V_M4).

)

P1 (Pin 1): Noninverting Gain-of-1 Input. Connects a 4k

internal resistor to the op amp’s noninverting input.

V_S⁺(Pin 7): Positive Supply Voltage.

P2 (Pin 2): Noninverting Gain-of-2 Input. Connects a 2k

internal resistor to the op amp’s noninverting input.

M4 (Pin 8): Inverting Gain-of-4 Input. Connects a 1k

internal resistor to the op amp’s inverting input.

P4 (Pin 3): Noninverting Gain-of-4 Input. Connects a 1k

internal resistor to the op amp’s noninverting input.

V_S^–(Pin 4): Negative Supply Voltage.

M2 (Pin 9): Inverting Gain-of-2 Input. Connects a 2k

internal resistor to the op amp’s inverting input.

M1 (Pin 10): Inverting Gain-of-1 Input. Connects a 4k

internal resistor to the op amp’s inverting input.

REF(Pin5):ReferenceVoltage.Setstheoutputlevelwhen

the difference between the inputs is zero. Connects a 4k

internal resistor to the op amp’s non inverting input.

1995fb

10

LT1995

W

BLOCK DIAGRA

+

V

S

7

R

= 4k

R

= 4k

P1

FB

P1

REF

1

2

5

0.5pF

0.3pF

= 2k

P2

P4

P2

= 1k

= 2k

P4

3

+

–

R

M4

M2

M1

8

M2

9

0.3pF

0.5pF

R

= 4k

R

= 4k

FB

M1

OUT

10

6

–

V

S

4

1995 BD

W U U

U

APPLICATIO S I FOR ATIO

Configuration Flexibility

the rails, which in low supply voltage and high gain

configurations will create a limitation on the usable input

range.Itshouldbenotedthatwhiletheinternalopampcan

withstand transient differential input voltages of up to 10V

without damage, this does generate large supply current

increases (tens of mA) as required for high slew rates. If

the device is used with sustained differential input across

the internal op amp (such as when the output is clipping),

the average supply current will increase, excessive power

dissipation will result, and the part may be damaged (i.e.,

the LT1995 is not recommended for use in comparator

applications or with the output clipped).

The LT1995 combines a high speed precision operational

amplifier with eight ratio-matched on-chip resistors. The

resistor configuration and pinout of the device is shown in

theBlockDiagram.Thetopologyisextremelyversatileand

provides for simple realizations of most classic functional

configurations including difference amplifiers, inverting

gain stages, noninverting gain stages (including Hi-Z

input buffers) and summing amplifiers. The LT1995 deliv-

ersloadcurrentsofatleast30mA, makingitidealforcable

driving applications as well.

The input voltage range depends on gain and configura-

tion. ESD diodes will clamp any input voltage that exceeds

the supply potentials by more than several tenths of a volt;

and the internal op amp input ports must remain at least

1.75V within the rails to assure normal operation of the

part. The output will swing to within one and a half volts of

Difference Amplifier

The LT1995 can be connected as a classic difference

amplifier with an output function given by:

V

_OUT= G • (V_IN⁺– V_IN^–) + V_REF

1995fb

11

LT1995

W U U

U

APPLICATIO S I FOR ATIO

As shown in Figure 1, the options for fixed gain G include:

1, 1.33, 1.67, 2, 3, 4, 5, 6 and 7, all achieved by pin-

strapping alone. With split-supply applications where the

outputistobegroundreferenced, theV_REFinputissimply

tied to ground. The input common mode voltage is

rejected by the high CMRR of the part within the usable

input range.

Noninverting Gain Amplifier Input Attenuation

The LT1995 can also be connected as a noninverting gain

amplifier having an input attenuation network to provide a

wide range of additional noninverting gain options. In

combination with the feedback configurations for gains of

G shown in Figure 2 (connections to the M inputs), the P

and REF inputs may be connected to form several resistor

divider attenuation ratios A, so that a compound output

function is given by:

Inverting Gain Amplifier

The LT1995 can be connected as an inverting gain ampli-

fier with an output function given by:

V

_OUT= A • G • V_IN

As shown in Figure 3, the options for fixed attenuation A

include0.875,0.857,0.833,0.8,0.75,0.714,0.667,0.625

and 0.571, all achieved by pin strapping alone. With just

the attenuation configurations of Figure 3 and the feed-

back configurations of Figure 2, seventy-three unique

composite gains in the range of 1 to 8 are available (many

options for gain below unity also exist). Figure 3 does not

include the additional pin-strap configurations offering A

valuesof0.5, 0.429, 0.375, 0.333, 0.286, 0.25, 0.2, 0.167,

0.143 and 0.125, as these values tend to compromise the

low noise performance of the part and don’t generally

contribute many more unique gain options. It should be

noted that with these configurations some degree of

imbalance will generally exist between the effective resis-

tances R_Pand R_Mseen by the internal op amp input ports,

noninverting and inverting, respectively. Depending on

the specific combination of A and G, the following DC

offseterrorduetoopampinputbiascurrent(I_B)shouldbe

anticipated: The I_Bof the internal op amp is typically 0.6µA

and is prepackage tested to a limit of 2µA. Additional

output-referred offset = I_B• (R_P– R_M) • G. In some

configurations, this could be as much as 1.7mV • G

additional output offset. The I_OSof the internal op amp is

typically 120nA and is prepackage tested to a limit of

350nA. The Electrical Characteristics table includes the

effects of I_Band I_OS.

V

_OUT= –(G • V_IN^–) + V_REF

As shown in Figure 1, the options for fixed gain G include:

1, 1.33, 1.67, 2, 3, 4, 5, 6 and 7, all achieved by pin

strapping alone. The V_INconnection used in the differ-

ence amp configuration is simply tied to ground (or a low

impedancepotentialequaltotheinputsignalbiastocreate

an input “virtual ground”). With split-supply applications

wheretheoutputistobegroundreferenced,theV_REFinput

is simply tied to ground as well.

+

Noninverting Gain Buffer Amplifier

The LT1995 can be connected as a high input impedance

noninverting gain buffer amplifier with an output function

given by:

V_OUT= G • V_IN

As shown in Figure 2, the options for fixed gain G include:

1, 1.14, 1.2, 1.33, 1.4, 1.6, 2, 2.33, 2.66, 3, 4, 5, 6, 7 and

8, all achieved by pin strapping alone. With single supply

applications, the grounded M input pins may be tied to a

low impedance potential equal to the input signal bias to

create a “virtual ground” for both the input and output

signals. While there is no input attenuation from V_INto the

internal noninverting op amp port in these configurations,

the P connections vary to minimize offset by providing

balanced input resistances to the internal op amp.

1995fb

12

LT1995

W U U

APPLICATIO S I FOR ATIO

U

+V

8

9

8

9

8

9

–

+

V

M4

M2

M1

M4

M2

M1

M4

M2

M1

IN

7

10

–

+

V

6

IN

LT1995

V

LT1995

V

LT1995

V

OUT

1

2

3

1

2

3

1

2

3

P1

P2

P4

REF

5

P1

P2

P4

REF

5

P1

P2

P4

REF

5

+

V

4

IN

V

REF

–V

V

REF

G = 1.00

G = 1.33

G = 1.67

+V

7

+V

7

+V

7

8

9

8

9

8

9

–

M4

M2

M1

M4

M2

M1

V

M4

M2

M1

IN

–

+

–

V

IN

10

6

LT1995

V

LT1995

V

LT1995

V

OUT

1

2

3

1

2

3

1

2

3

P1

P2

P4

REF

P1

P2

P4

REF

P1

P2

P4

REF

+

5

V

5

IN

+

V

4

V

REF

–V

G = 2.00

G = 3.00

G = 4.00

+V

7

+V

7

+V

7

8

9

8

9

8

9

–

+

–

+

–

M4

M2

M1

M4

M2

M1

M4

M2

M1

V

IN

10

6

LT1995

V

LT1995

V

LT1995

V

OUT

1995 F01

OUT

1

2

3

1

2

3

1

2

3

P1

P2

P4

REF

P1

P2

P4

REF

P1

P2

P4

REF

5

+

V

4

IN

V

REF

–V

G = 5.00

–V

G = 6.00

–V

G = 7.00

Figure 1. Difference (and Inverting) Amplifier Configurations

Table 1. Pin Use, Input Range, Input Resistance, Bandwidth in Difference Amplifier Configuration

GAIN

1

2

3

4

5

6

7

Use of P1/M1

Use of P2/M2

Use of P4/M4

V

Open

V

Open

V

Open

V

IN

Open

±15V

±5V

±1.5V

8k

V

Open

V

IN

V

IN

V

IN

Open

±15V

±4.88V

±1.13V

6k

Open

±15V

±4.33V

±1V

V

IN

Positive Input Range: V = 0V, V = ±15V

±15V

±4.06V

±0.94V

5k

±15V

±3.9V

±0.9V

4.8k

±15V

±3.79V

±0.88V

4.67k

±15V

±3.71V

±0.86V

4.57k

REF

S

Positive Input Range: V = 0V, V = ±5V

REF

S

Positive Input Range: V = 0V, V = ±2.5V

REF

S

Positive Input Resistance

5.33k

1.33k

5.33k

2.67k

27MHz

Minus Input Resistance

Ref Input Resistance

4k

2k

1k

800Ω

4.8k

667Ω

4.67k

571Ω

4.57k

8k

6k

5k

Input Common Mode Resistance, V = 0V

4k

3k

2.5k

2k

2.4k

2.33k

2.29k

REF

Input Differential Mode Resistance, V = 0V

8k

4k

1.6k

1.33k

1.14k

REF

–3dB Bandwidth

32MHz

27MHz

23MHz

18MHz

16MHz

15MHz

1995fb

13

LT1995

W U U

U

APPLICATIO S I FOR ATIO

+V

8

9

8

9

M4

M2

M1

M4

M2

M1

7

9

M2

M1

10

6

LT1995

V

OUT

LT1995

V

LT1995

V

OUT

1

2

3

1

2

3

1

2

3

P1

P2

P4

REF

5

P1

P2

P4

REF

5

P1

P2

P4

REF

5

4

–V

V

IN

V

IN

V

IN

G = 1.00

G = 1.14

G = 1.20

+V

7

+V

7

+V

7

8

9

8

9

8

9

M4

M2

M1

M4

M2

M1

M4

M2

M1

10

6

LT1995

V

OUT

LT1995

V

LT1995

V

OUT

1

2

3

1

2

3

1

2

3

P1

P2

P4

REF

P1

P2

P4

REF

P1

P2

P4

REF

5

4

–V

1995 F02

V

IN

V

IN

V

IN

G = 1.33

G = 1.40

G = 1.60

+V

7

+V

7

+V

7

8

9

8

9

8

9

M4

M2

M1

M4

M2

M1

M2

M1

10

6

LT1995

V

OUT

LT1995

V

LT1995

V

OUT

1

2

3

1

2

3

1

2

3

P1

P2

P4

REF

P1

P2

P4

REF

P1

P2

P4

REF

5

4

–V

V

IN

V

IN

V

IN

G = 2.00

G = 2.33

G = 2.66

+V

7

+V

7

+V

7

8

9

8

9

8

9

M4

M2

M1

M4

M2

M1

M4

M2

M1

10

6

LT1995

V

OUT

LT1995

V

LT1995

V

OUT

1

2

3

1

2

3

1

2

3

P1

P2

P4

REF

P1

P2

P4

REF

P1

P2

P4

REF

5

4

–V

V

IN

V

IN

V

IN

G = 3.00

G = 4.00

G = 5.00

+V

7

+V

7

+V

7

8

9

8

9

8

9

M4

M2

M1

M4

M2

M1

M4

M2

M1

10

6

LT1995

V

OUT

LT1995

V

OUT

LT1995

V

OUT

1

2

3

1

2

3

1

2

3

P1

P2

P4

REF

P1

P2

P4

REF

P1

P2

P4

REF

5

4

–V

G = 6.00

–V

G = 7.00

–V

G = 8.00

1995 F02b

V

IN

V

IN

V

IN

Figure 2. Noninverting Buffer Amplifier Configurations (Hi-Z Input)

1995fb

14

LT1995

W U U

APPLICATIO S I FOR ATIO

U

+V

8

9

8

9

8

9

M4

M2

M1

M4

M2

M1

M4

M2

M1

7

*

10

6

LT1995

V

OUT

LT1995

V

OUT

LT1995

V

OUT

1

2

3

1

2

3

1

2

3

V

IN

P1

P2

P4

REF

P1

P2

P4

REF

5

P1

P2

P4

REF

5

IN

5

V

IN

4

–V

A = 0.875

A = 0.857

A = 0.833

+V

7

+V

7

+V

7

8

9

8

9

8

9

M4

M2

M1

M4

M2

M1

M4

M2

M1

*

10

6

LT1995

REF

V

OUT

LT1995

REF

V

OUT

LT1995

REF

V

OUT

1

2

3

1

2

3

1

2

3

V

IN

V

IN

P1

P2

P4

P1

P2

P4

P1

P2

P4

5

4

V

IN

–V

A = 0.800

A = 0.750

A = 0.714

+V

7

+V

7

+V

7

8

9

8

9

8

9

M4

M2

M1

M4

M2

M1

M4

M2

M1

*

10

6

LT1995

REF

V

OUT

LT1995

REF

V

OUT

LT1995

REF

V

OUT

1

2

3

1

2

3

1

2

3

V

IN

P1

P2

P4

P1

P2

P4

P1

P2

P4

1995 F03

5

V

IN

4

V

IN

–V

A = 0.667

–V

A = 0.625

–V

A = 0.571

*CONFIGURE M INPUTS FOR DESIRED G PARAMETER; REFER TO FIGURE 2 FOR CONNECTIONS

Figure 3. Noninverting Amplifier Input Attenuation Configurations (A > 0.5)

8

AC-Coupling Methods for Single Supply Operation

7

6

TheLT1995canbeusedinmanysingle-supplyapplications

using AC-coupling without additional biasing circuitry.

5

4

3

2

AC-coupling the LT1995 in a difference amplifier configu-

ration(asinFigure1)isasimplematterofaddingcoupling

capacitors to each input and the output as shown in the

exampleofFigure5. TheinputvoltageV_BIASappliedtothe

REF pin establishes the quiescent voltage on the input and

output pins. The V_BIASsignal should have a low source

impedance to avoid degrading the CMRR (0.5Ω for

1dB CMRR change typically).

1

73

GAIN COMBINATION

1995 F04

Figure 4. Unique Noninverting Gain Configurations

1995fb

15

LT1995

W U U

U

APPLICATIO S I FOR ATIO

Using the LT1995 as an AC-coupled inverting gain stage,

theREFpinandtherelevantPinputsmayallbedrivenfrom

a V_BIASsource as depicted in the example of Figure 6, thus

establishing the quiescent voltage on the input and output

pins. The V_BIASsignal will only have to source the bias

current(I_B)ofthenoninvertinginputoftheinternalopamp

(0.6µA typically), so a high V_BIASsource impedance (R_S)

will cause the quiescent level of the amplifier output to

deviate from the intended V_BIASlevel by I_B• R_S.

In operation as a noninverting gain stage, the P and REF

inputs may be configured as a “supply splitter,” thereby

providing a convenient mid-supply operating point. Fig-

ure 7 illustrates the three attenuation configurations that

generate 50% mid-supply biasing levels with no external

components aside from the desired coupling capacitors.

As with the DC-coupled input attenuation ratios, A, a

compound output function including the feedback gain

parameter G is given by:

V

_OUT= A • G • V_IN

+V

8

M4

M2

M1

7

9

C

IN

M2

M1

C

OUT

10

–

+

–

V

IN

6

LT1995

V

OUT

LT1995

4

V

OUT

1

2

3

1

2

3

P1

P2

P4

REF

5

P1

P2

P4

REF

5

4

1995 F05

1995 F06

V

BIAS

Figure 5. AC-Coupled Difference Amplifier

General Configuation (G = 5 Example)

Figure 6. AC-Coupled Inverting Gain Amplifier

General Configuration (G = 5 Example)

+V

8

9

8

M4

M2

M1

M4

7

9

M2

M1

M2

M1

C

OUT

*

OUT

10

6

LT1995

V

LT1995

4

V

LT1995

V

OUT

1

2

3

1

2

3

1

2

3

P1

P2

P4

REF

P1

P2

P4

REF

P1

P2

P4

REF

5

V

IN

4

V

4

IN

C

IN

C

IN

1995 F07

A = 0.750

A = 0.667

A = 0.500

*CONFIGURE M INPUTS FOR DESIRED G PARAMETER; REFER TO FIGURE 2 FOR CONNECTIONS. ANY M

INPUTS SHOWN GROUNDED IN FIGURE 2 SHOULD INSTEAD BE CAPACITIVELY COUPLED TO GROUND

Figure 7. AC-Coupled Noninverting Amplifier Input Attenuation Configurations (Supply Splitting)

1995fb

16

LT1995

W U U

APPLICATIO S I FOR ATIO

U

If one of the A parameter configurations in Figure 3 is

preferred, or the use of an external biasing source is

desired,thePandREFinputconnectionsshowngrounded

in a Figure 3 circuit may be instead driven by a V_BIAS

voltage to establish a quiescent operating point for the

input and output pins. The V_INconnections of the Figure 3

circuit are then driven via a coupling capacitor. Any

grounded M inputs for the desired G configuration (refer

to Figure 2) must be individually or collectively

AC-coupled to ground. Figure 8 illustrates a complete

example circuit of an externally biased AC-coupled nonin-

verting amplifier. The V_BIASsource impedance should be

low(afewohms)toavoiddegradingtheinherentaccuracy

of the LT1995. 0.013% of additional Gain Error for each

ohm of resistance on the REF pin is typical.

at room temperature, and to within 0.3% over tempera-

ture. The temperature coefficient of the resistors is typi-

cally –30ppm/°C. The resistors have been sized to accom-

modate 15V across each resistor, or in terms of power,

225mWinthe1kresistors,113mWinthe2kresistors,and

56mW in the 4k resistors.

Power Supply Considerations

As with any high speed amplifier, the LT1995 printed

circuitlayoutshouldutilizegoodpowersupplydecoupling

practices. Good decoupling will typically consist of one or

more capacitors employing the shortest practical inter-

connection traces and direct vias to a ground plane. This

practice minimizes inductance at the supply pins so the

impedance is low at the operating frequencies of the part,

thereby suppressing feedback or crosstalk artifacts that

might otherwise lead to extended settling times, fre-

quency response anomalies, or even oscillation. For high

speed parts like the LT1995, 10nF ceramics are suitable

close-in bypass capacitors, and if high currents are being

delivered to a load, additional 4.7µF capacitors in parallel

can help minimize induced power supply transients.

+V

8

M4

7

9

C

BYP

M2

M1

C

OUT

10

6

LT1995

V

OUT

1

2

3

P1

P2

P4

REF

5

C

IN

CONFIGURATION EXAMPLE:

A = 0.625

V

4

IN

G = 6.00

Because unused input pins are connected via resistors to

the input of the op amp, excessive capacitances on these

pins will degrade the rise time, slew rate, and step re-

sponse of the output. Therefore, these pins should not be

connected to large traces which would add capacitance

when not in use.

(V /V = 3.75V)

OUT IN

V

BIAS

1995 F08

Figure 8. AC-Coupled Noninverting Amplifier

with External Bias Source (Example)

Resistor Considerations

Since the LT1995 has a wide operating supply voltage

range, it is possible to place the part in situations of

relativelyhighpowerdissipationthatmaycauseexcessive

die temperatures to develop. Maximum junction tempera-

ture (T_J) is calculated from the ambient temperature (T_A)

The resistors in the LT1995 are very well matched, low

temperaturecoefficientthinfilmbasedelements.Although

their absolute tolerance is fairly wide (typically ±5% but

±25% worst case), the resistor matching is to within 0.2%

1995fb

17

LT1995

W U U

U

APPLICATIO S I FOR ATIO

and power dissipation (P_D) as follows for a nominal PCB

layout:

Frequency Compensation

TheLT1995comfortablydrivesheavyresistiveloadssuch

as back-terminated cables and provides nicely damped

responses for all gain configurations when doing so.

Small capacitances are included in the on-chip resistor

networktooptimizebandwidthinthebasicdifferencegain

configurationsofFigure1. Forthenoninvertingconfigura-

tions of Figure 2, where the gain parameter G is 2 or less,

significant overshoot can occur when driving light loads.

For these low gain cases, providing an RC output network

as shown in Figure 9 to create an artificial load at high

frequency will assure good damping behavior.

T_J= T_A+ (P_D• θ_JA)

For example, in order to maintain a maximum junction

temperature of 150°C at 85°C ambient in an MS10 pack-

age, the power must be limited to 0.4W. It is important to

note that when operating at ±15V supplies, the quiescent

current alone will typically account for 0.24W, so careful

thermal management may be required if high load cur-

rents and high supply voltages are involved. By additional

copper area contact to the supply pins or effective thermal

coupling to extended ground plane(s), the thermal imped-

ance can be reduced to 130°C/W in the MS10 package. A

substantial reduction in thermal impedance of the DD10

package down to about 50°C/W can be achieved by

connecting the Exposed Pad on the bottom of the package

to a large PC board metal area which is either open-

–

circuited or connected to V_S.

+V

8

M4

7

9

M2

M1

10

6

LT1995

V

OUT

1

2

3

P1

P2

P4

REF

5

10nF

47Ω

4

–V

V

IN

1995 F09

CONFIGURATION EXAMPLE:

G = 1.14

Figure 10. Step Response of Circuit in Figure 9

Figure 9. Optional Frequency Compensation

Network for (1 ≤ G ≤ 2)

1995fb

18

LT1995

U

PACKAGE DESCRIPTIO

MS Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1661)

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

0.889 ± 0.127

(.035 ± .005)

0.497 ± 0.076

(.0196 ± .003)

REF

10 9

8

7 6

DETAIL “A”

0.254

5.23

3.20 – 3.45

(.206)

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

(.010)

4.90 ± 0.152

(.193 ± .006)

0° – 6° TYP

(.126 – .136)

MIN

GAUGE PLANE

0.53 ± 0.152

(.021 ± .006)

0.50

(.0197)

BSC

0.305 ± 0.038

(.0120 ± .0015)

TYP

1

2

3

4 5

DETAIL “A”

RECOMMENDED SOLDER PAD LAYOUT

0.86

(.034)

REF

1.10

(.043)

MAX

0.18

(.007)

SEATING

PLANE

NOTE:

0.17 – 0.27

(.007 – .011)

TYP

0.127 ± 0.076

(.005 ± .003)

MSOP (MS) 0603

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

0.50

(.0197)

BSC

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699)

R = 0.115

0.38 ± 0.10

TYP

6

10

0.675 ±0.05

3.50 ±0.05

2.15 ±0.05 (2 SIDES)

1.65 ±0.05

3.00 ±0.10

(4 SIDES)

1.65 ± 0.10

(2 SIDES)

PIN 1

TOP MARK

(SEE NOTE 6)

PACKAGE

OUTLINE

(DD10) DFN 1103

5

1

0.25 ± 0.05

0.50 BSC

0.75 ±0.05

0.200 REF

0.25 ± 0.05

0.50

BSC

2.38 ±0.10

(2 SIDES)

2.38 ±0.05

(2 SIDES)

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

1995fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

19

LT1995

U

TYPICAL APPLICATIO S

Tracking Negative Reference

High Input Impedance Precision Gain of 2 Configuration

3V

+V

8

M4

1.25V

LT1790-1.25

7

9

M2

M1

10

6

LT1995

V

OUT

M1

1

2

3

P1

P2

P4

REF

LT1995

G = –1

P1

1µF

–1.25V

5

REF

I

= 600nA

IN

4

1995 TA03

–V

1995 TA02

V

IN

–3V

0A to 2A Current Source

Current Sense with Alarm

15V

15V TO –15V

15V

I

LT6700-3

15V

10nF

M4

M1

P1

LT1995

G = 1

M1

10k

1k

–

+

R

LT1995

S

0.1Ω

0.2Ω

G = 5

REF

SENSE

OUTPUT

100mV/A

REF

P1

P4

LT1880

–15V

–

FLAG

OUTPUT

4A LIMIT

+

–15V

100Ω

V

IN

400mV

IRF9530

1995 TA05

1995 TA04

V

5 • R

IN

10nF

I

=

OUT

I

OUT

S

Single Supply Video Line Driver

5V

8

9

M4

7

+

47µF

M2

10

75Ω

M1

6

LT1995

4

V

–3dB

R

OUT

1

2

3

P1

P2

P4

f

= 27MHz

220µF

47µF

= 75Ω

5

L

10k

V

IN

1995 TA06

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

50ns Settling Time to 0.1%, C

LT1363

70MHz, 1000V/µs Op Amp

Stable

LOAD

LT1990

High Voltage Difference Amplifier

Precision Gain Selectable Amplifier

Fully Differential Amplifier

±250V Common Mode Voltage, Micropower, Pin Selectable G = 1, 10

LT1991

Micropower, Precision, Pin Selectable G = –13 to 14

LTC1992

Differential Input and Output, Rail-to-Rail Output, I = 1.2mA, C

Stable

LOAD

S

to 10,000pF, Adjustable Common Mode Voltage

LTC6910-x

Programmable Gain Amplifiers

3 Gain Configurations, Rail-to-Rail Input and Output

1995fb

LT/LT 0805 REV B • PRINTED IN THE USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT1995CDD
厂家：	Linear
描述：	32MHz, 1000V/μs Gain Selectable Amplifier 32MHz的， 1000V / μs增益可选放大器仪表放大器放大器电路
文件：	总20页 (文件大小：353K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT1995CDD [Linear]

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