LT1999CS8-10#PBF [Linear]
LT1999 - High Voltage, Bidirectional Current Sense Amplifier; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C;
| 型号： | LT1999CS8-10#PBF |
| 厂家： | 
Linear |
| 描述： | LT1999 - High Voltage, Bidirectional Current Sense Amplifier; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C 放大器 光电二极管 |
| 文件： | 总28页 (文件大小：1455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1999-10/LT1999-20/
LT1999-50
High Voltage, Bidirectional
Current Sense Amplifier
FEATURES
DESCRIPTION
The LT®1999 is a high speed precision current sense
amplifier, designed to monitor bidirectional currents over
a wide common mode range. The LT1999 is offered in
three gain options: 10V/V, 20V/V, and 50V/V.
n
Buffered Output with 3 Gain Options:
10V/V, 20V/V, 50V/V
Gain Accuracy: 0.5% Max
Input Common Mode Voltage Range: –5V to 80V
AC CMRR > 80dB at 100kHz
Input Offset Voltage: 1.5mV Max
–3dB Bandwidth: 2MHz
Smooth, Continuous Operation Over Entire Common
n
n
n
The LT1999 senses current via an external resistive shunt
and generates an output voltage, indicating both mag-
nitude and direction of the sensed current. The output
voltage is referenced halfway between the supply voltage
and ground, or an external voltage can be used to set
the reference level. With a 2MHz bandwidth and a com-
mon mode input range of –5V to 80V, the LT1999 is suit-
able for monitoring currents in H-Bridge motor controls,
switching power supplies, solenoid currents, and battery
charge currents from full charge to depletion.
n
n
n
Mode Range
4kV HBM Tolerant and 1kV CDM Tolerant
Low Power Shutdown <10µA
–55°C to 150°C Operating Temperature Range
8-Lead MSOP and 8-Lead SO (Narrow) Packages
8-Lead MSOP Pinout Option Engineered for FMEA
AEC-Q100 Qualified for Automotive Applications
n
n
n
n
n
n
The LT1999 operates from an independent 5V supply and
draws 1.55mA. A shutdown mode is provided for mini-
mizing power consumption.
APPLICATIONS
n
High Side or Low Side Current Sensing
H-Bridge Motor Control
Solenoid Current Sense
High Voltage Data Acquisition
PWM Control Loops
Fuse/MOSFET Monitoring
The LT1999 is available in an 8-lead SOP, an 8-lead MSOP
(original pinout), or an 8-lead pinout option engineered
for FMEA.
n
n
n
All registered trademarks and trademarks are the property of their respective owners.
n
n
TYPICAL APPLICATION
Full Bridge Armature Current Monitor
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ꢍ
SHDN
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ꢆ.ꢂꢊꢔ
ꢂꢃꢃꢃ ꢁꢋꢆꢂꢐ
Rev. E
1
Document Feedback
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
ABSOLUTE MAXIMUM RATINGS
Differential Input Voltage
(Note 1)
Specified Temperature Range (Note 6)
+IN to –IN (Notes 1, 3)................................. 60V, 10ms
+IN to GND, –IN to GND (Note 2)............. –5.25V to 88V
LT1999C .................................................. 0°C to 70°C
LT1999I................................................–40°C to 85°C
LT1999H ............................................ –40°C to 125°C
LT1999MP ......................................... –55°C to 150°C
Junction Temperature ........................................... 150°C
Storage Temperature Range .................. –65°C to 150°C
+
Total Supply Voltage (V to GND)................................6V
+
Input Voltage Pins 6 and 8 ...................V + 0.3V, –0.3V
Output Short-Circuit Duration (Note 4) ............ Indefinite
Operating Ambient Temperature (Note 5)
LT1999C ..............................................–40°C to 85°C
LT1999I................................................–40°C to 85°C
LT1999H ............................................ –40°C to 125°C
LT1999MP ......................................... –55°C to 150°C
PIN CONFIGURATION
ORIGINAL MSOP PINOUT
MSOP PINOUT ENGINEERED FOR FMEA
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SHDN
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ꢏꢍꢓ ꢄꢆEꢔ
ꢅ
ꢓꢌꢑ
ꢔꢌꢑ
ꢄ
ꢀ
ꢉ SHDN
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ꢋ REꢐ
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ꢊ SHDN
ꢋ ꢎꢏꢐ
ꢌ REꢑ
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ꢛꢜꢖꢝ
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ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
LTFPB
PACKAGE DESCRIPTION
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead MSOP FMEA Pinout
8-Lead MSOP FMEA Pinout
8-Lead MSOP FMEA Pinout
8-Lead MSOP FMEA Pinout
8-Lead Plastic SO
SPECIFIED TEMPERATURE RANGE
0°C to 70°C
LT1999CMS8-10#PBF
LT1999IMS8-10#PBF
LT1999HMS8-10#PBF
LT1999MPMS8-10#PBF
LT1999CMS8-10F#PBF
LT1999IMS8-10F#PBF
LT1999HMS8-10F#PBF
LT1999CMS8-10#TRPBF
LT1999IMS8-10#TRPBF
LT1999HMS8-10#TRPBF
LTFPB
–40°C to 85°C
–40°C to 125°C
–55°C to 150°C
0°C to 70°C
LTFPB
LT1999MPMS8-10#TRPBF LTFQP
LT1999CMS8-10F#TRPBF
LT1999IMS8-10F#TRPBF
LT1999HMS8-10F#TRPBF
LTGVB
LTGVB
LTGVB
–40°C to 85°C
–40°C to 125°C
–55°C to 150°C
0°C to 70°C
LT1999MPMS8-10F#PBF LT1999MPMS8-10F#TRPBF LTGVB
LT1999CS8-10#PBF
LT1999IS8-10#PBF
LT1999HS8-10#PBF
LT1999MPS8-10#PBF
LT1999CMS8-20#PBF
LT1999IMS8-20#PBF
LT1999HMS8-20#PBF
LT1999CS8-10#TRPBF
LT1999IS8-10#TRPBF
LT1999HS8-10#TRPBF
LT1999MPS8-10#TRPBF
LT1999CMS8-20#TRPBF
LT1999IMS8-20#TRPBF
LT1999HMS8-20#TRPBF
199910
199910
199910
99MP10
LTFNZ
8-Lead Plastic SO
–40°C to 85°C
–40°C to 125°C
–55°C to 150°C
0°C to 70°C
8-Lead Plastic SO
8-Lead Plastic SO
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
LTFNZ
–40°C to 85°C
–40°C to 125°C
LTFNZ
Rev. E
2
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
–55°C to 150°C
0°C to 70°C
LT1999MPMS8-20#PBF
LT1999CMS8-20F#PBF
LT1999IMS8-20F#PBF
LT1999HMS8-20F#PBF
LT1999MPMS8-20#TRPBF LTFQQ
8-Lead Plastic MSOP
8-Lead MSOP FMEA Pinout
8-Lead MSOP FMEA Pinout
8-Lead MSOP FMEA Pinout
8-Lead MSOP FMEA Pinout
8-Lead Plastic SO
LT1999CMS8-20F#TRPBF
LT1999IMS8-20F#TRPBF
LT1999HMS8-20F#TRPBF
LTGVC
LTGVC
LTGVC
–40°C to 85°C
–40°C to 125°C
–55°C to 150°C
0°C to 70°C
LT1999MPMS8-20F#PBF LT1999MPMS8-20F#TRPBF LTGVC
LT1999CS8-20#PBF
LT1999IS8-20#PBF
LT1999CS8-20#TRPBF
LT1999IS8-20#TRPBF
LT1999HS8-20#TRPBF
LT1999MPS8-20#TRPBF
LT1999CMS8-50#TRPBF
LT1999IMS8-50#TRPBF
LT1999HMS8-50#TRPBF
199920
199920
199920
99MP20
LTFPC
8-Lead Plastic SO
–40°C to 85°C
–40°C to 125°C
–55°C to 150°C
0°C to 70°C
LT1999HS8-20#PBF
LT1999MPS8-20#PBF
LT1999CMS8-50#PBF
LT1999IMS8-50#PBF
LT1999HMS8-50#PBF
LT1999MPMS8-50#PBF
LT1999CMS8-50F#PBF
LT1999IMS8-50F#PBF
LT1999HMS8-50F#PBF
8-Lead Plastic SO
8-Lead Plastic SO
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead MSOP FMEA Pinout
8-Lead MSOP FMEA Pinout
8-Lead MSOP FMEA Pinout
8-Lead MSOP FMEA Pinout
8-Lead Plastic SO
LTFPC
–40°C to 85°C
–40°C to 125°C
–55°C to 150°C
0°C to 70°C
LTFPC
LT1999MPMS8-50#TRPBF LTFQR
LT1999CMS8-50F#TRPBF
LT1999IMS8-50F#TRPBF
LT1999HMS8-50F#TRPBF
LTGVD
LTGVD
LTGVD
–40°C to 85°C
–40°C to 125°C
–55°C to 150°C
0°C to 70°C
LT1999MPMS8-50F#PBF LT1999MPMS8-50F#TRPBF LTGVD
LT1999CS8-50#PBF
LT1999IS8-50#PBF
LT1999CS8-50#TRPBF
LT1999IS8-50#TRPBF
LT1999HS8-50#TRPBF
LT1999MPS8-50#TRPBF
199950
199950
199950
99MP50
8-Lead Plastic SO
–40°C to 85°C
–40°C to 125°C
–55°C to 150°C
LT1999HS8-50#PBF
LT1999MPS8-50#PBF
AUTOMOTIVE PRODUCTS**
8-Lead Plastic SO
8-Lead Plastic SO
LT1999HMS8-10F#WPBF LT1999HMS8-10F#WTRPBF LTGVB
LT1999HMS8-20F#WPBF LT1999HMS8-20F#WTRPBF LTGVC
LT1999HMS8-50F#WPBF LT1999HMS8-50F#WTRPBF LTGVD
8-Lead MSOP FMEA Pinout
8-Lead MSOP FMEA Pinout
8-Lead MSOP FMEA Pinout
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. E
3
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
The ldenotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, 0°C < TA < 70°C for C-grade parts, –40°C < TA < 85°C for I-grade parts, and –40°C < TA < 125°C for H-grade parts, otherwise
specifications are at TA = 25°C. V+ = 5V, GND = 0V, VCM = 12V, VREF = floating, VSHDN = floating, unless otherwise specified. See Figure 2.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
V
Full-Scale Input Sense Voltage (Note 7)
SENSE
LT1999-10
LT1999-20
LT1999-50
–0.35
–0.2
–0.08
0.35
0.2
0.08
V
V
V
SENSE
V
= V – V
+IN –IN
l
l
V
CM Input Voltage Range
Differential Input Impedance
CM Input Impedance
–5
80
V
CM
R
R
ΔV
=
2V/Gain
6.4
8
9.6
kΩ
IN(DIFF)
INDIFF
l
l
ΔV = 5.5V to 80V
5
3.6
20
4.8
MΩ
kΩ
INCM
CM
ΔV = –5V to 4.5V
6
CM
V
Input Referred Voltage Offset
–750
–1500
500
750
1500
μV
μV
OSI
l
ΔV /ΔT
Input Referred Voltage Offset Drift
Gain
5
μV/°C
OSI
l
l
l
A
LT1999-10
LT1999-20
LT1999-50
9.95
19.9
49.75
10
20
50
10.05
20.1
50.25
V/V
V/V
V/V
V
l
A Error
V
Gain Error
ΔV
OUT
=
2V
–0.5
0.2
0.5
%
l
l
l
I
Input Bias Current
I(+IN) = I(–IN)
(Note 8)
V
V
V
> 5.5V
= –5V
SHDN
100
–2.35
137.5
–1.95
0.001
175
–1.5
2.5
μA
mA
μA
B
CM
CM
= 0.5V, 0V < V < 80V
CM
l
l
l
I
Input Offset Current
OS
(Note 8)
V
V
V
> 5.5V
–1
1
10
2.5
μA
μA
μA
OS
CM
CM
SHDN
+
I
= I(+IN) – I(–IN)
= –5V
–10
–2.5
= 0.5V, 0V < V < 80V
CM
l
PSRR
CMRR
Supply Rejection Ratio
Sense Input Common Mode Rejection
V = 4.5V to 5.5V
68
77
dB
l
l
l
l
V
V
V
V
= –5V to 80V
= –5V to 5.5V
96
96
75
80
105
120
90
dB
dB
dB
dB
CM
CM
CM
CM
= 12V, 7V , f = 100kHz,
P-P
P-P
= 0V, 7V , f = 100kHz
100
e
n
Differential Input Referred Noise Voltage Density
f = 10kHz
f = 0.1Hz to 10Hz
97
8
nV/√Hz
μV
P-P
+
REF
REF Pin Rejection, V = 5.5V
RR
l
l
l
ΔV = 3.0V
LT1999-10
LT1999-20
LT1999-50
62
62
62
70
70
70
dB
dB
dB
REF
REF
REF
ΔV = 3.25V
ΔV = 3.25V
l
l
R
REF Pin Input Impedance
60
80
100
kΩ
REF
V
V
= 0.5V
= 0.5V
0.15
0.4
0.65
MΩ
SHDN
l
l
V
V
Open Circuit Voltage
2.45
1
2.5
2.5
2.55
2.75
V
V
REF
SHDN
+
+
+
l
l
l
REF Pin Input Range (Note 9)
LT1999-10
LT1999-20
LT1999-50
1.25
1.125
1.125
V – 1.25
V
V
V
REFR
V – 1.125
V – 1.125
Rev. E
4
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
ELECTRICAL CHARACTERISTICS The ldenotes the specifications which apply over the full operating
temperature range, 0°C < TA < 70°C for C-grade parts, –40°C < TA < 85°C for I-grade parts, and –40°C < TA < 125°C for H-grade parts, otherwise
specifications are at TA = 25°C. V+ = 5V, GND = 0V, VCM = 12V, VREF = floating, VSHDN = floating, unless otherwise specified. See Figure 2.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
l
l
l
I
Pin Pull-Up Current
SHDN Pin Input High
SHDN Pin Input Low
Small Signal Bandwidth
V = 5.5V, V
= 0V
SHDN
–6
–2
μA
V
SHDN
+
V
V
V – 0.5
IH
IL
0.5
V
f
LT1999-10
LT1999-20
LT1999-50
2
2
1.2
MHz
MHz
MHz
3dB
SR
Slew Rate
3
V/μs
μs
t
t
Settling Time due to Input Step, ΔV
=
2V
0.5% Settling
2.5
s
r
OUT
Common Mode Step Recovery Time
ΔV 50V, 20ns
(Note 10)
LT1999-10
LT1999-20
LT1999-50
0.8
1
1.3
μs
μs
μs
=
CM
l
V
Supply Voltage (Note 11)
Supply Current
4.5
5
5.5
V
S
l
l
l
I
V
V
> 5.5V
= –5V
1.55
5.8
3
1.9
7.1
10
mA
mA
μA
S
CM
CM
+
V = 5.5V, V
= 0.5V, V > 0V
CM
SHDN
R
Output Impedance
ΔI = 2mA
0.15
31
Ω
mA
mA
O
O
l
l
I
I
Sourcing Output Current
Sinking Output Current
R
LOAD
R
LOAD
= 50Ω to GND
6
40
40
SRC
SNK
+
= 50Ω to V
15
26
+
l
l
V
Swing Output High (with Respect to V )
R
LOAD
R
LOAD
= 1kΩ to Mid-Supply
= Open
125
5
250
125
mV
mV
OUT
–
l
l
Swing Output Low (with Respect to V )
R
LOAD
R
LOAD
= 1kΩ to Mid-Supply
= Open
250
150
400
225
mV
mV
t
t
Turn-On Time
Turn-Off Time
V
SHDN
V
SHDN
= 0V to 5V
= 5V to 0V
1
1
μs
μs
ON
OFF
Rev. E
5
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, –55°C < TA < 150°C for MP-grade parts, otherwise specifications are at TA = 25°C. V+ = 5V, GND = 0V, VCM = 12V,
VREF = floating, VSHDN = floating, unless otherwise specified. See Figure 2.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
V
Full-Scale Input Sense Voltage (Note 7)
= V – V
LT1999-10
LT1999-20
LT1999-50
–0.35
–0.2
–0.08
0.35
0.2
0.08
V
V
V
SENSE
V
SENSE
+IN
–IN
l
l
V
CM Input Voltage Range
Differential Input Impedance
CM Input Impedance
–5
80
V
CM
R
R
ΔV
=
2V/GAIN
6.4
8
9.6
kΩ
IN(DIFF)
INDIFF
l
l
ΔV = 5.5V to 80V
5
3.6
20
4.8
MΩ
kΩ
INCM
CM
ΔV = –5V to 4.5V
6
CM
V
Input Referred Voltage Offset
–750
–2000
500
750
2000
μV
μV
OSI
l
ΔV /ΔT Input Referred Voltage Offset Drift
OSI
8
μV/°C
l
l
l
A
Gain
LT1999-10
LT1999-20
LT1999-50
9.95
19.9
49.75
10
20
50
10.05
20.1
50.25
V/V
V/V
V/V
V
l
A Error
V
Gain Error
ΔV
=
OUT
2V
–0.5
0.2
0.5
%
l
l
l
I
Input Bias Current
I(+IN) = I(–IN)
(Note 8)
V
V
V
> 5.5V
= –5V
SHDN
100
–2.35
137.5
–1.95
0.001
180
–1.5
10
μA
mA
μA
B
CM
CM
= 0.5V, 0V < V < 80V
CM
l
l
l
I
Input Offset Current
OS
(Note 8)
V
V
V
> 5.5V
–1
1
10
10
μA
μA
μA
OS
CM
CM
SHDN
+
I
= I(+IN) – I(–IN)
= –5V
–10
–10
= 0.5V, 0V < V < 80V
CM
l
PSRR
CMRR
Supply Rejection Ratio
Sense Input Common Mode Rejection
V = 4.5V to 5.5V
68
77
dB
l
l
l
l
V
V
V
V
= –5V to 80V
= –5V to 5.5V
96
96
75
80
105
120
90
dB
dB
dB
dB
CM
CM
CM
CM
= 12V, 7V , f = 100kHz,
P-P
P-P
= 0V, 7V , f = 100kHz
100
e
n
Differential Input Referred Noise Voltage Density f= 10kHz
f = 0.1Hz to 10Hz
97
8
nV/√Hz
μV
P-P
+
REF
REF Pin Rejection, V = 5.5V
ΔV = 2.75V
RR
l
l
l
LT1999-10
LT1999-20
LT1999-50
62
62
62
70
70
70
dB
dB
dB
REF
ΔV = 3.25V
ΔV = 3.25V
REF
REF
l
l
R
REF
REF Pin Input Impedance
60
0.15
80
0.4
100
0.65
kΩ
MΩ
V
= 0.5V
SHDN
l
l
V
V
Open Circuit Voltage
2.45
0.25
2.5
2.5
2.55
2.75
V
V
REF
V
= 0.5V
SHDN
+
+
+
l
l
l
REF Pin Input Range (Note 9)
LT1999-10
LT1999-20
LT1999-50
1.5
1.125
1.125
V – 1.25
V
V
V
REFR
V – 1.125
V – 1.125
+
l
l
l
I
Pin Pull-Up Current
SHDN Pin Input High
SHDN Pin Input Low
Small Signal Bandwidth
V = 5.5V, V
= 0V
SHDN
–6
–2
μA
V
SHDN
+
V
V
V – 0.5
IH
IL
0.5
V
f
LT1999-10
LT1999-20
LT1999-50
2
2
1.2
MHz
MHz
MHz
3dB
SR
Slew Rate
3
V/μs
μs
t
Settling Time Due to Input Step, ΔV
=
2V
0.5% Settling
2.5
S
OUT
Rev. E
6
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
The l denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, –55°C < TA < 150°C for MP-grade parts, otherwise specifications are at TA = 25°C. V+ = 5V, GND = 0V, VCM = 12V,
VREF = floating, VSHDN = floating, unless otherwise specified. See Figure 2.
SYMBOL PARAMETER
Common Mode Step Recovery Time
ΔV 50V, 20ns
(Note 10)
CONDITIONS
MIN
TYP
MAX
UNITS
t
LT1999-10
LT1999-20
LT1999-50
0.8
1
1.3
μs
μs
μs
r
=
CM
l
V
Supply Voltage (Note 11)
Supply Current
4.5
5
5.5
V
S
l
l
l
I
S
V
V
> 5.5V
= –5V
1.55
5.8
3
1.9
7.1
25
mA
mA
μA
CM
CM
+
V = 5.5V, V
= 0.5V, V > 0V
CM
SHDN
R
Output Impedance
ΔI = 2mA
0.15
31
Ω
mA
mA
O
O
l
l
I
I
Sourcing Output Current
Sinking Output Current
R
LOAD
R
LOAD
= 50Ω to GND
3
40
40
SRC
SNK
+
= 50Ω to V
10
26
+
l
l
V
Swing Output High (with Respect to V )
R
LOAD
R
LOAD
= 1kΩ to Mid-Supply
= Open
125
5
250
125
mV
mV
OUT
–
l
l
Swing Output Low (with Respect to V )
R
LOAD
R
LOAD
= 1kΩ to Mid-Supply
= Open
250
150
400
225
mV
mV
t
t
Turn-On Time
Turn-Off Time
V
SHDN
V
SHDN
= 0V to 5V
= 5V to 0V
1
1
μs
μs
ON
OFF
Note 1: Stresses beyond those listed underAbsolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Pin 2 (+IN) and Pin 3 (–IN) are protected by ESD voltage clamps
which have asymmetric bidirectional breakdown characteristics with respect
to the GND pin (Pin 5). These pins can safely support common mode
voltages which vary from –5.25V to 88V without triggering an ESD clamp.
Note 3: Exposure to differential sense voltages exceeding the normal
operating range for extended periods of time may degrade part
performance. A heat sink may be required to keep the junction temperature
below the Absolute Maximum Rating when the inputs are stressed
differentially. The amount of power dissipated in the LT1999 due to input
Note 7: Full-scale sense (V
differential input that can be applied with better than 0.5% gain accuracy.
Gain accuracy is degraded when the output saturates against either power
) gives indication of the maximum
SENSE
+
supply rail. V
is verified with V = 5.5V, V = 12V, with the REF pin
SENSE
CM
set to it’s voltage range limits. The maximum V
REF pin set to it’s minimum specified limit, verifying the gain error is less
than 0.5% at the output. The minimum V is verified with the REF pin
set to its maximum specified limit, verifying the gain error at the output is
less than 0.5%. See Note 9 for more information.
is verified with the
SENSE
SENSE
Note 8: I is defined as the average of the input bias currents to the +IN
B
and –IN pins (Pins 2 and 3). A positive current indicates current flowing
into the pin. I is defined as the difference of the input bias currents.
OS
I
= I(+IN) – I(–IN)
OS
overdrive can be approximated by:
Note 9: The REF pin voltage range is the minimum and maximum limits
that ensures the input referred voltage offset does not exceed 3mV over
the I, C, and H temperature ranges, and 3.5mV over the MP temperature
range.
2
V
+IN − V−IN
(
=
)
PDISS
8kΩ
Note 4: A heat sink may be required to keep the junction temperature
Note 10: Common mode recovery time is defined as the time it takes the
output of the LT1999 to recover from a 50V, 20ns input common mode
voltage transition, and settle to within the DC amplifier specifications.
below the absolute maximum rating.
Note 5: The LT1999C/LT1999I are guaranteed functional over the operating
temperature range –40°C to 85°C. The LT1999H is guaranteed functional
over the operating temperature range –40°C to 125°C. The LT1999MP is
guaranteed functional over the operating temperature range –55°C to 150°C.
Junction temperatures greater than 125°C will promote accelerated aging.
The LT1999 has a demonstrated typical life beyond 1000 hours at 150°C.
+
Note 11: Operating the LT1999 with V < 4.5V is possible, although the
LT1999 is not tested or specified in this condition. See the Applications
Information section.
Note 6: The LT1999C is guaranteed to meet specified performance from
0°C to 70°C. The LT1999C is designed, characterized, and expected to
meet specified performance from –40°C to 85°C but is not tested or
QA sampled at these temperatures. The LT1999I is guaranteed to meet
specified performance from –40°C to 85°C. The LT1999H is guaranteed
to meet specified performance from –40°C to 125°C. The LT1999MP is
guaranteed to meet specified performance from –55°C to 150°C.
Rev. E
7
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current
vs Input Common Mode
Supply Current vs Temperature
Supply Current vs Supply Voltage
ꢎ.ꢏ
ꢎ.ꢐ
ꢎ.ꢑ
ꢎ.ꢊ
ꢎ.ꢒ
ꢏ.ꢌ
ꢐ.ꢓ
ꢐ.ꢌ
ꢒ.ꢓ
ꢒ.ꢌ
ꢑ.ꢓ
ꢑ.ꢌ
ꢌ.ꢓ
ꢌ
ꢋ
ꢌ
ꢆ
ꢍ
ꢏ
ꢎ
ꢐ
ꢑ
ꢕ
ꢑꢓꢌꢘꢕ
ꢑꢐꢌꢘꢕ
ꢔꢌꢘꢕ
ꢒꢓꢘꢕ
ꢙꢏꢓꢘꢕ
ꢙꢓꢓꢘꢕ
ꢘ
ꢘ
ꢘ
ꢚ ꢛꢂEꢜ
ꢚ ꢓꢘ
ꢅ
ꢗ ꢑꢒꢅ
SHDN
ꢕꢖ
ꢀ
ꢖ ꢆꢀ
ꢋꢜꢝꢋꢞꢞ
ꢚ ꢎꢔꢘ
ꢇꢁ
ꢙ
ꢙ
ꢘ
ꢘ
ꢚ ꢊ.ꢊꢘ
ꢚ ꢒ.ꢊꢘ
ꢉꢊꢊ ꢉꢗꢓ ꢉꢊ ꢔꢓ ꢒꢊ ꢐꢓ ꢕꢊ ꢎꢔꢓ ꢎꢒꢊ
ꢌ
ꢑ
ꢒ
ꢐ
ꢏ
ꢓ
ꢅꢆ
ꢆ
ꢐꢆ ꢎꢆ ꢏꢆ ꢍꢆ ꢆꢆ ꢌꢆ ꢋꢆ ꢔꢑ
ꢃꢀꢄ
ꢀEꢁꢂERꢃꢀꢄRE ꢅꢆꢇꢈ
ꢀꢁꢂꢂꢃꢄ ꢅꢆꢃꢇꢈꢉE ꢊꢅꢋ
ꢀ
ꢁꢂ
ꢎꢕꢕꢕ ꢖꢓꢔ
ꢑꢔꢔꢔ ꢉꢌꢐ
ꢐꢒꢒꢒ ꢓꢑꢐ
Supply Current
Shutdown Supply Current
vs Temperature
Shutdown Input Bias Current
vs Input Common Mode
vs SHDN Pin Voltage
ꢈꢃ
ꢈ
ꢎꢏ
ꢐ
ꢊꢅꢅꢅ
ꢊꢅꢅ
ꢊꢅ
ꢑ
ꢔ
ꢘ
ꢘ
ꢘ
ꢚ ꢏꢘ
ꢚ ꢏꢘ
ꢀ
ꢀ
ꢀ
ꢒ ꢓꢀ
SHDN
ꢀ
ꢀ
ꢐ ꢍꢀ
ꢐ ꢈꢉꢀ
ꢖ
ꢖ
ꢖ
ꢒ ꢊꢓꢅꢘꢁ
ꢉ
ꢒ ꢅꢀ
ꢒ ꢅꢀ
ꢋꢛꢜꢋꢝꢝ
SHDN
ꢔEꢕꢔE
ꢒꢕ
ꢚ ꢎꢒꢘ
ꢇꢁ
ꢒꢊꢙꢅꢘꢁ
ꢒꢊꢊꢅꢘꢁ
ꢉ
ꢓ
ꢉ
ꢃ.ꢈ
ꢙ
ꢙ
ꢏ
ꢐ ꢈꢍꢃꢑꢒ
ꢘ
ꢘ
ꢚ ꢊ.ꢊꢘ
ꢚ ꢑ.ꢊꢘ
ꢇ
ꢑ
ꢖ
ꢖ
ꢒ ꢍꢅꢘꢁ
ꢒ ꢗꢅꢘꢁ
ꢉ
ꢉ
ꢃ.ꢃꢈ
ꢃ.ꢃꢃꢈ
ꢒ
ꢏ
ꢐ ꢓꢍꢍꢑꢒ
ꢇ
ꢏ
ꢐ ꢉꢍꢑꢒ
ꢉ
ꢇ
ꢏ
ꢊ
ꢃ
ꢈ
ꢎ
ꢁꢀꢂ
ꢊ
ꢍ
ꢉꢊꢊ ꢉꢗꢏ ꢉꢊ ꢒꢏ ꢑꢊ ꢔꢏ ꢕꢊ ꢎꢒꢏ ꢎꢑꢊ
ꢅ
ꢐꢅ
ꢋꢅ
ꢀ
ꢁꢂ
ꢏꢅ
ꢃꢀꢄ
ꢌꢅ
ꢊꢅꢅ
ꢀ
ꢀEꢁꢂERꢃꢀꢄRE ꢅꢆꢇꢈ
SHDN
ꢈꢋꢋꢋ ꢌꢃꢊ
ꢎꢕꢕꢕ ꢖꢏꢊ
ꢊꢍꢍꢍ ꢎꢅꢏ
Input Bias Current
vs Input Common Mode
Input Impedance
vs Input Common Mode Voltage
Input Bias Current vs Temperature
ꢋ.ꢆ
ꢋ
ꢎꢏꢐ
ꢎꢏꢏ
ꢎꢏꢔ
ꢎꢏꢑ
ꢎꢒꢓ
ꢎꢒꢐ
ꢎꢒꢏ
ꢎꢒꢔ
100000
10000
1000
100
ꢕ
ꢘ
ꢘ
ꢘ
ꢙ ꢚꢂEꢛ
ꢙ ꢑꢘ
SHDN
ꢀ
ꢖ ꢆꢀ
ꢋꢛꢜꢋꢝꢝ
ꢞ
ꢙ ꢊꢘ
COMMON MODE INPUT
IMPEDANCE
ꢘ
ꢘ
ꢙ ꢓꢑꢘ
ꢅꢋ.ꢆ
ꢅꢌ.ꢋ
ꢅꢌ.ꢆ
ꢅꢍ.ꢋ
ꢇꢁ
ꢇꢁ
ꢙ ꢊ.ꢊꢘ
DIFFERENTIAL INPUT IMPEDANCE
10
1
ꢅꢆ
ꢆ
ꢌꢆ ꢍꢆ ꢔꢆ ꢎꢆ ꢆꢆ ꢏꢆ ꢒꢆ ꢓꢋ
ꢃꢀꢄ
ꢉꢊꢊ ꢉꢒꢑ ꢉꢊ ꢔꢑ ꢏꢊ ꢕꢑ ꢖꢊ ꢎꢔꢑ ꢎꢏꢊ
–5
5
15 25 35 45 55 65 75
(V)
ꢀ
ꢀEꢁꢂERꢃꢀꢄRE ꢅꢆꢇꢈ
V
ꢁꢂ
CM
ꢌꢐꢐꢐ ꢑꢋꢒ
ꢎꢖꢖꢖ ꢗꢑꢓ
1999 G09
Rev. E
8
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
TYPICAL PERFORMANCE CHARACTERISTICS
Input Referred Voltage Offset
Input Referred Voltage Offset
vs Input Common Mode Voltage
vs Temperature and Gain Option
ꢋꢆꢌꢌ
ꢐꢊꢑꢑ
ꢐꢑꢑꢑ
ꢊꢑꢑ
ꢔ
ꢀ
ꢖ
ꢕ ꢆꢀ
ꢕ ꢎꢆꢘꢁ
ꢋ
ꢚ ꢐꢓꢋ
ꢇꢁ
ꢐꢓ ꢄꢛꢎꢀꢍ ꢂꢘꢌꢀꢀEꢜ
ꢗ
ꢋꢌꢌꢌ ꢋꢎ ꢙꢚꢉꢖꢈ ꢛꢜꢇꢖꢖEꢝ
ꢆꢌꢌ
ꢌ
ꢑ
ꢅꢆꢌꢌ
ꢉꢊꢑꢑ
ꢉꢐꢑꢑꢑ
ꢉꢐꢊꢑꢑ
ꢜꢖꢋꢐꢐꢐꢞꢋꢌ
ꢜꢖꢋꢐꢐꢐꢞꢎꢌ
ꢜꢖꢋꢐꢐꢐꢞꢆꢌ
ꢅꢋꢌꢌꢌ
ꢅꢋꢆꢌꢌ
ꢘꢀꢐꢔꢔꢔꢙꢐꢑ
ꢘꢀꢐꢔꢔꢔꢙꢓꢑ
ꢘꢀꢐꢔꢔꢔꢙꢊꢑ
ꢅꢆ
ꢆ
ꢋꢆ ꢎꢆ ꢓꢆ ꢍꢆ ꢆꢆ ꢏꢆ ꢒꢆ
ꢉꢊꢊ ꢉꢗꢑ ꢉꢊ ꢓꢑ ꢖꢊ ꢒꢑ ꢔꢊ ꢐꢓꢑ ꢐꢖꢊ
ꢀ
ꢃꢀꢄ
ꢀEꢁꢂERꢃꢀꢄRE ꢅꢆꢇꢈ
ꢁꢂ
ꢋꢐꢐꢐ ꢑꢋꢋ
ꢐꢔꢔꢔ ꢕꢐꢑ
LT1999-20 Small Signal
Frequency Response
LT1999-10 Small Signal
Frequency Response
ꢔꢕ
ꢔꢗ
ꢖꢕ
ꢖꢗ
ꢋꢕ
ꢋꢗ
ꢕ
ꢋꢙꢗ
ꢋꢔꢕ
ꢛꢗ
ꢔꢕ
ꢋꢙꢕ
ꢋꢔꢖ
ꢛꢕ
ꢘꢖ
ꢘꢕ
ꢋꢖ
ꢋꢕ
ꢖ
ꢌꢍꢎꢃ
ꢌꢍꢎꢃ
ꢚꢕ
ꢚꢖ
ꢑꢈꢍꢒE
ꢑꢈꢍꢒE
ꢗ
ꢕ
ꢘꢚꢕ
ꢘꢛꢗ
ꢘꢋꢔꢕ
ꢘꢋꢙꢗ
ꢗꢚꢖ
ꢗꢛꢕ
ꢗꢋꢔꢖ
ꢗꢋꢙꢕ
ꢕ
ꢗ
ꢗꢖ
ꢗꢋꢕ
ꢜ
ꢟ ꢗ.ꢕꢜ ꢍꢞ ꢋꢇꢈꢉ
ꢑꢠꢑ
ꢜ
ꢟ ꢕ.ꢖꢜ ꢍꢞ ꢋꢇꢈꢉ
ꢝꢂꢞ
ꢝꢂꢞ
ꢑꢠꢑ
ꢘꢕ
ꢋ
ꢋꢗ
ꢋꢗꢗ
ꢋꢗꢗꢗ
ꢋꢗꢗꢗꢗ
ꢋ
ꢋꢕ
ꢋꢕꢕ
ꢋꢕꢕꢕ
ꢋꢕꢕꢕꢕ
ꢀREꢁꢂEꢃꢄꢅ ꢆꢇꢈꢉꢊ
ꢀREꢁꢂEꢃꢄꢅ ꢆꢇꢈꢉꢊ
ꢋꢛꢛꢛ ꢌꢋꢔ
ꢋꢛꢛꢛ ꢌꢋꢘ
Gain Error
vs Input Common Mode Voltage
LT1999-50 Small Signal
Frequency Response
Gain Error vs Temperature
ꢔꢕ
ꢘꢗ
ꢘꢕ
ꢖꢗ
ꢖꢕ
ꢋꢗ
ꢋꢕ
ꢗ
ꢋꢙꢕ
ꢋꢘꢗ
ꢛꢕ
ꢍ.ꢆꢍ
ꢍ.ꢎꢆ
ꢍ
ꢐ.ꢊꢐ
ꢐ.ꢑꢊ
ꢐ
ꢕ
ꢀ
ꢗ
ꢖ ꢆꢀ
ꢗ
ꢘ ꢓꢑꢗ
ꢇꢁ
ꢌꢍꢎꢃ
ꢖ ꢎꢆꢘꢁ
ꢓꢑ ꢄꢍꢌꢀꢙ ꢂꢚꢎꢀꢀEꢛ
ꢈ
ꢑꢎ ꢙꢊꢉꢗꢚ ꢛꢜꢋꢗꢗEꢝ
ꢔꢗ
ꢑꢈꢍꢒE
ꢕ
ꢚꢔꢗ
ꢚꢛꢕ
ꢚꢋꢘꢗ
ꢅꢍ.ꢎꢆ
ꢅꢍ.ꢆꢍ
ꢉꢐ.ꢑꢊ
ꢉꢐ.ꢊꢐ
ꢚꢀꢓꢔꢔꢔꢜꢓꢐ
ꢚꢀꢓꢔꢔꢔꢜꢑꢐ
ꢚꢀꢓꢔꢔꢔꢜꢊꢐ
ꢜꢗꢑꢒꢒꢒꢞꢑꢍ
ꢜꢗꢑꢒꢒꢒꢞꢎꢍ
ꢜꢗꢑꢒꢒꢒꢞꢆꢍ
ꢜ
ꢟ ꢕ.ꢗꢜ ꢍꢞ ꢋꢇꢈꢉ
ꢑꢠꢑ
ꢝꢂꢞ
ꢕ
ꢚꢋꢙꢕ
ꢋ
ꢋꢕ
ꢋꢕꢕ
ꢋꢕꢕꢕ
ꢋꢕꢕꢕꢕ
ꢅꢆ
ꢆ
ꢑꢆ ꢎꢆ ꢔꢆ ꢏꢆ ꢆꢆ ꢐꢆ ꢓꢆ
ꢉꢊꢊ ꢉꢖꢐ ꢉꢊ ꢑꢐ ꢕꢊ ꢒꢐ ꢔꢊ ꢓꢑꢐ ꢓꢕꢊ
ꢀREꢁꢂEꢃꢄꢅ ꢆꢇꢈꢉꢊ
ꢀ
ꢃꢀꢄ
ꢁꢂ
ꢀEꢁꢂERꢃꢀꢄRE ꢅꢆꢇꢈ
ꢋꢛꢛꢛ ꢌꢋꢔ
ꢑꢒꢒꢒ ꢇꢑꢐ
ꢓꢔꢔꢔ ꢋꢓꢊ
Rev. E
9
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
TYPICAL PERFORMANCE CHARACTERISTICS
LT1999-10 Pulse Response
LT1999-20 Pulse Response
LT1999-50 Pulse Response
ꢉ
ꢉ
ꢉ
ꢋEꢌꢋE
ꢋEꢌꢋE
ꢋEꢌꢋE
ꢉ
ꢉ
ꢉ
ꢏꢐꢀ
ꢏꢐꢀ
ꢎꢏꢀ
ꢎꢑꢑꢑ ꢒꢎꢑ
ꢑꢒꢒꢒ ꢓꢑꢔ
ꢐꢑꢑꢑ ꢒꢐꢓ
ꢀꢁꢂE ꢃꢄꢅꢆꢇꢈꢁꢉꢊ
ꢀꢁꢂE ꢃꢄꢅꢆꢇꢈꢁꢉꢊ
ꢀꢁꢂE ꢃꢄꢅꢆꢇꢈꢁꢉꢊ
LT1999-20 2V Step Response
Settling Time
LT1999-10 2V Step Response
Settling Time
ꢇ.ꢈ
ꢇ.ꢌ
ꢉ.ꢈ
ꢉ.ꢌ
ꢋ.ꢈ
ꢋ.ꢌ
ꢊ.ꢈ
ꢊ.ꢌ
ꢌ.ꢈ
ꢌ.ꢋꢌ
ꢌ.ꢊꢈ
ꢌ.ꢊꢌ
ꢌ.ꢌꢈ
ꢌ
ꢎ.ꢏ
ꢎ.ꢒ
ꢐ.ꢏ
ꢐ.ꢒ
ꢑ.ꢏ
ꢑ.ꢒ
ꢇ.ꢏ
ꢇ.ꢒ
ꢒ.ꢏ
ꢒ.ꢇꢒꢒ
ꢒ.ꢒꢔꢏ
ꢒ.ꢒꢏꢒ
ꢒ.ꢒꢑꢏ
ꢒ
ꢀ
ꢁꢂꢃ
ꢀ
ꢁꢂꢃ
ꢍꢌ.ꢌꢈ
ꢍꢌ.ꢌꢊ
ꢍꢌ.ꢊꢈ
ꢍꢌ.ꢋꢌ
ꢓꢒ.ꢒꢑꢏ
ꢓꢒ.ꢒꢏꢒ
ꢓꢒ.ꢒꢔꢏ
ꢓꢒ.ꢇꢒꢒ
ꢁꢂꢃꢍꢂꢃ ERRꢁR
ꢁꢂꢃꢆꢂꢃ ERRꢁR
ꢇꢕꢕꢕ ꢖꢑꢒ
ꢍꢊ
ꢌ
ꢊ
ꢋ
ꢉ
ꢇ
ꢈ
ꢔ
ꢗ
ꢘ
ꢕ ꢊꢌ
ꢃꢄꢅE ꢆꢇꢈꢉꢊꢋꢄꢀꢌ
ꢃꢎꢏE ꢄꢊꢐꢑꢒꢓꢎꢀꢅ
ꢊꢕꢕꢕ ꢖꢋꢊ
LT1999-50 2V Step Response
Settling Time
CMRR vs Frequency
CMRR vs Frequency
ꢇ.ꢈ
ꢇ.ꢌ
ꢉ.ꢈ
ꢉ.ꢌ
ꢋ.ꢈ
ꢋ.ꢌ
ꢊ.ꢈ
ꢊ.ꢌ
ꢌ.ꢈ
ꢌ.ꢈꢌꢌ
ꢌ.ꢉꢎꢈ
ꢌ.ꢋꢈꢌ
ꢌ.ꢊꢋꢈ
ꢌ
ꢋꢏꢐ
ꢋꢐꢐ
ꢑꢐ
ꢓꢐ
ꢒꢐ
ꢏꢐ
ꢐ
ꢋꢏꢐ
ꢋꢐꢐ
ꢑꢐ
ꢓꢐ
ꢒꢐ
ꢏꢐ
ꢐ
ꢡꢛꢋꢔꢔꢔꢤꢋꢐ
ꢡꢛꢋꢔꢔꢔꢤꢏꢐ
ꢡꢛꢋꢔꢔꢔꢤꢚꢐ
ꢠꢚꢋꢔꢔꢔꢣꢋꢐ
ꢠꢚꢋꢔꢔꢔꢣꢏꢐ
ꢠꢚꢋꢔꢔꢔꢣꢙꢐ
ꢀ
ꢁꢂꢃ
ꢍꢌ.ꢊꢋꢈ
ꢍꢌ.ꢋꢈꢌ
ꢍꢌ.ꢉꢎꢈ
ꢍꢌ.ꢈꢌꢌ
ꢁꢂꢃꢆꢂꢃ ERRꢁR
ꢖ
ꢖ
ꢚ
ꢗ ꢐꢖ
ꢗ ꢙꢖ
ꢗ ꢏꢙꢜꢄ
ꢗ
ꢗ
ꢛ
ꢘ ꢋꢏꢗ
ꢘ ꢚꢗ
ꢘ ꢏꢚꢝꢄ
ꢄꢌ
ꢄꢌ
ꢘ
ꢙ
ꢛ
ꢜ
ꢓ ꢂꢃꢝꢚꢞ ꢟꢠꢡꢚꢚEꢢ
ꢓ ꢂꢃꢞꢛꢟ ꢠꢡꢢꢛꢛEꢣ
ꢊꢕꢕꢕ ꢖꢋꢋ
ꢋ
ꢋꢐ
ꢋꢐꢐ
ꢋꢐꢐꢐ
ꢋꢐꢐꢐꢐ
ꢋ
ꢋꢐ
ꢋꢐꢐ
ꢋꢐꢐꢐ
ꢋꢐꢐꢐꢐ
ꢃꢏꢐE ꢄꢊꢑꢒꢓꢔꢏꢀꢅ
ꢀREꢁꢂEꢃꢄꢅ ꢆꢇꢈꢉꢊ
ꢀREꢁꢂEꢃꢄꢅ ꢆꢇꢈꢉꢊ
ꢋꢔꢔꢔ ꢕꢏꢒ
ꢋꢔꢔꢔ ꢕꢏꢖ
Rev. E
10
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
TYPICAL PERFORMANCE CHARACTERISTICS
LT1999-10 Common Mode Rising
Edge Step Response
LT1999-10 Common Mode Falling
Edge Step Response
V
, t
≈ 20ns
CM RISE
V
, t
≈ 20ns
CM FALL
V
V
OUT
OUT
1999 G25
1999 G26
TIME (0.5µs/DIV)
TIME (0.5µs/DIV)
LT1999-20 Common Mode Rising
Edge Step Response
LT1999-20 Common Mode Falling
Edge Step Response
V
, t
≈ 20ns
CM RISE
V
, t
≈ 20ns
CM FALL
V
V
OUT
OUT
1999 G27
1999 G28
TIME (0.5µs/DIV)
TIME (0.5µs/DIV)
LT1999-50 Common Mode Rising
Edge Step Response
LT1999-50 Common Mode Falling
Edge Step Response
V
, t
≈ 20ns
CM RISE
V
, t
≈ 20ns
CM FALL
V
OUT
V
OUT
1999 G29
1999 G30
TIME (0.5µs/DIV)
TIME (0.5µs/DIV)
Rev. E
11
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
TYPICAL PERFORMANCE CHARACTERISTICS
LT1999 Input Referred Noise
Density vs Frequency
Short-Circuit Current
vs Temperature
REF Open Circuit Voltage
vs Temperature
ꢒ.ꢓ
ꢔ.ꢊ
ꢔ.ꢓ
ꢕ.ꢊ
ꢕ.ꢓ
ꢓ.ꢊ
ꢓ
1000
100
10
ꢎꢏ
ꢑꢏ
ꢃꢇꢀꢌꢎE ꢁꢏꢙE
SHDN ꢁꢏꢙE
ꢌꢋꢖꢗꢋꢖꢕ
ꢐꢏ
ꢒꢏ
ꢏ
ꢉꢒꢏ
ꢉꢐꢏ
ꢉꢑꢏ
ꢉꢎꢏ
ꢌꢘꢄRꢇꢋꢖꢕ
ꢚ
ꢎ
ꢛ ꢊꢎ
ꢉꢊꢊ ꢉꢒꢓ ꢉꢊ ꢔꢓ ꢘꢊ ꢖꢓ ꢗꢊ ꢕꢔꢓ ꢕꢘꢊ
0.001 0.01
0.1
1
10
1000 10000
ꢉꢊꢊ ꢉꢑꢏ ꢉꢊ ꢐꢏ ꢎꢊ ꢓꢏ ꢔꢊ ꢒꢐꢏ ꢒꢎꢊ
ꢀEꢁꢂERꢃꢀꢄRE ꢅꢆꢇꢈ
FREQUENCY (kHz)
ꢀEꢁꢂERꢃꢀꢄRE ꢅꢆꢇꢈ
ꢕꢗꢗꢗ ꢑꢒꢒ
1999 G31
ꢒꢔꢔꢔ ꢕꢑꢐ
SHDN Pin Current vs SHDN Pin
Voltage and Temperature
Turn-On/Turn-Off Time
vs SHDN Voltage
ꢃ
ꢇꢊ
ꢇꢈ
ꢇꢋ
ꢇꢉ
ꢓ
ꢈ
ꢚ ꢃꢛꢈ
ꢀ
ꢀ
ꢐ ꢌꢀ
ꢐ ꢊꢈꢀ
ꢙꢑ
ꢒꢔ
ꢀ
ꢁ
ꢏ
ꢐ ꢊꢌꢃꢑꢒ
ꢆ
ꢏ
ꢏ
ꢐ ꢈꢌꢑꢒ
ꢆ
ꢆ
ꢁꢖꢗꢎꢇꢌꢘꢋ
ꢐ ꢇꢌꢌꢑꢒ
ꢈ
SHDN
ꢃꢔꢔꢔ ꢏꢕꢐ
ꢃ
ꢊ
ꢈ
ꢋ
ꢉ
ꢌ
ꢎꢀꢑE ꢂꢃꢒꢓꢆꢇꢀꢈꢉ
ꢀ
ꢁꢀꢂ
SHDN
ꢊꢍꢍꢍ ꢎꢋꢉ
VOUT vs VSENSE Over the Sense
ABSMAX Range
VOUT vs VSENSE
ꢌ
ꢈ
ꢆ
ꢌ
ꢀ
ꢓ ꢇ.ꢈꢀ
ꢀ
ꢓꢔꢕꢁE REꢀERꢁꢕꢖ ꢗꢈR ꢀ
ꢘ ꢅꢎꢌꢀ
REꢒ
ꢈꢉꢊ
ꢁEꢂꢁE
ꢍ
ꢋ
ꢏ
ꢏ
ꢇ
ꢎ
ꢎ
ꢍ
ꢔꢋꢎꢐꢐꢐꢕꢎꢆ
ꢔꢋꢎꢐꢐꢐꢕꢇꢆ
ꢔꢋꢎꢐꢐꢐꢕꢈꢆ
ꢖꢊꢍꢐꢐꢐꢚꢍꢇ
ꢖꢊꢍꢐꢐꢐꢚꢎꢇ
ꢖꢊꢍꢐꢐꢐꢚꢌꢇ
ꢆ
ꢇ
ꢀ
ꢙ ꢎ.ꢌꢀ
REꢗ
ꢅꢎ
ꢅꢍ
ꢅꢆ.ꢇꢈ ꢅꢆ.ꢎꢈ ꢅꢆ.ꢆꢈ
ꢆ.ꢆꢈ
ꢃꢀꢄ
ꢆ.ꢎꢈ
ꢆ.ꢇꢈ
ꢅꢆꢇ
ꢅꢏꢇ
ꢇ
ꢏꢇ
ꢆꢇ
ꢀ
ꢀ
ꢃꢀꢄ
ꢁEꢂꢁE
ꢁEꢂꢁE
ꢎꢐꢐꢐ ꢑꢏꢌ
ꢍꢐꢐꢐ ꢑꢏꢒ
Rev. E
12
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
PIN FUNCTIONS (LT1999-XX/LT1999-XXF)
V (Pins 1, 4/Pin 4): Power Supply Voltage. Pins 1 and 4
are tied internally together. The specified range of opera-
tion is 4.5V to 5.5V, but lower supply voltages (down to
approximately 4V) is possible although the LT1999 is not
tested or characterized below 4.5V. See the Applications
Information section.
+
is mid-supply. It can be overdriven by an external voltage
source cable of driving 80k to a mid-supply potential (see
the Electrical Characteristics table for its specified input
voltage range).
OUT (Pin 7/Pin 7): Voltage Output. V
= A •(V
V SENSE
OUT
V
), where A is the gain, and V is the input referred
OSI
V OSI
+IN (Pin 2/Pin 1): Positive Sense Input Pin.
–IN (Pin 3/Pin 2): Negative Sense Input Pin.
NC (NA/Pin 3)
offset voltage. The output amplifier has a low impedance
output and is designed to drive up to 200pF capacitive
loads directly. Capacitive loads exceeding 200pF should
be decoupled with an external resistor of at least 100Ω.
GND (Pin 5/Pin 5): Ground Pin.
SHDN (Pin 8/Pin 8): Shutdown Pin. When pulled to within
0.5V of GND (Pin 5), will place the LT1999 into low power
shutdown. If the pin is left floating, an internal 2µA pull-
up current source will place the LT1999 into the active
(amplifying) state.
REF (Pin 6/Pin 6): Reference Pin Input. The REF pin
sets the output common mode level and is set halfway
+
between V and GND using a divider made of two 160k
resistors. The default open circuit potential of the REF pin
Rev. E
13
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
BLOCK DIAGRAM
ꢁ
ꢁ
ꢀ
ꢒ
ꢀ
ꢌꢍꢂꢆꢆꢆ
ꢌꢍꢂꢆꢆꢆꢎꢏꢏꢐ
ꢔꢅ
ꢔꢅ
ꢁ
ꢉꢊꢋ
ꢉꢊꢋ
ꢀ
ꢂ
ꢉ
ꢁ
ꢀ
ꢄ.ꢓꢅ
ꢄ.ꢓꢅ
ꢂ
ꢉ
ꢓ
ꢓ
SHDN
SHDN
R
R
ꢒ
ꢁ
ꢑ
ꢁ
ꢑ
ꢔꢅ
ꢔꢅ
ꢑ
ꢑ
ꢕ
ꢃ
ꢕ
ꢃ
ꢁ
ꢁ
ꢁ
ꢀ
ꢄ.ꢓꢅ
ꢄ.ꢓꢅ
ꢀꢁ
ꢀꢁ
ꢂꢃꢄꢅ
ꢂꢃꢄꢅ
ꢂꢃꢄꢅ
ꢂꢃꢄꢅ
ꢖ
ꢔ
ꢖ
ꢔ
ꢘꢙ
ꢁ
ꢁ
ꢀ
ꢀ
ꢗ
ꢗ
ꢂꢆꢆꢆ ꢇꢈ
ꢂꢆꢆꢆ ꢇꢈ
Figure 1. Simplified Block Diagram
TEST CIRCUIT
ꢐ
ꢐ
ꢕꢖ
ꢕꢖ
ꢁ
ꢁ
ꢔꢊꢂꢃꢃꢃ
ꢔꢊꢂꢃꢃꢃꢄ
ꢂ
ꢐ
ꢀꢁ
ꢁ
ꢐ
ꢐ
ꢁ
ꢆꢇꢙ
ꢆꢇꢙ
ꢅ.ꢗꢖ
ꢅ.ꢗꢖ
ꢐ
ꢑ
ꢂ
ꢆ
ꢗ
ꢛ
ꢗ
ꢛ
SHDN
SHDN
ꢁ
ꢁ
ꢁ
SHDN
SHDN
ꢋꢌꢍꢎꢋꢄꢄꢏ
ꢐ
ꢐ
ꢑ
R
ꢜ
ꢁ
R
ꢜ
ꢒꢓ
ꢐ
ꢑ
ꢑ
ꢐ
ꢑ
ꢑ
ꢆ
ꢕꢖ
ꢑ
ꢐ
ꢑ
ꢐ
ꢁ
ꢁ
ꢁ
ꢁ
ꢈꢉꢊ
REꢄ
ꢈꢉꢊ
ꢐ
ꢐ
ꢑ
ꢁ
ꢅ.ꢗꢖ
ꢅ.ꢗꢖ
ꢐ
ꢐ
ꢐ
ꢁ
ꢁ
ꢁ
ꢋꢌꢍꢎꢋꢄꢄꢏ
ꢚ
ꢌꢒ
ꢐ
ꢐ
ꢑ
ꢁ
ꢒꢓ
ꢑ
ꢂꢘꢅꢖ
ꢂꢘꢅꢖ
ꢂꢘꢅꢖ
ꢂꢘꢅꢖ
ꢑ
REꢄ
ꢕꢖ
ꢚ
ꢘ
ꢀ
ꢘ
ꢀ
ꢐ
ꢐ
ꢀꢁ
ꢀꢁ
ꢁ
ꢁ
ꢅ.ꢂꢇꢄ
ꢅ.ꢂꢇꢄ
ꢕ
ꢕ
ꢅ.ꢂꢇꢄ
ꢅ.ꢂꢇꢄ
ꢂꢃꢃꢃ ꢄꢅꢆ
ꢂꢃꢃꢃ ꢄꢅꢆ
Figure 2. Test Circuit
Rev. E
14
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
APPLICATIONS INFORMATION
The LT1999 current sense amplifier provides accurate
bidirectional monitoring of current through a user-
selected sense resistor. The voltage generated by the
current flowing in the sense resistor is amplified by a
fixed gain of 10V/V, 20V/V or 50V/V (LT1999-10, LT1999-
20, or LT1999-50 respectively) and is level shifted to the
OUT pin. The voltage difference and polarity of the OUT
pin with respect to REF (Pin 6) indicates magnitude and
direction of the current in the sense resistor.
FortheLT1999-10, RG isnominally40k. FortheLT1999-20,
R is nominally 80k, and for the LT1999-50, R is nomi-
G
G
nally 200k.
The voltage difference between the OUT pin and the REF
pin represent both polarity and magnitude of the sensed
voltage. The noninverting input of amplifier A is biased
O
+
by a resistive 160k to 160k divider tied between V and
GND to set the default REF pin bias to mid-supply.
+
Case 2: –5V < V < V
CM
THEORY OF OPERATION
For common mode inputs which transition or are set below
the supply voltage, diode D1 will turn on and will provide a
Refer to the Block Diagram (Figure 1.
source of current through R and R to bias the inputs
–
of transconductance amplif+ieSr G atSleast 2.25V above
+
Case 1: V < V < 80V
CM
IN
GND. The transition is smooth and continuous; there are
negligible changes to either gain or amplifier voltage off-
set. The only difference in amplifier operation is the bias
currents provided by D1 through R and R–S are steered
through the input pins, otherwise+aSmplifier operation is
identical. The inputs to transconductance amplifier GIN
are still forced to equal potentials forcing any differential
voltages appearing at the +IN and –IN pins into a dif-
ferential current. This differential current is combined,
level-shifted, and converted back into a voltage by trans-
resistance amplifier AO and Resistor RG. Resistors R+S
For input common mode voltages exceeding the power
supply, one can assume D1 ofFigure 1 is completely off.
The sensed voltage (VSENSE) is applied across Pin 2 (+IN)
and Pin 3 (–IN) to matched resistors R and R (nomi-
+
–
IN
+
nally 4k each). The opposite ends of R andIRN are
–
IN
IN
forced to equal potentials by transconductor G , which
IN
convert the differentially sensed voltage into a sensed
current. The sensed current in R and R is combined,
+
IN
–
IN
level-shifted, and converted back into a voltage by trans-
resistance amplifier AO and resistor RG. Amplifier AO
provides high open loop gain to accurately convert the
sensed current back into a voltage and to drive external
loads. The theoretical output voltage is determined by
and R are trimmed to match R and R respectively,
–
+
–
IN
IN
to prevSent common mode to differential conversion from
occurring (to the extent of the matched trim) when the
the sensed voltage (V ), and the ratio of two on-chip
SENSE
resistors:
+
input common mode transitions below V .
As described in case 1, the output is determined by the
sense voltage and the ratio of two on-chip resistors:
RG
VOUT − VREF = VSENSE
•
RIN
RG
RIN
VOUT − VREF = VSENSE
•
where
where
R
+IN + R−IN
RIN =
nominally 4k
2
R
+IN + R−IN
RIN =
2
Rev. E
15
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
APPLICATIONS INFORMATION
Input Common Mode Range
ꢑꢒ.ꢓ
ꢑꢒ.ꢔ
ꢑꢕ.ꢓ
ꢑꢕ.ꢔ
ꢑꢌ.ꢓ
ꢑꢌ.ꢔ
ꢑꢔ.ꢓ
ꢑꢔ.ꢔ
ꢑꢖ.ꢓ
The LT1999 was optimized for high common mode rejec
-
ꢛEꢃꢆꢏ ꢉRꢆꢁꢜꢝ ꢐꢜꢂꢁꢇ
ꢍꢆꢎꢎꢆꢜ ꢎꢆꢝE RꢈꢜꢉE
tion. Its input stage is balanced and fully differential,
designed to amplify differential signals and reject com-
mon mode signals. There is negligible crossover distor-
tion due to sense voltage reversals. The amplifier is most
linear in the zero-sense region.
ꢞ
ꢃꢐꢎꢐꢇEꢝ ꢛꢄ ꢅ
ꢀꢁꢂꢂꢃꢄ ꢅꢆꢃꢇꢈꢉE
ꢛEꢃꢆꢏ ꢉRꢆꢁꢜꢝ ꢐꢜꢂꢁꢇ
ꢍꢆꢎꢎꢆꢜ ꢎꢆꢝE RꢈꢜꢉE
ꢃꢐꢎꢐꢇEꢝ ꢛꢄ Eꢀꢝ ꢍꢃꢈꢎꢂꢀ
+
With the V supply configured within the specified and
+
ꢇꢄꢂꢐꢍꢈꢃ Eꢀꢝ ꢍꢃꢈꢎꢂ ꢅꢆꢃꢇꢈꢉE
tested range (4.5V < V < 5.5V), the LT1999’s common
mode range extends from –5V to 80V. Pushing +IN and
–IN beyond the limits specified in the Absolute Maximum
table can turn on the voltage clamps designed to protect
the +IN and –IN pins during ESD events.
ꢌ
ꢌ.ꢒꢔ
ꢌ.ꢔ
ꢌ.ꢗꢔ
ꢔ
ꢔ.ꢒꢔ
ꢔ.ꢔ
ꢀꢁꢂꢂꢃꢄ ꢅꢆꢃꢇꢈꢉE ꢊꢅꢋ
ꢘꢙꢙꢙ ꢚꢓꢕ
Figure 3. Lower Input Common Mode vs Supply Voltage
It is possible to operate the LT1999 on power supplies
as low as 4V (although it is not tested or specified below
4.5V). Operating the LT1999 on supplies below 4V will
produce erratic behavior. When operating the LT1999
with supplies as low as 4V, the common mode range for
inputs which extend below GND is reduced. Refer to the
Output Common Mode Range
The LT1999’s output common mode level is set by the
voltage on the REF pin. The REF pin sits in the middle of
a 160k to 160k voltage divider connected between V and
GND which sets the default open circuit potential of the
REF pin to mid-supply. It can be overdriven by an external
voltage source capable of driving 80k tied to a mid-supply
potential. See the Electrical Characteristics table for the
REF pin’s specified input voltage range.
+
+
Block Diagram (Figure 1). For inputs driven below V ,
diode D1 conducts. For proper operation, the input to the
transconductor V(G ) must be biased at approximately
+
IN
2.25V above the GND pin. V(G ) sits on the centertap
+
IN
of a voltage divider comprised of R and R V(G )
–
IN
Differential sampling of the OUT pin with respect the REF
pin provides the best noise immunity. Measurements of
the output voltage made differentially with respect to the
REF pin will provide the highest power supply and com-
mon mode rejection. Otherwise, power supply or GND
pin disturbances are divided by the REF pin’s voltage
divider and appear directly at the noninverting input of
+
+
S
IN
likewise sits in the middle of the voltage divider comprised
of R , and R ). The voltage on V(G ) input is given
–
–
+
IN
S
IN
by the following equation:
R+S
R+S + R+IN
R+IN
R+S + R+IN
V(G+IN)= V +IN
•
+ V+ −V
•
D1
the trans-resistance amplifier A and are not rejected.
O
Setting V(G+ ) = 2.25V, the ratio (R+ /R+ ) to 5, and VD1
IN
IN
S
If not driven by a low impedance (<100Ω), the REF pin
should be filtered with at least 1nF of capacitance to a
low impedance, low noise ground plane. This external
capacitance will also provide a charge reservoir during
high frequency sampling of the REF pin by ADC inputs
attached to this pin.
equal to 0.8V (cold temperatures), a plot of the lower input
common mode range plotted against supply is shown in
Figure 3.
Rev. E
16
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
APPLICATIONS INFORMATION
Shutdown Capability
bandwidth of the LT1999 that may introduce errors. The
pole is set by the following equation:
If SHDN (Pin 8) is driven to within 0.5V of GND, the LT1999
is placed into a low power shutdown state in which the
f = 1/(π•(R + R )•C ) ≈ 10MHz
+ –
filt IN IN F
+
part will draw about 3μA from the V supply. The input
Both the resistors and capacitors have a 15% variation
so the pole can vary by approximately 30% over manu-
facturing process and temperature variations.
pins (+IN and –IN) will draw approximately 1nA if biased
within the range of 0V to 80V (with no differential voltage
applied). If the input pins are pulled below the GND pin,
each input appears as a diode tied to GND in series with
approximately 4k of resistance. The REF pin appears as
approximately 0.4MΩ tied to a mid-supply potential. The
output appears as reverse biased diodes tied between the
The layout for lowest EMI/noise susceptibility is achieved
by keeping short direct connections and minimizing loop
areas (see Figure 4). If the user-supplied sense resistor
cannot be placed in close proximity to the LT1999, the
surface area of the loop comprising connections of +IN
to RSENSE and back to –IN should be minimized. This
+
output to either V or GND pins.
EMI Filtering and Layout Practices
requires routing PCB traces connecting +IN to R
SENSE
and –IN to RSENSE adjacent with one another with minimal
separation. The metal traces connecting +IN to the sense
resistor and –IN to the sense resistor should match and
use the same trace width.
An internal 1st order differential lowpass noise/EMI sup-
pression filter with a –3dB bandwidth of 10MHz (approxi-
mately 5× the LT1999’s –3dB bandwidth) is included to
help improve the LT1999’s EMI susceptibility and to assist
with the rejection of high frequency signals beyond the
+
Bypassing the V pin to the GND pin with a 0.1µF capaci-
tor with short wiring connection is recommended.
ꢖ
ꢑ
ꢗ
ꢠ
ꢟ
ꢡ
ꢢ
ꢣ
ꢤ
ꢥ
ꢚ
SHDN
ꢊꢁꢉ
REꢔ
ꢔRꢊꢍ ꢒꢇ ꢀꢊꢁRꢇE
ꢉꢊ ꢃꢊꢆꢒ
ꢑꢈꢎ
ꢓꢈꢎ
ꢒꢈꢔꢔEREꢎꢉꢈꢆꢃ
ꢆꢎꢆꢃꢊꢏ ꢊꢁꢉ
R
ꢀEꢎꢀE
ꢋ
ꢑ
ꢚ
ꢏꢎꢒ
ꢋꢋ
ꢀꢁꢂꢂꢃꢄ ꢅꢄꢂꢆꢀꢀ
ꢇꢆꢂꢆꢇꢈꢉꢊR
ꢗꢞꢞꢞ ꢔꢘꢟ
ꢋ ꢌEEꢂ ꢃꢊꢊꢂ ꢆREꢆ ꢇꢊꢍꢂRꢈꢀꢈꢎꢏ R
ꢆꢀ ꢀꢍꢆꢃꢃ ꢆꢀ ꢂꢊꢀꢀꢈꢅꢃE.
ꢐ ꢑꢈꢎ ꢆꢎꢒ ꢓꢈꢎ ꢂꢈꢎꢀ
ꢀEꢎꢀE
ꢋꢋREꢔ ꢅꢄꢂꢆꢀꢀ ꢉꢈEꢒ ꢉꢊ ꢆ ꢃꢊꢕ ꢎꢊꢈꢀEꢐ ꢃꢊꢕ ꢈꢍꢂEꢒꢆꢎꢇE
ꢀꢈꢏꢎꢆꢃ ꢏRꢊꢁꢎꢒ ꢂꢃꢆꢎE.
ꢖ ꢊꢂꢉꢈꢊꢎꢆꢃ ꢗꢘꢙꢔ ꢇꢆꢂꢆꢇꢈꢉꢊR ꢉꢊ ꢂREꢚEꢎꢉ ꢛꢚꢜꢛꢝ EꢒꢏEꢀ
ꢊꢎ ꢈꢎꢂꢁꢉ ꢇꢊꢁꢂꢃꢈꢎꢏ ꢉꢊ ꢔꢃꢊꢆꢉꢈꢎꢏ SHDN ꢂꢈꢎ.
Figure 4. Recommended Layout
Rev. E
17
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
APPLICATIONS INFORMATION
The REF pin should be either driven by a low source
impedance (<100Ω) or should be bypassed with at least
1nF to a low impedance, low noise, signal ground plane
Selection of the Current Sense Resistor
The external sense resistor selection presents a delicate
trade-off between power dissipation in the resistor and
current measurement accuracy.
+
(see Figure 4). Larger bypass capacitors on both V pins,
and the REF pin, will extend enhanced AC CMRR, and
PSRR performance to lower frequencies. Bypassing the
In high current applications, the user may want to mini-
mize the power dissipated in the sense resistor. The sense
resistor current will create heat and voltage loss, degrad-
ing efficiency. As a result, the sense resistor should be as
small as possible while still providing adequate dynamic
range required by the measurement. The dynamic range
is the ratio between the maximum accurately produced
signal generated by the voltage across the sense resis-
tor, and the minimum accurately reproduced signal. The
minimum accurately reproduced signal is primarily dic-
tated by the voltage offset of the LT1999. The maximum
accurately reproduced signal is dictated by the output
swing of the LT1999.
+
REF pin to a quiet ground plane filters the V pin or GND
pin noise that is sensed by the REF pin voltage divider and
applied to the noninverting input of output amplifier A .
O
Any common I•R drops generated by pulsating ground
currents in common with the REF pin filter capacitor can
compromise the filtering performance and should be
avoided.
If the SHDN pin is not driven and is left floating, routing
a PCB trace connecting Pins 1 and 8 under the part will
act as a shield, and will help limit edge coupling from the
inputs (Pins 2 and 3) to the SHDN pin. Periodic pulses on
the inputs with fast edges may glitch the high impedance
SHDN pin, periodically putting the part into low power
shutdown. Additional precaution against this may be
taken by adding an optional small (~10pF) capacitor may
Thus the dynamic range for the LT1999 can be thought of
the maximum sense voltage divided by the input referred
voltage offset or:
+
be tied between V (Pin 1) and Pin 8.
Finally, when connecting the LT1999 inputs to the sense
resistor, it is important to use good Kelvin sensing prac-
tices (sensing the resistor in a way that excludes PCB
trace I•R voltage drops). For sense resistors less than
1Ω, one might consider using a 4-wire sense resistor to
sense the resistive element accurately.
ΔVOUT(MAX)
Dynamic Range=
GAIN•VOSI
The above equation tells us that the dynamic range is
inversely proportional to the gain of the LT1999. Thus,
if accuracy is of greater importance than efficiency or
power loss, the LT1999-10 used with the highest valued
sense resistor possible is recommended. If efficiency,
heat generated, and power loss in the resistive shunt is
the primary concern, the LT1999-50 and the lowest value
sense resistor possible is recommended. The LT1999-20
is available for applications somewhere in between these
two extremes.
Rev. E
18
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LT1999-10/LT1999-20/
LT1999-50
APPLICATIONS INFORMATION
Pinout Option Engineered for FMEA (Failure Mode and
Effects Analysis)
The purpose of the FMEA is to emulate single faults and
determine whether or not they are destructive and/or
lead to conditions which could damage surrounding
components. The LT1999-XXF is configured as shown
in Figure 2, with an input common mode of either 12V
or 0V. Each pin is systematically shorted to its adjacent
pin (emulating solder bridging) and the resulting effects
recorded. Each pin is then opened (emulating a cold sol-
der joint) with the resulting effects recorded.
The LT1999 family of ICs is available with an 8-lead MSOP
pinout option engineered for FMEA (Failure Mode and
Effects Analysis): (LT1999-10F, LT1999-20F and the
LT1999-50F). See Figure 5 below.
The LT1999-XXF is designed to meet the most stringent
automotive requirements and to satisfactorily survive sin-
gle faults due to the most common PCB defects: 1) open
pins due to cold solder joints and 2) adjacent pin short cir-
cuits due to adjacent pin solder bridging. The No-Connect
Pin (Pin 3) has been inserted between the input pin (–IN)
In all instances, the LT1999-XXF recovers when these
fault conditions are removed. Furthermore, the output pin
(OUT) has been verified to never exceed the pin’s nominal
output range of 0V to 5V during fault testing.
+
and the V supply pin to isolate the input voltages which
may range from –5V to 80V from solder bridging to the
Table 1 lists the behavior which results from shorting
adjacent pins and Table 2 details the behavior from open-
ing any pin.
+
V supply (typically 5V). Pin 3 is not connected internally
to the die and should be left unconnected.
+
V
R
+IN
2µA
4.5k
2k
2k
2k
+IN
8
SHDN
1
0.8k
0.8k
R
G
+
–
C
F
+
G
V
4pF
–
+
2k
OUT
REF
–IN
NC
7
6
2
3
V+
R
–IN
300Ω
160k
160k
+
V
GND
5
4
1999 F05a
Figure 5. Simplified Block Diagram of the LT1999-XXF
Rev. E
19
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
APPLICATIONS INFORMATION
Table 1. Behavior due to Adjacent Pin-to-Pin Shorts for the LT1999-10F, LT1999-20F, or the LT1999-50F
+
Adjacent Pin Short Test: (V = 5V, Tested at V = 0V, V = 12V, V = 80V)
CM
CM
CM
Adjacent Pins
Shorted
Recovery when
PIN #
1 – 2
2 – 3
3 – 4
5 – 6
6 – 7
7 – 8
Fault is removed
BEHAVIOR
+IN – –IN
–IN – NC
YES
YES
YES
YES
YES
YES
V
approaches the voltage on pin V
.
OUT
REF
The circuit behaves normally.
The circuit behaves normally.
NC – V+
GND – REF
REF – OUT
OUT – SHDN
V
V
follows the voltage on Pin 6 or 0V.
approaches 5.0V
OUT
OUT
Supply Current drops by 5%.
Table 2. Behavior due to open pins for the LT1999-10F, LT1999-20F, or the LT1999-50F
+
Open Pin Test (V = 5V, Tested at V = 0V, V = 12V, V = 80V)
CM
CM
CM
Recovery when
Fault is removed
PIN #
Pin Opened
BEHAVIOR
+
1
+IN
YES
V
may go to either V or GND, depending on the voltage applied to –IN. Generally, for –5V< –IN< 4V,
OUT
OUT will be near 5V. For –IN > 5V, OUT will be near 0V. In the range of 4V < –IN < 5V, OUT may go to either
V or GND, depending on the voltage applied to –IN. The open input (+IN) is biased internal to the IC to one
+
+
diode below V .
+
2
–IN
NC
YES
V
may go to either V or GND, depending on the voltage applied to +IN. Generally, for –5V < +IN < 4V,
OUT
OUT will be near 0V. For +IN > 5V, OUT will be at 5V. In the range of 4V < –IN < 5V, OUT may go to either
V+ or GND, depending on the voltage applied to +IN. The open input (–IN) is biased internal to the IC to one
+
diode below V .
3
4
5
6
7
8
YES
YES
YES
YES
YES
YES
The circuit behaves normally.
+
V
The circuit will behave as if powered off.
OUT, REF will float up towards 3.9V.
GND
REF
The circuit behaves normally with more broadband noise on OUT.
OUT
No V
signal.
OUT
SHDN
The low power shutdown feature will not function, otherwise the circuit behaves normally in the active state.
FMEA information in this document (not limited to, but including the description of behavior under specific pin-connection conditions) is provided for
convenience only. Ultimately, the end-user is responsible for verifying proper and reliable operation in each actual application. Linear Technology assumes
no liability whatsoever with providing this information.
Rev. E
20
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LT1999-10/LT1999-20/
LT1999-50
APPLICATIONS INFORMATION
Fuse Monitor
power in the precision on-chip input resistors. Precaution
should be taken to prevent junction temperatures from
exceeding the Absolute Maximum ratings (see Note 3 in
the Electrical Characteristics section). Secondly, if the
load is inductive, and the fuse blows open without a clamp
diode, energy stored in the inductive load will be dissi-
pated in the LT1999, which could cause damage. A simple
steering diode as shown in Figure 6 will prevent this from
happening, and will protect the LT1999 from damage.
The inputs can be overdriven without fear of damaging
the LT1999. This makes the LT1999 ideal for monitoring
fuses if either +IN or –IN are shorted to ground while the
other is at the full common mode supply voltage (see
Figure 6). If the fuse in Figure 6 opens with the +IN tied
to the positive supply, the load will pull –IN to GND. The
+
output will be forced to the positive V supply rail. If it is
desired that the output be near ground if the fuse opens,
it is a simple matter of swapping the inputs. Precautions
should be followed: First, when the inputs are stressed
differentially due to the fuse blowing open, a large voltage
drop will be placed across the +IN to –IN pins, dissipating
Finally, the user should be aware that in fuse monitoring
applications with the sense voltage (V
= V – V
)
+
–
SENSE
IN
being driven in excess of –25V, the output of the LT19I9N9
will undergo phase reversal (seeFigure 7).
ꢐ
ꢀ
ꢖ
ꢀ
ꢅꢃꢆꢇꢇꢇ
ꢐ
ꢀ
ꢔꢀ
ꢍꢎꢏ
ꢆ
ꢍ
ꢋ
ꢓ
SHDN
ꢀ
ꢁꢘ ꢁꢄꢄ
ꢀ
SHDN
SHDN
R
ꢗ
ꢐ
ꢑ
ꢕ
ꢐ
ꢅꢁꢏꢙ
ꢈꢉ
ꢈꢉ
ꢀ
ꢐꢗꢘ
ꢑ
ꢐ
ꢀ
ꢀ
ꢐ
ꢀ
ꢀ
ꢁꢂꢃ
REꢄ
ꢁꢂꢃ
ꢀ
ꢊ.ꢋꢉ
ꢊ.ꢋꢉ
ꢄꢂꢖE
ꢀ
R
ꢖEꢘꢖE
ꢀ
ꢆꢌꢊꢉ
ꢆꢌꢊꢉ
ꢒ
ꢑꢗꢘ
REꢄ
ꢌ
ꢔ
ꢐ
ꢔꢀ
ꢀ
ꢊ.ꢆꢎꢄ
ꢖꢃEERꢗꢘꢕ
ꢙꢗꢁꢙE
ꢅꢁꢏꢙ
ꢈ
ꢊ.ꢆꢎꢄ
ꢆꢇꢇꢇ ꢄꢊꢔ
Figure 6. Using the LT1999 to Monitor a Fuse
ꢀ
ꢔꢕꢖꢁE REꢀERꢁꢖꢗ ꢓꢈR ꢀ
ꢘ ꢅꢙꢑꢀ
ꢈꢉꢊ
ꢁEꢂꢁE
ꢀ
ꢚ ꢙ.ꢑꢀ
REꢓ
ꢅꢆꢇ ꢅꢐꢑ ꢅꢏꢇ ꢅꢋꢑ
ꢀ
ꢇ
ꢋꢑ ꢏꢇ ꢐꢑ ꢆꢇ
ꢃꢀꢄ
ꢁEꢂꢁE
ꢋꢒꢒꢒ ꢓꢇꢆ
Figure 7. A Plot of the LT1999’s Output Voltage vs VSENSE (VSENSE = V+IN – V–IN).
In Applications Where the Sense Voltage Is Driven in Excess of –25V, the
Output of the LT1999 Will Undergo Phase Reversal
Rev. E
21
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
TYPICAL APPLICATIONS
Solenoid Current Monitor
Bidirectional PWM Motor Monitor
The solenoid of Figure 8 consists of a coil of wire in an
iron case with permeable plunger that acts as a mov-
able element. When the MOSFET turns on, the diode is
Pulse width modulation is commonly used to efficiently
vary the average voltage applied across a DC motor. The
H-bridge topology of Figure 10 allows full 4-quadrant
control: clockwise control, counter-clockwise control,
clockwise regeneration, and counter-clockwise regen-
eration. The LT1999 in conjunction with a non-inductive
current shunt is used to monitor currents in the rotor.
The LT1999 can be used to detect stuck rotors, provide
detection of overcurrent conditions in general, or provide
current mode feedback control.
reversed biased off, and current flows through R
to
SENSE
actuate the solenoid. If the MOSFET is turned off, the cur-
rent in the MOSFET is interrupted, but the energy stored
in the solenoid causes the diode to turn on and current
to freewheel in the loop consisting of the diode, R
and the solenoid.
SENSE
Figure 8 shows the LT1999 monitoring currents in a
ground referenced solenoid used when the coil is hard
tied to the case, and is tied to ground. Figure 9 shows a
supply referenced solenoid whose coil is insulated from
the case. The LT1999 will interface equally well to either
of these two configurations.
Figure 11 shows a plot of the output voltage of the LT1999.
ꢍ
ꢌ
ꢞ
ꢌ
ꢀꢁꢂꢃꢃꢃ
ꢍ
ꢌ
ꢛꢟꢟ
ꢑꢌ
ꢉꢊꢋ
ꢛꢝ
ꢂ
ꢉ
ꢇ
ꢐ
SHDN
ꢌ
SHDN
R
ꢍ
ꢎ
ꢒ
ꢍ
ꢄꢅ
ꢄꢅ
ꢌ
ꢍꢓꢝ
ꢎꢓꢝ
ꢎ
ꢍ
ꢍ
ꢌ
ꢌ
ꢛꢜꢁ
REꢟ
ꢌ
ꢆ.ꢇꢅ
ꢆ.ꢇꢅ
ꢉ.ꢑꢌ
ꢌ
ꢛꢜꢁ
ꢌ
R
ꢞEꢝꢞE
ꢞꢛꢀEꢝꢛꢓꢙ REꢀEꢋꢞEꢞ
ꢞꢛꢀEꢝꢛꢓꢙ ꢢꢀꢜꢝꢒER ꢢꢜꢀꢀꢞ ꢓꢝ
ꢂꢈꢆꢅ
ꢂꢈꢆꢅ
ꢌ
ꢏ
ꢈ
ꢑ
ꢑꢌ
ꢍ
ꢆ.ꢂꢊꢟ
ꢌ
ꢌ
ꢍꢓꢝ
ꢄ
ꢞꢛꢀEꢝꢛꢓꢙ
ꢆ.ꢂꢊꢟ
ꢂꢃꢃꢃ ꢟꢆꢐꢡ
ꢂꢃꢃꢃ ꢟꢆꢐꢠ
ꢁꢓꢔE ꢕꢑꢆꢖꢗꢘꢙꢓꢌꢚ
Figure 8. Solenoid Current Monitor for Ground Tied Solenoid. The Common Mode
Inputs to the LT1999 Switch Between VS and One Diode Drop Below Ground
Rev. E
22
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
TYPICAL APPLICATIONS
ꢍ
ꢌ
ꢀꢁꢂꢃꢃꢃ
ꢌ
ꢓ
ꢑꢌ
ꢍ
ꢉꢊꢋ
ꢌ
ꢇ
ꢐ
ꢂ
ꢉ
SHDN
ꢌ
SHDN
ꢓꢖꢀEꢗꢖꢘꢙ
ꢌ
R
ꢍ
ꢎ
ꢒ
ꢄꢅ
ꢍꢘꢗ
ꢎ
ꢍ
ꢍ
ꢌ
ꢌ
ꢌ
ꢖꢚꢁ
REꢔ
ꢆ.ꢇꢅ
ꢆ.ꢇꢅ
ꢉ.ꢑꢌ
ꢌ
ꢖꢚꢁ
ꢍ
ꢌ
R
ꢓEꢗꢓE
ꢓꢖꢀEꢗꢖꢘꢙ REꢀEꢋꢓEꢓ
ꢓꢖꢀEꢗꢖꢘꢙ ꢡꢀꢚꢗꢒER ꢡꢚꢀꢀꢓ ꢘꢗ
ꢂꢈꢆꢅ
ꢂꢈꢆꢅ
ꢄꢅ
ꢌ
ꢎꢘꢗ
ꢏ
ꢄ
ꢈ
ꢑ
ꢖꢗ
ꢑꢌ
ꢍ
ꢌ
ꢍꢘꢗ
ꢌ
ꢆ.ꢂꢊꢔ
ꢖꢔꢔ
ꢆ.ꢂꢊꢔ
ꢂꢃꢃꢃ ꢔꢆꢇꢢ
ꢂꢃꢃꢃ ꢔꢆꢇꢕ
ꢁꢘꢛE ꢜꢑꢆꢝꢞꢟꢙꢘꢌꢠ
Figure 9. Solenoid Current Monitor for Non-Grounded Solenoids. This Circuit Performs the
Same Function as Figure 7 Except One End of the Solenoid Is Tied to VS. The Common Mode
Voltage of Inputs of the LT1999 Switch Between Ground and One Diode Drop Above VS
Rev. E
23
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
TYPICAL APPLICATIONS
5V
+
+
V
V
LT1999-20
10µF
1
2
2µA
8
7
SHDN
V
V
V
SHDN
80k
0.1µF
+
–
24V
4k
4k
–
+
V
V
+
+IN
–IN
V
OUT
0.8k
0.8k
C4
+
1000µF
V
160k
160k
3
4
V
6
5
H-BRIDGE
BRIDGE
REF
0.1µF
5V
+
5V
V
PWM INPUT
DIRECTION
1999 F09
R
SENSE
0.025Ω
OUTA
OUTB
PWM IN
24V MOTOR
BRAKE INPUT
GND
Figure 10. Armature Current Monitor for DC Motor Applications
ꢊ
ꢌꢍꢀ
ꢄ.ꢓꢊ
ꢊ
ꢎꢁꢏ
ꢐꢑꢑꢑ ꢒꢐꢅ
ꢀꢁꢂE ꢃꢄꢅꢆꢇꢈꢉꢁꢊꢋ
Figure 11. LT1999 Output Waveforms for the Circuit of Figure 10
Rev. E
24
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
ꢄReꢩeꢪeꢫꢬe ꢓꢐꢗ ꢕꢙꢌ ꢭ ꢇꢍꢮꢇꢅꢮꢉꢎꢎꢇ Rev ꢌꢆ
ꢇ.ꢅꢅꢥ ꢇ.ꢉꢈꢣ
ꢄ.ꢇꢊꢍ .ꢇꢇꢍꢆ
ꢍ.ꢉꢇ
ꢄ.ꢈꢇꢉꢆ
ꢀꢑꢒ
ꢊ.ꢈꢇ ꢤ ꢊ.ꢡꢍ
ꢄ.ꢉꢈꢎ ꢤ .ꢉꢊꢎꢆ
ꢊ.ꢇꢇ ꢇ.ꢉꢇꢈ
ꢄ.ꢉꢉꢅ .ꢇꢇꢡꢆ
ꢄꢒꢂꢐE ꢊꢆ
ꢇ.ꢍꢈ
ꢄ.ꢇꢈꢇꢍꢆ
REꢛ
ꢇ.ꢎꢍ
ꢄ.ꢇꢈꢍꢎꢆ
ꢝꢁꢗ
ꢇ.ꢡꢈ ꢇ.ꢇꢊꢅ
ꢄ.ꢇꢉꢎꢍ .ꢇꢇꢉꢍꢆ
ꢐꢢꢃ
ꢅ
ꢣ ꢎ ꢍ
REꢗꢂꢀꢀEꢒꢕEꢕ ꢁꢂꢓꢕER ꢃꢏꢕ ꢓꢏꢢꢂꢚꢐ
ꢊ.ꢇꢇ ꢇ.ꢉꢇꢈ
ꢄ.ꢉꢉꢅ .ꢇꢇꢡꢆ
ꢄꢒꢂꢐE ꢡꢆ
ꢡ.ꢥꢇ ꢇ.ꢉꢍꢈ
ꢄ.ꢉꢥꢊ .ꢇꢇꢎꢆ
ꢕEꢐꢏꢑꢓ ꢧꢏꢨ
ꢇ.ꢈꢍꢡ
ꢄ.ꢇꢉꢇꢆ
ꢇꢦ ꢤ ꢎꢦ ꢐꢢꢃ
ꢌꢏꢚꢌE ꢃꢓꢏꢒE
ꢉ
ꢈ
ꢊ
ꢡ
ꢇ.ꢍꢊ ꢇ.ꢉꢍꢈ
ꢄ.ꢇꢈꢉ .ꢇꢇꢎꢆ
ꢉ.ꢉꢇ
ꢄ.ꢇꢡꢊꢆ
ꢀꢏꢞ
ꢇ.ꢅꢎ
ꢄ.ꢇꢊꢡꢆ
REꢛ
ꢕEꢐꢏꢑꢓ ꢧꢏꢨ
ꢇ.ꢉꢅ
ꢄ.ꢇꢇꢣꢆ
ꢁEꢏꢐꢑꢒꢌ
ꢃꢓꢏꢒE
ꢇ.ꢈꢈ ꢤ ꢇ.ꢊꢅ
ꢇ.ꢉꢇꢉꢎ ꢇ.ꢇꢍꢇꢅ
ꢄ.ꢇꢇꢥ ꢤ .ꢇꢉꢍꢆ
ꢄ.ꢇꢇꢡ .ꢇꢇꢈꢆ
ꢇ.ꢎꢍ
ꢄ.ꢇꢈꢍꢎꢆ
ꢝꢁꢗ
ꢐꢢꢃ
ꢀꢁꢂꢃ ꢄꢀꢁꢅꢆ ꢇꢈꢉꢊ REꢋ ꢌ
ꢒꢂꢐEꢔ
ꢉ. ꢕꢑꢀEꢒꢁꢑꢂꢒꢁ ꢑꢒ ꢀꢑꢓꢓꢑꢀEꢐERꢖꢄꢑꢒꢗꢘꢆ
ꢈ. ꢕRꢏꢙꢑꢒꢌ ꢒꢂꢐ ꢐꢂ ꢁꢗꢏꢓE
ꢊ. ꢕꢑꢀEꢒꢁꢑꢂꢒ ꢕꢂEꢁ ꢒꢂꢐ ꢑꢒꢗꢓꢚꢕE ꢀꢂꢓꢕ ꢛꢓꢏꢁꢘꢜ ꢃRꢂꢐRꢚꢁꢑꢂꢒꢁ ꢂR ꢌꢏꢐE ꢝꢚRRꢁ.
ꢀꢂꢓꢕ ꢛꢓꢏꢁꢘꢜ ꢃRꢂꢐRꢚꢁꢑꢂꢒꢁ ꢂR ꢌꢏꢐE ꢝꢚRRꢁ ꢁꢘꢏꢓꢓ ꢒꢂꢐ EꢞꢗEEꢕ ꢇ.ꢉꢍꢈꢟꢟ ꢄ.ꢇꢇꢎꢠꢆ ꢃER ꢁꢑꢕE
ꢡ. ꢕꢑꢀEꢒꢁꢑꢂꢒ ꢕꢂEꢁ ꢒꢂꢐ ꢑꢒꢗꢓꢚꢕE ꢑꢒꢐERꢓEꢏꢕ ꢛꢓꢏꢁꢘ ꢂR ꢃRꢂꢐRꢚꢁꢑꢂꢒꢁ.
ꢑꢒꢐERꢓEꢏꢕ ꢛꢓꢏꢁꢘ ꢂR ꢃRꢂꢐRꢚꢁꢑꢂꢒꢁ ꢁꢘꢏꢓꢓ ꢒꢂꢐ EꢞꢗEEꢕ ꢇ.ꢉꢍꢈꢟꢟ ꢄ.ꢇꢇꢎꢠꢆ ꢃER ꢁꢑꢕE
ꢍ. ꢓEꢏꢕ ꢗꢂꢃꢓꢏꢒꢏRꢑꢐꢢ ꢄꢝꢂꢐꢐꢂꢀ ꢂꢛ ꢓEꢏꢕꢁ ꢏꢛꢐER ꢛꢂRꢀꢑꢒꢌꢆ ꢁꢘꢏꢓꢓ ꢝE ꢇ.ꢉꢇꢈꢟꢟ ꢄ.ꢇꢇꢡꢠꢆ ꢀꢏꢞ
Rev. E
25
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
ꢅReꢤeꢥeꢦꢧe ꢚꢋꢕ ꢙꢟꢒ ꢨ ꢀꢄꢩꢀꢊꢩꢁꢂꢁꢀ Rev ꢒꢉ
.ꢁꢊꢓ ꢃ .ꢁꢓꢈ
ꢅꢆ.ꢊꢀꢁ ꢃ ꢄ.ꢀꢀꢆꢉ
.ꢀꢆꢄ ±.ꢀꢀꢄ
ꢖꢐꢋE ꢎ
.ꢀꢄꢀ ꢔꢏꢕ
ꢈ
ꢄ
ꢊ
ꢂ
.ꢇꢆꢄ
ꢗꢘꢖ
.ꢁꢂꢀ ±.ꢀꢀꢄ
.ꢁꢄꢀ ꢃ .ꢁꢄꢈ
ꢅꢎ.ꢊꢁꢀ ꢃ ꢎ.ꢓꢊꢊꢉ
ꢖꢐꢋE ꢎ
.ꢇꢇꢊ ꢃ .ꢇꢆꢆ
ꢅꢄ.ꢈꢓꢁ ꢃ ꢂ.ꢁꢓꢈꢉ
.ꢀꢎꢀ ±.ꢀꢀꢄ
ꢋꢌꢍ
ꢁ
ꢎ
ꢆ
ꢇ
REꢕꢐꢗꢗEꢖꢙEꢙ ꢏꢐꢚꢙER ꢍꢛꢙ ꢚꢛꢌꢐꢜꢋ
.ꢀꢁꢀ ꢃ .ꢀꢇꢀ
ꢅꢀ.ꢇꢄꢆ ꢃ ꢀ.ꢄꢀꢊꢉ
× ꢆꢄ°
.ꢀꢄꢎ ꢃ .ꢀꢂꢓ
ꢅꢁ.ꢎꢆꢂ ꢃ ꢁ.ꢈꢄꢇꢉ
.ꢀꢀꢆ ꢃ .ꢀꢁꢀ
ꢅꢀ.ꢁꢀꢁ ꢃ ꢀ.ꢇꢄꢆꢉ
.ꢀꢀꢊ ꢃ .ꢀꢁꢀ
ꢅꢀ.ꢇꢀꢎ ꢃ ꢀ.ꢇꢄꢆꢉ
ꢀ°ꢃ ꢊ° ꢋꢌꢍ
.ꢀꢁꢂ ꢃ .ꢀꢄꢀ
ꢅꢀ.ꢆꢀꢂ ꢃ ꢁ.ꢇꢈꢀꢉ
.ꢀꢄꢀ
ꢅꢁ.ꢇꢈꢀꢉ
ꢔꢏꢕ
.ꢀꢁꢆ ꢃ .ꢀꢁꢓ
ꢅꢀ.ꢎꢄꢄ ꢃ ꢀ.ꢆꢊꢎꢉ
ꢋꢌꢍ
ꢖꢐꢋEꢞ
ꢘꢖꢕꢝEꢏ
ꢁ. ꢙꢘꢗEꢖꢏꢘꢐꢖꢏ ꢘꢖ
ꢅꢗꢘꢚꢚꢘꢗEꢋERꢏꢉ
ꢇ. ꢙRꢛꢟꢘꢖꢒ ꢖꢐꢋ ꢋꢐ ꢏꢕꢛꢚE
ꢎ. ꢋꢝEꢏE ꢙꢘꢗEꢖꢏꢘꢐꢖꢏ ꢙꢐ ꢖꢐꢋ ꢘꢖꢕꢚꢜꢙE ꢗꢐꢚꢙ ꢠꢚꢛꢏꢝ ꢐR ꢍRꢐꢋRꢜꢏꢘꢐꢖꢏ.
ꢗꢐꢚꢙ ꢠꢚꢛꢏꢝ ꢐR ꢍRꢐꢋRꢜꢏꢘꢐꢖꢏ ꢏꢝꢛꢚꢚ ꢖꢐꢋ EꢡꢕEEꢙ .ꢀꢀꢂꢢ ꢅꢀ.ꢁꢄꢣꢣꢉ
ꢆ. ꢍꢘꢖ ꢁ ꢕꢛꢖ ꢔE ꢔEꢑEꢚ EꢙꢒE ꢐR ꢛ ꢙꢘꢗꢍꢚE
ꢏꢐꢊ REꢑ ꢒ ꢀꢇꢁꢇ
Rev. E
26
For more information www.analog.com
LT1999-10/LT1999-20/
LT1999-50
REVISION HISTORY
REV
DATE
5/11
3/12
DESCRIPTION
PAGE NUMBER
A
Revised +IN and –IN pin descriptions in Pin Functions section
12
B
Revised Voltage Output Swing Low specification (V ) under a loaded condition of 1kΩ to mid-supply.
4, 6
16
OUT
Updated Figure 4 to multicolor.
C
2/15
Addition of MSOP Pinout Option Engineered for FMEA
Correction to AV Specification for LT1999-50 from 48.75 to 49.75
Update to Pin Functions to include Pinout Option Engineered for FMEA
Addition of New Application Information "Pinout Option Engineered for FMEA"
Addition of Figure 5 and Renumbering of Figures 6 to 11
Addition of Table 1 and Table 2
All
5
12
18, 19
18 to 23
19
D
E
6/15
9/19
LT1999F added to Figure 1 (Simplified Block Diagram)
LT1999F added to Figure 2 (Test Circuit)
13
14
Additional test condition (V = 80) added to table 1 and table 2
19
CM
Note added regarding the use of FMEA information
19
Added Automotive Grade products, updated data sheet format
All
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
27
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LT1999-10/LT1999-20/
LT1999-50
TYPICAL APPLICATION
Battery Charge Current and Load Current Monitor
VOUT = 0.25V/A, Maximum Measured Current 9.5A
0.025Ω
CHARGER
BAT
42V
5V
+
V
LT1999-10
LOAD
+
5V
V
2µA
0.1µF
1
2
8
7
V
V
SHDN
SHDN
0.1µF
10µF
40k
+
–
4k
V
V
+IN
–IN
–
+
OUT
+
V
V
REF
ꢀS
V
CC
+IN
0.8k
0.8k
+
+
V
V
LTC2433-1
SCK
SDO
OUT
160k
160k
4k
3
4
V
REF
6
5
–
–IN
+
V
5V
0.1µF
1999 TA02
0.1µF
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LT1787/
Precision, Bidirectional High Side Current Sense Amplifier
Gain-Selectable High Side Current Sense Amplifier
High Voltage High Side Current Sense Amplifier
Zero Drift High Side Current Sense Amplifier
2.7V to 60V Operation, 75μV Offset, 60μA Current Draw
LT1787HV
LT6100
4.1V to 48V Operation, Pin-Selectable Gain:
10V/V, 12.5V/V, 20V/V, 25V/V, 40V/V, 50V/V
LTC6101/
LTC6101HV
4V to 60V/5V to 100V Operation, External Resistor Set Gain, SOT23
LTC6102/
LTC6102HV
4V to 60V/5V to 100V Operation, 10μV Offset, 1μs Step Response,
MSOP8/DFN Packages
LTC6103
LTC6104
LT6106
LT6105
LTC4150
LT1990
LT1991
Dual High Side Precision Current Sense Amplifier
Bidirectional, High Side Current Sense
4V to 60V, Gain Configurable, 8-Pin MSOP Package
4V to 60V, Gain Configurable, 8-Pin MSOP Package
2.7V to 36V, Gain Configurable, SOT23 Package
–0.3 to 44V, Gain Configurable, 8-Pin MSOP Package
Indicates Charge Quantity and Polarity
Low Cost, High Side Precision Current Sense Amplifier
Precision, Extended Input Range Current Sense Amplifier
Coulomb Counter/Battery Gas Gauge
Precision, 100μA Gain Selectable Amplifier
250V Input Range Difference Amplifier
2.7V to 36V Operation, CMRR > 70dB, Input Voltage = 250V
2.7V to 36V Operation, 50μV Offset, CMRR > 75B, Input Voltage = 60V
0.4V/μs Slew Rate, 230μA per Amplifier
LT1637/LT1638 1.1/1.2MHz, 0.4V/μs Over-The-Top, Rail-to-Rail Input and
Output Amplifier
Rev. E
09/19
www.analog.com
28
ANALOG DEVICES, INC. 2010-2019
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