LT2217 [Linear]
16-Bit, 65Msps/40Msps/25Msps Low Power Dual ADCs; 16位，支持65Msps / 40Msps的/ 25Msps时的低功耗双通道ADC
| 型号： | LT2217 |
| 厂家： | 
Linear |
| 描述： | 16-Bit, 65Msps/40Msps/25Msps Low Power Dual ADCs |
| 文件： | 总28页 (文件大小：3816K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Electrical Specifications SuLbjTecCt to2C1ha9ng2e
LTC2191/LTC2190
16-Bit, 65Msps/40Msps/
25Msps Low Power
Dual ADCs
FEATURES
DESCRIPTION
The LTC®2192/LTC2191/LTC2190 are 2-channel, simul-
taneous sampling 16-bit A/D converters designed for
digitizinghighfrequency,widedynamicrangesignals.They
are perfect for demanding communications applications
with AC performance that includes 77dB SNR and 90dB
spurious free dynamic range (SFDR). Ultralow jitter of
n
2-Channel Simultaneous Sampling ADC
n
Serial LVDS Outputs: 1, 2 or 4 Bits per Channel
n
77dB SNR
90dB SFDR
n
n
Low Power: 198mW/146mW/104mW Total
n
99mW/73mW/ꢀ2mW per Channel
n
Single 1.8V Supply
0.07ps
allows undersampling of IF frequencies with
RMS
n
Selectable Input Ranges: 1V to 2V
excellent noise performance.
P-P
P-P
n
n
n
n
ꢀꢀ0MHz Full-Power Bandwidth S/H
DC specs include 2LSB INL (typ), 0.ꢀLSB DNL (typ)
and no missing codes over temperature. The transition
Shutdown and Nap Modes
Serial SPI Port for Configuration
ꢀ2-Pin (7mm × 8mm) QFN Package
noise is 3.3LSB
.
RMS
To minimize the number of data lines the digital outputs
are serial LVDS. Each channel outputs one bit, two bits or
four bits at a time. The LVDS drivers have optional internal
termination and adjustable output levels to ensure clean
signal integrity.
APPLICATIONS
n
Communications
n
Cellular Base Stations
n
+
–
Software-Defined Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
The ENC and ENC inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL or CMOS
inputs. An internal clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
n
n
n
Nondestructive Testing
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
2-Tone FFT, fIN = 70MHz and 69MHz
0
–10
–20
–30
–40
–50
1.8V
1.8V
OV
V
DD
DD
OUT1A
OUT1B
OUT1C
OUT1D
OUT2A
OUT2B
OUT2C
OUT2D
CH1
ANALOG
INPUT
16-BIT
ADC CORE
S/H
S/H
CH2
ANALOG
INPUT
–60
–70
SERIALIZED
LVDS
OUTPUTS
16-BIT
ADC CORE
DATA
SERIALIZER
–80
–90
–100
–110
–120
ENCODE
INPUT
PLL
DATA CLOCK OUT
FRAME
GND
OGND
0
20
10
FREQUENCY (MHz)
30
219210 TA01a
219210 G07
219210p
1
LTC2192
LTC2191/LTC2190
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
TOP VIEW
Supply Voltages
V , OV ................................................ –0.3V to 2V
DD
DD
Analog Input Voltage
A +, A –, PAR/SER, SENSE
52 51 50 49 48 47 46 45 44 43 42 41
IN
IN
+
–
+
V
1
2
3
4
5
6
7
8
9
40 OUT1C
39 OUT1C
CM1
(Note 3) ....................................–0.3V to (V + 0.2V)
DD
GND
Digital Input Voltage
A
+
–
OUT1D
38
37
IN1
IN1
+
–
ENC , ENC , CS, SDI, SCK (Note 4)...... –0.3V to 3.9V
–
A
OUT1D
+
SDO (Note 4) ............................................ –0.3V to 3.9V
GND
REFH
REFL
REFH
REFL
36 DCO
–
DCO
35
Digital Output Voltage ................ –0.3V to (OV + 0.3V)
DD
34 OV
53
GND
DD
Operating Temperature Range
33 OGND
LTC2192C, LTC2191C, LTC2190C............. 0°C to 70°C
LTC2192I, LTC2191I, LTC2190I............ –40°C to 8ꢀ°C
Storage Temperature Range................... –6ꢀ°C to 1ꢀ0°C
+
32 FR
PAR/SER 10
31 FR–
+
–
+
–
A
IN2
+ 11
– 12
30 OUT2A
29 OUT2A
28 OUT2B
27 OUT2B
A
IN2
GND 13
14
V
CM2
15 16 17 18 19 20 21 22 23 24 25 26
UKG PACKAGE
52-LEAD (7mm × 8mm) PLASTIC QFN
T
= 1ꢀ0°C, θ = 29°C/W
JA
JMAX
EXPOSED PAD (PIN ꢀ3) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC2192CUKG#PBF
LTC2192IUKG#PBF
LTC2191CUKG#PBF
LTC2191IUKG#PBF
LTC2190CUKG#PBF
LTC2190IUKG#PBF
TAPE AND REEL
PART MARKING*
LTC2192UKG
LTC2192UKG
LTC2191UKG
LTC2191UKG
LTC2190UKG
LTC2190UKG
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC2192CUKG#TRPBF
LTC2192IUKG#TRPBF
LTC2191CUKG#TRPBF
LTC2191IUKG#TRPBF
LTC2190CUKG#TRPBF
LTC2190IUKG#TRPBF
ꢀ2-Lead (7mm × 8mm) Plastic QFN
ꢀ2-Lead (7mm × 8mm) Plastic QFN
ꢀ2-Lead (7mm × 8mm) Plastic QFN
ꢀ2-Lead (7mm × 8mm) Plastic QFN
ꢀ2-Lead (7mm × 8mm) Plastic QFN
ꢀ2-Lead (7mm × 8mm) Plastic QFN
–40°C to 8ꢀ°C
0°C to 70°C
–40°C to 8ꢀ°C
0°C to 70°C
–40°C to 8ꢀ°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
219210p
2
LTC2192
LTC2191/LTC2190
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2192
TYP
LTC2191
TYP
LTC2190
TYP
PARAMETER
CONDITIONS
MIN
16
MAX
MIN
16
MAX
MIN
16
MAX
UNITS
Bits
l
l
Resolution (No Missing Codes)
Integral Linearity Error
Differential Analog Input
(Note 6)
tbd
2
tbd
tbd
2
tbd
tbd
2
tbd
LSB
l
l
Differential Linearity Error
Offset Error
Differential Analog Input
(Note 7)
–1
–9
0.ꢀ
1.ꢀ
1
9
–1
–9
0.ꢀ
1.ꢀ
1
9
–1
–9
0.ꢀ
1.ꢀ
1
9
LSB
mV
Gain Error
Internal Reference
External Reference
1.ꢀ
–0.6
1.ꢀ
–0.6
1.ꢀ
–0.6
%FS
%FS
l
–2.1
0.9
–2.1
0.9
–2.1
0.9
Offset Drift
10
10
10
µV/°C
Full-Scale Drift
Internal Reference
External Reference
30
10
30
10
30
10
ppm/°C
ppm/°C
Gain Matching
Offset Matching
Transition Noise
0.3
1.ꢀ
3.3
0.3
1.ꢀ
3.3
0.3
1.ꢀ
3.2
%FS
mV
LSB
RMS
ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
V
V
V
Analog Input Range (A + – A –)
1.7V < V < 1.9V
1 to 2
V
P-P
IN
IN
IN
DD
Analog Input Common Mode (A + + A –)/2
Differential Analog Input (Note 8)
0.7
V
CM
1.2ꢀ
V
IN(CM)
SENSE
INCM
IN
IN
External Voltage Reference Applied to SENSE External Reference Mode
0.62ꢀ
1.2ꢀ0
1.300
V
I
Analog Input Common Mode Current
Per Pin, 6ꢀMsps
Per Pin, 40Msps
Per Pin, 2ꢀMsps
104
64
40
µA
µA
µA
l
l
l
I
I
I
t
t
Analog Input Leakage Current (No Encode)
PAR/SER Input Leakage Current
0 < A +, A – < V
DD
–1
–3
–6
1
3
6
µA
µA
µA
ns
IN1
IN
IN
0 < PAR/SER < V
IN2
DD
SENSE Input Leakage Current
0.62ꢀV < SENSE < 1.3V
IN3
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
0
AP
Single-Ended Encode
Differential Encode
0.07
0.09
ps
ps
JITTER
RMS
RMS
CMRR
Analog Input Common Mode Rejection Ratio
Full-Power Bandwidth
80
dB
BW–3B
Figure 6 Test Circuit
ꢀꢀ0
MHz
219210p
3
LTC2192
LTC2191/LTC2190
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
LTC2192
TYP
LTC2191
TYP
LTC2190
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
SNR
Signal-to-Noise Ratio
ꢀMHz Input
77
76.9
76.8
76.7
76.2
77.1
77
dBFS
dBFS
dBFS
dBFS
l
l
l
l
30MHz Input
70MHz Input
140MHz Input
tbd
76.9
76.8
76.3
tbd
tbd
76.9
76.4
SFDR
Spurious Free Dynamic Range ꢀMHz Input
2nd or 3rd Harmonic
90
90
89
84
90
90
89
84
90
90
89
84
dBFS
dBFS
dBFS
dBFS
30MHz Input
70MHz Input
140MHz Input
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
tbd
Spurious Free Dynamic Range ꢀMHz Input
4th Harmonic or Higher
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
dBFS
dBFS
dBFS
dBFS
30MHz Input
70MHz Input
140MHz Input
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio
ꢀMHz Input
76.8
76.7
76.4
76.3
76.7
76.6
76.3
7ꢀ.2
76.9
76.8
76.ꢀ
76.4
dBFS
dBFS
dBFS
dBFS
30MHz Input
70MHz Input
140MHz Input
Crosstalk
10MHz Input
–110
–110
–110
dBc
INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
I = 0
OUT
MIN
TYP
0.ꢀ • V
2ꢀ
MAX
UNITS
V
V
V
V
V
V
V
V
Output Voltage
0.ꢀ • V – 2ꢀmV
0.ꢀ • V + 2ꢀmV
CM
CM
CM
REF
REF
REF
REF
DD
DD
DD
Output Temperature Drift
Output Resistance
Output Voltage
ppm/°C
Ω
–600µA < I
< 1mA
< 1mA
4
OUT
I
= 0
1.22ꢀ
1.2ꢀ0
2ꢀ
1.27ꢀ
V
OUT
Output Temperature Drift
Output Resistance
Line Regulation
ppm/°C
Ω
–400µA < I
7
OUT
1.7V < V < 1.9V
0.6
mV/V
DD
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
ENCODE INPUTS (ENC , ENC )
–
Differential Encode Mode (ENC Not Tied to GND)
l
V
V
Differential Input Voltage
(Note 8)
0.2
V
ID
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
1.2
V
V
ICM
l
l
1.1
0.2
1.6
3.6
+
–
V
Input Voltage Range
Input Resistance
ENC , ENC to GND
See Figure 10
(Note 8)
V
kΩ
pF
IN
R
10
IN
C
Input Capacitance
3.ꢀ
IN
–
Single-Ended Encode Mode (ENC Tied to GND)
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
V
V
=1.8V
=1.8V
1.2
V
V
IH
IL
DD
DD
0.6
219210p
4
LTC2192
LTC2191/LTC2190
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
+
l
V
Input Voltage Range
Input Resistance
Input Capacitance
ENC to GND
0
3.6
IN
R
See Figure 11
(Note 8)
30
kΩ
pF
IN
IN
C
3.ꢀ
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
l
V
V
High Level Input Voltage
Low Level Input Voltage
Input Current
V
V
V
=1.8V
1.3
V
V
IH
IL
DD
DD
IN
l
l
=1.8V
0.6
10
I
= 0V to 3.6V
–10
µA
pF
IN
C
Input Capacitance
(Note 8)
3
200
3
IN
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
R
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
V
=1.8V, SDO = 0V
DD
Ω
µA
pF
OL
l
I
SDO = 0V to 3.6V
(Note 8)
–10
10
OH
C
OUT
DIGITAL DATA OUTPUTS
l
l
V
Differential Output Voltage
100Ω Differential Load, 3.ꢀmA Mode
100Ω Differential Load, 1.7ꢀmA Mode
247
12ꢀ
3ꢀ0
17ꢀ
4ꢀ4
2ꢀ0
mV
mV
OD
l
l
V
Common Mode Output Voltage
On-Chip Termination Resistance
100Ω Differential Load, 3.ꢀmA Mode
100Ω Differential Load, 1.7ꢀmA Mode
1.12ꢀ
1.12ꢀ
1.2ꢀ0
1.2ꢀ0
1.37ꢀ
1.37ꢀ
V
V
OS
R
Termination Enabled, OV = 1.8V
100
Ω
TERM
DD
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2192
TYP MAX MIN
LTC2191
TYP MAX MIN
LTC2190
TYP MAX
SYMBOL PARAMETER
CONDITIONS
MIN
1.7
UNITS
l
l
l
V
Analog Supply Voltage (Note 10)
1.8
1.8
99
1.9
1.9
tbd
1.7
1.7
1.8
1.8
72
1.9
1.9
tbd
1.7
1.7
1.8
1.8
49
1.9
1.9
tbd
V
V
DD
OV
DD
Output Supply Voltage (Note 10)
1.7
I
I
Analog Supply Current Sine Wave Input
mA
VDD
OVDD
Digital Supply Current
1-Lane Mode, 1.7ꢀmA Mode
10.2
17.6
13.6
24.7
21.1
39.6
tbd
tbd
tbd
tbd
tbd
tbd
9.2
tbd
tbd
tbd
tbd
tbd
tbd
8.7
tbd
tbd
tbd
tbd
tbd
tbd
mA
mA
mA
mA
mA
mA
1-Lane Mode, 3.ꢀmA Mode
2-Lane Mode, 1.7ꢀmA Mode
2-Lane Mode, 3.ꢀmA Mode
4-Lane Mode, 1.7ꢀmA Mode
4-Lane Mode, 3.ꢀmA Mode
16.6
12.8
23.9
20.3
38.8
16.1
12.3
23.4
19.9
38.4
l
l
l
l
P
Power Dissipation
1-Lane Mode, 1.7ꢀmA Mode
1-Lane Mode, 3.ꢀmA Mode
2-Lane Mode, 1.7ꢀmA Mode
2-Lane Mode, 3.ꢀmA Mode
4-Lane Mode, 1.7ꢀmA Mode
4-Lane Mode, 3.ꢀmA Mode
198
211
203
223
217
2ꢀ0
tbd
tbd
tbd
tbd
tbd
tbd
146
1ꢀ9
1ꢀ2
172
166
199
tbd
tbd
tbd
tbd
tbd
tbd
104
118
111
131
124
1ꢀ8
tbd
tbd
tbd
tbd
tbd
tbd
mW
mW
mW
mW
mW
mW
DISS
l
l
l
l
P
P
P
Sleep Mode Power
Nap Mode Power
1
1
1
mW
mW
mW
SLEEP
NAP
ꢀ0
20
ꢀ0
20
ꢀ0
20
Power Increase with Diffential Encode Mode Enabled
(No Increase for Sleep Mode)
DIFFCLK
219210p
5
LTC2192
LTC2191/LTC2190
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2192
TYP MAX MIN
LTC2191
TYP MAX MIN
LTC2190
TYP MAX
SYMBOL PARAMETER
CONDITIONS
MIN
UNITS
l
f
t
Sampling Frequency
(Notes 10, 11)
ꢀ
6ꢀ
100 11.88 12.ꢀ
100 12.ꢀ
100 11.88 12.ꢀ
ꢀ
40
ꢀ
2ꢀ
MHz
S
l
l
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
7.3
2
7.69
7.69
100
100
19
2
20
20
100
100
ns
ns
ENCL
2
l
l
t
t
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
7.3
2
7.69
7.69
100
100
19
2
20
20
100
100
ns
ns
ENCH
AP
100
2
12.ꢀ
Sample-and-Hold
Acquistion Delay Time
0
0
0
ns
SYMBOL PARAMETER
Digital Data Outputs (R
CONDITIONS
MIN
TYP
MAX
UNITS
= 100Ω Differential, C = 2pF to GND On Each Output)
TERM
L
t
Serial Data Bit Period
4-Lane Output Mode
2-Lane Output Mode
1-Lane Output Mode
1/(4 • f )
Sec
SER
S
1/(8 • f )
S
1/(16 • f )
S
l
l
l
t
t
t
t
t
FR to DCO Delay
Data to DCO Delay
Propagation Delay
Output Rise Time
Output Fall Time
DCO Cycle-Cycle Jitter
Pipeline Latency
(Note 8)
0.35 • t
0.35 • t
0.5 • t
0.5 • t
0.65 • t
0.65 • t
Sec
Sec
Sec
ns
FRAME
SER
SER
SER
SER
(Note 8)
DATA
SER
SER
(Note 8)
0.7n + 2 • t
1.1n + 2 • t
1.5n + 2 • t
SER
PD
SER
SER
Data, DCO, FR, 20% to 80%
Data, DCO, FR, 20% to 80%
0.17
0.17
60
r
f
ns
t
= 1ns
ps
P-P
SER
7
Cycles
SPI Port Timing (Note 8)
l
l
t
SCK Period
Write Mode
40
2ꢀ0
ns
ns
SCK
Readback Mode,
C
= 20pF, R
= 2k
SDO
PULLUP
l
l
l
l
l
t
t
t
t
t
CS-to-CLK Setup Time
SCK-to-CS Setup Time
SDI Setup Time
ꢀ
ꢀ
ꢀ
ꢀ
ns
ns
ns
ns
ns
S
H
DS
DH
DO
SDI Hold Time
SCK Falling to SDO
Valid
Readback Mode,
= 20pF, R
12ꢀ
C
= 2k
SDO
PULLUP
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.ꢀLSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111 in 2’s complement output mode.
Note 3: When these pin voltages are taken below GND or above V , they
Note 8: Guaranteed by design, not subject to test.
DD
will be clamped by internal diodes. This product can handle input currents
Note 9: V = OV =1.8V, f = 6ꢀMHz (LTC2192),
DD
DD
SAMPLE
of greater than 100mA below GND or above V without latchup.
DD
40MHz (LTC2191), or 2ꢀMHz (LTC2190), 2-lane output mode,
+
–
Note 4: When these pin voltages are taken below GND they will be
ENC = single-ended 1.8V square wave, ENC = 0V, input range = 2V
P-P
clamped by internal diodes. When these pin voltages are taken above V
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
with differential drive, unless otherwise noted. The supply current and
power dissipation specifications are totals for the entire IC, not per
channel.
DD
Note 5: V = OV = 1.8V, f = 6ꢀMHz (LTC2192), 40MHz
Note 10: Recommended operating conditions.
DD
DD
SAMPLE
(LTC2191), or 2ꢀMHz (LTC2190), 2-lane output mode, differential
Note 11: The maximum sampling frequency depends on the speed grade
of the part and also which serialization mode is used. The maximum serial
+
–
ENC /ENC = 2V sine wave, input range = 2V with differential drive,
P-P
P-P
unless otherwise noted.
data rate is 1000Mbps, so t
must be greater than or equal to 1ns.
SER
219210p
6
LTC2192
LTC2191/LTC2190
TIMING DIAGRAMS
4-Lane Output Mode
t
AP
ANALOG
INPUT
N
N+1
t
t
ENCL
ENCH
–
ENC
+
ENC
t
t
SER
DATA
–
DCO
+
DCO
t
t
SER
FRAME
+
FR
–
FR
t
t
PD
SER
–
OUT#A
D15
D13
D12
D5
D11
D10
D3
D9
D8
D1
D0
D15
D14
D7
D13
D12
D5
D11
D10
D3
D9
D8
D1
D0
D15
D14
D7
+
OUT#A
–
OUT#B
D14
+
OUT#B
–
OUT#C
D7
+
OUT#C
–
OUT#D
D6
D4
D2
D6
D4
D2
D6
+
OUT#D
SAMPLE N–7
SAMPLE N–6
SAMPLE N–5
219210 TD01
2-Lane Output Mode
t
AP
N+1
ANALOG
INPUT
N
t
t
ENCH
ENCL
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
t
SER
FRAME
DATA
–
FR
+
FR
t
t
PD
SER
–
OUT#A
D7
D6
D5
D3
D1
D15 D13 D11
D14 D12 D10
D9
D8
D7
D6
D5
D4
D3
D1
D0
D15 D13 D11
D14 D12 D10
+
OUT#A
–
OUT#B
D4
D2
D0
+
D2
+
OUT#B
SAMPLE N–7
+
SAMPLE N–6
–
SAMPLE N–5
219210 TD02
–
OUT#C , OUT#C , OUT#D , OUT#D ARE DISABLED
219210p
7
LTC2192
LTC2191/LTC2190
TIMING DIAGRAMS
1-Lane Output Mode
t
AP
ANALOG
INPUT
N+1
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
t
SER
FRAME
DATA
–
FR
+
FR
t
PD
t
SER
–
OUT#A
D3
D2
D1
D0 D15 D14 D13 D12 D11 D10 D9
SAMPLE N–6
D8
D7
D6
D5
D4
D3
D2
D1
D0 D15 D14 D13 D12
+
OUT#A
219210 TD03
SAMPLE N–7
+
SAMPLE N–5
–
+
–
+
–
OUT#B , OUT#B , OUT#C , OUT#C , OUT#D , OUT#D ARE DISABLED
SPI Port Timing (Readback Mode)
t
S
t
DS
t
DH
t
t
H
SCK
CS
SCK
t
DO
SDI
A6
A5
A4
A3
A2
A1
A0
XX
XX
D6
XX
D5
XX
D4
XX
XX
D2
XX
D1
XX
R/W
SDO
D7
D3
D0
HIGH IMPEDANCE
SPI Port Timing (Write Mode)
CS
SCK
SDI
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
SDO
219210 TD04
HIGH IMPEDANCE
219210p
8
LTC2192
LTC2191/LTC2190
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2192: Integral
Nonlinearity (INL)
LTC2192: Differential
Nonlinearity (DNL)
LTC2192: 64k Point FFT,
fIN = 5MHz, –1dBFS, 65Msps
1.0
0.8
4.0
3.0
0
–10
–20
–30
–40
–50
–60
–70
0.6
2.0
0.4
1.0
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.0
–2.0
–3.0
–4.0
–80
–90
–100
–110
–120
0
32768
49152
65536
16384
0
32768
49152
65536
16384
0
20
10
FREQUENCY (MHz)
30
OUTPUT CODE
OUTPUT CODE
219210 G02
219210 G01
219210 G03
LTC2192: 64k Point FFT,
fIN = 30MHz, –1dBFS, 65Msps
LTC2192: 64k Point FFT,
fIN = 70MHz, –1dBFS, 65Msps
LTC2192: 64k Point FFT,
fIN = 140MHz, –1dBFS, 65Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
20
10
FREQUENCY (MHz)
30
0
20
10
FREQUENCY (MHz)
30
0
20
10
FREQUENCY (MHz)
30
219210 G04
219210 G05
219210 G06
LTC2192: 64k Point 2-Tone FFT,
fIN = 69MHz, 70MHz, –7dBFS,
65Msps
LTC2192: SNR vs Input Frequency,
–1dBFS, 65Msps, 2V Range
LTC2192: Shorted Input Histogram
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
78
77
76
75
74
73
72
71
70
0
–10
–20
–30
–40
–50
–60
–70
SINGLE-ENDED
ENCODE
DIFFERENTIAL
ENCODE
–80
–90
–100
–110
–120
32831
32837
32843
32849
32855
0
50
100
150
200
250
300
0
20
10
FREQUENCY (MHz)
30
OUTPUT CODE
INPUT FREQUENCY (MHz)
219210 G08
219210 G09
219210 G07
219210p
9
LTC2192
LTC2191/LTC2190
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2192: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 65Msps,
2V Range
LTC2192: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 65Msps,
1V Range
LTC2192: SFDR vs Input Level,
fIN = 70MHz, 65Msps, 2V Range
100
95
90
85
80
75
70
65
130
120
110
100
90
100
95
90
85
80
75
70
65
dBFS
3RD
3RD
dBc
80
2ND
70
2ND
60
50
40
30
20
0
50
100
150
200
250
300
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
0
50
100
150
200
250
300
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
219210 G11
219210 G12
219210 G10
LTC2192: IVDD vs Sample Rate,
5MHz, –1dBFS Sine Wave on
Each Channel
LTC2192: IOVDD vs Sample Rate,
5MHz, –1dBFS Sine Wave on
Each Input
LTC2192: SNR vs SENSE,
fIN = 5MHz, –1dBFS
45
35
25
15
5
110
100
90
78
77
76
75
74
73
72
71
70
4 LANE, 3.5mA
2 LANE, 3.5mA
4 LANE, 1.75mA
1 LANE, 3.5mA
80
2 LANE, 1.75mA
1 LANE, 1.75mA
70
60
0
20
30
40
50
60
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
10
0
20
40
60
SAMPLE RATE (Msps)
SAMPLE RATE (Msps)
SENSE PIN (V)
219210 G15
219210 G13
219210 G14
LTC2191: Integral
Nonlinearity (INL)
LTC2191: Differential
Nonlinearity (DNL)
LTC2191: 64k Point FFT,
fIN = 5MHz, –1dBFS, 40Msps
4.0
3.0
1.0
0.8
0.6
0
–10
–20
–30
–40
–50
–60
–70
2.0
0.4
0.2
0
1.0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.0
–2.0
–3.0
–4.0
–80
–90
–100
–110
–120
0
32768
49152
65536
0
32768
49152
65536
16384
16384
0
5
10
15
20
OUTPUT CODE
OUTPUT CODE
FREQUENCY (MHz)
219210 G16
219210 G17
219210 G18
219210p
10
LTC2192
LTC2191/LTC2190
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2191: 64k Point FFT,
fIN = 30MHz, –1dBFS, 40Msps
LTC2191: 64k Point FFT,
fIN = 70MHz, –1dBFS, 40Msps
LTC2191: 64k Point FFT,
fIN = 140MHz, –1dBFS, 40Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
5
10
15
20
0
5
10
15
20
0
5
10
15
20
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
219210 G19
219210 G20
219210 G21
LTC2191: 64k Point 2-Tone FFT,
fIN = 69MHz, 70MHz, –7dBFS,
40Msps
LTC2191: SNR vs Input Frequency,
–1dBFS, 40Msps, 2V Range
LTC2191: Shorted Input Histogram
0
–10
–20
–30
–40
–50
–60
–70
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
78
77
76
75
74
73
72
71
70
SINGLE-ENDED
ENCODE
DIFFERENTIAL
ENCODE
–80
–90
–100
–110
–120
32823
32835 32841 32847
OUTPUT CODE
0
5
10
15
20
32829
0
50
100
150
200
250
300
FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
219210 G22
219210 G23
219210 G24
LTC2191: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 40Msps,
2V Range
LTC2191: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 40Msps,
1V Range
LTC2191: SFDR vs Input Level,
fIN = 70MHz, 40Msps, 2V Range
100
95
90
85
80
75
70
65
100
95
90
85
80
75
70
65
130
120
110
100
90
dBFS
3RD
3RD
dBc
80
2ND
70
2ND
60
50
40
30
20
0
50
100
150
200
250
300
0
50
100
150
200
250
300
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
219210 G25
219210 G26
219210 G27
219210p
11
LTC2192
LTC2191/LTC2190
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2191: IVDD vs Sample Rate,
5MHz, –1dBFS Sine Wave Input
on Each Channel
LTC2191: IOVDD vs Sample Rate,
5MHz, –1dBFS Sine Wave on
Each Input
LTC2191: SNR vs SENSE,
fIN = 5MHz, –1dBFS
80
75
45
35
25
15
5
78
77
76
75
74
73
72
71
70
4 LANE, 3.5mA
70
65
2 LANE, 3.5mA
4 LANE, 1.75mA
1 LANE, 3.5mA
2 LANE, 1.75mA
1 LANE, 1.75mA
60
55
50
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
0
10
20
30
40
0
20
30
40
10
SENSE PIN (V)
SAMPLE RATE (Msps)
SAMPLE RATE (Msps)
219210 G30
219210 G28
219210 G29
LTC2190: Integral
Nonlinearity (INL)
LTC2190: Differential
Nonlinearity (DNL)
LTC2190: 64k Point FFT,
fIN = 5MHz, –1dBFS, 25Msps
4.0
3.0
1.0
0.8
0.6
0
–10
–20
–30
–40
–50
–60
–70
2.0
0.4
0.2
0
1.0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.0
–2.0
–3.0
–4.0
–80
–90
–100
–110
–120
0
32768
49152
65536
0
32768
49152
65536
16384
16384
0
5
10
OUTPUT CODE
OUTPUT CODE
FREQUENCY (MHz)
219210 G31
219210 G32
219210 G33
LTC2190: 64k Point FFT,
fIN = 70MHz, –1dBFS, 25Msps
LTC2190: 64k Point FFT,
fIN = 30MHz, –1dBFS, 25Msps
LTC2190: 64k Point FFT,
fIN = 140MHz, –1dBFS, 25Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
5
10
0
5
10
0
5
10
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
219210 G34
219210 G35
219210 G36
219210p
12
LTC2192
LTC2191/LTC2190
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2190: 64k Point, 2-Tone FFT,
fIN = 69MHz, 70MHz, –7dBFS,
LTC2190: SNR vs Input Frequency,
–1dBFS, 25Msps, 2V Range
25Msps
LTC2190: Shorted Input Histogram
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
0
–10
–20
–30
–40
–50
–60
–70
78
77
SINGLE-ENDED
ENCODE
76
75
74
DIFFERENTIAL
ENCODE
73
–80
–90
–100
–110
–120
72
71
70
32836
32848
32854
32860
32842
0
5
10
0
50
100
150
200
250
300
OUTPUT CODE
FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
219210 G38
219210 G37
219210 G39
LTC2190: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 25Msps,
2V Range
LTC2190: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 25Msps,
1V Range
LTC2190: SFDR vs Input Level,
fIN = 70MHz, 25Msps, 2V Range
100
95
90
85
80
75
70
65
100
95
90
85
80
75
70
65
130
120
110
100
90
dBFS
dBc
3RD
3RD
80
2ND
70
2ND
60
50
40
30
20
0
50
100
150
200
250
300
0
50
100
150
200
250
300
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
219210 G40
219210 G41
219210 G42
LTC2190: IVDD vs Sample Rate,
5MHz, –1dBFS Sine Wave Input on
Each Channel
LTC2190: IOVDD vs Sample Rate,
5MHz, –1dBFS Sine Wave on Each
Input
LTC2190: SNR vs SENSE,
fIN = 5MHz, –1dBFS
78
77
76
75
74
73
72
71
70
55
50
45
40
35
45
40
35
20
15
4 LANE, 3.5mA
2 LANE, 3.5mA
4 LANE, 1.75mA
1 LANE, 3.5mA
2 LANE, 1.75mA
1 LANE, 1.75mA
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
0
5
10
15
20
25
0
5
10
15
20
25
SENSE PIN (V)
SAMPLE RATE (Msps)
SAMPLE RATE (Msps)
219210 G45
219210 G43
219210 G44
219210p
13
LTC2192
LTC2191/LTC2190
PIN FUNCTIONS
+
V
CM1
(Pin1):CommonModeBiasOutput,NominallyEqual
ENC (Pin 17): Encode Input. Conversion starts on the
to V /2. V
should be used to bias the common mode
rising edge.
DD
CM1
of the analog inputs of channel 1. Bypass to ground with
a 0.1µF ceramic capacitor.
–
ENC (Pin 18): Encode Complement Input. Conversion
starts on the falling edge. Tie to GND for single-ended
encode mode.
GND (Pins 2, 5, 13, 22, 45, 47, 49, Exposed Pad Pin 65):
ADC Power Ground. The exposed pad must be soldered
to the PCB ground.
CS (Pin 19): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When
CS is low, SCK is enabled for shifting data on SDI into
the mode control registers. In the parallel programming
A
+ (Pin 3): Channel 1 Positive Differential Analog
IN1
Input.
mode (PAR/SER = V ), CS along with SCK selects 1-,
DD
A
– (Pin 4): Channel 1 Negative Differential Analog
IN1
Input.
2- or 4-lane output mode (see Table 3). CS can be driven
with 1.8V to 3.3V logic.
REFH(Pins6,8):ADCHighReference.SeetheReference
sectionintheApplicationsInformationforrecommended
bypassing cIrcuits for REFH and REFL.
SCK (Pin 20): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = V ), SCK along with CS
DD
REFL (Pins 7, 9): ADC Low Reference. See the Reference
sectionintheApplicationsInformationforrecommended
bypassing cIrcuits for REFH and REFL.
selects 1-, 2- or 4-lane output mode (see Table 3). SCK
can be driven with 1.8V to 3.3V logic.
SDI (Pin 21): In Serial Programming Mode, (PAR/SER =
0V), SDI is the Serial Interface Data Input. Data on SDI
is clocked into the mode control registers on the rising
edge of SCK. In the parallel programming pode (PAR/SER
PAR/SER (Pin 10): Programming Mode Selection Pin.
Connecttogroundtoenabletheserialprogrammingmode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to V to enable the
= V ), SDI can be used to power down the part. SDI can
DD
DD
parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
be driven with 1.8V to 3.3V logic.
OGND (Pin 33): Output Driver Ground. This pin must be
shortedtothegroundplanebyaverylowinductancepath.
Use multiple vias close to the pin.
directly to ground or the V of the part and not be driven
DD
by a logic signal.
OV (Pin 34): Output Driver Supply. Bypass to ground
DD
A
+ (Pin 11): Channel 2 Positive Differential Analog
IN2
Input.
with a 0.1µF ceramic capacitor.
SDO (Pin 46): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control regis-
ters and can be latched on the falling edge of SCK. SDO
is an open-drain NMOS output that requires an external
2k pull-up resistor to 1.8V to 3.3V. If read back from the
mode control registers is not needed, the pull-up resistor
is not necessary and SDO can be left unconnected. In the
A
– (Pin 12): Channel 2 Negative Differential Analog
IN2
Input.
V
(Pin 14): Common Mode Bias Output, Nominally
CM2
Equal to V /2. V
should be used to bias the common
DD
CM2
mode of the analog inputs of channel 2. Bypass to ground
with a 0.1µF ceramic capacitor.
V
(Pins 15, 16, 51, 52): Analog Power Supply, 1.7V
DD
parallelprogrammingmode(PAR/SER=V ),SDOselects
DD
to 1.9V. Bypass to ground with 0.1µF ceramic capacitors.
3.ꢀmA or 1.7ꢀmA LVDS output currents. When used as an
input, SDO can be driven with 1.8V to 3.3V logic through
a 1k series resistor.
Adjacent pins can share a bypass capacitor.
219210p
14
LTC2192
LTC2191/LTC2190
PIN FUNCTIONS
–
–
+
+
–
+
–
+
V
(Pin48):ReferenceVoltageOutput.Bypasstoground
OUT2D /OUT2D , OUT2C /OUT2C , OUT2B /OUT2B ,
REF
with a 2.2µF ceramic capacitor. The reference output is
OUT2A /OUT2A (Pins23/24,25/26,27/28,29/30):Serial
nominally 1.2ꢀV.
Data Outputs for Channel 2. In 1-lane output mode only
–
–
+
+
OUT2A /OUT2A are used. In 2-Lane output mode only
SENSE(Pin50):ReferenceProgrammingPin.Connecting
–
+
OUT2A /OUT2A and OUT2B /OUT2B are used.
SENSEtoV selectstheinternalreferenceanda 1Vinput
DD
–
+
range. Connecting SENSE to ground selects the internal
reference and a 0.ꢀV input range. An external reference
between 0.62ꢀV and 1.3V applied to SENSE selects an
FR /FR (Pins 31/32): Frame Start Outputs.
–
+
DCO /DCO (Pins 35/36): Data Clock Outputs.
–
–
+
+
–
+
–
+
OUT1D /OUT1D , OUT1C /OUT1C , OUT1B /OUT1B ,
input range of ±0.8 • V
.
SENSE
OUT1A /OUT1A (Pins37/38,39/40,41/42,43/44):Serial
LVDS Outputs
Data Outputs for Channel 1. In 1-lane output mode only
–
–
+
+
OUT1A /OUT1A are used. In 2-lane output mode only
The following pins are differential LVDS outputs. The
output current level is programmable. There is an optional
internal 100Ω termination resistor between the pins of
each LVDS output pair.
–
+
OUT1A /OUT1A and OUT1B /OUT1B are used.
219210p
15
LTC2192
LTC2191/LTC2190
FUNCTIONAL BLOCK DIAGRAM
+
–
1.8V
1.8V
OV
ENC
ENC
V
DD
DD
PLL
OUT1A
OUT1B
OUT1C
OUT1D
OUT2A
OUT2B
OUT2C
OUT2D
CH1
ANALOG
INPUT
16-BIT
S/H
S/H
ADC CORE
DATA
SERIALIZER
CH2
ANALOG
INPUT
16-BIT
ADC CORE
DATA CLOCK OUT
FRAME
OGND
V
REF
1.25V
REFERENCE
2.2µF
RANGE
SELECT
REF BUF
REFH
REFL
SENSE
V
/2
DD
MODE
DIFF REF
AMP
CONTROL
REGISTERS
219210 F01
REFH
REFL
V
V
CM2
CM1
2.2µF
0.1µF
PAR/SER
SCK SDI
SDO
CS
0.1µF
0.1µF
0.1µF
Figure 1. Functional Block Diagram
219210p
16
LTC2192
LTC2191/LTC2190
APPLICATIONS INFORMATION
CONVERTER OPERATION
Single-Ended Input
TheLTC2192/LTC2191/LTC2190arelowpower,2-channel,
16-bit, 6ꢀ/40/2ꢀMsps A/D converters that are powered
by a single 1.8V supply. The analog inputs should be
driven differentially. The encode input can be driven dif-
ferentially or single ended for lower power consumption.
To minimize the number of data lines the digital outputs
are serial LVDS. Each channel outputs one bit at a time
(1-lane mode), two bits at a time (2-lane mode) or four
bits at a time (4-lane mode). Many additional features can
be chosen by programming the mode control registers
through a serial SPI port.
For applications less sensitive to harmonic distortion, the
+
A
input can be driven singled ended with a 1V signal
IN
P-P
–
centered around V . The A input should be connected
CM
IN
toV .Withasingled-endedinputtheharmonicdistortion
CM
and INL will degrade, but the noise and DNL will remain
unchanged.
INPUT DRIVE CIRCUITS
Input Filtering
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and
alsolimitswidebandnoisefromthedrivecircuitry.Figure 3
shows an example of an input RC filter. The RC component
values should be chosen based on the application’s input
frequency.
ANALOG INPUT
The analog inputs are differential CMOS sample-and-
hold circuits (Figure 2). The inputs should be driven
differentially around a common mode voltage set by the
V
or V
output pins, which are nominally V /2.
CM1
CM2 DD
For the 2V input range, the inputs should swing from
Transformer Coupled Circuits
V
– 0.ꢀV to V + 0.ꢀV. There should be 180° phase
CM
CM
difference between the inputs.
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
Thetwochannelsaresimultaneouslysampledbyashared
encode circuit (Figure 2).
tap is biased with V , setting the A/D input at its optimal
CM
LTC2192
V
DD
C
C
SAMPLE
5pF
R
ON
10Ω
10Ω
15Ω
A
+
–
IN
IN
C
PARASITIC
1.8pF
V
DD
SAMPLE
5pF
R
15Ω
ON
A
C
PARASITIC
1.8pF
V
DD
1.2V
10k
+
–
ENC
ENC
10k
1.2V
219210 F02
Figure 2. Equivalent Input Circuit. Only One of Two Analog Channels Is Shown
219210p
17
LTC2192
LTC2191/LTC2190
APPLICATIONS INFORMATION
50Ω
50Ω
V
V
CM
CM
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
T1
1:1
25Ω
A
+
A +
IN
IN
ANALOG
INPUT
ANALOG
INPUT
T2
LTC2192
LTC2192
T1
0.1µF
0.1µF
25Ω
25Ω
25Ω
25Ω
12pF
1.8pF
25Ω
A
–
A
–
IN
IN
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1L
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
219210 F03
219210 F05
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
Figure 5. Recommended Front-End Circuit for Input Frequencies
from 150MHz to 250MHz
50Ω
50Ω
V
V
CM
CM
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
4.7nH
0.1µF
12Ω
A
+
A
+
ANALOG
INPUT
IN
IN
ANALOG
INPUT
T2
LTC2192
LTC2192
T1
0.1µF
25Ω
25Ω
T1
25Ω
25Ω
8.2pF
4.7nH
12Ω
A
–
A
–
IN
IN
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1L
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
T1: MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
219210 F04
219210 F06
Figure 4. Recommended Front-End Circuit for Input Frequencies
from 5MHz to 150MHz
Figure 6. Recommended Front-End Circuit for Input Frequencies
Above 250MHz
V
CM
DC level. At higher input frequencies a transmission line
balun transformer (Figures 4 to 6) has better balance,
resulting in lower A/D distortion.
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
0.1µF
A
200Ω 200Ω
25Ω
0.1µF
0.1µF
+
–
IN
LTC2192
ANALOG
INPUT
12pF
+
–
Amplifier Circuits
Figure 7 shows the analog input being driven by a high
speeddifferentialamplifier.TheoutputoftheamplifierisAC
coupledtotheA/Dsotheamplifier’soutputcommonmode
voltage can be optimally set to minimize distortion.
25Ω
A
IN
12pF
219210 F07
Figure 7. Front-End Circuit Using a High Speed
Differential Amplifier
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
blockissingleended, thenatransformercircuit(Figures 4
to 6) should convert the signal to differential before driv-
ing the A/D.
219210p
18
LTC2192
LTC2191/LTC2190
APPLICATIONS INFORMATION
Reference
Figure 8c and 8d show the recommended circuit board
layout for the REFH/REFL bypass capacitors. Note that in
Figure 8c, every pin of the interdigitated capacitor (C1)
is connected since the pins are not internally connected
in some vendors’ capacitors. In Figure 8d the REFH and
REFL pins are connected by short jumpers in an internal
layer. To minimize the inductance of these jumpers they
can be placed in a small hole in the GND plane on the
second board layer.
The LTC2192/LTC2191/LTC2190 have an internal 1.2ꢀV
voltage reference. For a 2V input range using the internal
reference, connect SENSE to V . For a 1V input range
DD
using the internal reference, connect SENSE to ground.
For a 2V input range with an external reference, apply a
1.2ꢀV reference voltage to SENSE (Figure 9).
The input range can be adjusted by applying a voltage to
SENSE that is between 0.62ꢀV and 1.30V. The input range
will then be 1.6 • V
.
SENSE
LTC2192
REFH
REFL
C3
0.1µF
The V , REFH and REFL pins should be bypassed as
REF
shown in Figure 8. A low inductance 2.2µF interdigitated
capacitor is recommended for the bypass between REFH
and REFL. This type of capacitor is available at a low cost
from multiple suppliers.
C1
2.2µF
REFH
C2
0.1µF
REFL
219210 F08b
Alternatively, C1 can be replaced by a standard 2.2µF
capacitor between REFH and REFL. The capacitors should
be as close to the pins as possible (not on the back side
of the circuit board).
CAPACITORS ARE 0402 PACKAGE SIZE
Figure 8b. Alternative REFH/REFL Bypass Circuit
LTC2192
5Ω
V
REF
1.25V BANDGAP
REFERENCE
1.25V
2.2µF
0.625V
219210 F08c
Figure 8c. Recommended Layout for the REFH/REFL Bypass
Circuit in Figure 8a
RANGE
DETECT
AND
CONTROL
TIE TO V FOR 2V RANGE;
DD
SENSE
TIE TO GND FOR 1V RANGE;
RANGE = 1.6 • V
FOR
SENSE
BUFFER
0.625V < V
< 1.300V
SENSE
INTERNAL ADC
HIGH REFERENCE
REFH
REFL
C2
–
+
–
0.1µF
219210 F08d
+
Figure 8d. Recommended Layout for the REFH/REFL Bypass
Circuit in Figure 8b
0.8x
DIFF AMP
C1
REFH
REFL
–
+
+
–
C3
0.1µF
V
REF
INTERNAL ADC
LOW REFERENCE
2.2µF
C1: 2.2µF LOW INDUCTANCE
INTERDIGITATED CAPACITOR
TDK CLLE1AX7S0G225M
MURATA LLA219C70G225M
AVX W2L14Z225M
LTC2192
1.25V
EXTERNAL
REFERENCE
SENSE
1µF
219210 F08a
219210 F09
OR EQUIVALENT
Figure 8a. Reference Circuit
Figure 9. Using an External 1.25V Reference
219210p
19
LTC2192
LTC2191/LTC2190
APPLICATIONS INFORMATION
Encode Input
+
encode input. ENC can be taken above V (up to 3.6V)
DD
+
so 1.8V to 3.3V CMOS logic levels can be used. The ENC
thresholdis0.9V.ForgoodjitterperformanceENC should
have fast rise and fall times. If the encode signal is turned
off or drops below approximately ꢀ00kHz, the A/D enters
nap mode.
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
+
0.1µF
+
ENC
LTC2192
50Ω
50Ω
The differential encode mode is recommended for sinu-
soidal, PECL, or LVDS encode inputs (Figures 12, 13). The
encode inputs are internally biased to 1.2V through 10k
equivalentresistance.Theencodeinputscanbetakenabove
T1
100Ω
0.1µF
–
ENC
0.1µF
V
(upto3.6V),andthecommonmoderangeisfrom1.1V
DD
–
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
to 1.6V. In the differential encode mode, ENC should stay
atleast200mVabovegroundtoavoidfalselytriggeringthe
single-ended encode mode. For good jitter performance
219210 F12
Figure 12. Sinusoidal Encode Drive
+
ENC should have fast rise and fall times.
The single-ended encode mode should be used with
0.1µF
–
+
CMOS encode inputs. To select this mode, ENC is con-
ENC
+
nected to ground and ENC is driven with a square wave
PECL OR
LTC2192
LVDS
CLOCK
0.1µF
LTC2192
–
V
DD
ENC
DIFFERENTIAL
COMPARATOR
219210 F13
V
DD
Figure 13. PECL or LVDS Encode Drive
15k
30k
+
–
ENC
Clock PLL and Duty Cycle Stabilizer
ENC
Theencodeclockismultipliedbyaninternalphase-locked
loop (PLL) to generate the serial digital output data. If the
encode signal changes frequency or is turned off, the PLL
requires 2ꢀµs to lock onto the input clock.
219210 F10
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
A clock duty cycle stabilizer circuit allows the duty cycle
of the applied encode signal to vary from 30% to 70%.
In the serial programming mode it is possible to disable
the duty cycle stabilizer, but this is not recommended. In
the parallel programming mode the duty cycle stabilizer
is always enabled.
LTC2192
+
1.8V TO 3.3V
0V
ENC
–
30k
ENC
CMOS LOGIC
BUFFER
219210 F11
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
219210p
20
LTC2192
LTC2191/LTC2190
APPLICATIONS INFORMATION
DIGITAL OUTPUTS
Optional LVDS Driver Internal Termination
The digital outputs of the LTC2192/LTC2191/LTC2190 are
serialized LVDS signals. Each channel outputs one bit at
a time (1-lane mode), two bits at a time (2-lane mode) or
four bits at a time (4-lane mode). Please refer to the Tim-
ing Diagrams for details. In 4-lane mode the clock duty
cycle stabilizer must be enabled.
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
beenabledbyseriallyprogrammingmodecontrolregister
A2. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When
the internal termination is enabled, the output driver
current is doubled to maintain the same output voltage
swing. Internal termination can only be selected in serial
programming mode.
The output data should be latched on the rising and falling
edges of the data clock out (DCO). A data frame output
(FR) can be used to determine when the data from a new
conversion result begins.
Themaximumserialdatarateforthedataoutputsis1Gbps,
so the maximum sample rate of the ADC will depend on
the serialization mode as well as the speed grade of the
ADC (See Table 1). The minimum sample rate for all se-
rialization modes is ꢀMsps.
DATA FORMAT
Table 2 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A1.
By default the outputs are standard LVDS levels: 3.ꢀmA
output current and a 1.2ꢀV output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
Table 2. Output Codes vs Input Voltage
+
–
A
-A
D15-D0
D15-D0
IN
IN
(2V RANGE)
(OFFSET BINARY)
(2’s COMPLEMENT)
>1.000000V
+0.999970V
+0.999939V
1111 1111 1111 1111 0111 1111 1111 1111
1111 1111 1111 1111 0111 1111 1111 1111
1111 1111 1111 1110 0111 1111 1111 1110
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground.
+0.000030V
+0.000000V
–0.000030V
–0.000061V
1000 0000 0000 0001 0000 0000 0000 0001
1000 0000 0000 0000 0000 0000 0000 0000
0111 1111 1111 1111 1111 1111 1111 1111
0111 1111 1111 1110 1111 1111 1111 1110
Table 1. Maximum Sampling Frequency for All Serialization
Modes. Note That These Limits are for the LTC2192. The
Sampling Frequency for the Slower Speed Grades Cannot
Exceed 40MHz (LTC2191) or 25MHz (LTC2190)
–0.999939V
–1.000000V
<–1.000000V
0000 0000 0000 0001 1000 0000 0000 0001
0000 0000 0000 0000 1000 0000 0000 0000
0000 0000 0000 0000 1000 0000 0000 0000
MAXIMUM
SAMPLING
SERIALIZATION FREQUENCY,
DCO
FR
SERIAL
Digital Output Randomizer
MODE
4-Lane
2-Lane
1-Lane
f (MHz)
S
FREQUENCY FREQUENCY DATA RATE
6ꢀ
6ꢀ
2 • f
4 • f
8 • f
f
S
f
S
f
S
4 • f
8 • f
Interference from the A/D digital outputs is sometimes
unavoidable.Digitalinterferencemaybefromcapacitiveor
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off-chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
S
S
S
S
S
62.ꢀ
16 • f
S
Programmable LVDS Output Current
In LVDS mode, the default output driver current is 3.ꢀmA.
This current can be adjusted by control register A2 in the
serial programming mode. Available current levels are
1.7ꢀmA, 2.1mA, 2.ꢀmA, 3mA, 3.ꢀmA, 4mA and 4.ꢀmA.
In the parallel programming mode the SDO pin can select
either 3.ꢀmA or 1.7ꢀmA.
219210p
21
LTC2192
LTC2191/LTC2190
APPLICATIONS INFORMATION
The digital output is randomized by applying an exclusive
OR logic operation between the LSB and all other data
outputbits.Todecode,thereverseoperationisapplied—an
exclusive OR operation is applied between the LSB and all
other bits. The FR and DCO outputs are not affected. The
output randomizer is enabled by serially programming
mode control register A1.
leaves nap mode. Nap mode is enabled by mode control
register A1 in the serial programming mode.
DEVICE PROGRAMMING MODES
The operating modes of the LTC2192/LTC2191/LTC2190
can be programmed by either a parallel interface or a
simple serial interface. The serial interface has more flex-
ibility and can program all available modes. The parallel
interface is more limited and can only program some of
the more commonly used modes.
Digital Output Test Pattern
To allow in-circuit testing of the digital interface to the
A/D, there is a test mode that forces the A/D data outputs
(D1ꢀ-D0) of both channels to known values. The digital
output test patterns are enabled by serially programming
mode control registers A2, A3 and A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement and randomizer.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to V . The CS, SCK, SDI and SDO pins are binary
DD
logic inputs that set certain operating modes. These pins
can be tied to V or ground, or driven by 1.8V, 2.ꢀV or
DD
3.3V CMOS logic. When used as an input, SDO should
be driven through a 1k series resistor. Table 3 shows the
modes set by CS, SCK, SDI and SDO.
Output Disable
The digital outputs may be disabled by serially program-
ming mode control register A2. The current drive for all
digital outputs including DCO and FR are disabled to save
powerorenablein-circuittesting.Whendisabledthecom-
mon mode of each output pair becomes high impedance,
but the differential impedance may remain low.
Table3.ParallelProgrammingModeControlBits(PAR/SER=VDD
)
PIN
DESCRIPTION
CS/SCK
2-Lane/4-Lane/1-Lane Selection Bits
00 = 2-Lane Output Mode
01 = 4-Lane Output Mode
10 = 1-Lane Output Mode
11 = Not Used
Sleep and Nap Modes
SDI
Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire device is powered down,
resulting in 1mW power consumption. Sleep mode is
enabled by mode control register A1 (serial program-
ming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
SDO
LVDS Current Selection Bit
0 = 3.ꢀmA LVDS Current Mode
1 = 1.7ꢀmA LVDS Current Mode
Serial Programming Mode
depends on the size of the bypass capacitors on V
,
REF
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D mode control
registers. Data is written to a register with a 16-bit serial
word. Data can also be read back from a register to verify
its contents.
REFH and REFL. For the suggested values in Figure 8, the
A/D will stabilize after 2ms.
In nap mode any combination of A/D channels can be
powereddownwhiletheinternalreferencecircuitsandthe
PLL stay active, allowing faster wake up than from sleep
mode. Recovering from nap mode requires at least 100
clock cycles. If the application demands very accurate DC
settling then an additional ꢀ0µs should be allowed so the
on-chip references can settle from the slight temperature
shift caused by the change in supply current as the A/D
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
219210p
22
LTC2192
LTC2191/LTC2190
APPLICATIONS INFORMATION
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
then SDO can be left floating and no pull-up resistor is
needed.
Table 4 shows a map of the mode control registers.
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the Timing
Diagrams). During a read back command the register is
not updated and data on SDI is ignored.
Software Reset
If serial programming is used, the mode control registers
shouldbeprogrammedassoonaspossibleafterthepower
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset is
complete, bit D7 is automatically set back to zero.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and read back is not needed,
Table 4. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
X
Dꢀ
D4
X
D3
X
D2
X
D1
X
D0
X
RESET
X
Bit 7
RESET
0 = Not Used
Software Reset Bit
1 = Software Reset. All Mode Control Registers are Reset to 00h. The ADC is Momentarily Placed in Sleep Mode.
This Bit is Automatically Set Back to Zero After the Reset is Complete
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1: FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
Dꢀ
D4
D3
D2
X
D1
X
D0
DCSOFF
RAND
TWOSCOMP
SLEEP
NAP_2
NAP_1
Bit 7
Bit 6
Bit ꢀ
DCSOFF
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer On
1 = Clock Duty Cycle Stabilizer Off. This is not recommended.
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
TWOSCOMP
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
Two’s Complement Mode Control Bit
Bits 4, 3, 0
SLEEP:NAP_2:NAP_1 Sleep/Nap Mode Control Bits
000 = Normal Operation
0X1 = Channel 1 in Nap Mode
01X = Channel 2 in Nap Mode
1XX = Sleep Mode. Both Channels are Disabled.
Note: Any Combination of Channels Can Be Placed in Nap Mode
Bits 1, 2
Unused, Don’t Care Bits
219210p
23
LTC2192
LTC2191/LTC2190
APPLICATIONS INFORMATION
REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h)
D7
D6
Dꢀ
D4
D3
D2
D1
D0
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
OUTTEST
OUTMODE1
OUTMODE0
Bits 7-ꢀ
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.ꢀmA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.ꢀmA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.ꢀmA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.7ꢀmA LVDS Output Driver Current
Bit 4
Bit 3
TERMON
LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS Output Driver Current is 2× the Current Set by ILVDS2:ILVDS0
OUTOFF
0 = Digital Outputs are Enabled
1 = Digital Outputs are Disabled
Output Disable Bit
Bit 2
OUTTEST
Digital Output Test Pattern Control Bit
0 = Digital Output Test Pattern Off
1 = Digital Output Test Pattern On
Bits 1-0
OUTMODE1:OUTMODE0
00 = 2-Lane Output Mode
01 = 4-Lane Output Mode
10 = 1-Lane Output Mode
11 = Not Used
Digital Output Mode Control Bits
REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h)
D7
D6
Dꢀ
D4
D3
D2
D1
D0
TP1ꢀ
TP14
TP13
TP12
TP11
TP10
TP9
TP8
Bits 7-0
TP15:TP8
Test Pattern Data Bits (MSB)
TP1ꢀ:TP8 Set the Test Pattern for Data Bit 1ꢀ (MSB) Through Data Bit 8.
REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h)
D7
D6
Dꢀ
D4
D3
D2
D1
D0
TP7
TP6
TPꢀ
TP4
TP3
TP2
TP1
TP0
Bits 7-0
TP7:TP0
Test Pattern Data Bits (LSB)
TP7:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0 (LSB).
219210p
24
LTC2192
LTC2191/LTC2190
APPLICATIONS INFORMATION
GROUNDING AND BYPASSING
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
The LTC2192/LTC2191/LTC2190 require a printed circuit
board with a clean unbroken ground plane. A multilayer
board with an internal ground plane in the first layer be-
neath the ADC is recommended. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC.
HEAT TRANSFER
Most of the heat generated by the LTC2192/LTC2191/
LTC2190 is transferred from the die through the bottom-
sideexposedpadandpackageleadsontotheprintedcircuit
board. For good electrical and thermal performance, the
exposed pad must be soldered to a large grounded pad
on the PC board. This pad should be connected to the
internal ground planes by an array of vias.
High quality ceramic bypass capacitors should be used at
the V , OV , V , V , REFH and REFL pins. Bypass
DD
DD CM REF
capacitorsmustbelocatedasclosetothepinsaspossible.
Size0402ceramiccapacitorsarerecommended.Thetraces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
Of particular importance is the capacitor between REFH
and REFL. This capacitor should be on the same side of
the circuit board as the A/D, and as close to the device
as possible.
TYPICAL APPLICATIONS
C4
2.2µF
SDO
SENSE
V
DD
C5
0.1µF
C29
0.1µF
1
2
40
+
V
OUT1C
CM1
39
–
GND
OUT1C
3
38
+
A
A
+
–
A
A
+
–
OUT1D
IN1
IN1
IN1
4
37
–
OUT1D
IN1
5
36
+
C3 0.1µF
C2 0.1µF
GND
DCO
6
35
+
–
+
–
–
REFH
REFL
DCO
–
+
–
+
7
34
33
32
31
30
29
28
27
DIGITAL
OUTPUTS
OV
DD
OV
DD
LTC2192
CN1
8
REFH
REFL
OGND
9
+
FR
C16 0.1µF
10
11
12
13
14
PAR/SER
FR–
+
PAR/SER
A
A
+
OUT2A
A
+
IN2
IN2
–
–
IN2
OUT2A
A
–
IN2
+
GND
OUT2B
–
V
OUT2B
CM2
C37
0.1µF
V
DD
C7
0.1µF
219210 TA02
ENCODE
INPUT
SPI
PORT
219210p
25
LTC2192
LTC2191/LTC2190
TYPICAL APPLICATIONS
Top Side
Inner Layer 2
Inner Layer 4
Bottom Side
Inner Layer 3
Inner Layer 5
219210p
26
LTC2192
LTC2191/LTC2190
PACKAGE DESCRIPTION
UKG Package
52-Lead Plastic QFN (7mm × 8mm)
(Reference LTC DWG # 0ꢀ-08-1729 Rev Ø)
7.50 ±0.05
6.10 ±0.05
5.50 REF
(2 SIDES)
0.70 ±0.05
6.45 ±0.05
6.50 REF
(2 SIDES)
7.10 ±0.05 8.50 ±0.05
5.41 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.50 REF
(2 SIDES)
0.75 ± 0.05
7.00 ± 0.10
(2 SIDES)
R = 0.115
TYP
0.00 – 0.05
51
52
0.40 ± 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45°C
CHAMFER
6.45 ±0.10
8.00 ± 0.10
(2 SIDES)
6.50 REF
(2 SIDES)
5.41 ±0.10
(UKG52) QFN REV
Ø 0306
R = 0.10
TYP
0.25 ± 0.05
TOP VIEW
SIDE VIEW
0.50 BSC
0.200 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
0.75 ± 0.05
NOTE:
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
219210p
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC2192
LTC2191/LTC2190
TYPICAL APPLICATION
1.8V
1.8V
OV
2-Tone FFT, fIN = 70MHz and 69MHz
0
V
DD
DD
–10
OUT1A
OUT1B
OUT1C
OUT1D
OUT2A
OUT2B
OUT2C
OUT2D
CH1
ANALOG
INPUT
16-BIT
–20
–30
–40
–50
–60
–70
S/H
S/H
ADC CORE
CH2
ANALOG
INPUT
SERIALIZED
LVDS
OUTPUTS
16-BIT
ADC CORE
DATA
SERIALIZER
ENCODE
INPUT
–80
–90
–100
–110
–120
PLL
DATA CLOCK OUT
FRAME
GND
OGND
219210 TA01a
0
20
10
FREQUENCY (MHz)
30
219210 G07
RELATED PARTS
PART NUMBER
ADCs
DESCRIPTION
COMMENTS
LTC22ꢀ9-14/LTC2260-14/ 14-Bit, 80Msps/10ꢀMsps/12ꢀMsps
89mW/106mW/127mW, 73.4dB SNR, 8ꢀdB SFDR, DDR LVDS/DDR CMOS/CMOS
LTC2261-14
LTC2262-14
1.8V ADCs, Ultralow Power
Outputs, 6mm × 6mm QFN-36
14-Bit, 1ꢀ0Msps 1.8V ADC, Ultralow
Power
149mW, 72.8dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs,
6mm × 6mm QFN-36
LTC2266-14/LTC2267-14/ 14-Bit, 80Msps/10ꢀMsps/12ꢀMsps
LTC2268-14 1.8V Dual ADCs, Ultralow Power
216mW/2ꢀ0mW/293mW, 73.4dB SNR, 8ꢀdB SFDR, Serial LVDS Outputs,
6mm × 6mm QFN-36
LTC2266-12/LTC2267-12/ 12-Bit, 80Msps/10ꢀMsps/12ꢀMsps
216mW/2ꢀ0mW/293mW, 70.ꢀdB SNR, 8ꢀdB SFDR, Serial LVDS Outputs,
LTC2268-12
LTC2208
1.8V Dual ADCs, Ultralow Power
16-Bit, 130Msps 3.3V ADC
6mm × 6mm QFN-36
12ꢀ0mW, 77.7dB SNR, 100dB SFDR, CMOS/LVDS Outputs, 9mm × 9mm QFN-64
900mW/72ꢀmW, 77.9dB SNR, 100dB SFDR, CMOS Outputs, 7mm × 7mm QFN-48
1190mW/970mW, 81.2dB SNR, 100dB SFDR, CMOS/LVDS Outputs,
9mm × 9mm QFN-64
LT2207/LT2206
LT2217/LT2216
16-Bit, 10ꢀMsps/80Msps 3.3V ADCs
16-Bit, 10ꢀMsps/80Msps 3.3V ADCs
RF Mixers/Demodulators
LTCꢀꢀ17
40MHz to 900MHz Direct Conversion
Quadrature Demodulator
High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
LTCꢀꢀ27
LTCꢀꢀꢀ7
LTCꢀꢀ7ꢀ
400MHz to 3.7GHz High Linearity
Downconverting Mixer
24.ꢀdBm IIP3 at 900MHz, 23.ꢀdBm IIP3 at 3.ꢀGHz, NF = 12.ꢀdB,
ꢀ0Ω Single-Ended RF and LO Ports
400MHz to 3.8GHz High Linearity
Downconverting Mixer
23.7dBm IIP3 at 2.6GHz, 23.ꢀdBm IIP3 at 3.ꢀGHz, NF = 13.2dB, 3.3V Supply
Operation, Integrated Transformer
800MHz to 2.7GHz Direct Conversion
Quadrature Demodulator
High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated RF
and LO Transformer
Amplifiers/Filters
LTC6412
800MHz, 31dB Range, Analog-Controlled Continuously Adjustable Gain Control, 3ꢀdBm OIP3 at 240MHz, 10dB Noise Figure,
Variable Gain Amplifier
4mm × 4mm QFN-24
LTC6420-20
LTC6421-20
1.8GHz Dual Low Noise, Low Distortion
Differential ADC Drivers for 300MHz IF
Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 80mA Supply Current per Amplifier,
3mm × 4mm QFN-20
1.3GHz Dual Low Noise, Low Distortion
Differential ADC Drivers
Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 40mA Supply Current per Amplifier,
3mm × 4mm QFN-20
LTC660ꢀ-7/LTC660ꢀ-10/ Dual Matched 7MHz/10MHz/14MHz
Dual Matched 2nd Order Lowpass Filters with Differential Drivers,
Pin-Programmable Gain, 6mm × 3mm DFN-22
LTC660ꢀ-14
Filters with ADC Drivers
Signal Chain Receivers
LTM9002
14-Bit Dual Channel IF/Baseband
Receiver Subsystem
Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers
219210p
LT 0111 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 9ꢀ03ꢀ-7417
28
●
●
LINEAR TECHNOLOGY CORPORATION 2011
(408) 432-1900 FAX: (408) 434-0ꢀ07 www.linear.com
相关型号：
LT24001/6S912JT26
RESISTOR, TEMPERATURE DEPENDENT, PTC, 9100ohm, THROUGH HOLE MOUNT, AXIAL LEADED
KOA
©2020 ICPDF网 联系我们和版权申明