LT3022 [Linear]
Adjustable 3A Single Resistor Low Dropout Regulator; 可调3A单电阻器低压差稳压器型号: | LT3022 |
厂家: | Linear |
描述: | Adjustable 3A Single Resistor Low Dropout Regulator |
文件: | 总28页 (文件大小:256K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LT3083
Adjustable 3A
Single Resistor Low
Dropout Regulator
FEATURES
DESCRIPTION
n
Outputs May be Paralleled for Higher Current and
The LT®3083 is a 3A low dropout linear regulator that can
be paralleled to increase output current or spread heat on
surfacemountedboards.Architectedasaprecisioncurrent
source and voltage follower, this new regulator finds use
in many applications requiring high current, adjustability
to zero, and no heat sink. The device also brings out the
collectorofthepasstransistortoallowlowdropoutopera-
tion—downto310mV—whenusedwithmultiplesupplies.
Heat Spreading
n
Output Current: 3A
n
Single Resistor Programs Output Voltage
50μA Set Pin Current: 1% Initial Accuracy
Output Adjustable to 0V
Low Output Noise: 40μV
n
n
n
(10Hz to 100kHz)
RMS
n
Wide Input Voltage Range: 1.2V to 23V
(DD-Pak and TO-220 Packages)
Low Dropout Voltage: 310mV
A key feature of the LT3083 is the capability to supply a
wide output voltage range. By using a reference current
throughasingleresistor,theoutputvoltageisprogrammed
to any level between zero and 23V (DD-PAK and TO-220
packages). The LT3083 is stable with 10μF of capacitance
on the output, and the IC is stable with small ceramic ca-
pacitors that do not require additional ESR as is common
with other regulators.
n
n
n
n
n
n
<1mV Load Regulation
<0.001%/V Line Regulation
Minimum Load Current: 1mA
Stable with Minimum 10μF Ceramic Capacitor
Current Limit with Foldback and Overtemperature
Protection
n
Available in 16-Lead TSSOP, 12-Lead 4mm × 4mm
DFN, 5-Lead TO-220 and 5-Lead Surface Mount
DD-PAK Packages
Internal protection circuitry includes current limiting and
thermal limiting. The LT3083 is offered in the 16-lead
TSSOP (with an exposed pad for better thermal character-
istics), 12-lead 4mm × 4mm DFN (also with an exposed
pad), 5-lead TO-220, and 5-lead surface mount DD-PAK
packages.
APPLICATIONS
n
High Current All Surface Mount Supply
n
High Efficiency Linear Regulator
n
Post Regulator for Switching Supplies
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n
Low Parts Count Variable Voltage Supply
n
Low Output Voltage Power Supplies
TYPICAL APPLICATION
Set Pin Current Distribution
1.5V to 0.9V at 3A Supply (Using 3.3V VCONTROL
)
N = 1052
V
CONTROL
3.3V
4.7μF
10μF
V
CONTROL
V
= 0.9V
= 3A
LT3083
V
OUT
MAX
IN
IN
OUT
I
1.5V
*
10μF
SET
R
MIN
909Ω
3083 TA01a
*OPTIONAL FOR
MINIMUM 1mA LOAD
REQUIREMENT
R
18.2k
1%
SET
0.1μF
49
49.5
50
50.5
51
SET PIN CURRENT DISTRIBUTION (μA)
3083 TA01b
3083f
1
LT3083
ABSOLUTE MAXIMUM RATINGS
(Note 1) All Voltages Relative to VOUT
Output Short-Circuit Duration.......................... Indefinite
Operating Junction Temperature Range (Notes 2, 10)
E-, I-grades........................................ –40°C to 125°C
MP-grade........................................... –55°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
CONTROL Pin Voltage............................................. 28V
IN Pin Voltage (T5, Q Packages) ....................18V, –0.3V
No Overload or Short-Circuit .....................23V, –0.3V
IN Pin Voltage (DF, FE Packages).....................8V, –0.3V
No Overload or Short-Circuit .....................14V, –0.3V
SET Pin Current (Note 7) ..................................... 25mA
SET Pin Voltage (Relative to OUT).......................... 10V
T, Q, FE Packages Only .....................................300°C
PIN CONFIGURATION
TOP VIEW
OUT
OUT
OUT
OUT
OUT
OUT
SET
OUT
1
2
3
4
5
6
7
8
16
15
14
13
OUT
IN
TOP VIEW
1
2
3
4
5
6
12 IN
11 IN
OUT
OUT
OUT
OUT
OUT
SET
IN
IN
IN
IN
V
10
9
13
OUT
17
OUT
12 IN
8
CONTROL
11
10
9
V
V
CONTROL
CONTROL
7
V
CONTROL
DF PACKAGE
12-LEAD (4mm s 4mm) PLASTIC DFN
OUT
FE PACKAGE
16-LEAD PLASTIC TSSOP
T
= 125°C, θ = 37°C/W, θ = 8°C/W
JA JC
JMAX
EXPOSED PAD (PIN 13) IS OUT, MUST BE SOLDERED TO PCB
T
= 125°C, θ = 25°C/W, θ = 8°C/W
JA JC
JMAX
EXPOSED PAD (PIN 17) IS OUT, MUST BE SOLDERED TO PCB
FRONT VIEW
FRONT VIEW
5
4
3
2
1
IN
V
5
4
3
2
1
IN
V
CONTROL
CONTROL
TAB IS
OUT
TAB IS
OUT
OUT
SET
NC
OUT
SET
NC
Q PACKAGE
5-LEAD PLASTIC DD-PAK
T PACKAGE
5-LEAD PLASTIC TO-220
T
JMAX
= 125°C, θ = 40°C/W, θ = 3°C/W
T
= 125°C, θ = 15°C/W, θ = 3°C/W
JA JC
JA
JC
JMAX
ORDER INFORMATION
LEAD FREE FINISH
LT3083EDF#PBF
LT3083EFE#PBF
LT3083EQ#PBF
LT3083ET#PBF
LT3083IDF#PBF
LT3083IFE#PBF
TAPE AND REEL
PART MARKING*
3083
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
LT3083EDF#TRPBF
LT3083EFE#TRPBF
LT3083EQ#TRPBF
LT3083ET#TRPBF
LT3083IDF#TRPBF
LT3083IFE#TRPBF
12-Lead (4mm × 4mm) Plastic DFN
16-Lead Plastic TSSOP
3083FE
LT3083Q
LT3083T
3083
5-Lead Plastic DD-PAK
5-Lead Plastic TO-220
12-Lead (4mm × 4mm) Plastic DFN
16-Lead Plastic TSSOP
3083FE
3083f
2
LT3083
ORDER INFORMATION
LEAD FREE FINISH
LT3083IQ#PBF
LT3083IT#PBF
LT3083MPDF#PBF
LT3083MPFE#PBF
LT3083MPQ#PBF
LT3083MPT#PBF
LEAD BASED FINISH
LT3083EDF
TAPE AND REEL
LT3083IQ#TRPBF
LT3083IT#TRPBF
LT3083MPDF#TRPBF
LT3083MPFE#TRPBF
LT3083MPQ#TRPBF
LT3083MPT#TRPBF
TAPE AND REEL
LT3083EDF#TR
LT3083EFE#TR
PART MARKING*
LT3083Q
PACKAGE DESCRIPTION
5-Lead Plastic DD-PAK
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
–55°C to 125°C
–55°C to 125°C
–55°C to 125°C
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
–55°C to 125°C
–55°C to 125°C
–55°C to 125°C
LT3083T
5-Lead Plastic TO-220
083MP
12-Lead (4mm × 4mm) Plastic DFN
16-Lead Plastic TSSOP
3083MPFE
LT3083MPQ
LT3083MPT
PART MARKING*
3083
5-Lead Plastic DD-PAK
5-Lead Plastic TO-220
PACKAGE DESCRIPTION
12-Lead (4mm × 4mm) Plastic DFN
16-Lead Plastic TSSOP
LT3083EFE
3083FE
LT3083EQ
LT3083EQ#TR
LT3083Q
5-Lead Plastic DD-PAK
LT3083ET
LT3083ET#TR
LT3083T
5-Lead Plastic TO-220
LT3083IDF
LT3083IDF#TR
3083
12-Lead (4mm × 4mm) Plastic DFN
16-Lead Plastic TSSOP
LT3083IFE
LT3083IFE#TR
3083FE
LT3083IQ
LT3083IQ#TR
LT3083Q
5-Lead Plastic DD-PAK
LT3083IT
LT3083IT#TR
LT3083T
5-Lead Plastic TO-220
LT3083MPDF
LT3083MPFE
LT3083MPQ
LT3083MPDF#TR
LT3083MPFE#TR
LT3083MPQ#TR
LT3083MPT#TR
083MP
12-Lead (4mm × 4mm) Plastic DFN
16-Lead Plastic TSSOP
3083MPFE
LT3083MPQ
LT3083MPT
5-Lead Plastic DD-PAK
LT3083MPT
5-Lead Plastic TO-220
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SET Pin Current
I
V
V
= 1V, V
≥ 1V, V
= 2V, I
= 1mA, T = 25°C
LOAD
49.5
49
50
50
50.5
51
μA
μA
SET
IN
IN
CONTROL
CONTROL
LOAD
J
≥ 2V, 5mA ≤ I
≤ 3A (Note 9)
l
l
l
l
l
Output Offset Voltage (V
– V
LOAD
)
V
OS
DF, FE Packages
–3
–4
0
0
3
4
mV
mV
OUT
SET
V
= 1V, V
= 2V, I
= 1mA
IN
CONTROL
T, Q Packages
–4
–6
0
0
4
6
mV
mV
Load Regulation (DF, FE Packages)
Load Regulation (T, Q Packages)
Line Regulation (DF, FE Packages)
Line Regulation (T, Q Packages)
Minimum Load Current (Notes 3, 9)
ΔI
ΔV
ΔI
ΔI
= 1mA to 3A
= 5mA to 3A (Note 8)
–10
–0.4
nA
mV
SET
OS
LOAD
LOAD
–1
–4
ΔI
ΔV
ΔI
ΔI
= 1mA to 3A
= 5mA to 3A (Note 8)
–10
–0.7
nA
mV
SET
OS
LOAD
LOAD
ΔI
ΔV
ΔV = 1V to 14V, ΔV
ΔV = 1V to 14V, ΔV
= 2V to 25V, I
= 2V to 25V, I
= 1mA
= 1mA
0.1
0.002
nA/V
mV/V
SET
OS
IN
IN
CONTROL
CONTROL
LOAD
LOAD
0.01
0.01
ΔI
ΔV
ΔV = 1V to 23V, ΔV
ΔV = 1V to 23V, ΔV
= 2V to 25V, I
= 2V to 25V, I
= 1mA
= 1mA
0.1
0.002
nA/V
mV/V
SET
OS
IN
IN
CONTROL
CONTROL
LOAD
LOAD
l
l
V
IN
V
IN
= 1V, V
= 2V
350
500
1
μA
mA
CONTROL
= 14V (DF/FE) or 23V (T/Q), V
= 25V
CONTROL
3083f
3
LT3083
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Dropout Voltage (Note 4)
I
I
I
= 100mA
= 1A
= 3A
1.2
1.22
1.25
V
V
V
CONTROL
LOAD
LOAD
LOAD
l
l
1.55
1.6
l
V
Dropout Voltage (Note 4)
I
= 100mA
10
25
mV
IN
LOAD
l
l
I
I
= 1A, Q, T Packages
= 1A, DF, FE Packages
120
90
190
160
mV
mV
LOAD
LOAD
l
l
I
I
= 3A, Q, T Packages
= 3A, DF, FE Packages
310
240
510
420
mV
mV
LOAD
LOAD
l
l
l
V
Pin Current (Note 5)
I
I
I
= 100mA
= 1A
= 3A
5.5
18
40
10
35
80
mA
mA
mA
CONTROL
LOAD
LOAD
LOAD
l
Current Limit
V
= 5V, V
= 5V, V = 0V, V = –0.1V
OUT
3
3.7
40
1
A
IN
CONTROL
SET
Error Amplifier RMS Output Noise (Note 6)
Reference Current RMS Output Noise (Note 6)
Ripple Rejection
I
= 500mA, 10Hz ≤ f ≤ 100kHz, C
= 10μF, C = 0.1μF
μV
nA
LOAD
OUT
SET
RMS
RMS
10Hz ≤ f ≤ 100kHz
f = 120Hz
f = 10kHz
f = 1MHz
85
75
20
dB
dB
dB
V
C
= 0.5V , I = 0.1A, C = 0.1μF,
P-P L SET
RIPPLE
OUT
= 10μF
Thermal Regulation, I
10ms Pulse
0.003
%/W
SET
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: The V
pin current is the drive current required for the
CONTROL
output transistor. This current will track output current with roughly a 1:60
ratio. The minimum value is equal to the quiescent current of the device.
Note 6: Output noise is lowered by adding a small capacitor across the
voltage setting resistor. Adding this capacitor bypasses the voltage setting
resistor shot noise and reference current noise; output noise is then equal
to error amplifier noise (see the Applications Information section).
Note 2: Unless otherwise specified, all voltages are with respect to V
OUT.
The LT3083 is tested and specified under pulse load conditions such that
T ≅ T . The LT3083E is 100% tested at T = 25°C. Performance of the
J
A
A
LT3083E over the full –40°C to 125°C operating junction temperature
range is assured by design, characterization, and correlation with
statistical process controls. The LT3083I regulators are guaranteed
over the full –40°C to 125°C operating junction temperature range. The
LT3083MP is 100% tested and guaranteed over the –55°C to 125°C
operating junction temperature range.
Note 3: Minimum load current is equivalent to the quiescent current of
the part. Since all quiescent and drive current is delivered to the output
of the part, the minimum load current is the minimum current required to
maintain regulation.
Note 7: The SET pin is clamped to the output with diodes through 1k
resistors. These resistors and diodes will only carry current under
transient overloads.
Note 8: Load regulation is Kelvin sensed at the package.
Note 9: Current limit includes foldback protection circuitry. Current limit
decreases at higher input-to-output differential voltages.
Note 10: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed the maximum operating junction temperature
when overtemperature protection is active. Overtemperature protection
(thermal limit) is typically active at junction temperatures of 165°C.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 4: For the LT3083, dropout is caused by either minimum control
voltage (V
) or minimum input voltage (V ). Both parameters are
CONTROL
IN
specified with respect to the output voltage. The specifications represent
the minimum input-to-output differential voltage required to maintain
regulation.
3083f
4
LT3083
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
SET Pin Current
Set Pin Current Distribution
Offset Voltage (VOUT – VSET
)
1.0
50.5
50.4
50.3
50.2
50.1
50.0
49.9
49.8
49.7
49.6
49.5
N = 1052
I
= 5mA
LOAD
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
49
49.5
50
50.5
51
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
SET PIN CURRENT DISTRIBUTION (μA)
3083 G02
3083 G03
3083 G01
Offset Voltage Distribution
Offset Voltage (VOUT – VSET
)
Offset Voltage (VOUT – VSET)
1.00
0.75
0.50
0.25
0
0.25
0
N = 1052
I
= 5mA
LOAD
T
= 25°C
J
–0.25
–0.50
–0.75
–1.00
–1.25
–1.50
–1.75
T
= 125°C
J
–0.25
–0.50
–0.75
–1.00
–3
–2
–1
0
1
2
3
0
5
10
15
20
25
0
0.5
1
1.5
2
2.5
3
V
DISTRIBUTION (mV)
INPUT-TO-OUTPUT VOLTAGE (V)
LOAD CURRENT (A)
OS
3083 G04
3083 G05
3083 G06
Dropout Voltage, T/Q Packages
(Minimum IN Voltage)
Load Regulation
Minimum Load Current
1.4
400
350
300
250
200
150
100
50
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
100
50
V
= V
CONTROL
IN
CHANGE IN OFFSET VOLTAGE (V
– V
)
SET
OUT
1.2
1.0
0.8
0.6
0.4
0.2
0
T
= 125°C
J
0
V
– V
= 23V
OUT
IN,CONTROL
CHANGE IN REFERENCE CURRENT
–50
–100
–150
–200
–250
–300
T
= 25°C
J
T
= –50°C
J
V
– V
= 1.5V
OUT
IN,CONTROL
ΔI
IN
= 5mA TO 3A
LOAD
V
= V
= V
+ 2V
CONTROL
OUT
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
0
0.5
1
1.5
2
2.5
3
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
LOAD CURRENT (A)
3083 G08
3083 G09
3083 G07
3083f
5
LT3083
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Dropout Voltage, T/Q Packages
(Minimum IN Voltage)
Dropout Voltage, FE/DF Packages
(Minimum IN Voltage)
Dropout Voltage, FE/DF Packages
500
450
400
350
300
250
200
150
100
50
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
T
= 125°C
J
I
= 3A
LOAD
I
= 3A
LOAD
T
= 25°C
J
I
= 1.5A
LOAD
I
= 1.5A
LOAD
T
= –50°C
J
I
= 500mA
I
= 500mA
LOAD
LOAD
I = 100mA
LOAD
I
= 100mA
LOAD
0
0
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
0
0.5
1
1.5
2
2.5
3
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
LOAD CURRENT (A)
3083 G12
3083 G10
3083 G11
Dropout Voltage (Minimum
VCONTROL Pin Voltage)
Dropout Voltage (Minimum
VCONTROL Pin Voltage)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
I
= 3A
LOAD
T
= –50°C
J
T
= 25°C
J
T
= 125°C
J
0
0.5
1
1.5
2
2.5
3
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
LOAD CURRENT (A)
3083 G13
3083 G14
Current Limit
Current Limit
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
= 25°C
J
V
V
= V
= 7V
IN
OUT
CONTROL
0
= 0V
–50 –25
25 50 75 100 125 150
0
5
10
15
IN OUT
20
TEMPERATURE (°C)
IN-TO-OUT DIFFERENTIAL (V – V ) (V)
3083 G15
3083 G16
3083f
6
LT3083
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Load Transient Response
Load Transient Response
250
150
50
150
100
50
V
V
V
C
= 2V
IN
CONTROL
V
V
V
C
= 2V
IN
CONTROL
= 3V
= 3V
= 1V
OUT
SET
= 1V
OUT
SET
= 0.1μF
C
OUT
= 22μF CERAMIC
= 0.1μF
C
= 22μF CERAMIC
OUT
–50
–150
0
–50
–100
1.0
0.5
0
C
= 10μF CERAMIC
OUT
4
2
0
ΔI
= 500mA TO 3A
LOAD
ΔI
= 100mA TO 1A
LOAD
0
20 40 60 80 100 120 140 160 180 200
TIME (μs)
0
20 40 60 80 100 120 140 160 180 200
TIME (μs)
3083 G18
3083 G17
Line Transient Response
Turn-On Response
Turn-On Response
7
6
6
5
4
V
= 1V
= 10mA
OUT
I
LOAD
C
C
3
2
= 10μF CERAMIC
= 0.1μF
OUT
SET
4
5
3
4
1
2
3
1
0
0
10
0
1.0
1.0
0.5
0
0.5
R
SET
= 20k
= 0
R
= 20k
= 0.1μF
= 1Ω
SET
SET
C
C
SET
–10
–20
0
R
C
= 0.33Ω
R
C
LOAD
OUT
LOAD
= 10μF CERAMIC
= 10μF CERAMIC
OUT
–0.5
–0.5
0
20 40 60 80 100 120 140 160 180 200
TIME (μs)
0
5
10 15 20 25 30 35 40 45 50
TIME (μs)
0
2
4
6
8
10 12 14 16 18 20
TIME (ms)
3083 G19
3083 G20
3083 G21
Residual Output Voltage with
Less Than Minimum Load
VCONTROL Pin Current
VCONTROL Pin Current
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
600
500
400
300
200
100
0
V
V
– V
= 2V
OUT
CONTROL
– V
V
= 20V
= 1V
OUT
IN
IN
V
= 10V
IN
T
= –50°C
J
V
= 5V
IN
ADD 1N4148 FOR
< 1k
I
= 3A
LOAD
R
TEST
T
= 25°C
J
SET PIN = 0V
DEVICE IN
CURRENT LIMIT
V
V
OUT
IN
T
= 125°C
J
R
TEST
I
= 1.5A
LOAD
2
0
0.5
1
1.5
2
2.5
3
0
4
6
8
10 12 14 16 18
0
500
1000
R (Ω)
SET
1500
2000
LOAD CURRENT (A)
IN-TO-OUT DIFFERENTIAL (V – V ) (V)
IN
OUT
3083 G23
3083 G22
3083 G24
3083f
7
LT3083
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Ripple Rejection, Dual Supply,
VCONTROL Pin
Ripple Rejection, Dual Supply,
IN Pin
Ripple Rejection, Single Supply
100
90
80
70
60
50
40
30
20
10
0
120
105
90
75
60
45
30
15
0
120
105
90
75
60
45
30
15
0
I
= 0.1A
LOAD
I
= 0.1A
LOAD
I
= 0.5A
LOAD
I
= 0.1A
LOAD
I
= 1.5A
LOAD
I
= 0.5A
I
= 1.5A
LOAD
LOAD
I
= 1.5A
LOAD
C
C
= 10μF CERAMIC
= 0.1μF CERAMIC
C
C
V
V
= 10μF CERAMIC
= 0.1μF
C
C
V
V
= 10μF CERAMIC
= 0.1μF
OUT
SET
OUT
OUT
SET
IN
SET
RIPPLE = 50mV
= V
+ 1V
OUT(NOMINAL)
= V
+ 1V
OUT(NOMINAL)
P-P
= V
IN
OUT(NOMINAL)
= V
OUT(NOMINAL)
= V
V
– V
+ 2V
+ 2V
+ 2V
IN
CONTROL
OUT(NOMINAL)
10k 100k
CONTROL
CONTROL
10
100
1k
1M
10M
10
100
1k
10k 100k
1M
10M
10
100
1k
10k 100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
3083 G25
3083 G26
3083 G27
Ripple Rejection (120Hz)
Noise Spectral Density
80
79
78
77
76
75
74
73
72
71
70
1000
100
10
100
V
= V
= V
P-P
+ 2V
OUT(NOMINAL)
IN
CONTROL
RIPPLE = 500mV , ƒ = 120Hz
I
= 0.5A
LOAD
C
= 0.1μF, C
= 10μF
OUT
SET
1
100k
10
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
10
100
1k
FREQUENCY (Hz)
10k
3083 G28
3083 G29
Output Voltage Noise
Error Amplifier Gain and Phase
21
18
15
12
9
36
0
PHASE
–36
–72
–108
–144
–180
–216
–252
–288
–324
–360
6
V
OUT
3
100μV/DIV
0
GAIN
–3
–6
–9
–12
–15
I
I
I
= 0.5A
= 1.5A
= 3A
LOAD
LOAD
LOAD
–396
1M
3083 G30
TIME 1ms/DIV
10
100
1k
10k
100k
V
C
LOAD
= 1V, R
= 0.1μF, C
= 3A
= 20k
OUT
FREQUENCY (Hz)
OUT
SET
SET
= 10μF
3083 G31
I
3083f
8
LT3083
PIN FUNCTIONS (DF/FE/Q/T Packages)
OUT (Pins 1-5,13/Pins 1-6,8,9,16,17/Pin 3, Tab/Pin 3,
Tab): Output. The exposed pad of the DF package (Pin 13)
and the FE package (Pin 17) and the Tab of the DD-PAK
and TO-220 packages is an electrical connection to OUT.
Connect the exposed pad of the DF and FE packages and
the Tab of the DD-PAK package directly to OUT on the
PCB and the respective OUT pins for each package. There
must be a minimum load current of 1mA or the output
may not regulate.
V
(Pins 7,8/Pins 10,11/Pin 4/Pin 4): Bias Sup-
CONTROL
ply. This is the supply pin for the control circuitry of the
device. Minimum input capacitance is 2.2μF (see Input
Capacitance and Stability in the Applications Information
section). The current flow into this pin is about 1.7% of
the output current. For the device to regulate, this voltage
must be more than 1.2V to 1.4V greater than the output
voltage (see dropout specifications in the Electrical Char-
acteristics section).
SET (Pin 6/Pin 7/Pin 2/Pin 2): Set Point. This pin is the
non-inverting input to the error amplifier and the regula-
tion set point. A fixed current of 50ꢀA flows out of this
pin through a single external resistor, which programs
the output voltage of the device. Output voltage range is
IN (Pins 9-12/Pins 12-15/Pin 5/Pin 5): Power Input. This
is the collector to the power device of the LT3083. The
output load current is supplied through this pin. Minimum
IN capacitance is 10μF (see Input Capacitance and Stabil-
ity in Applications Information section). For the device to
regulate, the voltage at this pin must be more than 0.1V
to 0.5V greater than the output voltage (see dropout
specifications in the Electrical Characteristics section).
zero to the V
– V
. Transient performance
IN(MAX)
DROPOUT
can be improved by adding a small capacitor from the
SET pin to ground.
NC(NA/NA/Pin1/Pin1):NoConnection.NoConnectpins
have no connection to internal circuitry and may be tied
to V , V
, V , GND, or floated.
IN CONTROL OUT
3083f
9
LT3083
BLOCK DIAGRAM
IN
V
CONTROL
50μA
+
–
3083 BD
SET
OUT
3083f
10
LT3083
APPLICATIONS INFORMATION
The LT3083 has the collector of the output transistor con-
nected to a separate pin from the control input. Since the
dropout on the collector (IN pin) is typically only 310mV,
two supplies can be used to power the LT3083 to reduce
dissipation:ahighervoltagesupplyforthecontrolcircuitry
and a lower voltage supply for the collector. This increases
efficiency and reduces dissipation. To further spread the
heat, a resistor inserted in series with the collector moves
some of the heat out of the IC to spread it on the PC board
(see the section Reducing Power Dissipation).
TheLT3083regulatoriseasytouseandhasalltheprotection
featuresexpectedinhighperformanceregulators.Included
areshort-circuitprotectionandsafeoperatingareaprotec-
tion, as well as thermal shutdown with hysteresis.
The LT3083 fits well in applications needing multiple rails.
This new architecture adjusts down to zero with a single
resistor,handlingmodernlowvoltagedigitalIC’saswellas
allowing easy parallel operation and thermal management
withoutheatsinks.Adjustingtozerooutputallowsshutting
off the powered circuitry. When the input is pre-regulated,
such as with a 5V or 3.3V input supply, external resistors
can help spread the heat.
The LT3083 can be operated in two modes. Three termi-
nal mode has the V
pin connected to the IN pin
CONTROL
and gives a limitation of 1.25V dropout. Alternatively, the
pin is separately tied to a higher voltage and the
IN pin to a lower voltage giving 310mV dropout on the IN
pin, minimizing total power dissipation. This allows for a
Aprecision“0”TC50ꢀAreferencecurrentsourceconnects
to the noninverting input of a power operational amplifier.
Thepoweroperationalamplifierprovidesalowimpedance
buffered output to the voltage on the noninverting input.
A single resistor from the noninverting input to ground
sets the output voltage. If this resistor is set to 0Ω, zero
output voltage results. Therefore, any output voltage can
be obtained between zero and the maximum defined by
the input power supply.
V
CONTROL
3A supply regulating from 2.5V to 1.8V
or 1.8V to
IN
OUT
IN
1.2V
with low power dissipation.
OUT
Programming Output Voltage
The LT3083 sources a 50ꢀA reference current that flows
out of the SET pin. Connecting a resistor from SET to
ground generates a voltage that becomes the reference
point for the error amplifier (see Figure 1). The refer-
ence voltage equals 50μA multiplied by the value of
the SET pin resistor. Any voltage can be generated and
there is no minimum output voltage for the regulator.
The benefit of using a true internal current source as the
reference,asopposedtoabootstrappedreferenceinolder
regulators, is not so obvious in this architecture. A true
reference current source allows the regulator to have gain
and frequency response independent of the impedance on
the positive input. On older adjustable regulators, such as
the LT1086, loop gain changes with output voltage and
bandwidth changes if the adjustment pin is bypassed to
ground. For the LT3083, the loop gain is unchanged with
output voltage changes or bypassing. Output regulation
is not a fixed percentage of output voltage, but is a fixed
fraction of millivolts. Use of a true current source allows
all of the gain in the buffer amplifier to provide regulation,
and none of that gain is needed to amplify up the reference
to a higher output voltage.
IN
LT3083
V
CONTROL
50μA
+
–
+
+
V
V
CONTROL
IN
OUT
V
C
OUT
SET
R
OUT
C
SET
SET
3083 F01
V
OUT
= 50μA • R
SET
Figure 1. Basic Adjustable Regulator
3083f
11
LT3083
APPLICATIONS INFORMATION
Table 1 lists many common output voltages and the clos-
est standard 1% resistor values used to generate that
output voltage.
OUT
Regulation of the output voltage requires a minimum
load current of 1mA. For a true zero voltage output
operation, return this 1mA load current to a negative
supply voltage.
Table 1. 1% Resistors for Common Output Voltages
V
(V)
R
(k)
SET
OUT
GND
SET PIN
3083 F02
1
20
1.2
24.3
30.1
35.7
49.9
66.5
100
Figure 2. Guard Ring Layout Example
for DF Package
1.5
1.8
2.5
3.3
5
to remedy this is to bypass the SET pin with a small
amount of capacitance from SET to ground, 10pF to
20pF is sufficient.
With the lower level current used to generate the refer-
ence voltage, leakage paths to or from the SET pin can
create errors in the reference and output voltages. High
quality insulation should be used (e.g., Teflon, Kel-F);
cleaning of all insulating surfaces to remove fluxes and
other residues will probably be required. Surface coating
may be necessary to provide a moisture barrier in high
humidity environments.
Stability and Input Capacitance
Typical minimum input capacitance is 10μF for IN and
2.2μF for V
. These amounts of capacitance work
CONTROL
well using low ESR ceramic capacitors when placed close
to the LT3083 and the circuit is located in close proximity
to the power source. Higher values of input capacitance
may be necessary to maintain stability depending on the
application.
Minimize board leakage by encircling the SET pin and
circuitry with a guard ring operated at a potential close
to itself. Tie the guard ring to the OUT pin. Guard rings
on both sides of the circuit board are required. Bulk leak-
age reduction depends on the guard ring width. 50nA
of leakage into or out of the SET pin and its associated
circuitry creates a 0.1% reference voltage error. Leakages
of this magnitude, coupled with other sources of leakage,
can cause significant offset voltage and reference drift,
especially over the possible operating temperature range.
Figure 2 depicts an example of a guard ring layout.
Oscillatingregulatorcircuitsareoftenviewedasaproblem
of phase margin and inadequate stability with the output
capacitor used. More and more frequently, the problem
is not the regulator operating without sufficient output
capacitance, but instead with too little input capacitance.
The entire circuit must be analyzed and debugged as a
whole; conditions relating to the input of the regulator
cannot be ignored.
The LT3083 input presents a high impedance to its power
source:theoutputvoltageandloadcurrentareindependent
of input voltage variations. To maintain stability of the
regulator circuit as a whole, the LT3083 must be powered
from a low impedance supply. When using short supply
lines or powering directly from a large switching supply,
there is no issue—hundreds or thousands of microfarads
of capacitance are available through a low impedance.
If guard ring techniques are used, this bootstraps any
stray capacitance at the SET pin. Since the SET pin is
a high impedance node, unwanted signals may couple
into the SET pin and cause erratic behavior. This will
be most noticeable when operating with minimum
output capacitors at full load current. The easiest way
3083f
12
LT3083
APPLICATIONS INFORMATION
When longer supply lines, filters, current sense resistors,
or other impedances exist between the supply and the
input to the LT3083, input bypassing should be reviewed
if stability concerns are seen. Just as output capacitance
supplies the instantaneous changes in load current for
output transients until the regulator is able to respond,
inputcapacitancesupplieslocalpowertotheregulatoruntil
themainsupplyresponds.Whenimpedanceseparatesthe
LT3083 from its main supply, the local input can droop
so that the output follows. The entire circuit may break
intooscillations,usuallycharacterizedbylargeramplitude
oscillations on the input and coupling to the output.
to reduce overall inductance is to place both forward and
return current conductors (the input and GND wires) in
verycloseproximity.Two30-AWGwiresseparatedbyonly
0.02", used as forward- and return- current conductors,
reduce the overall self-inductance to approximately one-
fifth that of a single isolated wire.
If wiring modifications are not permissible for the applica-
tions,includingseriesresistancebetweenthepowersupply
and the input of the LT3083 also stabilizes the application.
Aslittleas0.1Ωto0.5Ω, oftenless, iseffectiveindamping
the LC resonance. If the added impedance between the
powersupplyandtheinputisunacceptable,addingESRto
theinputcapacitoralsoprovidesthenecessarydampingof
the LC resonance. However, the required ESR is generally
higher than the series impedance required.
Low ESR, ceramic input bypass capacitors are acceptable
forapplicationswithoutlonginputleads.However,applica-
tions connecting a power supply to an LT3083 circuit’s IN
and GND pins with long input wires combined with low
ESR, ceramicinputcapacitorsarepronetovoltagespikes,
reliability concerns and application-specific board oscil-
lations. The input wire inductance found in many battery
poweredapplications,combinedwiththelowESRceramic
inputcapacitor, formsahigh-QLCresonanttankcircuit. In
some instances this resonant frequency beats against the
output current dependent LDO bandwidth and interferes
with proper operation. Simple circuit modifications/solu-
tions are then required. This behavior is not indicative of
LT3083 instability, but is a common ceramic input bypass
capacitor application issue.
Stability and Output Capacitance
The LT3083 requires an output capacitor for stability. It
is designed to be stable with most low ESR capacitors
(typically ceramic, tantalum or low ESR electrolytic). A
minimum output capacitor of 10ꢀF with an ESR of 0.5ꢁ
or less is recommended to prevent oscillations. Larger
values of output capacitance decrease peak deviations
and provide improved transient response for larger load
current changes. Bypass capacitors, used to decouple
individual components powered by the LT3083, increase
the effective output capacitor value. For improvement in
transient performance, place a capacitor across the volt-
age setting resistor. Capacitors up to 1ꢀF can be used.
This bypass capacitor reduces system noise as well, but
start-up time is proportional to the time constant of the
The self-inductance, or isolated inductance, of a wire is
directly proportional to its length. Wire diameter is not a
major factor on its self-inductance. For example, the self-
inductance of a 2-AWG isolated wire (diameter = 0.26") is
about half the self-inductance of a 30-AWG wire (diameter
= 0.01"). One foot of 30-AWG wire has about 465nH of
self-inductance.
voltage setting resistor (R
bypass capacitor.
in Figure 1) and SET pin
SET
Give extra consideration to the use of ceramic capacitors.
Ceramic capacitors are manufactured with a variety of di-
electrics, each with different behavior across temperature
and applied voltage. The most common dielectrics used
are specified with EIA temperature characteristic codes of
Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are
good for providing high capacitances in a small package,
but they tend to have strong voltage and temperature
coefficients as shown in Figures 3 and 4. When used with
a 5V regulator, a 16V 10ꢀF Y5V capacitor can exhibit an
One of two ways reduces a wire’s self-inductance. One
method divides the current flowing towards the LT3083
between two parallel conductors. In this case, the farther
apart the wires are from each other, the more the self-in-
ductance is reduced; up to a 50% reduction when placed
a few inches apart. Splitting the wires basically connects
two equal inductors in parallel, but placing them in close
proximity gives the wires mutual inductance adding to
the self-inductance. The second and most effective way
3083f
13
LT3083
APPLICATIONS INFORMATION
20
effective value as low as 1ꢀF to 2ꢀF for the DC bias voltage
appliedandovertheoperatingtemperaturerange.TheX5R
and X7R dielectrics result in more stable characteristics
and are more suitable for use as the output capacitor.
The X7R type has better stability across temperature,
while the X5R is less expensive and is available in higher
values. Care still must be exercised when using X5R and
X7R capacitors. The X5R and X7R codes only specify
operating temperature range and maximum capacitance
change over temperature. Capacitance change due to DC
bias with X5R and X7R capacitors is better than Y5V and
Z5U capacitors, but can still be significant enough to drop
capacitor values below appropriate levels. Capacitor DC
bias characteristics tend to improve as component case
size increases, but expected capacitance at operating
voltage should be verified.
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
0
X5R
–20
–40
–60
Y5V
–80
–100
0
8
12 14
2
4
6
10
16
DC BIAS VOLTAGE (V)
3083 F03
Figure 3. Ceramic Capacitor DC Bias Characteristics
40
20
X5R
0
–20
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress. In a
ceramic capacitor, the stress can be induced by vibrations
in the system or thermal transients.
–40
Y5V
–60
–80
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
–100
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
Paralleling Devices
3083 F04
Higher output current is obtained by paralleling multiple
LT3083s together. Tie the individual SET pins together and
tie the individual IN pins together. Connect the outputs in
commonusingsmallpiecesofPCtraceasballastresistors
to promote equal current sharing. PC trace resistance in
mꢁ/inch is shown in Table 2. Ballasting requires only a
tiny area on the PCB.
Figure 4. Ceramic Capacitor Temperature Characteristics
V
LT3083
IN
V
CONTROL
+
–
10mꢁ
OUT
Table 2. PC Board Trace Resistance
SET
WEIGHT (oz)
10mil WIDTH
54.3
20mil WIDTH
27.1
V
IN
V
LT3083
IN
1
2
4.8V
TO 20V
27.1
13.6
V
CONTROL
Trace resistance is measured in mΩ/in
+
–
10μF
The worst-case room temperature offset, only 4mV
(DD-PAK, T Packages) between the SET pin and the OUT
pin, allows the use of very small ballast resistors.
10mꢁ
V
3.3V
6A
OUT
OUT
SET
33k
10μF
As shown in Figure 5, each LT3083 has a small 10mΩ
ballast resistor, which at full output current gives better
than 80% equalized sharing of the current. The external
3083 F05
Figure 5. Parallel Devices
3083f
14
LT3083
APPLICATIONS INFORMATION
resistance of 10mΩ (5mΩ for the two devices in paral-
lel) only adds about 30mV of output regulation drop at
an output of 6A. With an output voltage of 3.3V, this only
adds 1% to the regulation. Of course, paralleling more
than two LT3083s yields even higher output current.
Spreading the devices on the PC board also spreads the
heat. Series input resistors can further spread the heat if
the input-to-output difference is high.
TheLT3083’snoiseadvantageisthattheunitygainfollower
presents no noise gain whatsoever from the SET pin to the
output. Thus, noise figures do not increase accordingly.
Error amplifier noise is typically 126.5nV/√Hz (40μV
)
RMS
over the 10Hz to 100kHz bandwidth). The error amplifier’s
noise is RMS summed with the other noise terms to give
a final noise figure for the regulator.
Curves in the Typical Performance Characteristics sec-
tion show noise spectral density and peak-to-peak noise
characteristics for both the reference current and error
amplifier over the 10Hz to 100kHz bandwidth.
Quieting the Noise
The LT3083 offers numerous noise performance advan-
tages. Every linear regulator has its sources of noise. In
general, a linear regulator’s critical noise source is the
reference. In addition, consider the error amplifier’s noise
contribution along with the resistor divider’s noise gain.
Load Regulation
The LT3083 is a floating device. No ground pin exists on
the packages. Thus, the IC delivers all quiescent current
and drive current to the load. Therefore, it is not possible
toprovidetrueremoteloadsensing.Theconnectionresis-
tance between the regulator and the load determines load
regulation performance. The data sheet’s load regulation
specification is Kelvin sensed at the package’s pins. Nega-
tive-side sensing is a true Kelvin connection by returning
the bottom of the voltage setting resistor to the negative
side of the load (see Figure 6).
Manytraditionallownoiseregulatorsbondoutthevoltage
reference to an external pin (usually through a large value
resistor) to allow for bypassing and noise reduction. The
LT3083 does not use a traditional voltage reference like
other linear regulators. Instead, it uses a 50μA reference
current. The 50μA current source generates noise current
levels of 3.16pA/√Hz (1nA
) over the 10Hz to 100kHz
RMS
bandwidth). The equivalent voltage noise equals the RMS
noise current multiplied by the resistor value.
Connected as shown, system load regulation is the sum
of the LT3083’s load regulation and the parasitic line
resistance multiplied by the output current. To minimize
load regulation, keep the positive connection between the
regulator and load as short as possible. If possible, use
large diameter wire or wide PC board traces.
The SET pin resistor generates spot noise equal to √4kTR
–23
(k=Boltzmann’sconstant,1.38•10 J/°K,andTisabso-
lute temperature) which is RMS summed with the voltage
noise.Iftheapplicationrequireslowernoiseperformance,
bypassthevoltagesettingresistorwithacapacitortoGND.
Notethatthisnoise-reductioncapacitorincreasesstart-up
time as a factor of the RC time constant.
IN
LT3083
V
CONTROL
The LT3083 uses a unity-gain follower from the SET pin
to the OUT pin. Therefore, multiple possibilities exist
(besides a SET pin resistor) to set output voltage. For
example, using a high accuracy voltage reference from
SET to GND removes the errors in output voltage due to
reference current tolerance and resistor tolerance. Active
driving of the SET pin is acceptable.
PARASITIC
+
–
RESISTANCE
R
P
OUT
LOAD
R
SET
R
P
SET
R
P
3080 F06
The typical noise scenario for a linear regulator is that the
output voltage setting resistor divider gains up the noise
Figure 6. Connections for Best Load Regulation
reference, especially if V
is much greater than V
.
OUT
REF
3083f
15
LT3083
APPLICATIONS INFORMATION
Thermal Considerations
Table 4. FE Package, 16-Lead TSSOP
COPPER AREA
THERMAL RESISTANCE
The LT3083’s internal power and thermal limiting circuitry
protects itself under overload conditions. For continuous
normalloadconditions,donotexceedthe125°Cmaximum
junction temperature. Carefully consider all sources of
thermalresistancefromjunction-to-ambient.Thisincludes
(but is not limited to) junction-to-case, case-to-heat sink
interface, heat sink resistance or circuit board-to-ambient
astheapplicationdictates.Consideralladditional,adjacent
heat generating sources in proximity on the PCB.
TOPSIDE*
BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2
2
2
2
2
2
2
2
2
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
16°C/W
20°C/W
26°C/W
32°C/W
2
1000mm
2
225mm
2
100mm
*Device is mounted on topside.
Table 5. Q Package, 5-Lead DD-PAK
COPPER AREA
THERMAL RESISTANCE
BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
Surface mount packages provide the necessary heat
sinking by using the heat spreading capabilities of the
PC board, copper traces, and planes. Surface mount heat
sinks, plated through-holes and solder-filled vias can also
spread the heat generated by power devices.
TOPSIDE*
2
2
2
2
2
2
2
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
13°C/W
14°C/W
16°C/W
2
1000mm
2
125mm
*Device is mounted on topside.
Junction-to-case thermal resistance is specified from the
ICjunctiontothebottomofthecasedirectly, orthebottom
of the pin most directly in the heat path. This is the lowest
thermal resistance path for heat flow. Only proper device
mountingensuresthebestpossiblethermalflowfromthis
area of the packages to the heat sinking material.
T Package, 5-Lead TO-220
Thermal Resistance (Junction-to-Case) = 3°C/W
For further information on thermal resistance and using
thermal information, refer to JEDEC standard JESD51,
notably JESD51-12.
Note that the exposed pad of the DFN and TSSOP pack-
ages and the tab of the DD-PAK and TO-220 packages
PCB layers, copper weight, board layout and thermal vias
affect the resultant thermal resistance. Tables 3 through 5
provide thermal resistance numbers for best-case 4-layer
boards with 1oz internal and 2oz external copper. Modern,
multilayer PCBs may not be able to achieve quite the same
level performance as found in these tables.
are electrically connected to the output (V ).
OUT
Tables 3 through 5 list thermal resistance as a function
of copper areas on a fixed board size. All measurements
were taken in still air on a 4-layer FR-4 board with 1oz
solid internal planes and 2oz external trace planes with a
total finished board thickness of 1.6mm. Layers are not
connected electrically or thermally.
Calculating Junction Temperature
Example: Given an output voltage of 0.9V, a V
CONTROL
voltage of 3.3V 10%, an IN voltage of 1.5V 5%, output
current range from 10mA to 3A and a maximum ambient
temperature of 50°C, what will the maximum junction
Table 3. DF Package, 12-Lead DFN
COPPER AREA
THERMAL RESISTANCE
TOPSIDE*
BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2
2
2
2
2
2
2
2
2
2
temperature be for the DD-PAK on a 2500mm board with
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
18°C/W
22°C/W
29°C/W
35°C/W
2
2
topside copper of 1000mm ?
1000mm
2
225mm
2
100mm
*Device is mounted on topside.
3083f
16
LT3083
APPLICATIONS INFORMATION
The power in the drive circuit equals:
As an example, assume: V = V
= 5V, V
= 3.3V
IN
CONTROL
OUT
and I
= 2A. Use the formulas from the Calculating
OUT(MAX)
P
= (V
– V )(I
OUT CONTROL
)
DRIVE
CONTROL
Junction Temperature section previously discussed.
where I
is equal to I /60. I
is a function
canbefound
CONTROL
ofoutputcurrent. AcurveofI
OUT
CONTROL
WithoutseriesresistorR ,powerdissipationintheLT3083
S
vsI
CONTROL
OUT
equals:
in the Typical Performance Characteristics curves.
⎛
⎜
⎝
⎞
⎟
⎠
2A
60
The total power equals:
PTOTAL = 5V − 3.3V •
+ 5V − 3.3V • 2A
(
)
(
)
P
= P
+ P
TOTAL
DRIVE OUTPUT
= 3.46W
The current delivered to the SET pin is negligible and can
be ignored.
If the voltage differential (V ) across the NPN pass
transistor is chosen as 0.5V, then RS equals:
DIFF
V
V
V
= 3.630V (3.3V + 10%)
CONTROL(MAX_CONTINUOUS)
5V − 3.3V − 0.5V
= 1.575V (1.5V + 5%)
RS =
= 0.6Ω
IN(MAX_CONTINUOUS)
2A
= 0.9V, I
= 3A, T = 50°C
A
OUT
OUT
Power dissipation in the LT3083 now equals:
Power dissipation under these conditions is equal to:
= (V – V )(I
⎛
⎜
⎝
⎞
⎟
⎠
2A
60
PTOTAL = 5V − 3.3V •
+ 0.5V • 2A = 1.06W
P
)
OUT CONTROL
(
)
DRIVE
CONTROL
IOUT
3A
ICONTROL
=
=
= 50mA
TheLT3083’spowerdissipationisnowonly30%compared
60 60
= (3.630V – 0.9V)(50mA) = 137mW
to no series resistor. R dissipates 2.4W of power. Choose
S
P
P
P
appropriate wattage resistors or use multiple resistors in
DRIVE
parallel to handle and dissipate the power properly.
= (V – V )(I )
OUT OUT
OUTPUT
OUTPUT
IN
= (1.575V – 0.9V)(3A) = 2.03W
V
V
IN
IN
V
C1
CONTROL
LT3083
R
S
Total Power Dissipation = 2.16W
IN
a
Junction Temperature will be equal to:
T = T + P
• θ (using tables)
JA
J
A
TOTAL
+
–
T = 50°C + 2.16W • 16°C/W = 84.6°C
J
OUT
V
OUT
In this case, the junction temperature is below the maxi-
mum rating, ensuring reliable operation.
3083 F07
C2
SET
R
SET
Reducing Power Dissipation
Figure 7. Reducing Power Dissipation Using a Series Resistor
In some applications it may be necessary to reduce the
power dissipation in the LT3083 package without sacrific-
ingoutputcurrentcapability.Twotechniquesareavailable.
The first technique, illustrated in Figure 7, employs a
resistor in series with the regulator’s input. The voltage
drop across RS decreases the LT3083’s input-to-output
differential voltage and correspondingly decreases the
LT3083’s power dissipation.
3083f
17
LT3083
APPLICATIONS INFORMATION
The second technique for reducing power dissipation,
shown in Figure 8, uses a resistor in parallel with the
LT3083. This resistor provides a parallel path for current
flow, reducing the current flowing through the LT3083.
This technique works well if input voltage is reasonably
constant and output load current changes are small. This
technique also increases the maximum available output
current at the expense of minimum load requirements.
As an example, assume: V = V
= 5V, V
OUT(MAX)
=
IN(MAX)
IN
CONTROL
= 3.2V, I
5.5V, V
= 3.3V, V
= 2A and
OUT
OUT(MIN)
I
= 0.7A. Also, assuming that R carries no more
OUT(MIN)
P
than 90% of I
= 630mA.
OUT(MIN)
Calculating R yields:
P
5.5V − 3.2V
RP =
= 3.65Ω
0.63A
(5% Standard Value = 3.6Ω)
V
IN
V
C1
CONTROL
LT3083
The maximum total power dissipation is (5.5V – 3.2V) •
2A = 4.6W. However, the LT3083 supplies only:
IN
5.5V − 3.2V
R
P
2A −
= 1.36A
+
–
3.6Ω
Therefore, the LT3083’s power dissipation is only:
= (5.5V – 3.2V) • 1.36A = 3.13W
OUT
V
OUT
3083 F08
C2
SET
P
DISS
R
SET
R dissipates 1.47W of power. As with the first technique,
P
choose appropriate wattage resistors to handle and dis-
sipate the power properly. With this configuration, the
LT3083 supplies only 1.36A. Therefore, load current can
increase by 1.64A to a total output current of 3.64A while
keeping the LT3083 in its normal operating range.
Figure 8. Reducing Power Dissipation Using a Parallel Resistor
3083f
18
LT3083
TYPICAL APPLICATIONS
Adding Shutdown
Current Source
IN
LT3083
IN
LT3083
V
IN
V
IN
10V
V
CONTROL
V
CONTROL
+
–
+
–
10μF
0.33ꢁ
OUT
OUT
I
OUT
V
OUT
0A TO 3A
SET
R1
SET
10μF
Q1
VN2222LL
Q2*
VN2222LL
ON OFF
20k
3083 TA03
SHUTDOWN
3083 TA02
*Q2 INSURES ZERO OUTPUT
IN THE ABSENCE OF ANY
OUTPUT LOAD.
Low Dropout Voltage LED Driver
V
IN
V
C1
CONTROL
1A
D1
LT3083
IN
+
–
OUT
SET
R1
20k
R2
1ꢁ
3083 TA04
DAC-Controlled Regulator
IN
LT3083
V
IN
V
CONTROL
+
–
OUT
150k
450k
V
OUT
SET
10μF
–
150k
SPI
+
3083 TA05
LTC2641
LT1991
GAIN = 4
3083f
19
LT3083
TYPICAL APPLICATIONS
Coincident Tracking
IN
LT3083
V
CONTROL
IN
LT3083
+
–
V
CONTROL
OUT
V
OUT3
5V
IN
LT3083
V
IN
+
–
SET
34k
10μF
7V TO 20V
3083 TA06
V
CONTROL
OUT
V
OUT2
3.3V
+
–
SET
R2
16.2k
C3
10μF
C1
10μF
OUT
V
OUT1
2.5V
SET
R1
49.9k
C2
10μF
Adding Soft-Start
IN
LT3083
V
IN
4.8V to 20V
V
CONTROL
+
–
D1
1N4148
V
3.3V
3A
C1
10μF
OUT
OUT
SET
R1
C
OUT
C2
0.01μF
10μF
66.5k
3083 TA07
Lab Supply
IN
LT3083
IN
LT3083
V
IN
12V TO 18V
V
V
CONTROL
CONTROL
+
–
+
–
+
15μF
0.33ꢁ
OUT
OUT
V
OUT
0V TO 10V
SET
SET
R4
+
+
15μF
10μF
100μF
20k
0A TO 3A
200k
3083 TA08
3083f
20
LT3083
TYPICAL APPLICATIONS
High Voltage Regulator
6.1V
10k
V
IN
50V
1N4148
IN
LT3083
BUZ11
V
CONTROL
+
+
–
10μF
V
OUT
OUT
3A
V
OUT
V
OUT
= 20V
= 50μA • R
SET
+
10μF
SET
R
SET
15μF
402k
3083 TA09
Ramp Generator
Reference Buffer
IN
LT3083
IN
LT3083
V
IN
V
IN
5V
V
CONTROL
V
CONTROL
+
–
+
–
10μF
OUT
OUT
V
V
*
OUT
OUT
INPUT
OUTPUT
C2
SET
SET
10μF
3083 TA11
LT1019
10μF
C1
1μF
VN2222LL
VN2222LL
10nF
GND
*MIN LOAD 0.5mA
3083 TA10
Boosting Fixed Output Regulators
LT3083
IN
V
CONTROL
+
–
OUT
10mꢁ
SET
20mꢁ
42ꢁ*
3.3V
4.5A
OUT
LT1963-3.3
5V
10μF
47μF
3083 TA12
33k
*4mV DROP ENSURES LT3083 IS
OFF WITH NO LOAD
MULTIPLE LT3083’S CAN BE USED
3083f
21
LT3083
TYPICAL APPLICATIONS
Low Voltage, High Current Adjustable High Efficiency Regulator*
0.47μH
10k
PV
SV
SW
IN
+
2×
†
2.7V TO 5.5V
I
TH
LT3083
100μF
IN
IN
+
12.1k
294k
2×
100μF
470pF
LTC3610
R
T
2.2MEG 100k
1000pF
2N3906
V
CONTROL
PGOOD
RUN/SS
+
–
V
FB
OUT
10mꢁ
78.7k
124k
SYNC/MODE
SGND PGND
SET
IN
LT3083
V
CONTROL
+
–
*DIFFERENTIAL VOLTAGE ON LT3083
IS 0.6V SET BY THE V OF THE 2N3906 PNP.
BE
OUT
10mꢁ
†
0V TO 4V
12A
†
MAXIMUM OUTPUT VOLTAGE IS 1.5V
BELOW INPUT VOLTAGE
SET
IN
LT3083
V
CONTROL
+
–
OUT
10mꢁ
SET
IN
LT3083
V
CONTROL
+
–
OUT
10mꢁ
3083 TA13
SET
+
100μF
100k
3083f
22
LT3083
TYPICAL APPLICATIONS
Adjustable High Efficiency Regulator*
†
V
IN
BOOST
4.5V TO 25V
0.47μF
4.7μH
BD
10μF
1μF
LT3680
100k
IN
LT3083
RUN/SS
SW
FB
0.1μF
68μF
V
CONTROL
B340A
V
TP0610L
200k
CONTROL
+
–
15.4k
RT
63.4k
600kHz
GND
†
OUT
0V TO 10V
3A
10k
680pF
3083 TA14
SET
4.7μF
200k
*DIFFERENTIAL VOLTAGE ON LT3083
10k
≈ 1.4V SET BY THE TPO610L P-CHANNEL THRESHOLD.
†
MAXIMUM OUTPUT VOLTAGE IS 2V
BELOW INPUT VOLTAGE
2 Terminal Current Source
C
*
COMP
IN
LT3083
V
CONTROL
+
–
R1
SET
20k
3083 TA15
1V
R1
I
=
*C
OUT
COMP
R1 ≤ 10ꢁ 10μF
R1 ≥ 10ꢁ 2.2μF
3083f
23
LT3083
PACKAGE DESCRIPTION
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev H)
Exposed Pad Variation BB
4.90 – 5.10*
(.193 – .201)
3.58
(.141)
3.58
(.141)
16 1514 13 12 1110
9
6.60 p0.10
2.94
(.116)
4.50 p0.10
6.40
(.252)
BSC
SEE NOTE 4
2.94
(.116)
0.45 p0.05
1.05 p0.10
0.65 BSC
5
7
8
1
2
3
4
6
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.0433)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0o – 8o
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE16 (BB) TSSOP REV G 0910
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3083f
24
LT3083
PACKAGE DESCRIPTION
DF Package
12-Lead Plastic DFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1733 Rev Ø)
2.50 REF
0.70 p0.05
3.38 p0.05
4.50 p 0.05
2.65 p 0.05
3.10 p 0.05
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 p 0.10
(4 SIDES)
2.50 REF
7
12
0.40 p 0.10
3.38 p0.10
2.65 p 0.10
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 s 45o
PIN 1
TOP MARK
(NOTE 6)
CHAMFER
(DF12) DFN 0806 REV Ø
6
R = 0.115
TYP
1
0.25 p 0.05
0.50 BSC
0.200 REF
0.75 p 0.05
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3083f
25
LT3083
PACKAGE DESCRIPTION
Q Package
5-Lead Plastic DD-PAK
(Reference LTC DWG # 05-08-1461 Rev E)
.060
(1.524)
TYP
.390 – .415
(9.906 – 10.541)
.060
(1.524)
.165 – .180
(4.191 – 4.572)
.256
(6.502)
.045 – .055
(1.143 – 1.397)
15o TYP
+.008
.004
–.004
.060
(1.524)
.059
(1.499)
TYP
.183
(4.648)
.330 – .370
(8.382 – 9.398)
+0.203
–0.102
0.102
ꢀ
ꢁ
.095 – .115
(2.413 – 2.921)
.075
(1.905)
.067
(1.702)
BSC
.050 p .012
(1.270 p 0.305)
.300
(7.620)
.013 – .023
(0.330 – 0.584)
+.012
.143
–.020
.028 – .038
(0.711 – 0.965)
TYP
+0.305
BOTTOM VIEW OF DD PAK
HATCHED AREA IS SOLDER PLATED
COPPER HEAT SINK
3.632
ꢀ
ꢁ
–0.508
.420
.276
.080
.420
.350
.325
.205
.585
.585
.320
.090
.042
.090
.042
.067
.067
RECOMMENDED SOLDER PAD LAYOUT
NOTE:
1. DIMENSIONS IN INCH/(MILLIMETER)
2. DRAWING NOT TO SCALE
RECOMMENDED SOLDER PAD LAYOUT
FOR THICKER SOLDER PASTE APPLICATIONS
Q(DD5) 0610 REV E
3083f
26
LT3083
PACKAGE DESCRIPTION
T Package
5-Lead Plastic TO-220 (Standard)
(Reference LTC DWG # 05-08-1421)
.165 – .180
(4.191 – 4.572)
.147 – .155
(3.734 – 3.937)
DIA
.390 – .415
(9.906 – 10.541)
.045 – .055
(1.143 – 1.397)
.230 – .270
(5.842 – 6.858)
.570 – .620
(14.478 – 15.748)
.620
(15.75)
TYP
.460 – .500
(11.684 – 12.700)
.330 – .370
(8.382 – 9.398)
.700 – .728
(17.78 – 18.491)
.095 – .115
(2.413 – 2.921)
SEATING PLANE
.152 – .202
(3.861 – 5.131)
.155 – .195*
(3.937 – 4.953)
.260 – .320
(6.60 – 8.13)
.013 – .023
(0.330 – 0.584)
.067
BSC
.135 – .165
(3.429 – 4.191)
.028 – .038
(0.711 – 0.965)
(1.70)
* MEASURED AT THE SEATING PLANE
T5 (TO-220) 0801
3083f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3083
TYPICAL APPLICATION
Paralleling Regulators
IN
LT3083
V
CONTROL
+
–
10mꢁ
OUT
SET
IN
LT3083
V
IN
4.8V TO 28V
V
CONTROL
+
–
10mꢁ
V
3.3V
6A
OUT
OUT
10μF
SET
22μF
33.2k
3083 TA16
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LT1185
3A Negative Low Dropout Regulator V : –4.5V to –35V, 0.8V Dropout Voltage, DD-PAK and TO-220 Packages
IN
LT1764/
LT1764A
3A, Fast Transient Response,
Low Noise LDO
1.5A Low Noise, Fast Transient
Response LDO
1.1A, Low Noise, Low Dropout
Linear Regulator
1A, Low Voltage, VLDO Linear
Regulator
340mV Dropout Voltage, Low Noise: 40μV
, V = 2.7V to 20V, TO-220 and DD Packages.
RMS IN
“A” Version Stable Also with Ceramic Capacitors
340mV Dropout Voltage, Low Noise: 40μV , V = 2.5V to 20V, “A” Version Stable with
LT1963/A
LT1965
LT3022
RMS IN
Ceramic Capacitors, TO-220, DD, SOT-223 and SO-8 Packages
290mV Dropout Voltage, Low Noise: 40μV , V : 1.8V to 20V, V : 1.2V to 19.5V,
RMS IN
OUT
Stable with Ceramic Capacitors, TO-220, DD-PAK, MSOP and 3mm × 3mm DFN Packages
V : 0.9V to 10V, Dropout Voltage: 145mV Typical, Adjustable Output (V = V
= 200mV),
OUT(MIN)
IN
REF
Stable with Low ESR, Ceramic Output Capacitors, 16-Pin DFN (5mm × 3mm) and
16-Lead MSOP Packages
LT3070
LT3071
5A, Low Noise, Programmable V , Dropout Voltage: 85mV, Digitally Programmable V : 0.8V to 1.8V, Digital Output Margining:
OUT OUT
85mV Dropout Linear Regulator with 1%, 3% or 5%, Low Output Noise: 25ꢀV
(10Hz to 100kHz), Parallelable: Use Two for a
RMS
Digital Margining
10A Output, Stable with Low ESR Ceramic Output Capacitors (15ꢀF Minimum),
28-Lead 4mm × 5mm QFN Package
5A, Low Noise, Programmable Vout, Dropout Voltage: 85mV, Digitally Programmable V : 0.8V to 1.8V, Analog Margining: 10%,
OUT
85mV Dropout Linear Regulator with Low Output Noise: 25ꢀV
(10Hz to 100kHz), Parallelable: Use Two for a 10A Output, I
MON
RMS
Analog Margining
Output Current Monitor, Stable with Low ESR Ceramic Output Capacitors (15ꢀF Minimum),
28-Lead 4mm × 5mm QFN Package
LT3080/
LT3080-1
1.1A, Parallelable, Low Noise, Low
Dropout Linear Regulator
300mV Dropout Voltage (2-Supply Operation), Low Noise: 40μV
, V : 1.2V to 36V, V : 0V
RMS IN OUT
to 35.7V, Current-Based Reference with 1-Resistor V
Set; Directly Parallelable (No Op Amp
OUT
Required), Stable with Ceramic Capacitors, TO-220, DD-PAK, SOT-223, MS8E and 3mm × 3mm
DFN-8 Packages; “-1” Version Has Integrated Internal Ballast Resistor
LT3082
LT3085
LTC3026
200mA, Parallelable, Single Resistor, Outputs May Be Paralleled for Higher Output, Current or Heat Spreading, Wide Input Voltage
Low Dropout Linear Regulator
Range: 1.2V to 40V, Low Value Input/Output Capacitors Required: 0.22ꢀF, Single Resistor Sets
Output Voltage, 8-Lead SOT-23, 3-Lead SOT-223 and 8-Lead 3mm × 3mm DFN Packages
500mA, Parallelable, Low Noise,
Low Dropout Linear Regulator
275mV Dropout Voltage (2-Supply Operation), Low Noise: 40μV
, V : 1.2V to 36V, V : 0V
RMS IN OUT
to 35.7V, Current-Based Reference with 1-Resistor V
Set; Directly Parallelable (No Op Amp
OUT
Required), Stable with Ceramic Capacitors, MS8E and 2mm × 3mm DFN-6 Packages
V : 1.14V to 3.5V (Boost Enabled), 1.14V to 5.5V (with External 5V), V = 0.1V, I = 950μA,
1.5A, Low Input Voltage VLDO
Linear Regulator
IN
DO
Q
Stable with 10μF Ceramic Capacitors, 10-Lead MSOP-E and DFN-10 Packages
3083f
LT 0111 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
© LINEAR TECHNOLOGY CORPORATION 2011
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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