LT3023EMSE [Linear]
Dual 100mA, Low Dropout, Low Noise, Micropower Regulator; 双路100mA时低压差，低噪声，微功率稳压器
| 型号： | LT3023EMSE |
| 厂家： | 
Linear |
| 描述： | Dual 100mA, Low Dropout, Low Noise, Micropower Regulator |
| 文件： | 总16页 (文件大小：581K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3023
Dual 100mA,
Low Dropout, Low Noise,
Micropower Regulator
U
FEATURES
DESCRIPTIO
The LT®3023 is a dual, micropower, low noise, low drop-
out regulator. With an external 0.01µF bypass capacitor,
output noise drops to 20µVRMS over a 10Hz to 100kHz
bandwidth. Designedforuseinbattery-poweredsystems,
the low 20µA quiescent current per channel makes it an
ideal choice. In shutdown, quiescent current drops to less
than 0.1µA. Shutdown control is independent for each
channel,allowingforflexibilityinpowermanagement.The
device is capable of operating over an input voltage from
1.8Vto20V, andcansupply100mAofoutputcurrentfrom
each channel with a dropout voltage of 300mV. Quiescent
current is well controlled in dropout.
■
Low Noise: 20µVRMS (10Hz to 100kHz)
■
Low Quiescent Current: 20µA/Channel
■
Wide Input Voltage Range: 1.8V to 20V
■
Output Current: 100mA/Channel
Very Low Shutdown Current: <0.1µA
Low Dropout Voltage: 300mV at 100mA
Adjustable Output from 1.22V to 20V
Stable with 1µF Output Capacitor
Stable with Aluminum, Tantalum or
Ceramic Capacitors
■
■
■
■
■
■
■
■
■
■
Reverse Battery Protected
No Reverse Current
No Protection Diodes Needed
Overcurrent and Overtemperature Protected
Thermally Enhanced 10-Lead MSOP and DFN
Packages
The LT3023 regulator is stable with output capacitors as
low as 1µF. Small ceramic capacitors can be used without
the series resistance required by other regulators.
Internal protection circuitry includes reverse battery pro-
tection, current limiting, thermal limiting and reverse
current protection. The device is available as an adjustable
device with a 1.22V reference voltage. The LT3023 regu-
lator is available in the thermally enhanced 10-lead MSOP
and DFN packages.
U
APPLICATIO S
■
Cellular Phones
■
Pagers
■
Battery-Powered Systems
■
Frequency Synthesizers
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
Wireless Modems
U
TYPICAL APPLICATIO
3.3V/2.5V Low Noise Regulators
10Hz to 100kHz Output Noise
3.3V AT100mA
IN
OUT1
20µV
NOISE
V
IN
RMS
3.7V TO
20V
1µF
SHDN1
SHDN2
0.01µF
10µF
422k
249k
BYP1
ADJ1
LT3023
V
OUT
100µV/DIV
20µV
RMS
2.5V AT100mA
OUT2
20µV
NOISE
RMS
0.01µF
10µF
261k
249k
BYP2
ADJ2
3023 TA01b
GND
3023 TA01
3023f
1
LT3023
ABSOLUTE AXI U RATI GS
W W
U W
(Note 1)
IN Pin Voltage........................................................ ±20V
OUT1, OUT2 Pin Voltage ....................................... ±20V
Input to Output Differential Voltage ....................... ±20V
ADJ1, ADJ2 Pin Voltage ......................................... ±7V
BYP1, BYP2 Pin Voltage ....................................... ±0.6V
SHDN1, SHDN2 Pin Voltage ................................. ±20V
Output Short-Circut Duration.......................... Indefinite
Operating Junction Temperature Range
(Note 2) ............................................ –40°C to 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
U W
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
TOP VIEW
11
NUMBER
TOP VIEW
BYP2
ADJ2
GND
1
2
3
4
5
10 OUT2
BYP2
ADJ2
GND
ADJ1
BYP1
1
2
3
4
5
10 OUT2
LT3023EDD
LT3023EMSE
9
8
7
6
SHDN2
IN
9
8
7
6
SHDN2
IN
SHDN1
OUT1
11
ADJ1
BYP1
SHDN1
OUT1
MSE PACKAGE
10-LEAD PLASTIC MSOP
EXPOSED PAD (PIN 11) IS GND
MUST BE SOLDERED TO PCB
JMAX = 150°C, θJA = 40°C/ W, θJC = 10°C/ W
DD PART
MARKING
MSE PART
MARKING
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
EXPOSED PAD (PIN 11) IS GND
MUST BE SOLDERED TO PCB
T
LAJA
LTAHZ
TJMAX = 125°C, θJA = 40°C/ W, θJC = 10°C/ W
Consult factory for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
= 100mA
MIN
TYP
MAX
UNITS
Minimum Input Voltage
(Notes 3, 11)
I
●
1.8
2.3
V
LOAD
ADJ1, ADJ2 Pin Voltage
(Note 3, 4)
V
= 2V, I
= 1mA
LOAD
1.205
1.190
1.220
1.220
1.235
1.250
V
V
IN
2.3V < V < 20V, 1mA < I
< 100mA
LOAD
●
●
IN
Line Regulation (Note 3)
Load Regulation (Note 3)
∆V = 2V to 20V, I
= 1mA
1
1
10
mV
IN
LOAD
V
V
= 2.3V, ∆I
= 2.3V, ∆I
= 1mA to 100mA
= 1mA to 100mA
12
25
mV
mV
IN
IN
LOAD
LOAD
●
●
●
●
●
Dropout Voltage
I
I
= 1mA
= 1mA
0.10
0.17
0.24
0.30
0.15
0.19
V
V
LOAD
LOAD
V
= V
IN
OUT(NOMINAL)
(Notes 5, 6, 11)
I
I
= 10mA
= 10mA
0.22
0.29
V
V
LOAD
LOAD
I
I
= 50mA
= 50mA
0.28
0.38
V
V
LOAD
LOAD
I
I
= 100mA
= 100mA
0.35
0.45
V
V
LOAD
LOAD
3023f
2
LT3023
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
GND Pin Current (Per Channel)
I
I
I
I
I
= 0mA
●
●
●
●
●
20
55
230
1
2.2
45
100
400
2
µA
µA
LOAD
LOAD
LOAD
LOAD
LOAD
V
= V
= 1mA
IN
OUT(NOMINAL)
(Notes 5, 7)
= 10mA
= 50mA
= 100mA
µA
mA
mA
4
Output Voltage Noise
C
= 10µF, C
= 0.01µF, I
= 100mA, BW = 10Hz to 100kHz
20
30
µV
RMS
OUT
BYP
LOAD
ADJ1/ADJ2 Pin Bias Current
Shutdown Threshold
(Notes 3, 8)
100
1.4
nA
V
V
= Off to On
= On to Off
●
●
0.8
0.65
V
V
OUT
OUT
0.25
SHDN1/SHDN2 Pin Current
(Note 9)
V
V
= 0V
= 20V
●
●
0
1
0.5
3
µA
µA
SHDN
SHDN
Quiescent Current in Shutdown
Ripple Rejection (Note 3)
V
V
= 6V, V
= 0V (Both SHDN Pins)
SHDN
0.01
65
0.1
µA
IN
= 2.72V (Avg), V
= 50mA
= 0.5V , f = 120Hz,
P-P RIPPLE
55
dB
IN
RIPPLE
I
LOAD
Current Limit
V
V
= 7V, V
= 0V
OUT
200
mA
mA
IN
IN
OUT
= 2.3V, ∆V
= –5%
●
●
110
Input Reverse Leakage Current
V
= –20V, V
= 0V
1
mA
IN
OUT
Reverse Output Current (Notes 3,10) V
= 1.22V, V < 1.22V
5
10
µA
OUT
IN
Note 6: Dropout voltage is the minimum input to output voltage differential
needed to maintain regulation at a specified output current. In dropout, the
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
output voltage will be equal to: V – V
.
IN
DROPOUT
Note 2: The LT3023 regulator is tested and specified under pulse load
conditions such that T ≈ T . The LT3023 is 100% production tested at
Note 7: GND pin current is tested with V = 2.44V and a current source
IN
J
A
load. This means the device is tested while operating in its dropout region
or at the minimum input voltage specification. This is the worst-case GND
pin current. The GND pin current will decrease slightly at higher input
voltages.
T = 25°C. Performance at –40°C and 125°C is assured by design,
characterization and correlation with statistical process controls.
Note 3: The LT3023 is tested and specified for these conditions with the
ADJ1/ADJ2 pin connected to the corresponding OUT1/OUT2 pin.
A
Note 8: ADJ1 and ADJ2 pin bias current flows into the pin.
Note 9: SHDN1 and SHDN2 pin current flows into the pin.
Note 10: Reverse output current is tested with the IN pin grounded and the
OUT pin forced to the rated output voltage. This current flows into the OUT
pin and out the GND pin.
Note 11: For the LT3023 dropout voltage will be limited by the minimum
input voltage specification under some output voltage/load conditions. See
the curve of Minimum Input Voltage in the Typical Performance
Characteristics.
Note 4: Operating conditions are limited by maximum junction
temperature. The regulated output voltage specification will not apply for
all possible combinations of input voltage and output current. When
operating at maximum input voltage, the output current range must be
limited. When operating at maximum output current, the input voltage
range must be limited.
Note 5: To satisfy requirements for minimum input voltage, the LT3023 is
tested and specified for these conditions with an external resistor divider
(two 250k resistors) for an output voltage of 2.44V. The external resistor
divider will add a 5µA DC load on the output.
3023f
3
LT3023
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Typical Dropout Voltage
Dropout Voltage
Guaranteed Dropout Voltage
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
= TEST POINTS
T
≤ 125°C
≤ 25°C
J
T = 125°C
J
I
= 100mA
L
T
J
I
= 50mA
= 10mA
L
T = 25°C
J
I
L
I
= 1mA
L
0
–50
0
0
0
25
50
75 100 125
–25
40
40
50 60 70 80 90 100
0
10 20 30
50 60 70 80 90 100
0
10 20 30
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
3023 G03
3023 G01
3023 G02
Quiescent Current
ADJ1 or ADJ2 Pin Voltage
Quiescent Current
1.240
30
25
20
15
10
5
40
35
30
25
20
15
10
5
T = 25°C
V
= 6V
I
= 1mA
J
R
IN
L
L
= 250k
R
= 250k
1.235
1.230
1.225
1.220
1.215
1.210
1.205
1.200
L
L
I
= 5µA
I
= 5µA
L
V
= V
IN
SHDN
V
= V
IN
SHDN
V
SHDN
= 0V
V
= 0V
50
SHDN
25
0
0
–50
–25
0
25
50
75
125
0
2
4
6
8
10 12 14 16 18 20
INPUT VOLTAGE (V)
–50
100
–25
0
75
125
100
TEMPERATURE (°C)
TEMPERATURE (°C)
3023 G05
3023 G06
3023 G03
SHDN1 or SHDN2 Pin Threshold
(On-to-Off)
GND Pin Current vs ILOAD
GND Pin Current
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
I
L
= 1mA
V
IN
= V
+ 1V
T = 25°C
OUT(NOMINAL)
J
*FOR V
= 1.22V
OUT
R
L
= 12.2Ω
L
I
= 100mA*
R
L
= 24.4Ω
L
I
= 50mA*
R
L
= 1.22k
L
R
L
= 122Ω
L
I
= 1mA*
I
= 10mA*
40
50 60 70 80 90 100
0
10 20 30
4
–50
0
25
50
75
125
0
1
2
3
5
6
7
8
9
10
–25
100
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
INPUT VOLTAGE (V)
3023 G08
3023 G07
3023 G09
3023f
4
LT3023
U W
TYPICAL PERFOR A CE CHARACTERISTICS
SHDN1 or SHDN2 Pin Input
Current
SHDN1 or SHDN2 Pin Input
Current
SHDN1 or SHDN2 Pin Threshold
(Off-to-On)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 20V
SHDN
I
= 100mA
L
I
= 1mA
L
–50
0
25
50
75 100 125
–50
–25
0
25
50
75 100 125
–25
4
0
1
2
3
5
6
7
8
9
10
TEMPERATURE (°C)
TEMPERATURE (°C)
SHDN PIN VOLTAGE (V)
3023 G10
3023 G12
3023 G11
Current Limit
ADJ1 or ADJ2 Pin Bias Current
Current Limit
100
90
80
70
60
50
40
30
20
10
0
350
300
250
200
150
100
50
350
300
250
200
150
100
50
V
= 0V
V
V
= 7V
OUT
OUT
J
IN
T
= 25°C
= 0V
0
0
–50
0
25
TEMPERATURE (°C)
50
75 100 125
0
1
2
3
4
5
6
7
–50
–25
0
25
50
75 100 125
–25
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3023 G13
3023 G14
3023 G15
Reverse Output Current
Reverse Output Current
Input Ripple Rejection
18
15
12
9
100
90
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
V
V
= 0V
= V
T
V
V
= 25°C
IN
OUT
A
= 1.22V
ADJ
= 0V
IN
OUT
= V
ADJ
CURRENT FLOWS
INTO OUTPUT PIN
C
= 10µF
OUT
6
3
I
V
C
= 100mA
L
C
= 1µF
= 2.3V + 50mV
RIPPLE
RMS
OUT
IN
= 0
BYP
0
50
TEMPERATURE (°C)
100 125
4
–50 –25
0
25
75
0
1
2
3
5
6
7
8
9
10
0.01
0.1
1
10
100
1000
FREQUENCY (kHz)
OUTPUT VOLTAGE (V)
LTXXXX GXX
3023 G17
3023 G16
3023f
5
LT3023
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Input Ripple Rejection
Input Ripple Rejection
Channel-to-Channel Isolation
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
C
= 0.01µF
BYP
V
OUT1
20mV/DIV
C
= 1000pF
BYP
C
= 100pF
BYP
V
OUT2
20mV/DIV
V
= V
+
IN
OUT (NOMINAL)
1V + 0.5V RIPPLE
P-P
3023 G21a
I
V
C
= 100mA
50µs/DIV
L
AT f = 120Hz
= 2.3V + 50mV
RIPPLE
RMS
IN
I
= 50mA
–25
C
, C = 10µF
OUT1 OUT2
L
= 10µF
OUT
C
, C
= 0.01µF
BYP1 BYP2
∆I = 10mA to 100mA
0
25
50
75
125
–50
100
L1
0.01
0.1
1
10
100
1000
∆I = 10mA to 100mA
L2
= 6V, V
TEMPERATURE (°C)
FREQUENCY (kHz)
V
IN
= V
= 5V
OUT1
OUT2
3023 G20
3023 G19
Minimum Input Voltage
Load Regulation
Channel-to-Channel Isolation
100
90
80
70
60
50
40
30
20
10
0
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
2.5
2.0
1.5
1.0
0.5
0
I
= 100mA PER CHANNEL
LOAD
I
= 100mA
L
I
= 50mA
L
∆
= 1mA TO 100mA
IL
0.01
0.1
1
10
100
1000
–50 –25
0
25
50
75 100 125
–50
0
25
50
75 100 125
–25
FREQUENCY (kHz)
TEMPERATURE (°C)
TEMPERATURE (°C)
3023 G21b
3023 G23
3023 G22
RMS Output Noise vs
Bypass Capacitor
Output Noise Spectral Density
Output Noise Spectral Density
10
1
160
140
120
100
80
10
1
C
= 10µF
C
C
L
= 10µF
OUT
= 100mA
L
OUT
BYP
C
L
= 10µF
OUT
= 100mA
I
= 0
I
f = 10Hz TO 100kHz
I
= 100mA
V
SET FOR 5V
OUT
C
= 1000pF
BYP
V
OUT
SET FOR 5V
V
SET FOR 5V
OUT
C
BYP
= 100pF
V
=V
ADJ
OUT
V
OUT
=V
ADJ
60
0.1
0.1
0.01
C
BYP
= 0.01pF
40
V
=V
ADJ
OUT
20
0
0.01
10
100
1k
10k
0.01
0.1
1
10
100
0.01
0.1
1
10
100
C
(pF)
BYP
FREQUENCY (kHz)
FREQUENCY (kHz)
3023 G26
3023 G25
3023 G24
3023f
6
LT3023
U W
TYPICAL PERFOR A CE CHARACTERISTICS
10Hz to 100kHz Output Noise
BYP = 100pF
RMS Output Noise vs
Load Current (10Hz to 100kHz)
10Hz to 100kHz Output Noise
CBYP = 0
C
160
140
120
100
80
C
= 10µF
OUT
C
= 0µF
BYP
BYP
C
= 0.01µF
V
SET FOR 5V
OUT
VOUT
100µV/DIV
VOUT
100µV/DIV
V
=V
ADJ
OUT
60
40
3023 G29
3023 G28
V
SET FOR 5V
1ms/DIV
OUT
1ms/DIV
20
COUT = 10µF
C
OUT = 10µF
IL = 100mA
OUT SET FOR 5V OUT
V
=V
ADJ
IL = 100mA
OUT
10
0
0.01
VOUT SET FOR 5V OUT
V
0.1
1
100
LOAD CURRENT (mA)
3023 G27
10Hz to 100kHz Output Noise
BYP = 1000pF
10Hz to 100kHz Output Noise
CBYP = 0.01µF
C
VOUT
100µV/DIV
VOUT
100µV/DIV
3023 G31
3023 G30
1ms/DIV
1ms/DIV
COUT = 10µF
COUT = 10µF
L = 100mA
I
IL = 100mA
VOUT SET FOR 5V OUT
VOUT SET FOR 5V OUT
Transient Response
CBYP = 0.01µF
Transient Response
CBYP = 0
0.2
0.1
0.04
0.02
0
0
–0.1
–0.2
–0.02
–0.04
V
C
C
V
= 6V
IN
IN
V
C
C
V
= 6V
IN
IN
= 10µF
= 10µF
= 10µF
OUT
OUT
= 10µF
OUT
OUT
SET FOR 5V OUT
SET FOR 5V OUT
100
50
0
100
50
0
800
TIME (µs)
80
0
400
1200
1600
2000
0
20 40 60
100 120 140 160 180 200
TIME (µs)
3023 G32
3023 G33
3023f
7
LT3023
U
U
U
PI FU CTIO S
GND (Pin 3): Ground.
SHDN1/SHDN2(Pins7/9):Shutdown.TheSHDN1/SHDN2
pins are used to put the corresponding channel of the
LT3023 regulator into a low power shutdown state. The
output will be off when the pin is pulled low. The
SHDN1/SHDN2 pins can be driven either by 5V logic or
open-collector logic with pull-up resistors. The pull-up
resistors are required to supply the pull-up current of the
open-collector gates, normally several microamperes,
and the SHDN1/SHDN2 pin current, typically 1µA. If
unused, the pin must be connected to VIN. The device will
not function if the SHDN1/SHDN2 pins are not connected.
ADJ1/ADJ2 (Pins 4/2): Adjust Pin. These are the inputs to
the error amplifiers. These pins are internally clamped to
±7V. Theyhaveabiascurrentof30nAwhichflowsintothe
pin(seecurveofADJ1/ADJ2PinBiasCurrentvsTempera-
ture in the Typical Performance Characteristics section).
The ADJ1 and ADJ2 pin voltage is 1.22V referenced to
ground and the output voltage range is 1.22V to 20V.
BYP1/BYP2 (Pins 5/1): Bypass. The BYP1/BYP2 pins are
used to bypass the reference of the LT3023 regulator to
achieve low noise performance from the regulator. The
BYP1/BYP2 pins are clamped internally to ±0.6V (one
VBE)fromground. Asmallcapacitorfromthecorrespond-
ing output to this pin will bypass the reference to lower the
output voltage noise. A maximum value of 0.01µF can be
usedforreducingoutputvoltagenoisetoatypical20µVRMS
over a 10Hz to 100kHz bandwidth. If not used, this pin
must be left unconnected.
IN (Pin 8): Input. Power is supplied to the device through
the IN pin. A bypass capacitor is required on this pin if the
device is more than six inches away from the main input
filter capacitor. In general, the output impedance of a
battery rises with frequency, so it is advisable to include a
bypass capacitor in battery-powered circuits. A bypass
capacitor in the range of 1µF to 10µF is sufficient. The
LT3023 regulator is designed to withstand reverse volt-
ages on the IN pin with respect to ground and the OUT pin.
Inthecaseofareverseinput, whichcanhappenifabattery
is plugged in backwards, the device will act as if there is a
diode in series with its input. There will be no reverse
current flow into the regulator and no reverse voltage will
appear at the load. The device will protect both itself and
the load.
OUT1/OUT2 (Pins 6/10): Output. The outputs supply
power to the loads. A minimum output capacitor of 1µF is
required to prevent oscillations. Larger output capacitors
will be required for applications with large transient loads
to limit peak voltage transients. See the Applications
Information section for more information on output ca-
pacitance and reverse output characteristics.
Exposed Pad (Pin 11): Ground. This pin must be soldered
to the PCB and electrically connected to ground.
3023f
8
LT3023
W U U
APPLICATIO S I FOR ATIO
U
The LT3023 is a dual 100mA low dropout regulator with
micropower quiescent current and shutdown. The device
is capable of supplying 100mA per channel at a dropout
voltage of 300mV. Output voltage noise can be lowered to
20µVRMS over a 10Hz to 100kHz bandwidth with the
addition of a 0.01µF reference bypass capacitor. Addition-
ally, the reference bypass capacitor will improve transient
response of the regulator, lowering the settling time for
transient load conditions. The low operating quiescent
current (20µA per channel) drops to less than 1µA in
shutdown. In addition to the low quiescent current, the
LT3023regulatorincorporatesseveralprotectionfeatures
which make it ideal for use in battery-powered systems.
The device is protected against both reverse input and
reverse output voltages. In battery backup applications
where the output can be held up by a backup battery when
the input is pulled to ground, the LT3023 acts like it has a
diodeinserieswithitsoutputandpreventsreversecurrent
flow. Additionally, in dual supply applications where the
regulator load isreturned to a negative supply, the output
can be pulled below ground by as much as 20V and still
allow the device to start and operate.
IN OUT1/OUT2
LT3023
V
OUT
R2
R1
V
= 1.22V 1+
= 1.22V
+ I
(
R2
+
)(
)
OUT
ADJ
V
IN
R2
R1
V
ADJ
ADJ1/ADJ2
GND
I
= 30nA AT 25°C
ADJ
OUTPUT RANGE = 1.22V TO 20V
3023 F01
Figure 1. Adjustable Operation
The device is tested and specified with the ADJ1/ADJ2 pin
tied to the corresponding OUT1/OUT2 pin for an output
voltageof1.22V.Specificationsforoutputvoltagesgreater
than 1.22V will be proportional to the ratio of the desired
output voltage to 1.22V: VOUT/1.22V. For example, load
regulation for an output current change of 1mA to 100mA
is –1mV typical at VOUT = 1.22V. At VOUT = 12V, load
regulation is:
(12V/1.22V)(–1mV) = –9.8mV
Bypass Capacitance and Low Noise Performance
The LT3023 regulator may be used with the addition of a
bypass capacitor from VOUT to the corresponding BYP1/
BYP2pintoloweroutputvoltagenoise. Agoodqualitylow
leakage capacitor is recommended. This capacitor will
bypass the reference of the regulator, providing a low fre-
quency noise pole. The noise pole provided by this bypass
capacitor will lower the output voltage noise to as low as
20µVRMS with the addition of a 0.01µF bypass capacitor.
Using a bypass capacitor has the added benefit of improv-
ing transient response. With no bypass capacitor and a
10µF output capacitor, a 10mA to 100mA load step will
settletowithin1%ofitsfinalvalueinlessthan100µs.With
the addition of a 0.01µF bypass capacitor, the output will
stay within 1% for a 10mA to 100mA load step (see Tran-
sientReponseinTypicalPerformanceCharacteristicssec-
tion). However, regulator start-up time is inversely pro-
portional to the size of the bypass capacitor, slowing to
15ms with a 0.01µF bypass capacitor and 10µF output
capacitor.
Adjustable Operation
The LT3023 has an output voltage range of 1.22V to 20V.
The output voltage is set by the ratio of two external resis-
tors as shown in Figure 1. The device servos the output to
maintain the corresponding ADJ1/ADJ2 pin voltage at
1.22Vreferencedtoground.ThecurrentinR1isthenequal
to 1.22V/R1 and the current in R2 is the current in R1 plus
the ADJ1/ADJ2 pin bias current. The ADJ1/ADJ2 pin bias
current,30nAat25°C,flowsthroughR2intotheADJ1/ADJ2
pin.Theoutputvoltagecanbecalculatedusingtheformula
inFigure1. ThevalueofR1shouldbenogreaterthan250k
tominimizeerrorsintheoutputvoltagecausedbytheADJ1/
ADJ2 pin bias current. Note that in shutdown the output is
turned off and the divider current will be zero. Curves of
ADJ1/ADJ2PinVoltagevsTemperatureandADJ1/ADJ2Pin
Bias Current vs Temperature appear in the Typical Perfor-
mance Characteristics.
3023f
9
LT3023
W U U
U
APPLICATIO S I FOR ATIO
dielectrics used are Z5U, Y5V, X5R and X7R. The Z5U and
Y5V dielectrics are good for providing high capacitances
in a small package, but exhibit strong voltage and tem-
perature coefficients as shown in Figures 3 and 4. When
used with a 5V regulator, a 10µF Y5V capacitor can exhibit
an effective value as low as 1µF to 2µF over the operating
temperature range. The X5R and X7R dielectrics result in
more stable characteristics and are more suitable for use
as the output capacitor. The X7R type has better stability
across temperature, while the X5R is less expensive and
is available in higher values.
Output Capacitance and Transient Response
TheLT3023regulatorisdesignedtobestablewithawide
rangeofoutputcapacitors. TheESRoftheoutputcapaci-
tor affects stability, most notably with small
capacitors. A minimum output capacitor of 1µF with an
ESR of 3Ω or less is recommended to prevent oscilla-
tions. The LT3023 is a micropower device and output
transient response will be a function of output capaci-
tance. Larger values of output capacitance decrease the
peakdeviationsandprovideimprovedtransientresponse
for larger load current changes. Bypass capacitors, used
to decouple individual components powered by the
LT3023,willincreasetheeffectiveoutputcapacitorvalue.
With larger capacitors used to bypass the reference (for
low noise operation), larger values of output capacitors
are needed. For 100pF of bypass capacitance, 2.2µF of
output capacitor is recommended. With a 330pF bypass
capacitor or larger, a 3.3µF output capacitor is recom-
mended.TheshadedregionofFigure2definestheregion
over which the LT3023 regulator is stable. The minimum
ESR needed is defined by the amount of bypass capaci-
tance used, while the maximum ESR is 3Ω.
20
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
0
X5R
–20
–40
–60
Y5V
–80
–100
0
8
12 14
2
4
6
10
16
DC BIAS VOLTAGE (V)
Extra consideration must be given to the use of ceramic
capacitors. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior across
temperature and applied voltage. The most common
3023 F03
Figure 3. Ceramic Capacitor DC Bias Characteristics
40
20
4.0
3.5
X5R
0
–20
3.0
STABLE REGION
2.5
–40
2.0
Y5V
C
= 0
1.5
1.0
0.5
0
BYP
C
–60
= 100pF
BYP
C
= 330pF
BYP
–80
BOTH CAPACITORS ARE 16V,
C
BYP
> 3300pF
1210 CASE SIZE, 10µF
–100
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
1
3
6
9 10
8
2
4
5
7
OUTPUT CAPACITANCE (µF)
3023 F04
3023 F02
Figure 4. Ceramic Capacitor Temperature Characteristics
Figure 2. Stability
3023f
10
LT3023
W U U
APPLICATIO S I FOR ATIO
U
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or
microphone works. For a ceramic capacitor the stress
can be induced by vibrations in the system or thermal
transients. The resulting voltages produced can cause
appreciable amounts of noise, especially when a ceramic
capacitor is used for noise bypassing. A ceramic capaci-
tor produced Figure 5’s trace in response to light tapping
from a pencil. Similar vibration induced behavior can
masquerade as increased output voltage noise.
dissipation from both channels must be considered dur-
ing thermal analysis.
The LT3023 regulator has internal thermal limiting de-
signed to protect the device during overload conditions.
For continuous normal conditions, the maximum junction
temperature rating of 125°C must not be exceeded. It is
important to give careful consideration to all sources of
thermal resistance from junction to ambient. Additional
heat sources mounted nearby must also be considered.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat gener-
ated by power devices.
COUT = 10µF
C
BYP = 0.01µF
ILOAD = 100mA
The following tables list thermal resistance for several
different board sizes and copper areas. All measurements
were taken in still air on 3/32" FR-4 board with one ounce
copper.
VOUT
500µV/DIV
Table 1. MSE Package, 10-Lead MSOP
COPPER AREA
THERMAL RESISTANCE
100ms/DIV
3023 F05
TOPSIDE*
2500mm2
1000mm2
225mm2
BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2500mm2
2500mm2
2500mm2
2500mm2
2500mm2
2500mm2
2500mm2
2500mm2
40°C/W
45°C/W
50°C/W
62°C/W
Figure 5. Noise Resulting from Tapping on a Ceramic Capacitor
Thermal Considerations
100mm2
The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C). The
power dissipated by the device will be made up of two
components (for each channel):
*Device is mounted on topside.
Table 2. DD Package, 10-Lead DFN
COPPER AREA
THERMAL RESISTANCE
1. Output current multiplied by the input/output voltage
differential: (IOUT)(VIN – VOUT), and
TOPSIDE*
2500mm2
1000mm2
225mm2
BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2500mm2
2500mm2
2500mm2
2500mm2
2500mm2
2500mm2
2500mm2
2500mm2
40°C/W
45°C/W
50°C/W
62°C/W
2. GND pin current multiplied by the input voltage:
(IGND)(VIN).
100mm2
The ground pin current can be found by examining the
GND Pin Current curves in the Typical Performance
Characteristicssection. Powerdissipationwillbeequalto
the sum of the two components listed above. Power
*Device is mounted on topside.
The thermal resistance juncton-to-case (θJC), measured
at the Exposed Pad on the back of the die is 10°C/W.
3023f
11
LT3023
U
W U U
APPLICATIONS INFORMATION
Calculating Junction Temperature
limiting and thermal limiting, the devices are protected
against reverse input voltages, reverse output voltages
and reverse voltages from output to input.
Example: Given an output voltage on the first channel of
3.3V, an output voltage of 2.5V on the second channel, an
input voltage range of 4V to 6V, output current ranges of
0mA to 100mA for the first channel and 0mA to 50mA for
the second channel, with a maximum ambient tempera-
ture of 50°C, what will the maximum junction temperature
be?
Current limit protection and thermal overload protection
areintendedtoprotectthedeviceagainstcurrentoverload
conditions at the output of the device. For normal opera-
tion, the junction temperature should not exceed 125°C.
The input of the device will withstand reverse voltages of
20V.Currentflowintothedevicewillbelimitedtolessthan
1mA (typically less than 100µA) and no negative voltage
will appear at the output. The device will protect both itself
and the load. This provides protection against batteries
which can be plugged in backward.
The power dissipated by each channel of the device will be
equal to:
IOUT(MAX)(VIN(MAX) – VOUT) + IGND(VIN(MAX))
where (for the first channel):
IOUT(MAX) = 100mA
The output of the LT3023 can be pulled below ground
withoutdamagingthedevice.Iftheinputisleftopencircuit
or grounded, the output can be pulled below ground by
20V. The output will act like an open circuit; no current will
flow out of the pin. If the input is powered by a voltage
source, the output will source the short-circuit current of
the device and will protect itself by thermal limiting. In this
case, grounding the SHDN1/SHDN2 pins will turn off the
device and stop the output from sourcing the short-circuit
current.
VIN(MAX) = 6V
IGND at (IOUT = 100mA, VIN = 6V) = 2mA
so:
P1 = 100mA(6V – 3.3V) + 2mA(6V) = 0.28W
and (for the second channel):
IOUT(MAX) = 50mA
VIN(MAX) = 6V
IGND at (IOUT = 50mA, VIN = 6V) = 1mA
The ADJ1 and ADJ2 pins can be pulled above or below
ground by as much as 7V without damaging the device. If
the input is left open circuit or grounded, the ADJ1 and
ADJ2 pins will act like an open circuit when pulled below
ground and like a large resistor (typically 100k) in series
with a diode when pulled above ground.
so:
P2 = 50mA(6V – 2.5V) + 1mA(6V) = 0.18W
The thermal resistance will be in the range of 40°C/W to
60°C/W depending on the copper area. So the junction
temperature rise above ambient will be approximately
equal to:
InsituationswheretheADJ1andADJ2pinsareconnected
to a resistor divider that would pull the pins above their 7V
clamp voltage if the output is pulled high, the ADJ1/ADJ2
pin input current must be limited to less than 5mA. For
example, a resistor divider is used to provide a regulated
1.5V output from the 1.22V reference when the output is
forced to 20V. The top resistor of the resistor divider must
be chosen to limit the current into the ADJ pin to less than
5mA when the ADJ1/ADJ2 pin is at 7V. The 13V difference
between output and ADJ1/ADJ2 pin divided by the 5mA
maximum current into the ADJ1/ADJ2 pin yields a mini-
mum top resistor value of 2.6k.
(0.28W + 018W)(60°C/W) = 27.8°C
The maximum junction temperature will then be equal to
the maximum junction temperature rise above ambient
plus the maximum ambient temperature or:
TJMAX = 50°C + 27.8°C = 77.8°C
Protection Features
The LT3023 regulator incorporates several protection
features which makes it ideal for use in battery-powered
circuits. In addition to the normal protection features
associated with monolithic regulators, such as current
3023f
12
LT3023
W U U
APPLICATIO S I FOR ATIO
U
100
90
80
760
60
50
40
30
20
10
0
In circuits where a backup battery is required, several
different input/output conditions can occur. The output
voltage may be held up while the input is either pulled to
ground, pulledtosomeintermediatevoltageorisleftopen
circuit. Current flow back into the output will follow the
curve shown in Figure 6.
T
V
V
= 25°C
A
= 0V
IN
OUT
= V
ADJ
CURRENT FLOWS
INTO OUTPUT PIN
When the IN pin of the LT3023 is forced below the OUT1
or OUT2 pins or the OUT1/OUT2 pins are pulled above the
IN pin, input current will typically drop to less than 2µA.
This can happen if the input of the device is connected to
a discharged (low voltage) battery and the output is held
up by either a backup battery or a second regulator circuit.
The state of the SHDN1/SHDN2 pins will have no effect on
thereverseoutputcurrentwhentheoutputispulledabove
the input.
4
0
1
2
3
5
6
7
8
9
10
OUTPUT VOLTAGE (V)
3023 F06
Figure 6. Reverse Output Current
U
TYPICAL APPLICATIO S
Noise Bypassing Slows Startup, Allows Outputs to Track
V
SHDN1/SHDN2
1V/DIV
V
OUT1
1V/DIV
V
OUT2
V
1V/DIV
IN
3.7V TO 20V
3.3V
IN
OUT1
AT 100mA
0.01µF
0.01µF
10µF
422k
1µF
BYP1
ADJ1
3023 TA02b
2ms/DIV
249k
LT3023
Startup Time
OFF ON
2.5V
AT 100mA
SHDN1
SHDN2
OUT2
100
10
1
10µF
261k
BYP2
ADJ2
GND
249k
3023 TA02a
0.1
10
100
1000
10000
C
BYP
(pF)
3023 TA02c
3023f
13
LT3023
U
PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
0.675 ±0.05
3.50 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
R = 0.115
TYP
6
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.38 ± 0.10
10
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 5)
(DD10) DFN 0403
5
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3023f
14
LT3023
U
PACKAGE DESCRIPTIO
MSE Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1663)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.06 ± 0.102
(.081 ± .004)
2.794 ± 0.102
(.110 ± .004)
0.889 ± 0.127
(.035 ± .005)
1
1.83 ± 0.102
(.072 ± .004)
5.23
(.206)
MIN
2.083 ± 0.102 3.20 – 3.45
(.082 ± .004) (.126 – .136)
10
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ± .0015)
TYP
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.497 ± 0.076
(.0196 ± .003)
REF
10 9
8
7 6
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
1
2
3
4 5
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.127 ± 0.076
(.005 ± .003)
MSOP (MSE) 0603
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3023f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LT3023
TYPICAL APPLICATIO S
U
Startup Sequencing
Turn-On Waveforms
V
SHDN1
1V/DIV
V
IN
3.7V TO 20V
3.3V
AT
V
OUT1
IN
OUT1
1V/DIV
100mA
V
OUT2
0.01µF
0.01µF
10µF
LT3023
1µF
1V/DIV
BYP1
ADJ1
422k
35.7k
249k
28k
3023 TA03b
2ms/DIV
2.5V
AT
100mA
OFF ON
SHDN1
SHDN2
OUT2
10µF
Turn-Off Waveforms
261k
249k
BYP2
ADJ2
GND
V
SHDN1
0.47µF
1V/DIV
3023 TA03a
V
OUT1
1V/DIV
OUT2
V
1V/DIV
3023 TA03c
2ms/DIV
RELATED PARTS
PART NUMBER
DESCRIPTION
700mA, Micropower, LDO
COMMENTS
V : 4.2V to 30V, V
LT1129
: 3.75V, I : 50µA, I : 16µA,
OUT(MIN) Q SD
IN
DD, SOT-223, S8,TO220, TSSOP20 Packages
Guaranteed Voltage Tolerance and Line/Load Regulation
V : –20V to –4.3V, V : –3.8V, I : 45µA, I : 10µA,
LT1175
500mA, Micropower Negative LDO
IN
OUT(MIN)
Q
SD
DD,SOT-223, S8 Packages
Accurate Programmable Current Limit, Remote Sense
V : –35V to –4.2V, V : –2.40V, I : 2.5mA, I : <1µA, TO220-5 Package
LT1185
3A, Negative LDO
IN
OUT(MIN)
Q
SD
LT1761
100mA, Low Noise Micropower, LDO
150mA, Low Noise Micropower, LDO
500mA, Low Noise Micropower, LDO
Low Noise < 20µV
IN
Stable with 1µF Ceramic Capacitors,
OUT(MIN):
RMS,
V : 1.8V to 20V, V
1.22V, I : 20µA, I : <1µA, ThinSOT Package
Q SD
LT1762
Low Noise < 20µV
V : 1.8V to 20V, V
RMS,
: 1.22V, I : 25µA, I : <1µA, MS8 Package
IN
OUT(MIN)
Q
SD
LT1763
Low Noise < 20µV
V : 1.8V to 20V, V
RMS,
: 1.22V, I : 30µA, I : <1µA, S8 Package
IN
OUT(MIN)
Q
SD
LT1764/LT1764A
LTC1844
3A, Low Noise, Fast Transient Response, LDO
150mA, Very Low Drop-Out LDO
Low Noise < 40µV
IN
"A" Version Stable with Ceramic Capacitors,
OUT(MIN)
RMS,
V : 2.7V to 20V, V
: 1.21V, I : 1mA, I : <1µA, DD, TO220 Packages
Q SD
Low Noise < 30µV
IN
, Stable with 1µF Ceramic Capacitors,
RMS
V : 1.6V to 6.5V, V
: 1.25V, I : 40µA, I : <1µA, ThinSOT Package
OUT(MIN) Q SD
LT1962
300mA, Low Noise Micropower, LDO
1.5A, Low Noise, Fast Transient Response, LDO
Low Noise < 20µV
RMS,
V : 1.8V to 20V, V
: 1.22V, I : 30µA, I : <1µA, MS8 Package
Q SD
IN
OUT(MIN)
LT1963/LT1963A
Low Noise < 40µV
IN
DD, TO220, SOT-223, S8 Packages
"A" Version Stable with Ceramic Capacitors,
RMS,
OUT(MIN)
V : 2.1V to 20V, V
: 1.21V, I : 1mA, I : <1µA,
Q SD
LT1964
200mA, Low Noise Micropower, Negative LDO
Low Noise < 30µV Stable with Ceramic Capacitors,
RMS,
V : –0.9V to –20V, V
: –1.21V, I : 30µA, I : 3µA, ThinSOT Package
Q SD
IN
OUT(MIN)
LTC3407
Dual 600mA. 1.5MHz Synchronous Step Down
DC/DC Converter
V : 2.5V to 5.5V, V
IN
: 0.6 V, I : 40µA, I : <1µA, MSE Package
OUT(MIN) Q SD
3023f
LT/TP 1103 1K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
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LINEAR TECHNOLOGY CORPORATION 2003
相关型号：
LT3023IDD#PBF
LT3023 - Dual 100mA, Low Dropout, Low Noise, Micropower Regulator; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
Linear
LT3023IMSE
LT3023 - Dual 100mA, Low Dropout, Low Noise, Micropower Regulator; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
Linear
LT3024EDE#PBF
LT3024 - Dual 100mA/500mA Low Dropout, Low Noise, Micropower Regulator; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C
Linear
LT3024EDE#TR
LT3024 - Dual 100mA/500mA Low Dropout, Low Noise, Micropower Regulator; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C
Linear
LT3024EDE#TRPBF
LT3024 - Dual 100mA/500mA Low Dropout, Low Noise, Micropower Regulator; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C
Linear
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