LT3024IDE [Linear]
Dual 100mA/500mA Low Dropout, Low Noise,Micropower Regulator; 双100毫安/ 500毫安低压差，低噪声，微功率稳压器
| 型号： | LT3024IDE |
| 厂家： | 
Linear |
| 描述： | Dual 100mA/500mA Low Dropout, Low Noise,Micropower Regulator |
| 文件： | 总20页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3024
Dual 100mA/500mA
Low Dropout, Low Noise,
Micropower Regulator
FEATURES
DESCRIPTION
TheLT®3024isadual, micropower, lownoise, lowdropout
regulator.Withanexternal0.01μFbypasscapacitor,output
n
Low Noise: 20μV
(10Hz to 100kHz)
RMS
n
Low Quiescent Current: 30μA/Output
Wide Input Voltage Range: 1.8V to 20V
Output Current: 100mA/500mA
n
n
n
n
n
n
n
noisedropsto20μV
overa10Hzto100kHzbandwidth.
RMS
Designedforuseinbattery-poweredsystems,thelow30μA
quiescent current per output makes it an ideal choice. In
shutdown, quiescent current drops to less than 0.1μA.
Shutdowncontrolisindependentforeachoutput,allowing
for flexibility in power management. The device is capable
ofoperatingoveraninputvoltagerangeof1.8Vto20V.The
device can supply 100mA of output current from Output
2 with a dropout voltage of 300mV. Output 1 can supply
500mA of output current with a dropout voltage of 300mV.
Quiescent current is well controlled in dropout.
Very Low Shutdown Current: <0.1μA
Low Dropout Voltage: 300mV at 100mA/500mA
Adjustable Outputs from 1.22V to 20V
Stable with 1μF/3.3μF Output Capacitor
Stable with Aluminum, Tantalum or
Ceramic Capacitors
n
n
n
n
n
Reverse Battery Protected
No Reverse Current
No Protection Diodes Needed
Overcurrent and Overtemperature Protected
Thermally Enhanced 16-Lead TSSOP and 12-Lead
(4mm × 3mm) DFN Packages
The LT3024 regulator is stable with output capacitors as
low as 1μF for the 100mA output and 3.3μF for the 500mA
output. Small ceramic capacitors can be used without the
series resistance required by other regulators.
APPLICATIONS
Internal protection circuitry includes reverse-battery
protection, current limiting, thermal limiting and reverse
current protection. The device is available as an adjust-
able device with a 1.22V reference voltage. The LT3024
regulator is available in the thermally enhanced 16-lead
TSSOP and 12-lead, low profile (4mm × 3mm × 0.75mm)
DFN packages.
n
Cellular Phones
n
Pagers
n
Battery-Powered Systems
n
Frequency Synthesizers
n
Wireless Modems
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
TYPICAL APPLICATION
3.3V/2.5V Low Noise Regulators
10Hz to 100kHz Output Noise
3.3V AT 500mA
20μV NOISE
IN
OUT1
RMS
V
IN
0.01μF
10μF
10μF
SHDN1
SHDN2
422k
249k
1μF
3.7V TO
20V
BYP1
ADJ1
LT3024
V
OUT
20μV
RMS
100μV/DIV
2.5V AT 100mA
20μV NOISE
OUT2
RMS
0.01μF
261k
BYP2
ADJ2
GND
249k
3024 TA01b
3024 TA01a
3024fa
1
LT3024
ABSOLUTE MAXIMUM RATINGS
(Note 1)
IN Pin Voltage ......................................................... 20V
OUT1, OUT2 Pin Voltage......................................... 20V
Input-to-Output Differential Voltage........................ 20V
ADJ1, ADJ2 Pin Voltage............................................ 7V
BYP1, BYP2 Pin Voltage ........................................ 0.6V
SHDN1, SHDN2 Pin Voltage ................................... 20V
Output Short-Circut Duration........................... Indefinite
Operating Junction Temperature Range
(Note 2) ............................................. –40°C to 125°C
Storage Temperature Range
FE Package ........................................ –65°C to 150°C
DE Package........................................ –65°C to 125°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
(FE package only)
PIN CONFIGURATION
TOP VIEW
TOP VIEW
GND
BYP1
OUT1
OUT1
GND
1
2
3
4
5
6
7
8
16
15
14
GND
BYP1
OUT1
OUT1
GND
1
2
3
4
5
6
12 ADJ1
11 SHDN1
10 IN
ADJ1
SHDN1
13 IN
17
13
12
11
10
9
IN
9
8
7
IN
OUT2
BYP2
GND
SHDN2
ADJ2
GND
OUT2
BYP2
SHDN2
ADJ2
DE12 PACKAGE
12-LEAD (4mm s 3mm) PLASTIC DFN
FE PACKAGE
T
= 150°C, θ = 40°C/W, θ = 10°C/W
16-LEAD PLASTIC TSSOP
= 150°C, θ = 38°C/W, θ = 8°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
JMAX
JA
JC
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
T
JMAX
JA JC
ORDER INFORMATION
LEAD FREE FINISH
LT3024EDE#PBF
LT3024IDE#PBF
LT3024EFE#PBF
LT3024IFE#PBF
LEAD BASED FINISH
LT3024EDE
TAPE AND REEL
LT3024EDE#TRPBF
LT3024IDE#TRPBF
LT3024EFE#TRPBF
LT3024IFE#TRPBF
TAPE AND REEL
LT3024EDE#TR
LT3024IDE#TR
PART MARKING*
3024
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
12-Lead (4mm × 3mm) Plastic DFN
12-Lead (4mm × 3mm) Plastic DFN
16-Lead Plastic TSSOP
3024
3024EFE
3024IFE
PART MARKING*
3024
16-Lead Plastic TSSOP
PACKAGE DESCRIPTION
12-Lead (4mm × 3mm) Plastic DFN
12-Lead (4mm × 3mm) Plastic DFN
16-Lead Plastic TSSOP
LT3024IDE
3024
LT3024EFE
LT3024EFE#TR
3024EFE
3024IFE
LT3024IFE
LT3024IFE#TR
16-Lead Plastic TSSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3024fa
2
LT3024
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
Minimum Input Voltage
(Notes 3, 11)
Output 2, I
Output 1, I
= 100mA
= 500mA
1.8
1.8
2.3
2.3
V
V
LOAD
LOAD
ADJ1, ADJ2 Pin Voltage
(Note 3, 4)
V
= 2V, I
= 1mA
1.205
1.190
1.190
1.220
1.220
1.220
1.235
1.250
1.250
V
V
V
IN
LOAD
l
l
Output 2, 2.3V < V < 20V, 1mA < I
< 100mA
< 500mA
IN
IN
LOAD
LOAD
Output 1, 2.3V < V < 20V, 1mA < I
l
l
l
l
l
l
l
l
l
l
l
Line Regulation (Note 3)
Load Regulation (Note 3)
ΔV = 2V to 20V, I
= 1mA
1
1
10
mV
IN
LOAD
Output 2, V = 2.3V, ΔI
= 1mA to 100mA
= 1mA to 100mA
12
25
mV
mV
IN
IN
LOAD
LOAD
V
= 2.3V, ΔI
Output 1, V = 2.3V, ΔI
= 1mA to 500mA
= 1mA to 500mA
1
12
25
mV
mV
IN
IN
LOAD
LOAD
V
= 2.3V, ΔI
Dropout Voltage (Output 2)
I
I
= 1mA
= 1mA
0.10
0.17
0.24
0.30
0.13
0.17
0.20
0.30
0.15
0.19
V
V
LOAD
LOAD
V
IN
= V
(Notes 5, 6, 11)
OUT(NOMINAL)
I
I
= 10mA
= 10mA
0.22
0.29
V
V
LOAD
LOAD
I
I
= 50mA
= 50mA
0.31
0.40
V
V
LOAD
LOAD
I
I
= 100mA
= 100mA
0.35
0.45
V
V
LOAD
LOAD
Dropout Voltage (Output 1)
= V (Notes 5, 6, 11)
I
I
= 10mA
= 10mA
0.19
0.25
V
V
LOAD
LOAD
V
IN
OUT(NOMINAL)
I
I
= 50mA
= 50mA
0.22
0.32
V
V
LOAD
LOAD
I
I
= 100mA
= 100mA
0.34
0.44
V
V
LOAD
LOAD
I
I
= 500mA
= 500mA
0.35
0.45
V
V
LOAD
LOAD
l
l
l
l
l
GND Pin Current (Output 2)
= V (Notes 5, 7)
I
I
I
I
I
= 0mA
20
55
45
90
400
2
μA
μA
LOAD
LOAD
LOAD
LOAD
LOAD
V
= 1mA
IN
OUT(NOMINAL)
= 10mA
= 50mA
= 100mA
230
1
μA
mA
mA
2.2
4
l
l
l
l
l
l
GND Pin Current (Output 1)
= V (Notes 5, 7)
I
I
I
I
I
I
= 0mA
30
65
1.1
2
75
120
1.6
3
μA
μA
mA
mA
mA
mA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
V
= 1mA
IN
OUT(NOMINAL)
= 50mA
= 100mA
= 250mA
= 500mA
5
8
11
16
Output Voltage Noise
C
= 10μF, C
= 0.01μF, I
= Full Current,
20
μV
RMS
OUT
BYP
LOAD
BW = 10Hz to 100kHz
ADJ Pin Bias Current
Shutdown Threshold
ADJ1, ADJ2 (Notes 3, 8)
30
100
1.4
nA
l
l
V
OUT
V
OUT
= Off to On
= On to Off
0.8
0.65
V
V
0.25
55
l
l
SHDN1/SHDN2 Pin Current
(Note 9)
V
V
, V
= 0V
= 20V
0
1
0.5
3
μA
μA
SHDN1 SHDN2
, V
SHDN1 SHDN2
Quiescent Current in Shutdown
Ripple Rejection
V
V
= 6V, V
= 0V, V = 0V
SHDN2
0.01
65
0.1
μA
dB
IN
SHDN1
= 2.72V (Avg), V
= Full Current
= 0.5V , f
= 120Hz,
IN
RIPPLE
P-P RIPPLE
I
LOAD
3024fa
3
LT3024
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
Output 2, V = 7V, V
MIN
110
520
TYP
MAX
UNITS
Current Limit
= 0V
OUT
200
mA
mA
IN
l
V
= 2.3V, ΔV
= –0.1V
IN
OUT
Output 1, V = 7V, V
= 0V
700
5
mA
mA
IN
OUT
l
l
V
= 2.3V, ΔV
= –0.1V
IN
OUT
Input Reverse Leakage Current
V
V
= –20V, V
= 0V
1
mA
μA
IN
OUT
Reverse Output Current (Notes 3,10)
= 1.22V, V < 1.22V
10
OUT
IN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 6: Dropout voltage is the minimum input to output voltage differential
needed to maintain regulation at a specified output current. In dropout, the
output voltage will be equal to: V – V
.
IN
DROPOUT
Note 7: GND pin current is tested with V = 2.44V and a current source
IN
Note 2: The LT3024 is tested and specified under pulse load conditions
load. This means the device is tested while operating in its dropout region
or at the minimum input voltage specification. This is the worst-case GND
pin current. The GND pin current will decrease slightly at higher input
voltages. Total GND pin current is equal to the sum of GND pin currents
from Output 1 and Output 2.
such that T ≅ T . The LT3024E is 100% tested at T = 25°C. Performance
J
A
A
at –40°C and 125°C is assured by design, characterization and correlation
with statistical process controls. The LT3024I is guaranteed over the full
–40°C to 125°C operating junction temperature range.
Note 3: The LT3024 is tested and specified for these conditions with the
ADJ1/ADJ2 pin connected to the corresponding OUT1/OUT2 pin.
Note 8: ADJ1 and ADJ2 pin bias current flows into the pin.
Note 9: SHDN1 and SHDN2 pin current flows into the pin.
Note 4: Operating conditions are limited by maximum junction
temperature. The regulated output voltage specification will not apply
for all possible combinations of input voltage and output current. When
operating at maximum input voltage, the output current range must be
limited. When operating at maximum output current, the input voltage
range must be limited.
Note 5: To satisfy requirements for minimum input voltage, the LT3024 is
tested and specified for these conditions with an external resistor divider
(two 250k resistors) for an output voltage of 2.44V. The external resistor
divider will add a 5μA DC load on the output.
Note 10: Reverse output current is tested with the IN pin grounded and the
OUT pin forced to the rated output voltage. This current flows into the OUT
pin and out the GND pin.
Note 11: For the LT3024 dropout voltage will be limited by the minimum
input voltage specification under some output voltage/load conditions.
See the curve of Minimum Input Voltage in the Typical Performance
Characteristics.
3024fa
4
LT3024
TYPICAL PERFORMANCE CHARACTERISTICS
Output 2
Typical Dropout Voltage
Output 2
Guaranteed Dropout Voltage
Output 2 Dropout Voltage
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
= TEST POINTS
T
≤ 125°C
≤ 25°C
J
T
= 125°C
J
I
L
= 100mA
T
J
I
L
= 50mA
T
= 25°C
J
I
L
= 10mA
I
= 1mA
L
0
0
0
40
40
50 60 70 80 90 100
–50 –25
0
25
50
75 100 125
0
10 20 30
50 60 70 80 90 100
0
10 20 30
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
3024 G03
3024 G01
3024 G02
Output 1
Typical Dropout Voltage
Output 1
Guaranteed Dropout Voltage
Output 1 Dropout Voltage
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
= TEST POINTS
I
= 500mA
L
I
= 250mA
T
= 125°C
L
J
T
≤ 125°C
≤ 25°C
J
I
= 100mA
L
I
L
= 50mA
T
J
T
= 25°C
J
I
= 1mA
L
I
L
= 10mA
0
0
0
200
200
250 300 350 400 450 500
–50 –25
0
25
50
75 100 125
0
50 100 150
250 300 350 400 450 500
0
50 100 150
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
3024 G06
3024 G04
3024 G05
Quiescent Current (Per Output)
ADJ1 or ADJ2 Pin Voltage
1.240
1.235
1.230
1.225
1.220
1.215
1.210
1.205
1.200
50
45
40
35
30
25
20
15
10
5
I
= 1mA
L
V
SHDN
= V
IN
V
= 6V
= 250k, I = 5μA
L
IN
L
R
0
–25
0
25
50
75
125
–25
0
25
50
75
125
–50
100
–50
100
TEMPERATURE (°C)
TEMPERATURE (°C)
3024 G07
3024 G08
3024fa
5
LT3024
TYPICAL PERFORMANCE CHARACTERISTICS
Output 2
GND Pin Current vs ILOAD
Quiescent Current (Per Output)
Output 2 GND Pin Current
40
35
30
25
20
15
10
5
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
T
= 25°C
= 250k
V
IN
= V + 1V
OUT(NOMINAL)
J
L
T
= 25°C
J
R
*FOR V
= 1.22V
OUT
V
= V
IN
SHDN
R
L
= 12.2Ω
L
I
= 100mA*
R
= 24.4Ω
= 50mA*
L
I
L
R
L
= 1.22k
L
R
L
= 122Ω
L
I
= 1mA*
I
= 10mA*
V
SHDN
= 0V
0
0
2
4
6
8
10 12 14 16 18 20
4
40
10 20 30
50 60 70 80 90 100
0
1
2
3
5
6
7
8
9
10
0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
3024 G09
3024 G10
3024 G11
Output 1
GND Pin Current vs ILOAD
Output 1 GND Pin Current
Output 1 GND Pin Current
12
10
8
12
10
8
1200
1000
800
600
400
200
0
V
IN
= V
+ 1V
T
= 25°C
OUT(NOMINAL)
J
V
= V
IN
SHDN
R
L
= 24.4Ω
*FOR V
= 1.22V
L
OUT
I
= 50mA*
R
L
= 2.44Ω
L
I
= 500mA*
T
= 25°C
= V
J
IN
R
L
L
= 4.07Ω
V
SHDN
6
6
I
= 300mA*
*FOR V
= 1.22V
OUT
R
L
= 122Ω
4
4
L
I
= 10mA*
R
L
= 12.2Ω
L
I
= 100mA*
2
2
R
I
= 1.22k
= 1mA*
L
L
0
0
4
200
250 300 350 400 450 500
0
1
2
3
5
6
7
8
9
10
0
50 100 150
4
0
1
2
3
5
6
7
8
9
10
INPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
INPUT VOLTAGE (V)
3024 G13
3024 G14
3024 G12
SHDN1 or SHDN2 Pin Threshold
(On-to-Off)
SHDN1 or SHDN2 Pin Threshold
(Off-to-On)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
I
= 1mA
L
I
= FULL
= 1mA
L
I
L
–50
0
25
50
75 100 125
125
–25
–50
0
25
50
75
–25
100
TEMPERATURE (°C)
TEMPERATURE (°C)
3024 G15
3024 G16
3024fa
6
LT3024
TYPICAL PERFORMANCE CHARACTERISTICS
SHDN1 or SHDN2 Pin Input
Current
SHDN1 or SHDN2 Pin Input
Current
ADJ1 or ADJ2 Pin Bias Current
100
90
80
70
60
50
40
30
20
10
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 20V
SHDN
–50
0
25
50
75 100 125
50
4
–25
–50
–25
0
25
75 100 125
0
1
2
3
5
6
7
8
9
10
TEMPERATURE (°C)
TEMPERATURE (°C)
SHDN PIN VOLTAGE (V)
3024 G18
3024 G19
3024 G17
Output 2 Current Limit
Output 2 Current Limit
Output 1 Current Limit
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
350
300
250
200
150
100
50
350
300
250
200
150
100
50
V
= 0V
V
V
= 7V
OUT
V
OUT
= 0V
OUT
J
IN
T
= 25°C
= 0V
0
0
0
2
3
4
5
6
7
–50 –25
0
25
50
75 100 125
0
2
3
4
5
6
7
1
1
INPUT VOLTAGE (V)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3024 G20
3024 G21
3024 G22
Reverse Output Current
Output 1 Current Limit
1.2
1.0
0.8
0.6
0.4
0.2
0
100
V
V
= 7V
OUT
IN
T
V
V
= 25°C
A
= 0V
90
80
70
60
50
40
30
20
10
0
= 0V
IN
OUT
= V
ADJ
CURRENT FLOWS
INTO OUTPUT PIN
–50
0
25
50
75 100 125
4
–25
0
1
2
3
5
6
7
8
9
10
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
3024 G23
3024 G24
3024fa
7
LT3024
TYPICAL PERFORMANCE CHARACTERISTICS
Output 2
Input Ripple Rejection
Output 2
Input Ripple Rejection
Reverse Output Current
80
70
60
50
40
30
20
10
0
18
15
12
9
80
70
60
50
40
30
20
10
0
V
V
= 0V
OUT
IN
= V
= 1.22V
ADJ
C
= 0.01μF
BYP
C
= 1000pF
BYP
C
= 100pF
BYP
C
= 10μF
OUT
6
C
= 1μF
OUT
I
V
C
= 100mA
3
L
I
V
C
= 100mA
L
IN
OUT
= 2.3V + 50mV
RIPPLE
10
IN
BYP
RMS
= 2.3V + 50mV
RIPPLE
RMS
= 0
= 10μF
0
50
TEMPERATURE (°C)
100 125
0.01
0.1
1
100
1000
–50 –25
0
25
75
0.01
0.1
1
10
100
1000
FREQUENCY (kHz)
FREQUENCY (kHz)
3024 G26
3024 G27
3024 G25
Output 1
Input Ripple Rejection
Output 2
Input Ripple Rejection
Output 1
Input Ripple Rejection
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
C
= 0.01μF
BYP
C
OUT
= 10μF
C
BYP
= 1000pF
C
BYP
= 100pF
V
= V
+
I
= 500mA
= V
I
= 500mA
IN
OUT (NOMINAL)
L
IN
L
V
C
= 4.7μF
1V + 0.5V RIPPLE
P-P
OUT
V
+
= V
+
OUT(NOMINAL)
IN
OUT(NOMINAL)
AT f = 120Hz
1V + 50mV
C
RIPPLE
1V + 50mV
C
RIPPLE
1k
RMS
RMS
I
L
= 50mA
= 0
= 10μF
BYP
OUT
–25
0
25
50
75
125
–50
100
10
100
1k
10k
100k
1M
10
100
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
TEMPERATURE (°C)
3024 G29
3024 G30
3024 G28
Output 1 Ripple Rejection
Output 2 Minimum Input Voltage
2.5
68
66
64
62
60
58
56
54
52
V
OUT
= 1.22V
2.0
1.5
1.0
0.5
0
I
L
= 100mA
I
L
= 50mA
V
= V
+
OUT (NOMINAL)
IN
1V + 0.5V RIPPLE
P-P
AT f = 120Hz
I
= 500mA
L
–25
0
25
50
75
125
–50
100
50
125
–50
0
25
75 100
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
3024 G31
3024 G32
3024fa
8
LT3024
TYPICAL PERFORMANCE CHARACTERISTICS
Output 1 Minimum Input Voltage
Channel-to-Channel Isolation
Channel-to-Channel Isolation
100
90
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
V
OUT
= 1.22V
CHANNEL 2
I
L
= 500mA
80
V
OUT1
20mV/DIV
70
CHANNEL 1
I
L
= 1mA
60
50
V
OUT2
20mV/DIV
40
30
20
10
0
GIVEN CHANNEL IS TESTED
WITH 50mV
SIGNAL ON
RMS
3024 G50
OPPOSING CHANNEL, BOTH
CHANNELS DELIVERING FULL
CURRENT
50μs/DIV
C
C
C
= 22μF
= 10μF
BYP2
OUT1
OUT2
BYP1
L1
L2
= C = 0.01μF
–50
0
25
50
75 100 125
–25
10
100
1k
10k
100k
1M
ΔI = 50mA TO 500mA
TEMPERATURE (°C)
FREQUENCY (Hz)
ΔI = 10mA TO 100mA
V
3024 G34
3024 G33
= 6V, V
= V
= 5V
IN
OUT1
OUT2
Output 2 Load Regulation
Output 1 Load Regulation
Output Noise Spectral Density
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
5
0
10
1
ΔI = 1mA TO 500mA
L
C
C
L
= 10μF
= 0
OUT
BYP
I
= FULL LOAD
V
OUT
SET FOR 5V
V
OUT
=V
ADJ
–5
0.1
0.01
Δ
IL
= 1mA TO 100mA
–10
–25
0
25
50
75
125
–50 –25
0
25
50
75 100 125
–50
100
0.01
0.1
1
10
100
TEMPERATURE (°C)
TEMPERATURE (°C)
FREQUENCY (kHz)
3024 G37
3024 G35
3024 G36
RMS Output Noise
vs Bypass Capacitor
Output Noise Spectral Density
10
1
140
120
100
80
C
I
= 10μF
C
= 10μF
OUT
L
V
= 5V
OUT
OUT
= FULL LOAD
I
f
= FULL LOAD
L
BW
= 10Hz TO 100kHz
V
SET FOR 5V
OUT
CHANNEL 2
C
= 1000pF
BYP
C
= 100pF
BYP
CHANNEL 1
= 1.22V
V
OUT
V
=V
OUT
ADJ
60
CHANNEL 2
0.1
40
C
BYP
= 0.01μF
CHANNEL 1
20
0.01
0.01
0
10
100
1000
10000
0.1
1
10
100
FREQUENCY (kHz)
C
BYP
(pF)
3023 G38
3024 G39
3024fa
9
LT3024
TYPICAL PERFORMANCE CHARACTERISTICS
Output 2
RMS Output Noise vs Load
Current (10Hz to 100kHz)
Output 1
RMS Output Noise vs Load
Current (10Hz to 100kHz)
10Hz to 100kHz Output Noise
BYP = 0pF
C
160
140
120
100
80
160
140
120
100
80
C
OUT
= 10μF
C
= 10μF
OUT
C
= 0μF
BYP
BYP
C
= 0
BYP
BYP
C
= 0.01μF
C
= 0.01μF
V
OUT
SET FOR 5V
V
OUT
SET FOR 5V
V
OUT
100μV/DIV
V
=V
ADJ
OUT
60
60
V
= V
ADJ
OUT
40
40
3024 G42
V
SET FOR 5V
= V
V
OUT
SET FOR 5V
OUT
1ms/DIV
20
20
C
L
= 10μF
OUT
V
OUT
V
=V
ADJ
ADJ
OUT
10
I
= 100mA
0
0.01
0
0.01
V SET FOR 5V
OUT
0.1
1
10
100
1000
0.1
1
100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3024 G40
3024 G41
10Hz to 100kHz Output Noise
CBYP = 100pF
10Hz to 100kHz Output Noise
CBYP = 1000pF
10Hz to 100kHz Output Noise
CBYP = 0.01µF
V
V
OUT
V
OUT
100μV/DIV
OUT
100μV/DIV
100μV/DIV
3024 G43
3024 G45
3024 G44
1ms/DIV
1ms/DIV
1ms/DIV
C
I
= 10μF
C
L
= 10μF
OUT
L
OUT
C
I
= 10μF
OUT
OUT
= 100mA
I
= 100mA
= 100mA
L
V
SET FOR 5V
V
SET FOR 5V
V
SET FOR 5V
OUT
OUT
3024fa
10
LT3024
TYPICAL PERFORMANCE CHARACTERISTICS
Output 2 Transient Response
CBYP = 0pF
Output 2 Transient Response
CBYP = 0.01µF
V
C
C
= 6V, V
= 10μF
OUT
SET FOR 5V
OUT
V
C
C
= 6V, V
= 10μF
OUT
SET FOR 5V
OUT
IN
IN
IN
IN
0.2
0.1
0.04
0.02
0
= 10μF
= 10μF
0
–0.1
–0.2
–0.02
–0.04
100
50
0
100
50
0
800
TIME (μs)
80
0
400
1200
1600
2000
0
20 40 60
100 120 140 160 180 200
TIME (μs)
3024 G46
3024 G47
Output 1 Transient Response
CBYP = 0pF
Output 1 Transient Response
CBYP = 0.01µF
V
C
C
= 6V, V
= 10μF
OUT
SET FOR 5V
OUT
V
C
C
= 6V, V
= 10μF
OUT
SET FOR 5V
OUT
IN
IN
IN
IN
0.4
0.2
0.10
0.05
0
= 10μF
= 10μF
0
–0.2
–0.4
–0.05
–0.10
600
400
200
0
600
400
200
0
400
TIME (μs)
40
50 60 70 80 90 100
TIME (μs)
0
200
600
800
1000
0
10 20 30
3024 G48
3024 G49
3024fa
11
LT3024
PIN FUNCTIONS (DFN/TSSOP)
GND (Pins 4, 13)/(Pins 1, 5, 8, 9, 16, 17): Ground. The
ExposedPadmustbesolderedtoPCBgroundforoptimum
thermal performance.
SHDN1/SHDN2 (Pins 11/8)/(Pins 14/11): Shutdown. The
SHDN1/SHDN2 pins are used to put the corresponding
output of the LT3024 regulator into a low power shutdown
state. The output will be off when the pin is pulled low.
The SHDN1/SHDN2 pins can be driven either by 5V logic
or open-collector logic with pull-up resistors. The pull-up
resistors are required to supply the pull-up current of the
open-collectorgates,normallyseveralmicroamperes,and
theSHDN1/SHDN2pincurrent,typically1μA.Ifunused,the
ADJ1/ADJ2 (Pins 12/7)/(Pins 15/10): Adjust Pin. These
are the input to the error amplifiers. These pins are inter-
nally clamped to 7V. They have a bias current of 30nA
which flows into the pin (see curve of ADJ1/ADJ2 Pin
Bias Current vs Temperature in the Typical Performance
Characteristics section). The ADJ1 and ADJ2 pin voltage
is 1.22V referenced to ground and the output voltage
range is 1.22V to 20V.
pin must be connected to V . The device will not function
IN
if the SHDN1/SHDN2 pins are not connected.
IN (Pins 9, 10)/(Pins 12, 13): Input. Power is supplied
to the device through the IN pin. A bypass capacitor is
required on this pin if the device is more than six inches
away from the main input filter capacitor. In general, the
output impedance of a battery rises with frequency, so
it is advisable to include a bypass capacitor in battery-
powered circuits. A bypass capacitor in the range of 1μF
to 10μF is sufficient. The LT3024 regulator is designed to
withstand reverse voltages on the IN pin with respect to
ground and the OUT pin. In the case of a reverse input,
which can happen if a battery is plugged in backwards, the
device will act as if there is a diode in series with its input.
There will be no reverse current flow into the regulator
and no reverse voltage will appear at the load. The device
will protect both itself and the load.
BYP1/BYP2 (Pins 1/6)/(Pins 2/7): Bypass. The BYP1/
BYP2 pins are used to bypass the reference of the LT3024
regulator to achieve low noise performance from the
regulator. The BYP1/BYP2 pins are clamped internally to
0.6V (one V ) from ground. A small capacitor from the
BE
corresponding output to this pin will bypass the reference
to lower the output voltage noise. A maximum value of
0.01μF can be used for reducing output voltage noise to
a typical 20μV
over a 10Hz to 100kHz bandwidth. If
RMS
not used, this pin must be left unconnected.
OUT1/OUT2(Pins2,3/5)/(Pins3,4/6):Output.Theoutputs
supply power to the loads. A minimum output capacitor of
1μF is required to prevent oscillations on Output 2; Output
1 requires a minimum of 3.3μF. Larger output capacitors
will be required for applications with large transient loads
tolimitpeakvoltagetransients. SeetheApplicationsInfor-
mationsectionformoreinformationonoutputcapacitance
and reverse output characteristics.
3024fa
12
LT3024
APPLICATIONS INFORMATION
TheLT3024isadual100mA/500mAlowdropoutregulator
with micropower quiescent current and shutdown. The
device is capable of supplying 100mA from Output 2 at a
dropout voltage of 300mV. Output 1 delivers 500mA at a
dropout voltage of 300mV. The two regulators have com-
IN OUT1/OUT2
LT3024
V
OUT
⎛
⎞
⎟
R2
R1
+
V
= 1.22V 1+
+ I
(
R2
)(
)
OUT
ADJ
V
IN
⎜
⎝
⎠
R2
R1
V
= 1.22V
ADJ
ADJ1/ADJ2
GND
I
= 30nA AT 25°C
ADJ
OUTPUT RANGE = 1.22V TO 20V
monV andGNDpinsandarethermallycoupled,however,
IN
3024 F01
thetwooutputsoftheLT3024operateindependently.They
can be shut down independently and a fault condition on
one output will not affect the other output electrically.
Figure 1. Adjustable Operation
value of R1 should be no greater than 250k to minimize
errors in the output voltage caused by the ADJ pin bias
current. Note that in shutdown the output is turned off and
the divider current will be zero. Curves of ADJ Pin Voltage
vs Temperature and ADJ Pin Bias Current vs Temperature
appear in the Typical Performance Characteristics.
Output voltage noise can be lowered to 20μV
over a
RMS
10Hz to 100kHz bandwidth with the addition of a 0.01μF
reference bypass capacitor. Additionally, the reference
bypass capacitor will improve transient response of the
regulator, lowering the settling time for transient load
conditions.Thelowoperatingquiescentcurrent(30μAper
output) drops to less than 1μA in shutdown. In addition to
the low quiescent current, the LT3024 regulator incorpo-
rates several protection features which make it ideal for
use in battery-powered systems. The device is protected
against both reverse input and reverse output voltages.
In battery backup applications where the output can be
held up by a backup battery when the input is pulled to
ground, the LT3024 acts like it has a diode in series with
its output and prevents reverse current flow. Additionally,
in dual supply applications where the regulator load is
returned to a negative supply, the output can be pulled
below ground by as much as 20V and still allow the device
to start and operate.
The device is tested and specified with the ADJ pin tied to
the corresponding OUT pin for an output voltage of 1.22V.
Specifications for output voltages greater than 1.22V will
be proportional to the ratio of the desired output voltage
to 1.22V: V /1.22V. For example, load regulation on
OUT
Output 2 for an output current change of 1mA to 100mA
is –1mV typical at V
regulation is:
= 1.22V. At V
= 12V, load
OUT
OUT
(12V/1.22V)(–1mV) = –9.8mV
Bypass Capacitance and Low Noise Performance
The LT3024 regulator may be used with the addition of a
bypass capacitor from V
to the corresponding BYP pin
OUT
to lower output voltage noise. A good quality low leakage
capacitor is recommended. This capacitor will bypass the
reference of the regulator, providing a low frequency noise
pole. The noise pole provided by this bypass capacitor will
Adjustable Operation
The LT3024 has an output voltage range of 1.22V to 20V.
The output voltage is set by the ratio of two external resis-
tors as shown in Figure 1. The device servos the output
to maintain the corresponding ADJ pin voltage at 1.22V
referenced to ground. The current in R1 is then equal to
1.22V/R1 and the current in R2 is the current in R1 plus
the ADJ pin bias current. The ADJ pin bias current, 30nA
at 25°C, flows through R2 into the ADJ pin. The output
voltagecanbecalculatedusingtheformulainFigure1.The
lower the output voltage noise to as low as 20μV
with
RMS
the addition of a 0.01μF bypass capacitor. Using a bypass
capacitor has the added benefit of improving transient
response. With no bypass capacitor and a 10μF output
capacitor,a10mAto100mAloadsteponOutput2willsettle
to within 1% of its final value in less than 100μs. With the
addition of a 0.01μF bypass capacitor, the output will stay
3024fa
13
LT3024
APPLICATIONS INFORMATION
within1%forthesameloadstep. Bothoutputsexhibitthis
improvementintransientresponse(seeTransientReponse
in Typical Performance Characteristics section). However,
regulator start-up time is proportional to the size of the
bypass capacitor, slowing to 15ms with a 0.01μF bypass
capacitor and 10μF output capacitor.
shaded region of Figures 2 and 3 define the regions over
which the LT3024 regulator is stable. The minimum ESR
needed is defined by the amount of bypass capacitance
used, while the maximum ESR is 3Ω.
Extra consideration must be given to the use of ceramic
capacitors. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior across
temperature and applied voltage. The most common
dielectrics used are specified with EIA temperature char-
acteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and
Y5V dielectrics are good for providing high capacitances
in a small package, but they tend to have strong voltage
and temperature coefficients as shown in Figures 4 and 5.
When used with a 5V regulator, a 16V 10μF Y5V capacitor
can exhibit an effective value as low as 1μF to 2μF for the
DC bias voltage applied and over the operating tempera-
ture range. The X5R and X7R dielectrics result in more
stable characteristics and are more suitable for use as the
output capacitor. The X7R type has better stability across
temperature, while the X5R is less expensive and is avail-
able in higher values. Care still must be exercised when
using X5R and X7R capacitors; the X5R and X7R codes
only specify operating temperature range and maximum
capacitancechangeovertemperature.Capacitancechange
due to DC bias with X5R and X7R capacitors is better than
Y5VandZ5Ucapacitors,butcanstillbesignificantenough
to drop capacitor values below appropriate levels. Capaci-
tor DC bias characteristics tend to improve as component
casesizeincreases, butexpectedcapacitanceatoperating
voltage should be verified.
Output Capacitance and Transient Response
The LT3024 regulator is designed to be stable with a wide
range of output capacitors. The ESR of the output capaci-
tor affects stability, most notably with small capacitors. A
minimum output capacitor of 1μF with an ESR of 3Ω or
less is recommended for Output 2 to prevent oscillations.
A minimum output capacitor of 3.3μF with an ESR of 3Ω
or less is recommended for Output 1. The LT3024 is a
micropower device and output transient response will be
a function of output capacitance. Larger values of output
capacitance decrease the peak deviations and provide im-
provedtransientresponseforlargerloadcurrentchanges.
Bypasscapacitors,usedtodecoupleindividualcomponents
powered by the LT3024, will increase the effective output
capacitor value. With larger capacitors used to bypass the
reference(forlownoiseoperation),largervaluesofoutput
capacitorsareneeded.For100pFofbypasscapacitanceon
Output2, 2.2μFofoutputcapacitorisrecommended. With
a 330pF bypass capacitor or larger on this output, a 3.3μF
output capacitor is recommended. For Output 1, 4.7μF of
output capacitor is recommended for 100pF of bypass
capacitance. With 1000pF or larger bypass capacitor on
thisoutput,a6.8μFoutputcapacitorisrecommended.The
4.0
3.5
4.0
3.5
3.0
3.0
STABLE REGION
2.5
STABLE REGION
2.5
2.0
2.0
C
BYP
= 0
C
= 0
1.5
1.0
0.5
0
1.5
1.0
0.5
0
BYP
C
= 100pF
C
BYP
= 100pF
BYP
C
BYP
= 330pF
C
= 330pF
BYP
C
BYP
≥ 1000pF
C
BYP
> 3300pF
1
3
6
9 10
1
3
6
9 10
8
2
4
5
7
8
2
4
5
7
OUTPUT CAPACITANCE (μF)
OUTPUT CAPACITANCE (μF)
3024 F02
3024 F03
Figure 2. Output 2 Stability
Figure 3. Output 1 Stability
3024fa
14
LT3024
APPLICATIONS INFORMATION
20
40
20
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
0
X5R
X5R
0
–20
–20
–40
–60
–80
–100
–40
Y5V
–60
Y5V
–80
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
–100
0
8
12 14
2
4
6
10
16
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
DC BIAS VOLTAGE (V)
3024 F04
3024 F05
Figure 4. Ceramic Capacitor DC Bias Characteristics
Figure 5. Ceramic Capacitor Temperature Characteristics
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or
microphone works. For a ceramic capacitor the stress can
beinducedbyvibrationsinthesystemorthermaltransients.
The resulting voltages produced can cause appreciable
amounts of noise, especially when a ceramic capacitor is
used for noise bypassing. A ceramic capacitor produced
Figure 6’s trace in response to light tapping from a pencil.
Similar vibration induced behavior can masquerade as
increased output voltage noise.
Thermal Considerations
The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C). The
power dissipated by the device will be made up of two
components for each output:
1. Output current multiplied by the input/output voltage
differential: (I )(V – V ), and
OUT
IN
OUT
2. GND pin current multiplied by the input voltage:
(I )(V ).
GND
IN
The ground pin current can be found by examining the
GND Pin Current curves in the Typical Performance Char-
acteristics section. Power dissipation will be equal to the
sum of the two components listed above.
C
C
LOAD
= 10μF
= 0.01μF
= 100mA
OUT
BYP
The LT3024 regulator has internal thermal limiting de-
signed to protect the device during overload conditions.
For continuous normal conditions, the maximum junction
temperature rating of 125°C must not be exceeded. It is
important to give careful consideration to all sources of
thermal resistance from junction to ambient. Additional
heat sources mounted nearby must also be considered.
I
V
OUT
500μV/DIV
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
3024 F06
100ms/DIV
Figure 6. Noise Resulting from Tapping on a Ceramic Capacitor
3024fa
15
LT3024
APPLICATIONS INFORMATION
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat gener-
ated by power devices.
The power dissipated by each output will be equal to:
(V – V ) + I (V
I
)
GND IN(MAX)
OUT(MAX) IN(MAX)
OUT
Where for Output 1:
The following tables list thermal resistance for several
different board sizes and copper areas. All measurements
were taken in still air on 3/32" FR-4 board with one ounce
copper.
I
= 500mA
= 5V
OUT
OUT(MAX)
V
IN(MAX)
I
at (I
= 500mA, V = 5V) = 9mA
GND
IN
For Output 2:
= 100mA
Table 1. FE Package, 16-Lead TSSOP
COPPER AREA
I
OUT(MAX)
THERMAL RESISTANCE
TOPSIDE*
BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
V
= 5V
IN(MAX)
2
2
2
2
2
2
2
2
2
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
38°C/W
43°C/W
48°C/W
60°C/W
I
at (I
= 100mA, V = 5V) = 2mA
OUT IN
GND
2
1000mm
So for Output 1:
2
225mm
2
P = 500mA (5V – 3.3V) + 9mA (5V) = 0.90W
For Output 2:
100mm
*Device is mounted on topside.
Table 2. UE Package, 12-Lead DFN
COPPER AREA
P = 100mA (5V – 2.5V) + 2mA (5V) = 0.26W
THERMAL RESISTANCE
The thermal resistance will be in the range of 35°C/W to
55°C/W depending on the copper area. So the junction
temperature rise above ambient will be approximately
equal to:
TOPSIDE*
BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2
2
2
2
2
2
2
2
2
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
40°C/W
45°C/W
50°C/W
62°C/W
2
1000mm
2
225mm
(0.90W + 0.26W) 50°C/W = 57.8°C
2
100mm
*Device is mounted on topside.
The maximum junction temperature will then be equal to
the maximum junction temperature rise above ambient
plus the maximum ambient temperature or:
The thermal resistance junction-to-case (θ ), measured
JC
at the Exposed Pad on the back of the die is 10°C/W for
the DFN package and 8°C/W for the TSSOP package.
T
= 50°C + 57.8°C = 107.8°C
JMAX
Calculating Junction Temperature
Protection Features
Example: Given Output 1 set for an output voltage of
3.3V, Output 2 set for an output voltage of 2.5V, an input
voltage range of 3.8V to 5V, an output current range of
0mA to 500mA for Output 1, an output current range of
0mA to 100mA for Output 2 and a maximum ambient
temperature of 50°C, what will the maximum junction
temperature be?
The LT3024 regulator incorporates several protection fea-
tureswhichmakeitidealforuseinbattery-poweredcircuits.
In addition to the normal protection features associated
with monolithic regulators, such as current limiting and
thermal limiting, the device is protected against reverse
inputvoltages,reverseoutputvoltagesandreversevoltages
from output to input. The two regulators have common
3024fa
16
LT3024
APPLICATIONS INFORMATION
V and GND pins and are thermally coupled, however, the
1.22V reference when the output is forced to 20V. The top
resistor of the resistor divider must be chosen to limit the
current into the ADJ pin to less than 5mA when the ADJ
pin is at 7V. The 13V difference between output and ADJ
pin divided by the 5mA maximum current into the ADJ pin
yields a minimum top resistor value of 2.6k.
IN
two outputs of the LT3024 operate independently. They
can be shut down independently and a fault condition on
one output will not affect the other output electrically.
Current limit protection and thermal overload protection
areintendedtoprotectthedeviceagainstcurrentoverload
conditionsattheoutputofthedevice.Fornormaloperation,
the junction temperature should not exceed 125°C.
In circuits where a backup battery is required, several
different input/output conditions can occur. The output
voltage may be held up while the input is either pulled
to ground, pulled to some intermediate voltage or is left
open circuit. Current flow back into the output will follow
the curve shown in Figure 7.
The input of the device will withstand reverse voltages
of 20V. Current flow into the device will be limited to less
than 1mA (typically less than 100μA) and no negative
voltage will appear at the output. The device will protect
both itself and the load. This provides protection against
batteries which can be plugged in backward.
When the IN pin of the LT3024 is forced below either OUT
pin or either OUT pin is pulled above the IN pin, input cur-
rent for the corresponding regulator will typically drop to
less than 2μA. This can happen if the input of the device
is connected to a discharged (low voltage) battery and the
output is held up by either a backup battery or a second
regulator circuit. The state of the SHDN1/SHDN2 pin will
have no effect on the reverse output current when the
output is pulled above the input.
The output of the LT3024 can be pulled below ground
withoutdamagingthedevice.Iftheinputisleftopencircuit
or grounded, the output can be pulled below ground by
20V. The output will act like an open circuit; no current will
flow out of the pin. If the input is powered by a voltage
source, the output will source the short-circuit current of
the device and will protect itself by thermal limiting. In
this case, grounding the SHDN1/SHDN2 pins will turn off
the device and stop the output from sourcing the short-
circuit current.
100
T
V
V
= 25°C
A
90
80
70
60
50
40
30
20
10
0
= 0V
IN
OUT
= V
ADJ
CURRENT FLOWS
INTO OUTPUT PIN
The ADJ pins can be pulled above or below ground by as
much as 7V without damaging the device. If the input is
left open circuit or grounded, the ADJ pins will act like an
open circuit when pulled below ground and like a large
resistor (typically 100k) in series with a diode when pulled
above ground.
InsituationswheretheADJpinsareconnectedtoaresistor
divider that would pull the pins above their 7V clamp volt-
age if the output is pulled high, the ADJ pin input current
must be limited to less than 5mA. For example, a resistor
divider is used to provide a regulated 1.5V output from the
4
0
1
2
3
5
6
7
8
9
10
OUTPUT VOLTAGE (V)
3024 F07
Figure 7. Reverse Output Current
3024fa
17
LT3024
PACKAGE DESCRIPTION
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695 Rev D)
0.70 0.05
3.30 0.05
3.60 0.05
2.20 0.05
1.70 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
2.50 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.40 0.10
4.00 0.10
(2 SIDES)
R = 0.115
TYP
7
12
R = 0.05
TYP
3.30 0.10
3.00 0.10
(2 SIDES)
1.70 0.10
PIN 1
TOP MARK
(NOTE 6)
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
(UE12/DE12) DFN 0806 REV D
6
1
0.25 0.05
0.75 0.05
0.200 REF
0.50 BSC
2.50 REF
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3024fa
18
LT3024
PACKAGE DESCRIPTION
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BB
4.90 – 5.10*
(.193 – .201)
3.58
(.141)
3.58
(.141)
16 1514 13 12 1110
9
6.60 0.10
2.94
(.116)
4.50 0.10
SEE NOTE 4
6.40
(.252)
BSC
2.94
(.116)
0.45 0.05
1.05 0.10
0.65 BSC
5
7
8
1
2
3
4
6
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.0433)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE16 (BB) TSSOP 0204
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3024fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT3024
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
V : 4.2V to 30V, V
LT1129
700mA, Micropower, LDO
= 3.75V, I = 50μA, I = 16μA, DD, SOT-223, S8,TO220,
OUT(MIN) Q SD
IN
TSSOP20 Packages
LT1175
500mA, Micropower Negative LDO
3A, Negative LDO
Guaranteed Voltage Tolerance and Line/Load Regulation, V : –20V to –4.3V,
IN
V
= –3.8V, I = 45μA, I = 10μA, DD,SOT-223, S8 Packages
OUT(MIN)
Q SD
LT1185
Accurate Programmable Current Limit, Remote Sense, V : –35V to –4.2V, V
IN OUT(MIN)
= –2.40V, I = 2.5mA, I <1μA, TO220-5 Package
Q
SD
LT1761
100mA, Low Noise Micropower, LDO
150mA, Low Noise Micropower, LDO
500mA, Low Noise Micropower, LDO
3A, Low Noise, Fast Transient Response, LDO
150mA, Very Low Drop-Out LDO
300mA, Low Noise Micropower, LDO
Low Noise < 20μV
OUT(MIN) =
Stable with 1μF Ceramic Capacitors, V : 1.8V to 20V,
RMS, IN
V
1.22V, I = 20μA, I <1μA, ThinSOT Package
Q SD
LT1762
Low Noise < 20μV
MS8 Package
V : 1.8V to 20V, V
= 1.22V, I = 25μA, I <1μA,
Q SD
RMS, IN
OUT(MIN)
LT1763
Low Noise < 20μV
S8 Package
V : 1.8V to 20V, V
= 1.22V, I = 30μA, I <1μA,
Q SD
RMS, IN
OUT(MIN)
LT1764/LT1764A
LTC1844
LT1962
Low Noise < 40μV
OUT(MIN)
"A" Version Stable with Ceramic Capacitors, V : 2.7V to 20V,
RMS, IN
V
= 1.21V, I = 1mA, I <1μA, DD, TO220 Packages
Q
SD
Low Noise < 30μV
OUT(MIN)
, Stable with 1μF Ceramic Capacitors, V : 1.6V to 6.5V,
IN
RMS
V
= 1.25V, I = 40μA, I <1μA, ThinSOT Package
Q SD
Low Noise < 20μV
MS8 Package
V : 1.8V to 20V, V = 1.22V, I = 30μA, I <1μA,
OUT(MIN) Q SD
RMS, IN
LT1963/LT1963A
LT1964
1.5A, Low Noise, Fast Transient Response, LDO Low Noise < 40μV
"A" Version Stable with Ceramic Capacitors, V : 2.1V to 20V,
RMS, IN
Q
V
= 1.21V, I = 1mA, I <1μA, DD, TO220, SOT-223, S8 Packages
OUT(MIN)
SD
200mA, Low Noise Micropower, Negative LDO
Dual 100mA, Low Noise, Micropower LDO
Low Noise < 30μV
OUT(MIN)
Stable with Ceramic Capacitors, V : –0.9V to –20V,
RMS, IN
V
= –1.21V, I = 30μA, I = 3μA, ThinSOT Package
Q
SD
LT3023
Low Noise < 20μV
OUT(MIN)
Stable with 1μF Ceramic Capacitors, V : 1.8V to 20V,
RMS, IN
V
= 1.22V, I = 40μA, I <1μA, MS10E, DFN Packages
Q
SD
LTC3407
Dual 600mA. 1.5MHz Synchronous Step Down V : 2.5V to 5.5V, V
= 0.6 V, I = 40μA, I <1μA, MSE Package
OUT(MIN) Q SD
IN
DC/DC Converter
3024fa
LT 0208 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2004
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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