LT3050IDDB#TR [Linear]
IC VREG 0.6 V-44.5 V ADJUSTABLE POSITIVE LDO REGULATOR, 0.55 V DROPOUT, PDSO12, 3 X 2 MM, PLASTIC, DFN-12, Adjustable Positive Single Output LDO Regulator;
| 型号： | LT3050IDDB#TR |
| 厂家： | 
Linear |
| 描述： | IC VREG 0.6 V-44.5 V ADJUSTABLE POSITIVE LDO REGULATOR, 0.55 V DROPOUT, PDSO12, 3 X 2 MM, PLASTIC, DFN-12, Adjustable Positive Single Output LDO Regulator 稳压器 |
| 文件： | 总20页 (文件大小：344K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3050
100mA, Low Noise
Linear Regulator With Precision Current
Limit And Diagnostic Functions
DESCRIPTION
FEATURES
The LT®3050 is a micro-power, low noise, low dropout
voltage(LDO)linearregulator. Thedevicesupplies100mA
n
Output Current: 100mA
Dropout Voltage: 340mV
n
n
Input Voltage Range: 1.6V to 45V
of output current with a dropout voltage of 340mV. A 10nF
bypass capacitor reduces output noise to 30μV in a
10Hz to 100kHz bandwidth and soft-starts the reference.
The LT3050’s 45V input voltage rating combined with its
precisioncurrentlimitanddiagnosticfunctionsmaketheIC
an ideal choice for robust, high reliability applications.
n
n
n
n
Programmable Precision Current Limit: 5ꢀ
RMS
Programmable Minimum I
Monitor
OUT
th
Output Current Monitor: 1/100 of I
OUT
Fault Indicator: Current Limit, Minimum I
or
OUT
Thermal Limit
n
n
n
n
Low Noise: 30μV
(10Hz to 100kHz)
RMS
AsingleresistorprogramstheLT3050’scurrentlimit,accurate
to 5ꢀ over a wide input voltage and temperature range.
A single resistor programs the LT3050’s minimum output
currentmonitor,usefulfordetectingopen-circuitconditions.
The current monitor function sources a current equal to
1/100th of output current. A logic FAULT pin asserts low if
the LT3050 is in current limit, operating below its minimum
output current (open-circuit) or is in thermal shutdown.
Adjustable Output (V = V
= 0.6V)
REF
OUT(MIN)
Output Tolerance: 2ꢀ Over Line, Load and Temperature
Stable with Low ESR, Ceramic Output Capacitors
(2.2μF minimum)
n
n
Shutdown Current: <1μA
Reverse-Battery, Reverse-Output and
Reverse-Current Protection
n
n
Thermal Limit Protection
The LT3050 optimizes stability and transient response
with low ESR ceramic capacitors, requiring a minimum
of 2.2μF. The LT3050 is available as an adjustable device
with an output voltage range down to the 0.6V reference.
TheLT3050isavailableinthethermally-enhanced12-Lead
3mm × 2mm DFN and MSOP packages.
12-Lead 3mm × 2mm DFN and MSOP Packages
APPLICATIONS
n
Protected Antenna Supplies
Automotive Telematics
n
n
Industrial Applications (Trucks, Forklifts, etc.)
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
n
High Reliability Applications
Technology Corporation. All other trademarks are the property of their respective owners.
External Current Limit
RIMAX = 1.15k
TYPICAL APPLICATION
105
5V Supply with 100mA Precision Current Limit, 10mA IMIN
V
= 5V
OUT
104
103
102
101
100
99
IN
OUT
5V
1ꢀ
442k
V
IN
= 15V
12V
IN
SHDN
2.2ꢁF
1ꢁF
120k
V
ADJ
FAULT
1ꢀ
60.4k
V
V
= 12V
IN
IN
LT3050
I
MAX
I
= 5.6V
TO ꢁP ADC
0.1ꢁF
MON
98
1.15k
10nF
3k
(THRESHOLD = 100mA)
97
(ADC FULL SCALE = 3V)
96
I
REF/BYP
MIN
11.3k
95
0.1ꢁF
GND
–75 –50 –25
0
–25 50 75 100 125 150 175
10nF
(THRESHOLD = 10mA)
TEMPERATURE (°C)
3050 TA01
3050 TA01a
3050f
1
LT3050
(Note 1)
ABSOLUTE MAXIMUM RATINGS
IN Pin Voltage ........................................................ 50V
OUT Pin Voltage..................................................... 50V
Input-to-Output Differential Voltage....................... 50V
ADJ Pin Voltage ..................................................... 50V
REF/BYP Pin Voltage........................................–0.3V, 1V
SHDN Pin Voltage ................................................... 50V
FAULT Pin Voltage..........................................–0.3V, 50V
Output Short-Circuit Duration .......................... Indefinite
Operating Junction Temperature Range (Notes 2, 3)
E, I Grades.........................................–40°C to 125°C
MP Grade...........................................–55°C to 125°C
Storage Temperature Range...................–65°C to 150°C
Lead Temperature: Soldering, 10 sec.................... 300°C
(MSOP Package Only)
I
I
I
Pin Voltage ..............................................–0.3V, 7V
Pin Voltage ...............................................–0.3V, 7V
Pin Voltage...............................................–0.3V, 7V
MON
MIN
MAX
PIN CONFIGURATION
TOP VIEW
TOP VIEW
1
2
3
4
5
6
REF/BYP
12
11
I
I
MON
1
2
3
4
5
6
REF/BYP
12
11
10 GND
9
8
7
I
I
MON
MAX
I
MIN
MAX
I
MIN
13
GND
FAULT
SHDN
IN
10 GND
FAULT
SHDN
IN
13
GND
ADJ
OUT
OUT
9
8
7
ADJ
OUT
OUT
IN
IN
MSE PACKAGE
DDB PACKAGE
12-LEAD PLASTIC MSOP
12-LEAD (3mm s 2mm) PLASTIC DFN
T
JMAX
= 125°C, θ = 45°C/W, θ = 5°C/W TO 10°C/W
JA JC
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
T
= 125°C, θ = 49°C/W, θ = 13.5°C/W
JMAX
JA
JC
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LT3050EMSE#PBF
LT3050IMSE#PBF
LT3050MPMSE#PBF
LT3050EDDB#PBF
LT3050IDDB#PBF
LEAD BASED FINISH
LT3050EMSE
TAPE AND REEL
PART MARKING*
3050
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3050EMSE#TRPBF
LT3050IMSE#TRPBF
LT3050MPMSE#TRPBF
LT3050EDDB#TRPBF
LT3050IDDB#TRPBF
TAPE AND REEL
12-Lead Plastic MSOP
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
–40°C to 125°C
–40°C to 125°C
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
–40°C to 125°C
–40°C to 125°C
3050
12-Lead Plastic MSOP
3050
12-Lead Plastic MSOP
LFGC
12-Lead (3mm × 2mm) Plastic DFN
12-Lead (3mm × 2mm) Plastic DFN
PACKAGE DESCRIPTION
LFGC
PART MARKING*
3050
LT3050EMSE#TR
LT3050IMSE#TR
12-Lead Plastic MSOP
LT3050IMSE
3050
12-Lead Plastic MSOP
LT3050MPMSE
LT3050EDDB
LT3050MPMSE#TR
LT3050EDDB#TR
3050
12-Lead Plastic MSOP
LFGC
12-Lead (3mm × 2mm) Plastic DFN
12-Lead (3mm × 2mm) Plastic DFN
LT3050IDDB
LT3050IDDB#TR
LFGC
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3050f
2
LT3050
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
= 100mA
MIN
TYP
1.6
MAX
UNITS
l
Minimum Input Voltage (Notes 3, 11)
ADJ Pin Voltage (Notes 3, 4)
I
2.2
V
LOAD
V
= 2.2V, I
= 1mA
LOAD
594
588
600
606
612
mV
mV
IN
l
l
l
2.2V < V < 15V, 1mA < I
< 100mA (Note 15)
IN
LOAD
Line Regulation (Note 3)
Load Regulation (Note 3)
Dropout Voltage
ΔV = 2.2V to 45V, I
IN
= 1mA
0.25
0.2
3
4
mV
mV
LOAD
V
IN
= 2.2V, I
= 1mA to 100mA
LOAD
I
I
= 1mA
= 1mA
110
150
220
mV
mV
LOAD
LOAD
l
l
l
l
V
= V
(Notes 5, 6)
IN
OUT(NOMINAL)
I
I
= 10mA
= 10mA
195
280
340
240
340
mV
mV
LOAD
LOAD
I
I
= 50mA
= 50mA
330
450
mV
mV
LOAD
LOAD
I
I
= 100mA
= 100mA
400
550
mV
mV
LOAD
LOAD
l
l
l
l
l
GND Pin Current
= V
I
I
I
I
I
= 0mA
45
60
175
0.85
2.2
90
160
370
2
ꢁA
ꢁA
LOAD
LOAD
LOAD
LOAD
LOAD
V
+ 0.6V (Notes 6, 7, 11)
OUT(NOMINAL)
= 1mA
IN
= 10mA
= 50mA
= 100mA
ꢁA
mA
mA
5.2
Quiescent Current in Shutdown
ADJ Pin Bias Current (Notes 3, 12)
Output Voltage Noise
V
V
C
= 12V, V
= 0V
0.17
12.5
90
1
ꢁA
nA
IN
SHDN
l
= 12V
60
IN
= 10μF, I
= 100mA, V
= 600mV,
ꢁV
ꢁV
OUT
LOAD
OUT
RMS
BW = 10Hz to 100kHz
Output Voltage Noise
C
OUT
= 10μF, C = 0.01μF, I
= 100mA, V = 600mV
OUT
30
BYP
LOAD
RMS
BW = 10Hz to 100kHz
l
l
Shutdown Threshold
V
V
= Off to On
= On to Off
0.7
0.6
1.5
V
V
OUT
OUT
0.3
70
l
l
SHDN Pin Current (Note 13)
Ripple Rejection (Note 3)
V
V
= 0V
= 45V
1
3
ꢁA
ꢁA
SHDN
SHDN
0.9
85
V
–V
OUT
= 2V (AVG), V
= 0.5V ,
P-P
dB
IN
RIPPLE
f
= 120Hz, I
= 100mA
LOAD
RIPPLE
l
l
FAULT Pin Logic Low Voltage
FAULT Pin Leakage Current
V
= 2.2V, FAULT Asserted, I
= 100μA
140
250
1
mV
ꢁA
IN
FAULT
FAULT = 5V, FAULT Not Asserted
0.01
Input Reverse Leakage Current
Reverse Output Current (Note 14)
Internal Current Limit (Note 3)
V
V
V
= –45V, V
= 0
300
10
ꢁA
IN
OUT
= 1.2V, V = 0
0.2
ꢁA
OUT
IN
= 2.2V, V
OUT
= 0, I Pin Grounded
MAX
240
mA
IN
ΔV
OUT
l
l
l
l
= –5ꢀ
110
47.8
72.1
94.4
External Programmed Current Limit (Note 8) 5.6V < V < 15V, V
= 5V, R
= 2.26K
= 1.5K
IN
OUT
IMAX
IMAX
IMAX
50.4
75.9
99.3
52.9
79.7
mA
mA
mA
FAULT Pin Threshold
5.6V < V < 15V, V = 5V, R
IN
OUT
FAULT Pin Threshold
5.6V < V < 15V, V = 5V, R
= 1.15K
IN
OUT
104.3
FAULT Pin Threshold
3050f
3
LT3050
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
Minimum I
CONDITIONS
5.6V < V < 15V, V
MIN
0.9
9
TYP
1
MAX
1.1
UNITS
mA
l
l
l
Threshold Accuracy (Note 9)
= 5V, R
= 5V, R
= 110K
= 11.3K
MIN
IN
OUT
OUT
IMIN
IMIN
I
Threshold Accuracy (Note 9)
5.6V < V < 15V, V
10
11
mA
MIN
IN
Current Monitor Ratio (Note10)
Ratio = I /I
I
= 5mA, 25mA, 50mA, 75mA, 100mA
95
100
105
LOAD
OUT MON
V
IMON
= V
= 5V, 5.6V < V < 15V
OUT IN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. Absolute maximum input-to-output differential
voltage is not achievable with all combinations of rated IN pin and OUT pin
voltages. With the IN pin at 50V, the OUT pin may not be pulled below 0V.
The total differential voltage from IN to OUT must not exceed 50V.
Note 7: GND pin current is tested with V = V
current source load. GND pin current increases in dropout. See GND pin
current curves in the Typical Performance Characteristics section.
+ 0.5V and a
OUT(NOMINAL)
IN
Note 8: Current limit varies inversely with the external resistor value tied
from the I
pin to GND. For detailed information on how to set the
MAX
I
pin resistor value, please see the Operation section. If a programmed
MAX
current limit is not needed, the I
pin must be tied to GND and internal
MAX
Note 2: The LT3050 is tested and specified under pulse load conditions
protection circuitry implements short-circuit protection as specified.
such that T ~ T . The LT3050E is 100ꢀ production tested at T = 25°C.
J
A
A
Note 9: The I fault condition asserts if the output current falls below the
MIN
Performance at –40°C and 125°C is assured by design, characterization
and correlation with statistical process controls. The LT3050I is
guaranteed over the full –40°C to 125°C operating junction temperature
range. The LT3050MP is 100ꢀ tested over the –55°C to 125°C operating
junction temperature range.
I
threshold defined by an external resistor from the I
pin to GND.
MIN
MIN
For detailed information on how to set the I
see the Operation section. I
specification in the Electrical Characteristics section are not guaranteed
to 10ꢀ tolerance. If the I fault condition is not needed, the I pin
pin resistor value, please
MIN
settings below the Minimum I
Accuracy
MIN
MIN
MIN
MIN
Note 3: The LT3050 is tested and specified for these conditions with ADJ
must be left floating (unconnected).
pin connected to the OUT pin.
Note 10: The current monitor ratio varies slightly when V
≠ V . For
OUT
IMON
Note 4: Maximum junction temperature limits operating conditions.
Regulated output voltage specifications do not apply for all possible
combinations of input voltage and output current. If operating at the
maximum input voltage, limit the output current range. If operating at the
maximum output current, limit the input voltage range.
detailed information on how to calculate the output current from the I
MON
pin, please see the Operation section. If the current monitor function is not
needed, the I pin must be tied to GND.
MON
Note 11: To satisfy requirements for minimum input voltage, current limit
is tested at V = V +1V or V = 2.2V, whichever is greater.
IN
OUT(NOMINAL)
IN
Note 5: Dropout voltage is the minimum differential IN-to-OUT voltage
needed to maintain regulation at a specified output current. In dropout,
Note 12: ADJ pin bias current flows out of the ADJ pin:
Note 13: SHDN pin current flows into the SHDN pin.
Note 14: Reverse output current is tested with the IN pin grounded and the
OUT pin forced to the specified voltage. This current flows into the OUT pin
and out of the GND pin.
the output voltage equals (V - V
). For some output voltages,
DROPOUT
IN
minimum input voltage requirements limit dropout voltage.
Note 6: To satisfy minimum input voltage requirements, the LT3050 is
tested and specified for these conditions with an external resistor divider
Note 15: 100mA of output current does not apply to the full range of input
voltage due to the internal current limit foldback.
(60k bottom, 440k top) which sets V
to 5V. The external resistor
OUT
divider adds 10μA of DC load on the output. This external current is not
factored into GND pin current.
3050f
4
LT3050
TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25°C, unless otherwise noted.
Guaranteed Dropout Voltage
Dropout Voltage
Typical Dropout Voltage
600
550
500
450
400
350
300
250
200
150
100
50
600
550
500
450
400
350
300
250
200
150
100
50
600
550
500
450
400
350
300
250
200
150
100
50
=TEST POINTS
I
= 100mA
= 50mA
L
I
L
T
= 125°C
= 25°C
T
≤ 125°C
J
J
I
L
= 10mA
T
J
T
≤ 25°C
J
I
L
= 1mA
0
0
0
–75 –50 –25
0
25 50 75 100 125 150 175
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
TEMPERATURE (°C)
3050 G01
3050 G02
3050 G03
Quiescent Current
ADJ Pin Voltage
5V Quiescent Current
80
70
60
50
40
30
20
10
0
612
610
608
606
604
602
600
598
596
594
592
590
588
100
90
80
70
60
50
40
30
20
10
0
V
V
L
= V
= 5V
= 5ꢁA
= 12V
SHDN
IN
OUT
I
V
V
= V , R = 500k
IN L
SHDN
SHDN
V
IN
= 12V
ALL OTHER PINS = 0V
= 0 , R = 0
V
L
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
0
5
10 15 20 25 30 35 40 45
(V)
TEMPERATURE (°C)
TEMPERATURE (°C)
V
IN
3050 G06
3050 G04
3050 G05
SHDN Pin Threshold
GND Pin Current
GND Pin Current vs ILOAD
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
V
V
= 5.6V
OUT
I = 1mA
L
V
OUT
= 5V
IN
= 5V
R
R
= 50, I = 100mA
L
L
L
OFF TO ON
= 100, I = 50mA
L
ON TO OFF
R
= 5k, I = 1mA
L
L
R
= 500, I = 10mA
L
L
0
10 20 30 40 50 60 70 80 90 100
(mA)
–75 –50 –25
0
25 50 75 100 125 150 175
0
1
2
3
4
5
6
7
8
9 10 11 12
I
TEMPERATURE (°C)
INPUT VOLTAGE (V)
LOAD
3050 G08
3050 G09
3050 G07
3050f
5
LT3050
TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25°C, unless otherwise noted.
SHDN Pin Input Current
SHDN Pin Input Current
ADJ Pin Bias Current
3.0
2.5
2.0
1.5
1.0
0.5
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
50
45
40
35
30
25
20
15
10
5
V
SHDN
= 45V
0
–75 –50 –25
0
25 50 75 100 125 150 175
0
10
20
30
40
50
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
SHDN PIN VOLTAGE (V)
TEMPERATURE (°C)
3050 G10
3050 G11
3050 G12
Internal Current Limit
vs Output Voltage
Internal Current Limit
Internal Current Limit
350
300
250
200
150
100
50
250
225
200
175
150
125
100
75
225
200
175
150
125
100
75
V
V
= 12V
= 0V
V
IN
– V
= 1V
OUT(NOMINAL)
IN
OUT
T
T
T
T
= 125°C
= 25°C
= –40°C
= –55°C
T
T
T
T
= 125°C
= 25°C
= –40°C
= –55°C
J
J
J
J
J
J
J
J
50
50
CURRENT LIMIT
AT FAULT
THRESHOLD
CURRENT LIMIT
AT FAULT
THRESHOLD
25
25
0
0
0
–75 –50 –25
0
25 50 75 100 125 150 175
0
5
10 15 20 25 30 35 40 45
0
5
10 15 20 25 30 35 40 45
TEMPERATURE (°C)
INPUT/OUTPUT DIFFERENTIAL (V)
OUTPUT VOLTAGE (V)
3050 G13
3050 G14
3050 G15
Reverse Output Current
Reverse Output Current
Input Ripple Rejection
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
50
45
40
35
30
25
20
15
10
5
90
80
70
60
50
40
30
20
10
0
V
V
= V
= 1.2V
ADJ
ALL PINS GROUNDED EXCEPT FOR OUT
C
= 10nF
= 100pF
= 0
OUT
IN
REF/BYP
= 0
C
C
REF/BYP
REF/BYP
I
ADJ
I
= 100mA
L
C
V
V
= 10ꢁF
= 5V
OUT
OUT
I
OUT
= 5.8V + 50mV
RIPPLE
IN
RMS
0
0
10
20
V
30
(V)
40
50
–75 –50 –25
0
25 50 75 100 125 150 175
10
100
1K
10K 100K 1M
10M
TEMPERATURE (°C)
FREQUENCY (Hz)
OUT
3050 G16
3050 G17
3050 G18
3050f
6
LT3050
TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25°C, unless otherwise noted.
Input Ripple Rejection
Ripple Rejection vs Temperature
Minimum Input Voltage
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
I
=100mA
C
C
= 10ꢁF
= 2.2ꢁF
C
C
= 10μF
L
OUT
OUT
OUT
REF/BYP
= 10nF
I
= 100mA
L
I
V
V
= 100mA
= 5V
IN
C
V
V
= 100pF
L
OUT
REF/BYP
= 5V
OUT
= 5.8V + 0.5V RIPPLE AT f = 120Hz
= 5.8V + 50mV
RIPPLE
P-P
IN
RMS
–75 –50 –25
0
25 50 75 100 125 150 175
10
100
1K
10K 100K 1M
10M
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
FREQUENCY (Hz)
TEMPERATURE (°C)
3050 G19a
3050 G19
3050 G20
Output Noise Spectral Density
CREF/BYP = 0
Output Noise Spectral Density
vs CREF/BYP
Load Regulation
4
3
10
1
10
1
ΔI = 1mA TO 100mA
L
C
= 100pF
REF/BYP
V
OUT
= 5V
V
V
= 0.6V
OUT
IN
= 2.2V
2
1
V
OUT
= 0.6V
0
V
V
V
V
V
V
V
= 5V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
–1
–2
–3
–4
= 3.3V
= 2.5V
= 1.8V
= 1.5V
= 1.2V
= 0.6V
0.1
0.01
0.1
0.01
C
= 10nF
REF/BYP
C
= 1nF
REF/BYP
C
I
= 10ꢁF
C
I
= 10ꢁF
OUT
= 100mA
OUT
L
= 100mA
L
10
100
1k
FREQUENCY (Hz)
10k
100k
–75 –50 –25
0
25 50 75 100 125 150 175
10
100
1K
FREQUENCY (Hz)
10K
100k
TEMPERATURE (°C)
3050 G21
3050 G22
3050 G23
RMS Output Noise vs Load Current
vs CREF/BYP
RMS Output Noise vs Load Current
CREF/BYP = 10nF
Startup Time
vs REF/BYP Capacitor
110
100
90
80
70
60
50
40
30
20
10
0
60
50
40
30
20
10
0
170
160
150
140
130
120
110
100
90
V
C
= 0.6V
= 10ꢁF
f
= 10Hz TO 100kHz
= 10ꢁF
OUT
OUT
OUT
OUT
V
= 5V
OUT
C
C
= 0
REF/BYP
V
OUT
= 2.5V
C
= 10pF
V
= 3.3V
REF/BYP
OUT
V
OUT
= 1.8V
V
= 1.5V
OUT
C
= 100pF
REF/BYP
80
70
60
C
= 1nF
50
REF/BYP
40
V
V
= 1.2V
= 0.6V
OUT
OUT
C
= 10nF
30
REF/BYP
20
C
1
= 100nF
REF/BYP
10
0
0.01
0.1
10
100
0.01
0.1
1
10
100
0
10 20 30 40 50 60 70 80 90 100
LOAD CURRENT (mA)
REF/BYP CAPACITOR (nF)
LOAD CURRENT (mA)
3050 G33
3050 G24
3050 G25
3050f
7
LT3050
TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25°C, unless otherwise noted.
5V 10Hz to 100kHz Output Noise
CREF/BYP = 0
5V 10Hz to 100kHz Output Noise
CREF/BYP = 10nF
Transient Response
V
OUT
100mV/DIV
V
V
OUT
500ꢁV/DIV
OUT
I
= 10mA TO 100mA
= 6V
OUT
IN
500ꢁV/DIV
V
V
C
= 5V
OUT
OUT
I
OUT
= C = 10ꢁF
IN
50mA/DIV
3050 G27
3050 G26
3050 G28
C
L
= 10ꢁF
1ms/DIV
C
L
= 10ꢁF
1ms/DIV
200ꢁs/DIV
OUT
OUT
I
= 100mA
I = 100mA
SHDN Transient Response
CREF/BYP = 10nF
SHDN Transient Response
CREF/BYP =0
Transient Response (Load Dump)
OUT
OUT
V
OUT
5V/DIV
5V/DIV
20mV/DIV
I =100mA
I
= 100mA
L
L
45V
12V
REF/BYP
REF/BYP
500mV/DIV
500mV/DIV
V
= 5V
= 50mA
= 2.2ꢁF
OUT
OUT
V
IN
I
SHDN
1V/DIV
SHDN
1V/DIV
10V/DIV
C
OUT
3050 G30
3050 G31
3050 G29
2ms/DIV
2ms/DIV
1ms/DIV
External Current Limit
RIMAX = 2.26k
External Current Limit
RIMAX = 1.5k
External Current Limit
RIMAX = 1.5k
52.8
52.3
51.8
51.3
50.8
50.3
49.8
49.3
48.8
48.3
47.8
79.50
78.75
78.00
77.25
76.50
75.75
75.00
74.25
73.50
72.75
72.00
105
104
103
102
101
100
99
V
OUT
= 5V
V
= 5V
V
OUT
= 5V
OUT
V
IN
= 15V
V
= 15V
V
= 15V
IN
IN
V
V
= 12V
V
V
= 12V
IN
IN
IN
IN
V
V
= 12V
IN
IN
= 5.6V
= 5.6V
= 5.6V
98
97
96
95
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
–25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3050 G34
3050 G35
3050 G36
3050f
8
LT3050
TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25°C, unless otherwise noted.
Minimum Output Current
Threshold RIMIN = 11.3k
Minimum Output Current
Threshold RIMIN = 110k
11.00
10.75
10.50
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
0.900
V
OUT
= 5V
V
OUT
= 5V
10.25
10.00
V
IN
= 15V
V
IN
= 15V
V
V
= 12V
IN
IN
V
V
= 12V
IN
IN
= 5.6V
= 5.6V
9.75
9.50
9.25
9.00
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
3050 G38
3050 G37
IOUT/IMON Current Ratio
VOUT = 5V, VIN = 12V
IOUT/IMON Current Ratio
VOUT = 5, VIN = 5.6V
IOUT/IMON Current Ratio
VOUT = 5V, VIN = 5.6V
102
101
100
99
102
101
100
99
102
100
99
98
97
96
95
94
93
92
91
V
IMON
= 5V
V
V
= 5V
= 4V
IMON
IMON
98
98
125°C
25°C
–55°C
97
97
V
V
V
V
= 3V
= 2V
= 1V
= 0V
IMON
IMON
96
96
V
V
V
V
V
V
= 5V
= 4V
= 3V
= 2V
= 1V
= 0V
IMON
IMON
IMON
IMON
IMON
IMON
95
95
V
IMON
= 0V
IMON
IMON
94
94
93
93
92
92
0
25
50
75
(mA)
100
125
0
25
50
75
100
125
0
25
50
75
100
125
I
OUT
I
(mA)
I
(mA)
OUT
OUT
3050 G39
3050 G40
3050 G41
IOUT/IMON Current Ratio
VOUT = 5V, VIN = 12V
IOUT Calculated From IMON
VOUT = 5V
103
102
101
100
9
5
4
V
70 + V – V
IN
IMON
OUT
OUT
I
= I
OUT MONR •
•
R
70 + V – V
IN
IMON
V
IMON
= 5V
3
(SEE PAGE 12 FOR DETAILS)
2
125°C
25°C
–55°C
1
98
0
97
–1
–2
–3
–4
–5
V
V
V
V
V
V
=5.6V, R
=5.6V, R
=5.6V, R
=1k
V
= 0V
IN
IN
IN
IN
IN
IN
IMON
IMON
=2k
IMON
=3k
IMON
96
95
=12V, R
=12V, R
=12V, R
=1k
=2k
=3k
IMON
IMON
IMON
94
93
0
25
50
I
75
(mA)
100
125
0
25
50
75
(mA)
100
125
I
OUT
OUT
3050 G42
3050 G43
3050f
9
LT3050
PIN FUNCTIONS
REF/BYP (Pin 1): Bypass/Soft-Start. Connecting a single
capacitor from this pin to GND bypasses the LT3050’s
reference noise and soft-starts the reference. A 10nF
bypass capacitor typically reduces output voltage noise to
microamperes,andtheSHDNpincurrent,typicallylessthan
2μA. If unused, connect the SHDN pin to IN. The LT3050
does not function if the SHDN pin is not connected. The
SHDN pin cannot be driven below GND unless tied to the
IN pin. If the SHDN pin is driven below GND while IN is
powered, the output may turn on. SHDN pin logic cannot
be referenced to a negative rail.
30μV
in a 10Hz to 100kHz bandwidth. Soft-start time
RMS
is directly proportional to the REF/BYP capacitor value.
If the LT3050 is placed in shutdown, REF/BYP is actively
pulled low by an internal device to reset soft-start. If low
noise or soft-start performance is not required, this pin
must be left floating (unconnected). Do not drive this pin
with any active circuitry. Because the REF/BYP pin is the
reference input to the error amplifier, stray capacitance at
this point should be minimized. Special attention should
begiventoanystraycapacitancesthatcancoupleexternal
signalsontotheREF/BYPpinproducingundesirableoutput
transients or ripple. A minimum REF/BYP capacitance of
100pF is recommended.
IN (Pin 5,6): Input. These pins supply power to the
device. The LT3050 requires a local IN bypass capacitor
if it is located more than six inches from the main input
filter capacitor. In general, battery output impedance rises
with frequency, so adding a bypass capacitor in battery
powered circuits is advisable. A minimum input of 1ꢁF
generally suffices.
OUT (Pin 7,8): Output. These pins supply power to the
load. Stability requirements demand a minimum 2.2μF
ceramic output capacitor to prevent oscillations. Large
loadtransientapplicationsrequirelargeroutputcapacitors
to limit peak voltage transients. See the Applications
Information section for details on transient response and
reverseoutputcharacteristics. Permissibleoutputvoltage
range is 600mV to 44.5V.
I
(Pin 2): Minimum Output Current Programming
MIN
Pin. This pin is the collector of a PNP current mirror that
outputs 1/200th of the power PNP load current. This pin
is also the input to the minimum output current fault
comparator. Connecting a resistorbetween I
sets the minimum output current fault threshold. For
and GND
MIN
ADJ(Pin9):Adjust.Thispinistheerroramplifier’sinverting
terminal. Its typical bias of 16nA current flows out of the
pin (see curve of ADJ Pin Bias Current vs. Temperature
in the Typical Performance Characteristics section). The
typical ADJ pin voltage is 600mV referenced to GND.
detailed information on how to set the I
value, please see the Operation section.
pin resistor
MIN
A small external decoupling capacitor (10nF minimum)
is required to improve I PSRR. If minimum output
MIN
current programming is not required, the I
be left floating (unconnected).
pin must
MIN
GND (PIN 10, Exposed Pad Pin 13): Ground. The exposed
pad of the DFN and MSOP packages is an electrical
connection to GND. To ensure proper electrical and
thermal performance, solder Pin 13 to the PCB ground
and tie directly to Pin 10. Connect the bottom of the output
voltage setting resistor divider directly to GND (Pin 10)
for optimum load regulation performance.
FAULT (Pin 3): Fault Pin. This is an open collector logic
pin which asserts during current limit, thermal limit or
a minimum current fault condition. The maximum low
logic output level is defined for sinking 100μA of current.
Off state logic may be as high as 45V without damaging
internal circuitry regardless of the V used.
IN
I
(Pin 11): Precision Current Limit Programming
MAX
SHDN(Pin4):Shutdown.PullingtheSHDNpinlowputsthe
LT3050intoalowpowerstateandturnstheoutputoff.Drive
the SHDN pin with either logic or an open collector/drain
with a pull-up resistor. The resistor supplies the pull-up
current to the open collector/drain logic, normally several
Pin. This pin is the collector of a current mirror PNP that
th
is 1/200 the size of the output power PNP. This pin is
also the input to the current limit amplifier. Current limit
threshold is set by connecting a resistor between the I
pin and GND.
MAX
3050f
10
LT3050
PIN FUNCTIONS
For detailed information on how to set the I pin resistor
value, please see the Operation section.
of the power PNP current. When OUT = I
current exactly equals 1/100 that of the output current.
For detailed information on how to calculate the output
, the pin
MIN
MON
th
The I
pin requires a 10nF decoupling capacitor to
MAX
currentfromtheI
pin,pleaseseetheOperationsection.
MON
ground. If not used, tie I
to GND.
MAX
The I
pin requires a small (22nF minimum) external
MON
I
(Pin 12): Output Current Monitor. This pin is the
decoupling capacitor. If the I
be tied to GND.
pin is not used, it must
MON
MON
th
collector of a PNP current mirror that outputs 1/100
BLOCK DIAGRAM
IN
5, 6
R1
D1
QI
QI
QI
MAX
1/200
MIN
MON
1/200
1/100
QPOWER
1
THERMAL/
CURRENT LIMITS
30k
R4
ADJ
–
+
9
OUT
7, 8
Q3
CURRENT
LIMIT
Q2
IDEAL DIODE
D3
100k
R3
AMPLIFIER
ERROR
AMPLIFIER
I
MAX
11
12
+
–
D2
I
MON
I
MIN
COMPARATOR
100k
R2
+
–
I
MIN
600mV
REFERENCE
SHDN
2
3
+
4
–
FAULT
U1
QFAULT
GND
10, 13
REF/BYP
1
3050 BD01
3050f
11
LT3050
OPERATION
I
Pin Operation (Current Monitor)
A small decoupling capacitor (22nF minimum) from I
MON
MON
to GND is required to improve I
pin power supply
MON
The I
pin is the collector of a PNP which mirrors the
MON
rejection. If the current monitor is not needed, it must be
tied to GND.
LT3050 output PNP at a ratio of 1:100 (see block diagram
on page 11). The current sourced by the I
pin is
MON
th
~1/100 of the current sourced by the OUT pin when the
Open Circuit Detection (I
Pin)
MIN
I
and OUT pin voltages are equal and the device is not
MON
The I
pin is the collector of a PNP which mirrors the
operating in dropout. If the I
and OUT pin voltages
MIN
MON
LT3050 output at a ratio of approximately 1:200 (see block
diagram on page 11). The I fault comparator asserts
are not the same, the ratio deviates from 1/100 due to
the Early voltages of the I
to the equation:
and OUT PNPs according
MIN
MON
the FAULT pin if the I
pin voltage is below 0.6V. This
MIN
low output current fault threshold voltage (I
) is set
OPEN
¥
´
I
70ꢁ V ꢂ V
1
by attaching a resistor from I
to GND.
IMON
IN
¦
IMON µ
MIN
ꢀ
v
IOUT IMONR
70ꢁ V ꢂ V
IN OUT
§
¶
119.85–(1.68 – 36.8 •IOPEN )• VOUT
IOPEN
144424443
RIMIN
=
Early Voltage Compensation
where the Early voltage of the PNPs is 70V and I
is
MONR
current ratio.
This equation is empirically derived and partially
compensates for early voltage effects in the I current
a variable which represents the I
to I
OUT
MON
I
varies with V to V
voltage according to the
MIN
MONR
IN
OUT
mirror. It is valid for an input voltage range from 0.6V
above the output to 10V above the output. It is valid for
output voltages up to 12V. The accuracy of this equation
for setting the resistor value is approximately 2ꢀ. Unit
values are Amps, Volts, and Ohms.
empirically derived equation:
= 97 + 5 • log (1+V – V ) for (V – V )
OUT
I
MONR
≥0.5
10
IN
OUT
IN
I
= 96 + 2 • (V – V ) for (V – V ) < 0.5
IN OUT IN OUT
MONR
The I
pin current can be converted into a voltage for
Iftheopencircuitdetectionfunctionisnotneeded,theI
MIN
MON
use by monitoring circuitry simply by connecting the I
pin to a resistor.
pinmustbeleftfloating(unconnected).Asmalldecoupling
capacitor (10nF minimum) from I to GND is required
MON
MIN
to improve I
pin power supply rejection and to prevent
MIN
Connecting a resistor from I
to GND converts the
MON
FAULT pin glitches.
I
pin current into a voltage that can be monitored by
MON
circuitry such as an ADC.
See the Typical Performance Characteristics section for
additional information.
For example, a 1.2k resistor results in a I
pin voltage
MON
of 1.2V for an output current of 100mA and an output
voltage of 1.2V.
The output current of the device can be calculated from
the I
pin voltage by the following equation:
MON
¥
´
V
70ꢁ V ꢂ VOUT
IMON
IN
IOUT ꢀ IMONR
v
v
¦
µ
{
OUT
RIMON
70ꢁ V ꢂ V
§
¶
IN
IMON
123
144424443
I
Ratio
I
Early VoltageCompensation
IMON
I
MON
3050f
12
LT3050
OPERATION
External Programmable Current Limit (I
requires a 10nF decoupling capacitor.
Pin)
MAX
See the Typical Performance Characteristics section for
additional information.
The I
pin is the collector of a PNP which mirrors the
MAX
LT3050outputataratioofapproximately1:200(seeBlock
Diagram). The I pin is also the input to the precision
MAX
FAULT Pin Operation
current limit amplifier. If the output load increases to the
point where it causes the I pin voltage to reach 0.6V,
thecurrentlimitamplifiertakescontrolofoutputregulation
so that the I pin clamps at 0.6V, regardless of the
output voltage. The current limit threshold (I
by attaching a resistor (R
MAX
The FAULT pin is an open collector logic pin which asserts
duringinternalcurrentlimit,precisioncurrentlimit,thermal
limit, or a minimum current fault. There is no internal
pull-up on the FAULT pin; an external pull-up resistor is
required. The FAULT pin provides drive for up to 100μA
of pull-down current. Off state logic may be as high as
45V, regardless of the input voltage used. When asserted,
the FAULT pin drive circuitry adds 50μA (nominal) of GND
pin current.
MAX
) is set
LIMIT
to GND:
) from I
IMAX
MAX
119.22− 0.894• VOUT
RIMAX
=
ILIMIT
This equation is empirically derived and partially
compensates for early voltage effects in the I current
mirror. It is valid for an input voltage range from 0.6V
above the output to 10V above the output. It is valid for
output voltages up to 12V. The accuracy of this equation
for setting the resistor value is approximately 1ꢀ. Unit
values are Amps, Volts, and Ohms.
MAX
Depending on the I
capacitance, BYP capacitance,
MIN
and OUT capacitance, the FAULT pin may assert during
startup. Consideration should be given to masking the
FAULT signal during startup. The FAULT pin circuitry is
inactive (not asserted) during shutdown and when the
OUT pin is pulled above the IN pin.
In cases where the IN to OUT voltage exceeds 10V, fold-
back current limit will lower the internal current level limit,
possibly causing it to preempt the external programmable
Operation in Dropout
The LT3050 contains circuitry which prevents the PNP
output power device from saturating in dropout. This also
current limit. See the Internal Current Limit vs V – V
IN
OUT
graph in the Typical Performance Characteristics section.
keepstheI
, I , andI
MON MIN
currentmirrorsfunctioning
MAX
accurately, even in dropout. However, this anti-saturation
circuitry becomes less active at lower output currents, so
there is some degradation of current mirror function for
output currents less than 10mA.
If the external programmable current limit is not needed,
the I
pin must be connected to GND. The I
pin
MAX
MAX
3050f
13
LT3050
APPLICATIONS INFORMATION
The LT3050 is a micropower, low noise and low dropout
voltage,100mAlinearregulatorwithmicropowershutdown,
programmablecurrentlimit,anddiagnosticfunctions.The
device supplies up to 100mA at a typical dropout voltage
of 340mV and operates over a 2.2V to 45V input range.
to ground. The current in R1 is then equal to 0.6V/R1, and
the current in R2 is the current in R1 minus the ADJ pin
bias current.
V
OUT
IN
OUT
LT3050
Asingleexternalcapacitorcanprovidelownoisereference
performance and output soft-start functionality. For
example,connectinga10nFcapacitorfromtheREF/BYPpin
V
IN
R2
R1
SHDN ADJ
GND
to GND lowers output noise to 30μV
over a 10Hz to
RMS
3050 F01
100kHz bandwidth. This capacitor also soft-starts the
reference and prevents output voltage overshoot at turn-on.
⎛
⎞
R2
R1
VOUT = 0.6V 1+
– I
(
•R2
ADJ
⎜
⎟
)
The LT3050’s quiescent current is merely 45μA but
provides fast transient response with a minimum low ESR
2.2μF ceramic output capacitor. In shutdown, quiescent
current is less than 1μA and the reference soft-start
capacitor is reset.
⎝
⎠
V
ADJ = 0.6V
ADJ = 16nA at 25°C
OUTPUT RANGE = 0.6V to 44.5V
I
The LT3050 optimizes stability and transient response
with low ESR, ceramic output capacitors. The regulator
does not require the addition of ESR as is common with
other regulators. The LT3050 typically provides 0.1ꢀ line
regulation and 0.1ꢀ load regulation. Internal protection
circuitry includes reverse-battery protection, reverse-
outputprotection,reverse-currentprotection,currentlimit
with fold-back and thermal shutdown.
Figure 1. Adjustable Operation
The ADJ pin bias current, 16nA at 25°C, flows from the
ADJ pin through R1 to GND. Calculate the output voltage
using the formula in Figure 1. The value of R1 should be
no greater than 124k to provide a minimum 5μA load
current so that output voltage errors, caused by the ADJ
pin bias current, are minimized. Note that in shutdown,
the output is turned off and the divider current is zero.
CurvesofADJPinVoltagevsTemperatureandADJPinBias
CurrentvsTemperatureappearintheTypicalPerformance
Characteristics Section.
This “bullet-proof” protection set makes it ideal for use in
battery-powered, automotive and industrial systems.
In battery backup applications where the output is held
up by a backup battery and the input is pulled to ground,
the LT3050 acts like it has a diode in series with its output
and prevents reverse current flow.
The LT3050 is tested and specified with the ADJ pin tied
to the OUT pin, yielding V
= 0.6V. Specifications for
OUT
output voltages greater than 0.6V are proportional to the
ratio of the desired output voltage to 0.6V: V /0.6V. For
OUT
Adjustable Operation
example, load regulation for an output current change
of 1mA to 100mA is –0.2mV (typical) at V
= 0.6V.
The LT3050 has an output voltage range of 0.6V to 44.5V.
The output voltage is set by the ratio of two external
resistors, as shown in Figure 1. The device servos the
output to maintain the ADJ pin voltage at 0.6V referenced
OUT
at V
= 12V, load regulation is:
OUT
12V
0.6V
• –0.2mV = – 4mV
(
)
3050f
14
LT3050
APPLICATIONS INFORMATION
Table1shows1ꢀresistordividervaluesforsomecommon
output voltages with a resistor divider current of 5ꢁA.
Output Capacitance and Transient Response
The LT3050 regulator is stable with a wide range of output
capacitors.TheESRoftheoutputcapacitoraffectsstability,
mostnotablywithsmallcapacitors.Useaminimumoutput
capacitor of 2.2μF to prevent oscillations. The LT3050 is a
micropower device and output load transient response is
a function of output capacitance. Larger values of output
capacitance decrease the peak deviations and provide
improved transient response for larger load current
changes. Bypass capacitors, used to decouple individual
componentspoweredbytheLT3050,increasetheeffective
output capacitor value. For applications with large load
current transients, a low ESR ceramic capacitor in parallel
with a bulk tantalum capacitor often provides an optimally
damped response.
Table 1. Output Voltage Resistor Divider Valves
V
(V)
R1 (kΩ)
118
R2 (kΩ)
118
OUT
1.2
1.5
1.8
2.5
3
121
182
124
249
115
365
124
499
3.3
5
124
562
115
845
Bypass Capacitance and Output Voltage Noise
The LT3050 regulator provides low output voltage noise
over the 10Hz to 100kHz bandwidth while operating at
full load with the addition of a bypass capacitor from the
REF/BYPpintoGND.Agoodquality,lowleakagecapacitor
isrecommended.Thiscapacitorbypassesthereferenceof
the regulator, providing a low frequency noise pole for the
internal reference. The noise pole provided by this bypass
capacitor decreases the output voltage noise to as low
Give extra consideration to the use of ceramic capacitors.
Manufacturers make ceramic capacitors with a variety of
dielectrics,eachwithdifferentbehavioracrosstemperature
and applied voltage. The most common dielectrics are
specified with EIA temperature characteristic codes of
Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics
provide high C-V products in a small package at low cost,
butexhibitstrongvoltageandtemperaturecoefficients, as
shown in Figures 2 and 3. When used with a 5V regulator,
a 16V 10μF Y5V capacitor can exhibit an effective value
as low as 1μF to 2μF for the DC bias voltage applied, and
over the operating temperature range. The X5R and X7R
dielectrics yield much more stable characteristics and are
more suitable for use as the output capacitor.
as 30μV
with the addition of a 10nF bypass capacitor
RMS
whentheoutputvoltageis0.6V.Forhigheroutputvoltages
(generated by using a resistor divider), the output voltage
noise increases proportionately.
Higher values of output voltage noise are often measured
if care is not exercised with regard to circuit layout and
testing. Crosstalk from nearby traces induces unwanted
noise onto the LT3050’s output. Power supply ripple
rejection must also be considered. The LT3050 regulator
doesnothaveunlimitedpowersupplyrejectionandpasses
a small portion of the input noise through to the output.
The X7R type works over a wider temperature range and
has better temperature stability, while the X5R is less
expensive and is available in higher values. Care still must
beexercisedwhenusingX5RandX7Rcapacitors;theX5R
and X7R codes only specify operating temperature range
and maximum capacitance change over temperature.
Capacitance change due to DC bias with X5R and X7R
capacitors is better than Y5V and Z5U capacitors, but can
still be significant enough to drop capacitor values below
appropriate levels. Capacitor DC bias characteristics tend
toimproveascomponentcasesizeincreases,butexpected
capacitance at operating voltage should be verified.
During start-up, the internal reference will soft-start the
reference if a bypass capacitor is present. Regulator start-
up time is directly proportional to the size of the bypass
capacitor, slowing to 5.5ms with a 10nF bypass capacitor
and 2.2μF output capacitor.
3050f
15
LT3050
APPLICATIONS INFORMATION
20
V
C
C
= 5V
OUT
OUT
BOTH CAPACITORS ARE 16V,
= 10ꢁF
1210 CASE SIZE, 10ꢁF
0
= 10nF
REF/BYP
X5R
V
–20
OUT
1mV/DIV
–40
–60
Y5V
3050 F04
–80
10ms/DIV
Figure 4. Noise Resulting from Tapping on a Ceramic Capacitor
–100
0
8
12 14
2
4
6
10
16
DC BIAS VOLTAGE (V)
3050 F02
Overload Recovery
Figure 2. Ceramic Capacitor DC Bias Characteristics
Like many IC power regulators, the LT3050 has safe
operating area protection. The safe area protection
decreases current limit as input-to-output voltage
increases, and keeps the power transistor inside a safe
operating region for all values of input-to-output voltage.
The LT3050 provides some output current at all values of
input-to-output voltage up to the device breakdown.
40
20
X5R
0
–20
–40
Whenpowerisfirstapplied, theinputvoltagerisesandthe
output follows the input; allowing the regulator to start-up
intoveryheavyloads. Duringstart-up, astheinputvoltage
is rising, the input-to-output voltage differential is small,
allowing the regulator to supply large output currents.
With a high input voltage, a problem can occur wherein
the removal of an output short will not allow the output
to recover. Other regulators, such as the LT1083/LT1084/
LT1085familyandLT1764Aalsoexhibitthisphenomenon,
so it is not unique to the LT3050. The problem occurs with
a heavy output load when the input voltage is high and the
outputvoltageislow.Commonsituationsare:immediately
after the removal of a short-circuit or if the shutdown pin
is pulled high after the input voltage is already turned on.
The load line for such a load intersects the output current
curve at two points. If this happens, there are two stable
output operating points for the regulator. With this double
intersection, the input power supply needs to be cycled
down to zero and brought up again to make the output
recover.
Y5V
–60
–80
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10ꢁF
–100
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
3050 F03
Figure 3. Ceramic Capacitor Temperature Characteristics
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltageacrossitsterminalsduetotechnicalstress,similar
to the way a piezoelectric accelerometer or microphone
works. For a ceramic capacitor, the stress is induced by
vibrationsinthesystemorthermaltransients.Theresulting
voltages produced cause appreciable amounts of noise.
A ceramic capacitor produced the trace in Figure 4 in
response to light tapping from a pencil. Similar vibration
induced behavior can masquerade as increased output
voltage noise.
3050f
16
LT3050
APPLICATIONS INFORMATION
Thermal Considerations
Table 1. MSOP Measured Thermal Resistance
COPPER AREA
The LT3050’s maximum rated junction temperature of
125°Climitsitspowerhandlingcapability.Twocomponents
comprise the power dissipated by the device:
THERMAL RESISTANCE
TOPSIDE
BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2500 sq mm 2500 sq mm 2500 sq mm
1000 sq mm 2500 sq mm 2500 sq mm
225 sq mm 2500 sq mm 2500 sq mm
100 sq mm 2500 sq mm 2500 sq mm
40°C/W
41°C/W
43°C/W
45°C/W
1. Output current multiplied by the input/output
voltage differential: I
• (V – V ), and
OUT
IN OUT
2. GND pin current multiplied by the input voltage:
• V
Table 2. DFN Measured Thermal Resistance
I
GND
IN
COPPER AREA
TOPSIDE
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
GND pin current is determined using the GND Pin Current
curvesintheTypicalPerformanceCharacteristicssection.
Power dissipation equals the sum of the two components
listed above.
BOARD AREA
2500 sq mm
2500 sq mm
2500 sq mm
2500 sq mm
2500 sq mm
1000 sq mm
225 sq mm
100 sq mm
44°C/W
45°C/W
47°C/W
49°C/W
The LT3050 regulator has internal thermal limiting that
protects the device during overload conditions. For
continuousnormalconditions,donotexceedthemaximum
junction temperature of 125°C. Carefully consider all
sources of thermal resistance from junction-to-ambient
including other heat sources mounted in proximity to the
LT3050.
Calculating Junction Temperature
Example: Given an output voltage of 5V, an input voltage
range of 12V 5ꢀ, a maximum output current range of
75mAandamaximumambienttemperatureof85°C, what
will the maximum junction temperature be?
The undersides of the LT3050 DFN and MSOP packages
have exposed metal from the lead frame to the die
attachment. Thesepackagesallowheattodirectlytransfer
from the die junction to the printed circuit board metal
to control maximum operating junction temperature.
The dual-in-line pin arrangement allows metal to extend
beyondtheendsofthepackageonthetopside(component
side) of a PCB. Connect this metal to GND on the PCB.
The multiple IN and OUT pins of the LT3050 also assist
in spreading heat to the PCB.
The power dissipated by the device equals:
I
* (V
– V ) + I
* V
OUT(MAX)
IN(MAX)
OUT
GND IN(MAX)
where,
I
= 75mA
= 12.6V
OUT(MAX)
V
IN(MAX)
I
at (I = 75mA, V = 12V) = 1.5mA
OUT IN
GND
So,
P = 75mA • (12.6V - 5V) + 1.5mA • 12.6V = 0.589W
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes also can spread the heat generated by
powerdevices.Thefollowingtableslistthermalresistance
as a function of copper area in a fixed board size. All
measurements were taken in still air on a four-layer FR-4
board with one ounce solid internal planes and two ounce
externaltraceplaneswithatotalboardthicknessof1.6mm.
For further information on thermal resistance and using
thermal information, refer to JEDEC standard JESD51,
notably JESD51-12.
Using a DFN package, the thermal resistance ranges from
44°C/W to 49°C/W depending on the copper area. So the
junction temperature rise above ambient approximately
equals:
0.589W • 49°C/W = 28.86°C
The maximum junction temperature equals the maximum
ambient temperature plus the maximum junction
temperature rise above ambient or:
T
= 85°C + 28.86°C = 113.86°C
JMAX
3050f
17
LT3050
APPLICATIONS INFORMATION
Protection Features
The LT3050 incurs no damage if its output is pulled below
ground. If the input is left open-circuit or grounded, the
output can be pulled below ground by 50V. No current
flows through the pass transistor from the output.
However, current flows in (but is limited by) the resistor
divider that sets the output voltage. Current flows from
the bottom resistor in the divider and from the ADJ pin’s
internal clamp through the top resistor in the divider to
the external circuitry pulling OUT below ground. If the
input is powered by a voltage source, the output sources
current equal to its current limit capability and the LT3050
protects itself by thermal limiting. In this case, grounding
the SHDN pin turns off the device and stops the output
from sourcing current.
The LT3050 incorporates several protection features
that make it ideal for use in battery-powered circuits. In
addition to the normal protection features associated with
monolithicregulators,suchascurrentlimitingandthermal
limiting, the device also protects against reverse-input
voltages, reverse-output voltages and reverse output-to-
input voltages.
Current limit protection and thermal overload protection
protect the device against current overload conditions at
the output of the device. For normal operation, do not
exceed a junction temperature of 125°C.
TheLT3050INpinwithstandsreversevoltagesof50V. The
devicelimitscurrentflowtolessthan300μA(typicallyless
than 10μA) and no negative voltage appears at OUT. The
device protects both itself and the load against batteries
that are plugged in backwards.
1.0
ALL PINS GROUNDED EXCEPT FOR OUT
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
The SHDN pin cannot be driven below GND unless tied
to the IN pin. If the SHDN pin is driven below GND while
IN is powered, the output may turn on. SHDN pin logic
cannot be referenced to a negative rail.
0
10
20
V
30
(V)
40
50
OUT
3050 F05
Figure 5. Reverse Output Current
3050f
18
LT3050
PACKAGE DESCRIPTION
DDB Package
12-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1723 Rev Ø)
0.64 0.05
(2 SIDES)
R = 0.115
TYP
7
0.40 0.10
12
3.00 0.10
(2 SIDES)
R = 0.05
TYP
0.70 0.05
2.55 0.05
1.15 0.05
2.00 0.10
PIN 1 BAR
(2 SIDES)
TOP MARK
PIN 1
R = 0.20 OR
0.25 s 45°
(SEE NOTE 6)
PACKAGE
OUTLINE
0.64 0.10
(2 SIDES)
CHAMFER
6
1
(DDB12) DFN 0106 REV Ø
0.25 0.05
0.23 0.05
0.75 0.05
0.200 REF
0.45 BSC
0.45 BSC
2.39 0.05
(2 SIDES)
2.39 0.10
(2 SIDES)
0 – 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAG
MSE Package
12-Lead Plastic MSOP Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev B)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 p 0.102
(.112 p .004)
2.845 p 0.102
(.112 p .004)
0.889 p 0.127
(.035 p .005)
1
6
0.35
REF
5.23
(.206)
MIN
1.651 p 0.102
(.065 p .004)
3.20 – 3.45
(.126 – .136)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
12
4.039 p 0.102
(.159 p .004)
(NOTE 3)
7
NO MEASUREMENT PURPOSE
0.65
(.0256)
BSC
0.42 p 0.038
(.0165 p .0015)
TYP
0.406 p 0.076
RECOMMENDED SOLDER PAD LAYOUT
(.016 p .003)
12 11 10 9 8 7
REF
DETAIL “A”
0.254
(.010)
3.00 p 0.102
(.118 p .004)
(NOTE 4)
0o – 6o TYP
4.90 p 0.152
(.193 p .006)
GAUGE PLANE
0.53 p 0.152
(.021 p .006)
1
2 3 4 5 6
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.1016 p 0.0508
(.004 p .002)
MSOP (MSE12) 0608 REV B
0.650
(.0256)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3050f
19
LT3050
TYPICAL APPLICATION
5V Protected Antenna Supply with 100mA Current Limit, 10mA IMIN
IN
OUT
5V
2.2ꢁF
1ꢀ
12V
IN
1ꢁF
SHDN
FAULT
120k
442k
V
ADJ
1ꢀ
60.4k
LT3050
I
MAX
1.15k
I
10nF
TO ꢁP ADC
0.1ꢁF
MON
(THRESHOLD = 100mA)
3k
(ADC FULL SCALE = 3V)
I
MIN
REF/BYP
GND
11.3k
0.1ꢁF
10nF
(THRESHOLD = 10mA)
3050 TA02
RELATED PARTS
PART
DESCRIPTION
COMMENTS
300mV Dropout Voltage, Low Noise: 20μV
NUMBER
LT1761
LT1762
LT1763
LT1962
LT1963/A
100mA, Low Noise LDO
150mA, Low Noise LDO
500mA, Low Noise LDO
300mA, Low Noise LDO
, V = 1.8V to 20V, ThinSOT Package
RMS IN
300mV Dropout Voltage, Low Noise: 20μV
300mV Dropout Voltage, Low Noise: 20μV
, V = 1.8V to 20V, MS8 Package
RMS IN
, V = 1.8V to 20V, SO-8 Package
RMS IN
270mV Dropout Voltage, Low Noise: 20μV
340mV Dropout Voltage, Low Noise: 40μV
, V = 1.8V to 20V, MS8 Package
RMS IN
1.5A Low Noise, Fast Transient
Response LDO
, V = 2.5V to 20V, “A” Version Stable with Ceramic
RMS IN
Capacitors, TO-220, DD-PAK, SOT-223 and SO-8 Packages
LT1965
LT3008
1.1A, Low Noise, Low Dropout Linear
Regulator
290mV Dropout Voltage, Low Noise: 40μV , V : 1.8V to 20V, V : 1.2V to 19.5V, Stable with
RMS IN
OUT
Ceramic Capacitors, TO-220, DD-PAK, MSOP and 3 × 3 DFN Packages
20mA, 45V, 3uA I Micropower LDO
300mV Dropout Voltage, Low I : 3μA, V = 2.0V to 45V, V = 0.6V to 39.5V; ThinSOT and
Q
Q
IN
OUT
2mm × 2mm DFN-6 Packages
LT3009
LT3010
20mA, 3uA I Micropower LDO
280mV Dropout Voltage, Low I : 3μA, V = 1.6V to 20V, ThinSOT and SC-70 Packages
Q
Q
IN
50mA, High Voltage, Micropower LDO
V : 3V to 80V, V : 1.275V to 60V, VDO = 0.3V, I = 30μA, ISD < 1μA, Low Noise: <100μV
,
IN
OUT
Q
RMS
Stable with 1μF Output Capacitor, Exposed MS8 Package
LT3011
LT3012
LT3013
50mA, High Voltage, Micropower LDO
with PWRGD
V : 3V to 80V, V : 1.275V to 60V, VDO = 0.3V, I = 46μA, ISD < 1μA, Low Noise: <100μV
,
IN
OUT
Q
RMS
Power Good, Stable with 1μF Output Capacitor, 3 × 3 DFN-10 and Exposed MS12E Packages
250mA, 4V to 80V, Low Dropout
Micropower Linear Regulator
V : 4V to 80V, V : 1.24V to 60V, VDO = 0.4V, I = 40μA, ISD < 1μA, TSSOP-16E and
IN
OUT
Q
4mm × 3mm DFN-12 Packages
250mA, 4V to 80V, Low Dropout
Micropower Linear Regulator with PWRGD TSSOP-16E and 4mm × 3mm DFN-12 Packages
V : 4V to 80V, V : 1.24V to 60V, VDO = 0.4V, I = 65μA, ISD < 1μA, Power Good feature;
IN
OUT
Q
LT3014/HV 20mA, 3V to 80V, Low Dropout
Micropower Linear Regulator
V : 3V to 80V (100V for 2ms, “HV” version), V : 1.22V to 60V, VDO = 0.35V, I = 7μA, ISD <
IN OUT Q
1μA, ThinSOT and 3mm × 3mm DFN-8 Packages
LT3060
100mA, Low Noise LDO with Soft Start
300mV Dropout Voltage, Low Noise: 20μV , V = 1.8V to 45V, DFN Package
RMS IN
LT3080/-1 1.1A, Parallelable, Low Noise, Low
Dropout Linear Regulator
300mV Dropout Voltage (2-supply operation), Low Noise: 40μV
, V : 1.2V to 36V, V : 0V
RMS IN OUT
to 35.7V, Current-Based Reference with 1-Resistor V
set; Directly Parallelable (no op amp
OUT
required), Stable with Ceramic Caps, TO-220, SOT-223, MSOP and 3mm × 3mm DFN Packages;
“–1” Version has Integrated Internal Ballast Resistor
LT3085
500mA, Parallelable. Low Noise, Low
Dropout Linear Regulator
275mV Dropout Voltage (2-supply operation), Low Noise: 40ꢁV
, V : 1.2V to 36V, V : 0V
RMS IN OUT
to 35.7V, Current-Based Reference with 1-Resistor V
set; Directly Parallelable (no op amp
OUT
required), Stable with Ceramic Caps, MSOP-8 and 2mm × 3mm DFN Packages
3050f
LT 1209 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2009
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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