LT3070MPUFD#TR [Linear]
LT3070 - 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator; Package: QFN; Pins: 28; Temperature Range: -55°C to 125°C;
| 型号： | LT3070MPUFD#TR |
| 厂家： | 
Linear |
| 描述： | LT3070 - 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator; Package: QFN; Pins: 28; Temperature Range: -55°C to 125°C 稳压器 |
| 文件： | 总28页 (文件大小：504K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3070
5A, Low Noise,
Programmable Output,
85mV Dropout
Linear Regulator
FeAtures
Description
TheꢀLT®3070ꢀisꢀaꢀlowꢀvoltage,ꢀUltraFast™ꢀtransientꢀre-
sponseꢀlinearꢀregulator.ꢀTheꢀdeviceꢀsuppliesꢀupꢀtoꢀ5Aꢀofꢀ
outputꢀcurrentꢀwithꢀaꢀtypicalꢀdropoutꢀvoltageꢀofꢀ85mV.ꢀ
Aꢀ0.01µFꢀreferenceꢀbypassꢀcapacitorꢀdecreasesꢀoutputꢀ
n
ꢀ Output Current: 5A
n
Dropout Voltage: 85mV Typical
n
Digitally Programmable V : 0.8V to 1.8V
OUT
n
Digital Output Margining: 1ꢀ, ꢁꢀ or 5ꢀ
n
Low Output Noise: 25µV
(10Hz to 100kHz)
voltageꢀnoiseꢀtoꢀ25µV
.ꢀTheꢀLT3070’sꢀhighꢀbandwidthꢀ
RMS
RMS
n
n
n
n
Parallel Multiple Devices for 10A or More
permitsꢀtheꢀuseꢀofꢀlowꢀESRꢀceramicꢀcapacitors,ꢀsavingꢀ
bulkꢀcapacitanceꢀandꢀcost.ꢀTheꢀLT3070’sꢀfeaturesꢀmakeꢀ
itꢀidealꢀforꢀhighꢀperformanceꢀFPGAs,ꢀmicroprocessorsꢀorꢀ
sensitiveꢀcommunicationꢀsupplyꢀapplications.ꢀ
Precision Current Limit: 20ꢀ
ꢀ 1ꢁꢀAccuracyꢀOverꢀLine,ꢀLoadꢀandꢀTemperature
ꢀ StableꢀwithꢀLowꢀESRꢀCeramicꢀOutputꢀCapacitorsꢀ
(15µFꢀMinimum)
Outputꢀvoltageꢀisꢀdigitallyꢀselectableꢀinꢀ50mVꢀincrementsꢀ
overꢀaꢀ0.8Vꢀtoꢀ1.8Vꢀrange.ꢀAꢀmarginingꢀfunctionꢀallowsꢀ
theꢀuserꢀtoꢀadjustꢀsystemꢀoutputꢀvoltageꢀinꢀincrementsꢀofꢀ
1ꢁ,ꢀ 3ꢁꢀorꢀ 5ꢁ.ꢀTheꢀICꢀincorporatesꢀaꢀuniqueꢀtrackingꢀ
functionꢀtoꢀcontrolꢀaꢀbuckꢀregulatorꢀpoweringꢀtheꢀLT3070’sꢀ
input.ꢀThisꢀtrackingꢀfunctionꢀdrivesꢀtheꢀbuckꢀregulatorꢀtoꢀ
n
n
n
ꢀ HighꢀFrequencyꢀPSRR:ꢀ30dBꢀatꢀ1MHzꢀ
ꢀ EnableꢀFunctionꢀTurnsꢀOutputꢀOn/Off
ꢀ VIOCꢀPinꢀControlsꢀBuckꢀConverterꢀtoꢀMaintainꢀLowꢀ
PowerꢀDissipationꢀandꢀOptimizeꢀEfficiency
ꢀ PWRGD/UVLO/ThermalꢀShutdownꢀFlag
ꢀ CurrentꢀLimitꢀwithꢀFoldbackꢀProtection
ꢀ ThermalꢀShutdown
n
n
n
n
maintainꢀtheꢀLT3070’sꢀinputꢀvoltageꢀtoꢀV ꢀ+ꢀ300mV,ꢀ
minimizingꢀpowerꢀdissipation.ꢀ
OUT
ꢀ 28-Leadꢀ(4mmꢀ×ꢀ5mmꢀ×ꢀ0.75mm)ꢀQFNꢀPackage
InternalꢀprotectionꢀincludesꢀUVLO,ꢀreverse-currentꢀprotec-
tion,ꢀprecisionꢀcurrentꢀlimitingꢀwithꢀpowerꢀfoldbackꢀandꢀ
thermalꢀshutdown.ꢀTheꢀLT3070ꢀregulatorꢀisꢀavailableꢀinꢀaꢀ
thermallyꢀenhancedꢀ28-lead,ꢀ4mmꢀ×ꢀ5mmꢀQFNꢀpackage.
L,ꢀLT,ꢀLTC,ꢀLTM,ꢀLinearꢀTechnologyꢀandꢀtheꢀLinearꢀlogoꢀareꢀregisteredꢀtrademarksꢀandꢀ
UltraFastꢀandꢀVLDOꢀareꢀtrademarksꢀofꢀLinearꢀTechnologyꢀCorporation.ꢀAllꢀotherꢀtrademarksꢀareꢀ
theꢀpropertyꢀofꢀtheirꢀrespectiveꢀowners.ꢀPatentsꢀpending.
ApplicAtions
n
ꢀ FPGAꢀandꢀDSPꢀSupplies
n
ꢀ ASICꢀandꢀMicroprocessorꢀSupplies
n
ꢀ ServersꢀandꢀStorageꢀDevices
n
ꢀ PostꢀBuckꢀRegulationꢀandꢀSupplyꢀIsolation
typicAl ApplicAtion
Dropout Voltage
0.9V, 5A Regulator
150
V
IN
= V
OUT(NOMINAL)
50k
V
BIAS
2.2V TO 3.6V
PWRGD
2.2µF
120
90
60
30
0
BIAS
V
IN
1.2V
IN
EN
V
PWRGD
SENSE
330µF
V
0.9V
5A
OUT
V
= 1.8V
= 3.3V
OUT
LT3070
OUT
O0
V
BIAS
2.2µF*
4.7µF*
10µF*
V
O1
V
O2
V
BIAS
= 0.8V
= 2.5V
OUT
V
*X5R OR X7R CAPACITORS
MARGSEL
MARGTOL
VIOC
REF/BYP
GND
1nF
0.01µF
0
1
2
3
4
5
3070 TA01a
OUTPUT CURRENT (A)
3070 TA01b
3070fa
ꢀ
REF/BYPꢀOutput........................................... –0.3Vꢀtoꢀ4V
OutputꢀShort-CircuitꢀDuration……...................Indefinite
OperatingꢀJunctionꢀTemperatureꢀ(Noteꢀ2)
ꢀ LT3070E/LT3070Iꢀ............................. ꢀ–40°Cꢀtoꢀ125°C
ꢀ LT3070MPꢀ......................................... –55°Cꢀtoꢀ125°C
StorageꢀTemperatureꢀRangeꢀ.................. –65°Cꢀtoꢀ150°C
BIAS............................................................. –0.3Vꢀtoꢀ4V
LT3070
Absolute mAximum rAtings
pin conFigurAtion
(Note 1)
TOP VIEW
IN,ꢀOUTꢀ..................................................... –0.3Vꢀtoꢀ3.3V
28 27 26 25 24 23
V ,ꢀV ,ꢀV ꢀInputsꢀ.................................... –0.3Vꢀtoꢀ4V
O2 O1 O0
VIOC
PWRGD
REF/BYP
GND
IN
1
2
3
4
5
6
7
8
22
21
20
19
18
17
16
15
MARGTOL
MARGSEL
GND
MARGSEL,ꢀMARGTOLꢀInputꢀ........................ –0.3Vꢀtoꢀ4V
ENꢀInputꢀ....................................................... –0.3Vꢀtoꢀ4V
SENSEꢀInput................................................. –0.3Vꢀtoꢀ4V
VIOC,ꢀPWRGDꢀOutputsꢀ................................ –0.3Vꢀtoꢀ4V
SENSE
OUT
29
GND
IN
OUT
IN
OUT
IN
OUT
9
10 11 12 13 14
UFD PACKAGE
28-LEAD (4mm s 5mm) PLASTIC QFN
ꢀ
T
JMAX
ꢀ=ꢀ125°C,ꢀθ ꢀ=ꢀ30°C/WꢀTOꢀ35°C/Wꢀ
JA
EXPOSEDꢀPADꢀ(PINꢀ29)ꢀISꢀGND,ꢀMUSTꢀBEꢀSOLDEREDꢀTOꢀPCB
orDer inFormAtion
LEAD FREE FINISH
LT3070EUFD#PBF
LT3070IUFD#PBF
LT3070MPUFD#PBF
LEAD BASED FINISH
LT3070EUFD
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3070EUFD#TRPBF
LT3070IUFD#TRPBF
LT3070MPUFD#TRPBF
TAPE AND REEL
3070
–40°Cꢀtoꢀ125°C
–40°Cꢀtoꢀ125°C
–55°Cꢀtoꢀ125°C
TEMPERATURE RANGE
–40°Cꢀtoꢀ125°C
–40°Cꢀtoꢀ125°C
–55°Cꢀtoꢀ125°C
28-Leadꢀ(4mmꢀ×ꢀ5mm)ꢀPlasticꢀQFN
28-Leadꢀ(4mmꢀ×ꢀ5mm)ꢀPlasticꢀQFN
28-Leadꢀ(4mmꢀ×ꢀ5mm)ꢀPlasticꢀQFN
PACKAGE DESCRIPTION
3070
3070
PART MARKING*
3070
LT3070EUFD#TR
28-Leadꢀ(4mmꢀ×ꢀ5mm)ꢀPlasticꢀQFN
28-Leadꢀ(4mmꢀ×ꢀ5mm)ꢀPlasticꢀQFN
28-Leadꢀ(4mmꢀ×ꢀ5mm)ꢀPlasticꢀQFN
LT3070IUFD
LT3070IUFD#TR
3070
LT3070MPUFD
LT3070MPUFD#TR
3070
ConsultꢀLTCꢀMarketingꢀforꢀpartsꢀspecifiedꢀwithꢀwiderꢀoperatingꢀtemperatureꢀranges.ꢀ*Theꢀtemperatureꢀgradeꢀisꢀidentifiedꢀbyꢀaꢀlabelꢀonꢀtheꢀshippingꢀcontainer.
Forꢀmoreꢀinformationꢀonꢀleadꢀfreeꢀpartꢀmarking,ꢀgoꢀto:ꢀhttp://www.linear.com/leadfree/ꢀꢀ
Forꢀmoreꢀinformationꢀonꢀtapeꢀandꢀreelꢀspecifications,ꢀgoꢀto:ꢀhttp://www.linear.com/tapeandreel/
3070fa
ꢁ
LT3070
electricAl chArActeristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.ꢁV (Note 5), VBIAS = 2.5V unless
otherwise noted.
PARAMETER
CONDITIONS
MIN
0.95
2.2
TYP
MAX
3.0
UNITS
l
l
INꢀPinꢀVoltageꢀRange
BIASꢀPinꢀVoltageꢀRangeꢀ(Noteꢀ3)
RegulatedꢀOutputꢀVoltage
V ꢀ≥ꢀV ꢀ+ꢀ150mV,ꢀI =ꢀ5A
V
V
IN
OUT
OUT
3.6
l
l
l
l
l
l
l
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
ꢀ=ꢀ0.8V,ꢀ10mAꢀ≤ꢀI ꢀ≤ꢀ5A,ꢀ1.05Vꢀ≤ꢀV ꢀ≤ꢀ1.25Vꢀ
0.792ꢀ
0.891ꢀ
0.990ꢀ
1.089ꢀ
1.188ꢀ
1.485ꢀ
1.782
0.800ꢀ
0.900ꢀ
1.000ꢀ
1.100ꢀ
1.200ꢀ
1.500ꢀ
1.800
0.808ꢀ
0.909ꢀ
1.010ꢀ
1.111ꢀ
1.212ꢀ
1.515ꢀ
1.818
Vꢀ
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
ꢀ=ꢀ0.9V,ꢀ10mAꢀ≤ꢀI ꢀ≤ꢀ5A,ꢀ1.15Vꢀ≤ꢀV ꢀ≤ꢀ1.35Vꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
V
ꢀ=ꢀ1V,ꢀ10mAꢀ≤ꢀI ꢀ≤ꢀ5A,ꢀ1.25Vꢀ≤ꢀV ꢀ≤ꢀ1.45Vꢀ
IN
ꢀ=ꢀ1.1V,ꢀ10mAꢀ≤ꢀI ꢀ≤ꢀ5A,ꢀ1.35Vꢀ≤ꢀV ꢀ≤ꢀ1.55Vꢀ
IN
IN
IN
IN
ꢀ=ꢀ1.2V,ꢀ10mAꢀ≤ꢀI ꢀ≤ꢀ5A,ꢀ1.45Vꢀ≤ꢀV ꢀ≤ꢀ1.65V,ꢀV
ꢀ=ꢀ3.3Vꢀ
ꢀ=ꢀ3.3Vꢀ
ꢀ=ꢀ3.3V
BIAS
BIAS
BIAS
ꢀ=ꢀ1.5V,ꢀ10mAꢀ≤ꢀI ꢀ≤ꢀ5A,ꢀ1.75Vꢀ≤ꢀV ꢀ≤ꢀ1.95V,ꢀV
ꢀ=ꢀ1.8V,ꢀ10mAꢀ≤ꢀI ꢀ≤ꢀ5A,ꢀ2.05Vꢀ≤ꢀV ꢀ≤ꢀ2.25V,ꢀV
l
l
RegulatedꢀOutputꢀVoltageꢀMarginingꢀ MARGTOLꢀ=ꢀ0V,ꢀMARGSELꢀ=ꢀV
ꢀ
0.8ꢀ
–1.2
1ꢀ
–1
1.2ꢀ
–0.8
ꢁꢀ
ꢁ
BIAS
(Noteꢀ3)
MARGTOLꢀ=ꢀ0V,ꢀMARGSELꢀ=ꢀ0V,ꢀI ꢀ=ꢀ10mA
OUT
l
l
MARGTOLꢀ=ꢀFLOAT,ꢀMARGSELꢀ=ꢀV
ꢀ
2.7ꢀ
–3.3
3ꢀ
–3
3.3ꢀ
–2.7
ꢁꢀ
ꢁ
BIAS
MARGTOLꢀ=ꢀFLOAT,ꢀMARGSELꢀ=ꢀ0V,ꢀI ꢀ=ꢀ10mA
OUT
l
l
MARGTOLꢀ=ꢀV
MARGTOLꢀ=ꢀV
,ꢀMARGSEL=ꢀV
ꢀ
4.6ꢀ
–5.4
5ꢀ
–5
5.4ꢀ
–4.6
ꢁꢀ
ꢁ
BIAS
BIAS
BIAS
,ꢀMARGSELꢀ=ꢀ0V,ꢀI ꢀ=ꢀ10mA
OUT
l
l
LineꢀRegulationꢀtoꢀV
LineꢀRegulationꢀtoꢀV
LoadꢀRegulation,ꢀꢀ
1.0ꢀ
1.0
mVꢀ
mV
V
V
ꢀ=ꢀ0.8V,ꢀ∆V ꢀ=ꢀ1.05Vꢀtoꢀ2.7V,ꢀV
ꢀ=ꢀ3.3V,ꢀI ꢀ=ꢀ10mAꢀ
OUT
IN
OUT
OUT
IN
BIAS
BIAS
ꢀ=ꢀ1.8V,ꢀ∆V ꢀ=ꢀ2.05Vꢀtoꢀ2.7V,ꢀV
ꢀ=ꢀ3.3V,ꢀI ꢀ=ꢀ10mA
OUT
IN
l
l
2.0ꢀ
1.0
mVꢀ
mV
V
OUT
V
OUT
ꢀ=ꢀ0.8V,ꢀ∆V
ꢀ=ꢀ1.8V,ꢀ∆V
ꢀ=ꢀ2.2Vꢀtoꢀ3.6V,ꢀV ꢀ=ꢀ1.1V,ꢀI ꢀ=ꢀ10mAꢀꢀ
IN OUT
BIAS
BIAS
BIAS
ꢀ=ꢀ3.25Vꢀtoꢀ3.6V,ꢀV ꢀ=ꢀ2.1V,ꢀI ꢀ=ꢀ10mA
IN
OUT
V
V
V
V
V
ꢀ=ꢀ2.5V,ꢀV ꢀ=ꢀ1.05V,ꢀV ꢀ=ꢀ0.8V
–1.5
–2
–3.0ꢀ
–5.5
mVꢀ
mV
BIAS
BIAS
BIAS
BIAS
BIAS
IN
OUT
l
l
l
l
∆I ꢀ=ꢀ10mAꢀtoꢀ5A
OUT
ꢀ=ꢀ2.5V,ꢀV ꢀ=ꢀ1.25V,ꢀV ꢀ=ꢀ1.0V
–4.0ꢀ
–7.5
mVꢀ
mV
IN
OUT
ꢀ=ꢀ3.3V,ꢀV ꢀ=ꢀ1.45V,ꢀV ꢀ=ꢀ1.2V
–2
–4.0ꢀ
–7.5
mVꢀ
mV
IN
OUT
ꢀ=ꢀ3.3V,ꢀV ꢀ=ꢀ1.75V,ꢀV ꢀ=ꢀ1.5V
–2.5
–3
–5.0ꢀ
–9.0
mVꢀ
mV
IN
OUT
ꢀ=ꢀ3.3V,ꢀV ꢀ=ꢀ2.05V,ꢀV ꢀ=ꢀ1.8V
–7.0ꢀ
–13
mVꢀ
mV
IN
OUT
l
l
DropoutꢀVoltage,ꢀꢀ
I
I
ꢀ=ꢀ1A,ꢀV ꢀ=ꢀ1V
20
50
35
mV
OUT
OUT
V ꢀ=ꢀV
IN
ꢀ(Noteꢀ6)
OUT(NOMINAL)
ꢀ=ꢀ2.5A,ꢀV ꢀ=ꢀ1V
65ꢀ
85
mVꢀ
mV
OUT
OUT
l
I
ꢀ=ꢀ5A,ꢀV ꢀ=ꢀ1V
85
120ꢀ
150
mVꢀ
mV
OUT
OUT
l
l
l
SENSEꢀPinꢀCurrent
V ꢀ=ꢀ1.1V,ꢀV
BIAS
ꢀ=ꢀ0.8Vꢀ
SENSE
IN
35ꢀ
200
50ꢀ
300
65ꢀ
400
µAꢀ
µA
IN
V
ꢀ=ꢀ3.3V,ꢀV ꢀ=ꢀ2.1V,ꢀV
ꢀ=ꢀ1.8V
SENSE
l
l
GroundꢀPinꢀCurrent,ꢀꢀ
V ꢀ=ꢀ1.3V,ꢀV ꢀ=ꢀ1V
I
I
ꢀ=ꢀ10mAꢀ
OUT
ꢀ=ꢀ5A
OUT
0.65ꢀ
0.9
1.1ꢀ
1.35
1.8ꢀ
2.3
mAꢀ
mA
IN
OUT
3070fa
ꢂ
LT3070
electricAl chArActeristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.ꢁV (Note 5), VBIAS = 2.5V unless
otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
BIASꢀPinꢀCurrentꢀinꢀNapꢀModeꢀ
ENꢀ=ꢀLowꢀ(AfterꢀPORꢀCompleted)
120
200
320
µA
l
l
l
l
l
l
BIASꢀPinꢀCurrent,ꢀꢀ
I
I
I
I
I
I
ꢀ=ꢀ10mAꢀ
ꢀ=ꢀ100mAꢀ
ꢀ=ꢀ500mAꢀ
ꢀ=ꢀ1Aꢀ
0.75ꢀ
1.25ꢀ
2.0ꢀ
2.6ꢀ
3.5ꢀ
4.5
1.08ꢀ
1.8ꢀ
3.0ꢀ
3.8ꢀ
5.2ꢀ
6.9
1.5ꢀ
2.4ꢀ
4.0ꢀ
5.0ꢀ
7.0ꢀ
10.0
mAꢀ
mAꢀ
mAꢀ
mAꢀ
mAꢀ
mA
OUT
OUT
OUT
OUT
OUT
OUT
V ꢀ=ꢀ1.3V,ꢀV ꢀ=ꢀ1Vꢀ
IN
OUT
ꢀ=ꢀ2.5Aꢀ
ꢀ=ꢀ5A
l
l
l
CurrentꢀLimitꢀ(Noteꢀ5)
V ꢀ–ꢀV ꢀ<ꢀ0.3V,ꢀV
ꢀ=ꢀ3.3Vꢀ
ꢀ=ꢀ3.3Vꢀ
ꢀ=ꢀ3.3V
5.1ꢀ
3.2ꢀ
1.2
6.4ꢀ
4.5ꢀ
2.5
7.7ꢀ
5.8ꢀ
4.3
Aꢀ
Aꢀ
A
IN
OUT
BIAS
BIAS
BIAS
V ꢀ–ꢀV ꢀ=ꢀ1.0V,ꢀV
IN
OUT
V ꢀ–ꢀV ꢀ=ꢀ1.7V,ꢀV
IN
OUT
l
ReverseꢀOutputꢀCurrentꢀ(Noteꢀ8)
V ꢀ=ꢀ0V,ꢀV ꢀ=ꢀ1.8V
300
450
µA
IN
OUT
l
l
PWRGDꢀV ꢀThreshold
PercentageꢀofꢀV
PercentageꢀofꢀV
,ꢀV ꢀRisingꢀ
OUT(NOMINAL) OUT
OUT(NOMINAL) OUT
87ꢀ
82
90ꢀ
85
93ꢀ
88
ꢁꢀ
ꢁ
OUT
,ꢀV ꢀFalling
l
PWRGDꢀV
I
ꢀ=ꢀ200µAꢀ(FaultꢀCondition)
PWRGD
50
150
mV
OL
l
l
V
ꢀUndervoltageꢀLockoutꢀ
BIAS
V
V
ꢀRisingꢀ
BIAS
ꢀFalling
BIAS
1.1ꢀ
0.9
1.55ꢀ
1.4
2.1ꢀ
1.7
Vꢀ
V
l
V -V ꢀServoꢀVoltageꢀbyꢀVIOC
IN OUT
250
300
350
mV
l
l
VIOCꢀOutputꢀCurrent
V ꢀ=ꢀV
IN
ꢀ+ꢀ150mV,ꢀSourcingꢀOutꢀofꢀtheꢀPinꢀ
OUT(NOMINAL)
ꢀ+ꢀ450mV,ꢀSinkingꢀIntoꢀtheꢀPin
OUT(NOMINAL)
160ꢀ
170
235ꢀ
255
310ꢀ
340
µAꢀ
µA
IN
V ꢀ=ꢀV
l
l
l
V ꢀInputꢀThresholdꢀ(Logic-0ꢀState),ꢀ InputꢀFalling
O2 O1 O0
0.25
V
IL
V
,ꢀV ,ꢀV ,ꢀMARGSEL,ꢀMARGTOL
V ꢀInputꢀRangeꢀ(Logic-ZꢀState),ꢀ
0.75
V
ꢀ–ꢀ0.9
BIAS
V
IZ
V
,ꢀV ,ꢀV ,ꢀMARGSEL,ꢀMARGTOL
O2 O1 O0
V ꢀInputꢀThresholdꢀ(Logic-1ꢀState),ꢀ InputꢀRising
V
ꢀ–ꢀ0.25
BIAS
V
IH
V
,ꢀV ,ꢀV ,ꢀMARGSEL,ꢀMARGTOL
O2 O1 O0
InputꢀHysteresisꢀ(BothꢀThresholds),ꢀ
,ꢀV ,ꢀV ,ꢀMARGSEL,ꢀMARGTOL
60
25
25
mV
µA
µA
V
O2 O1 O0
l
l
InputꢀCurrentꢀHigh,ꢀꢀ
,ꢀV ,ꢀV ,ꢀMARGSEL,ꢀMARGTOLꢀ
V ꢀ=ꢀV
ꢀ=ꢀ2.5V,ꢀCurrentꢀFlowsꢀIntoꢀPin
40
40
IH
BIAS
V
O2 O1 O0
InputꢀCurrentꢀLow,ꢀꢀ
,ꢀV ,ꢀV ,ꢀMARGSEL,ꢀMARGTOLꢀ
V ꢀ=ꢀ0V,ꢀV
IL
ꢀ=ꢀ2.5V,ꢀCurrentꢀFlowsꢀOutꢀofꢀPin
BIAS
V
O2 O1 O0
l
l
ENꢀPinꢀThreshold
V
V
ꢀ=ꢀOffꢀtoꢀOnꢀ
OUT
ꢀ=ꢀOnꢀtoꢀOff
OUT
ꢀ
1.4
Vꢀ
V
0.9
l
l
ENꢀPinꢀLogicꢀHighꢀCurrent
ENꢀPinꢀLogicꢀLowꢀCurrent
V
V
ꢀ=ꢀV
ꢀ=ꢀ2.5V
BIAS
2.5
4.0
6.5
0.1
µA
µA
EN
EN
ꢀ=ꢀ0V
3070fa
ꢃ
LT3070
electricAl chArActeristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.ꢁV (Note 5), VBIAS = 2.5V unless
otherwise noted.
PARAMETER
ꢀRippleꢀRejection
CONDITIONS
=ꢀV ꢀ+ꢀ1.5V ,ꢀV
MIN
TYP
MAX
UNITS
V
V
ꢀ=0.5V ꢀ,ꢀf ꢀ=ꢀ120Hz,ꢀꢀ
P-P RIPPLE
75
dB
BIAS
BIASꢀ
OUT
AVG RIPPLE
V ꢀ–ꢀV ꢀ=ꢀ300mV,ꢀI ꢀ=ꢀ2.5A
IN
OUT
OUT
V ꢀRippleꢀRejectionꢀꢀ
V
IN
ꢀ=ꢀ2.5V,ꢀV
OUT
ꢀ=ꢀ50mV ,ꢀf ꢀ=ꢀ120Hz,ꢀꢀ
P-Pꢀ RIPPLE
OUT
66
10
25
dB
IN
BIAS
RIPPLE
(Notesꢀ3,ꢀ4,ꢀ5)
V ꢀ–ꢀV ꢀ=ꢀ300mV,ꢀI ꢀ=ꢀ2.5Aꢀ
ReferenceꢀVoltageꢀNoiseꢀꢀ
(REF/BYPꢀPin)
C
ꢀ=ꢀ10nF,ꢀBWꢀ=ꢀ10Hzꢀtoꢀ100kHz
µV
µV
REF/BYP
RMS
RMS
OutputꢀVoltageꢀNoise
V
OUT
ꢀ=ꢀ1V,ꢀI ꢀ=ꢀ5A,ꢀC
=ꢀ10nF,ꢀC =ꢀ15µF,ꢀꢀ
REF/BYPꢀ OUTꢀ
OUT
BWꢀ=ꢀ10Hzꢀtoꢀ100kHzꢀ
Note 5:ꢀTheꢀLT3070ꢀincorporatesꢀsafeꢀoperatingꢀareaꢀprotectionꢀcircuitry.ꢀ
Note 1:ꢀStressesꢀbeyondꢀthoseꢀlistedꢀunderꢀAbsoluteꢀMaximumꢀRatingsꢀ
mayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.ꢀExposureꢀtoꢀanyꢀAbsoluteꢀ
MaximumꢀRatingꢀconditionꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀdeviceꢀ
reliabilityꢀandꢀlifetime.
CurrentꢀlimitꢀdecreasesꢀasꢀtheꢀV -V ꢀvoltageꢀincreases.ꢀCurrentꢀlimitꢀ
IN OUT
foldbackꢀstartsꢀatꢀV ꢀ–ꢀV ꢀ>ꢀ500mV.ꢀSeeꢀtheꢀTypicalꢀPerformanceꢀ
IN
OUT
CharacteristicsꢀforꢀaꢀgraphꢀofꢀCurrentꢀLimitꢀvsꢀV ꢀ–ꢀV ꢀvoltage.ꢀTheꢀ
IN
OUT
currentꢀlimitꢀfoldbackꢀfeatureꢀisꢀindependentꢀofꢀtheꢀthermalꢀshutdownꢀ
circuity.
Note 2:ꢀTheꢀLT3070ꢀregulatorsꢀareꢀtestedꢀandꢀspecifiedꢀunderꢀpulseꢀloadꢀ
conditionsꢀsuchꢀthatꢀT ꢀ≅ꢀT .ꢀTheꢀLT3070Eꢀisꢀ100ꢁꢀtestedꢀatꢀT ꢀ=ꢀ25°C.ꢀ
J
A
A
Note 6:ꢀDropoutꢀvoltage,ꢀV ,ꢀisꢀtheꢀminimumꢀinputꢀtoꢀoutputꢀvoltageꢀ
Performanceꢀatꢀ–40°Cꢀandꢀ125°Cꢀisꢀassuredꢀbyꢀdesign,ꢀcharacterizationꢀ
andꢀcorrelationꢀwithꢀstatisticalꢀprocessꢀcontrols.ꢀTheꢀLT3070Iꢀisꢀ
guaranteedꢀoverꢀtheꢀ–40°Cꢀtoꢀ125°Cꢀoperatingꢀjunctionꢀtemperatureꢀrange.ꢀ
TheꢀLT3070MPꢀisꢀ100ꢁꢀtestedꢀandꢀguaranteedꢀoverꢀtheꢀ–55°Cꢀtoꢀ125°Cꢀ
operatingꢀjunctionꢀtemperatureꢀrange.ꢀ
DO
differentialꢀatꢀaꢀspecifiedꢀoutputꢀcurrent.ꢀInꢀdropout,ꢀtheꢀoutputꢀvoltageꢀ
equalsꢀV ꢀ–ꢀV .ꢀ
IN
DO
Note 7:ꢀGNDꢀpinꢀcurrentꢀisꢀtestedꢀwithꢀV ꢀ=ꢀV
ꢀ+ꢀ300mVꢀandꢀaꢀ
OUT(NOMINAL)
IN
currentꢀsourceꢀload.ꢀVIOCꢀisꢀaꢀbufferedꢀoutputꢀdeterminedꢀbyꢀtheꢀvalueꢀofꢀ
ꢀasꢀprogrammedꢀbyꢀtheꢀV -V ꢀpins.ꢀVIOC’sꢀoutputꢀisꢀindependentꢀofꢀ
V
OUT
Note ꢁ:ꢀToꢀmaintainꢀproperꢀperformanceꢀandꢀregulation,ꢀtheꢀBIASꢀsupplyꢀ
O2 O0
theꢀmarginingꢀfunction.
voltageꢀmustꢀbeꢀhigherꢀthanꢀtheꢀINꢀsupplyꢀvoltage.ꢀForꢀaꢀgivenꢀV ,ꢀtheꢀ
OUTꢀ
BIASꢀvoltageꢀmustꢀsatisfyꢀtheꢀfollowingꢀconditions:ꢀ2.2Vꢀ≤ꢀV
ꢀ≤ꢀ3.6Vꢀ
Note 8:ꢀReverseꢀoutputꢀcurrentꢀisꢀtestedꢀwithꢀtheꢀINꢀpinsꢀgroundedꢀandꢀtheꢀ
OUTꢀ+ꢀSENSEꢀpinsꢀforcedꢀtoꢀtheꢀratedꢀoutputꢀvoltage.ꢀThisꢀisꢀmeasuredꢀasꢀ
currentꢀintoꢀtheꢀOUTꢀ+ꢀSENSEꢀpins.
BIAS
andꢀV
ꢀ≥ꢀ(1.25ꢀ•ꢀV ꢀ+ꢀ1V).ꢀForꢀV ꢀ≤ꢀ0.95V,ꢀtheꢀminimumꢀBIASꢀ
BIAS
OUT OUT
voltageꢀisꢀlimitedꢀtoꢀ2.2V.
Note 4:ꢀOperatingꢀconditionsꢀareꢀlimitedꢀbyꢀmaximumꢀjunctionꢀ
Note 9:ꢀFrequencyꢀCompensation:ꢀTheꢀLT3070ꢀmustꢀbeꢀfrequencyꢀ
temperature.ꢀTheꢀregulatedꢀoutputꢀvoltageꢀspecificationꢀdoesꢀnotꢀapplyꢀ
forꢀallꢀpossibleꢀcombinationsꢀofꢀinputꢀvoltageꢀandꢀoutputꢀcurrent.ꢀWhenꢀ
operatingꢀatꢀmaximumꢀoutputꢀcurrent,ꢀlimitꢀtheꢀinputꢀvoltageꢀrangeꢀtoꢀ
V ꢀ<ꢀV ꢀ+ꢀ500mV.
compensatedꢀatꢀitsꢀOUTꢀpinsꢀwithꢀaꢀminimumꢀC ꢀofꢀ15µFꢀconfiguredꢀ
OUT
asꢀaꢀclusterꢀofꢀ(15×)ꢀ1µFꢀceramicꢀcapacitorsꢀorꢀasꢀaꢀgraduatedꢀclusterꢀ
ofꢀ10µF/4.7µF/2.2µFꢀceramicꢀcapacitorsꢀofꢀtheꢀsameꢀcaseꢀsize.ꢀLinearꢀ
TechnologyꢀonlyꢀrecommendsꢀX5RꢀorꢀX7Rꢀdielectricꢀcapacitors.ꢀ
IN
OUT
3070fa
ꢄ
LT3070
typicAl perFormAnce chArActeristics
Dropout Voltage vs IOUT
Dropout Voltage vs Temperature
Dropout Voltage vs Temperature
100
90
80
70
60
50
40
30
20
10
0
150
120
90
30
25
V
= V
V
I
= V
IN OUT(NOMINAL)
OUT
V
I
= V
OUT(NOMINAL)
OUT
IN
OUT(NOMINAL)
IN
T = 25°C
J
= 1A
= 2.5A
20
15
V
BIAS
= 1.8V
= 3.3V
OUT
V
60
30
0
10
5
V
V
= 0.8V
= 2.5V
OUT
BIAS
V
V
V
= 1.8V, V
= 0.8V, V
= 1.2V, V
= 3.3V
= 2.5V
= 3.3V
V
V
V
= 1.8V, V
= 0.8V, V
= 1.2V, V
= 3.3V
= 2.5V
= 3.3V
OUT
OUT
OUT
BIAS
BIAS
BIAS
OUT
OUT
OUT
BIAS
BIAS
BIAS
0
–75 –50 –25
0
25 50 75 100 125 150 175
0
1
2
3
4
5
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
OUTPUT CURRENT (A)
3070 G03
3070 G01
3070 G02
Output Voltage (0.8V)
vs Temperature
Dropout Voltage vs Temperature
Dropout Voltage vs VBIAS
200
180
160
140
120
100
80
0.808
0.806
0.804
0.802
0.800
0.798
0.796
0.794
0.792
150
120
90
I
= 5A
I
= 10mA
V
I
= V
OUT(NOMINAL)
OUT
OUT
J
LOAD
IN
T = 25°C
= 5A
60
30
0
60
40
V
V
V
= 1.8V, V
= 0.8V, V
= 1.2V, V
= 3.3V
= 2.5V
= 3.3V
OUT = 1.8V
OUT = 1.5V
OUT = 0.8V
OUT
OUT
OUT
BIAS
BIAS
BIAS
20
0
2.2
2.6 2.8 3.0
3.2 3.4 3.6
–75 –50 –25
0
25 50 75 100 125 150 175
2.4
–75 –50 –25
0
25 50 75 100 125 150 175
BIAS VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
3070 G05
3070 G06
3070 G04
Output Voltage (1V)
vs Temperature
Output Voltage (1.2V)
vs Temperature
Output Voltage (1.5V)
vs Temperature
1.010
1.008
1.006
1.004
1.002
1.000
0.998
0.996
0.994
0.992
0.990
1.212
1.208
1.515
1.510
I
= 10mA
I
= 10mA
I
= 10mA
LOAD
LOAD
LOAD
1.204
1.200
1.505
1.500
1.196
1.192
1.188
1.495
1.490
1.485
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3070 G07
3070 G08
3070 G09
3070fa
ꢅ
LT3070
typicAl perFormAnce chArActeristics
Output Voltage (1.8V)
vs Temperature
REF/BYP Pin Voltage
vs Temperature
GND Pin Current vs IOUT
606
604
1.818
1.814
1.810
1.806
1.802
1.798
1.794
1.790
1.786
1.782
3.0
2.5
I
= 10mA
V
= V
+ 300mV
C
= 0.01µF
REF/BYP
LOAD
IN
OUT
T = 25°C
J
602
600
2.0
1.5
598
596
594
1.0
0.5
0
V
V
V
= 1.8V, V
= 1.2V, V
= 0.8V, V
= 3.3V
= 3.3V
= 2.5V
OUT
OUT
OUT
BIAS
BIAS
BIAS
–75 –50 –25
0
25 50 75 100 125 150 175
0
1
2
3
4
5
–75 –50 –25
0
25 50
175
75 100 125 150
TEMPERATURE (°C)
OUTPUT CURRENT (A)
TEMPERATURE (°C)
3070 G10
3070 G12
3070 G11
BIAS Pin Undervoltage Lockout
Threshold
BIAS Pin Current in Nap Mode
BIAS Pin Current vs IOUT
400
350
300
250
200
150
100
50
10
9
8
7
6
5
4
3
2
1
0
2.5
2.0
1.5
V
J
= V
+ 300mV
OUT
V
V
= 2.5V
IN
BIAS
EN
T = 25°C
= 0V
V
RISING
BIAS
V
BIAS
= 1.8V
= 3.3V
OUT
V
V
V
= 0.8V
OUT
BIAS
V
BIAS
FALLING
= 2.5V
1.0
0.5
0
0
0
1
2
3
4
5
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
OUTPUT CURRENT (A)
TEMPERATURE (°C)
TEMPERATURE (°C)
3070 G14
3070 G15
3070 G13
EN Pin Thresholds
PWRGD Threshold Voltage
PWRGD VOL vs Temperature
100
80
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.00
0.95
0.90
0.85
0.80
V
= 2.5V
V
= 2.5V
BIAS
V
BIAS
V
OUT
= 2.5V
= 1V
BIAS
I
= 200µA
PWRGD
EN PIN RISING
60
V
RISING
OUT
EN PIN FALLING
40
20
0
V
FALLING
OUT
–75 –50 –25
0
25 50 75 100 125 150
–75 –50 –25
0
25 50 75 100 125 150 175
–50 –25
50
75 100 125 150 175
–75
0
25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3070 G50
3070 G16
3070 G17
3070fa
ꢆ
LT3070
typicAl perFormAnce chArActeristics
Logic Input Threshold Voltages
Logic Low to Hi-Z State Transitions
Logic Input Threshold Voltages
Logic Hi-Z to High State Transitions
EN Pin Logic High Current
0.8
0.7
0.6
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
3.0
2.9
2.8
SEE APPLICATIONS INFORMATION
FOR MORE DETAILS
V
= 3.3V
V
= V
= 2.5V
BIAS
BIAS
EN
LOGIC Hi-Z TO HIGH THRESHOLD IS
RELATIVE TO V VOLTAGE
BIAS
SEE APPLICATIONS INFORMATION
FOR MORE DETAILS
INPUT RISING
LOGIC LOW TO Hi-Z
INPUT RISING
LOGIC Hi-Z TO HIGH
INPUT FALLING
LOGIC Hi-Z TO LOW
0.5
0.4
0.3
2.7
2.6
2.5
INPUT FALLING
LOGIC HIGH TO Hi-Z
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
75 100 125 150 175
0
25 50
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3070 G18
3070 G16
3070 G19
Logic Pin Input Current,
High State
Logic Pin Input Current,
Low State
SENSE Pin Current
65
60
55
50
45
40
35
30
25
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
V
V
= 2.5V
= 0.8V
V
= V
= 2.5V
V
V
= 2.5V
= 0V
BIAS
OUT
LOGIC
BIAS
BIAS
LOGIC
CURRENT FLOWS INTO THE PIN
CURRENT FLOWS INTO SENSE
CURRENT FLOWS OUT OF THE PIN
0
0
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3070 G23
3070 G21
3070 G22
SENSE Pin Current
Current Limit vs Temperature
Current Limit vs VIN – VOUT
400
375
350
325
300
275
250
225
200
7.50
7.25
7.00
6.75
6.50
6.25
6.00
5.75
5.50
5.25
5.00
8
7
6
5
4
3
2
1
0
V
T
= 3.3V
V
V
= 3.3V
= 1.8V
V
IN
– V
= 300mV
OUT(NOMINAL)
BIAS
J
BIAS
OUT
= 25°C
CURRENT FLOWS INTO SENSE
V
V
V
= 1.8V
= 1.2V
= 0.8V
V
V
V
= 1.8V, V
= 1.2V, V
= 0.8V, V
= 3.3V
= 3.3V
= 2.5V
OUT
OUT
OUT
OUT
OUT
OUT
BIAS
BIAS
BIAS
1.00 1.25
0
0.25 0.50 0.75
1.50 1.75 2.00
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
IN-TO-OUT VOLTAGE DIFFERENTIAL (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
3070 G26
3070 G24
3070 G25
3070fa
ꢇ
LT3070
typicAl perFormAnce chArActeristics
BIAS Pin Ripple Rejection
IN Pin Ripple Rejection
IN Pin Ripple Rejection
100
90
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
V
V
= 1.3V
IN
= 1V
OUT
OUT
I
= 5A
80
C
OUT
= 10µF + 4.7µF + 2.2µF
70
60
50
40
30
20
10
0
C
C
= 117µF
= 16.9µF
C
C
= 117µF
= 16.9µF
OUT
OUT
OUT
OUT
V
V
V
I
= 1V
V
V
V
I
= 1V
OUT
IN
BIAS
OUT
OUT
V
V
V
= 2.5V + 500mV
= 2.7V + 500mV
= 3.3V + 500mV
= 1.3V + 50mV RIPPLE
= 1.3V + 50mV RIPPLE
IN P-P
BIAS
BIAS
BIAS
P-P
P-P
P-P
P-P
= 2.5V
= 1A
= 2.5V
= 5A
BIAS
OUT
10
100
1k
10k 100k
1M
10M
10
100
1k
10k 100k
1M
10M
10
100
1k
10k 100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
3070 G27
3070 G28
3070 G29
Minimum BIAS Voltage
vs Temperature
Minimum BIAS Voltage vs IOUT
Minimum BIAS Voltage vs VOUT
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
V
$V
= V
OUT
V
V
V
V
+ 300mV
OUT(NOMINAL)
IN
V
V
V
= 1.8V
= 1.2V
= 0.8V
I
= 5A
I
= 5A
OUT
OUT
OUT
OUT
OUT
J
= –1%, T = 25°C
J
T = 25°C
= 1.8V
OUT
= 1.5V
OUT
OUT
OUT
= 1.2V
= 0.8V TO 1V
1
2
4
–75 –50 –25
0
25 50 75 100 125 150 175
0
5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
3
TEMPERATURE (°C)
OUTPUT CURRENT (A)
OUTPUT VOLTAGE (V)
3070 G51
3070 G30
3070 G31
Load Regulation
Bias Voltage Line Regulation
Bias Voltage Line Regulation
400
300
800
700
600
500
400
300
200
100
0
0
–2
–4
V
V
V
I
= 3.25V TO 3.6V
V
V
V
I
= 2.2V TO 3.6V
BIAS
IN
OUT
OUT
BIAS
IN
OUT
OUT
= 2.1V
= 1.1V
= 1.8V
= 10mA
= 0.8V
= 10mA
200
100
0
–6
–8
V
V
= V
+ 300mV
OUT(NOMINAL)
–100
–200
–300
–400
IN
= 3.3V
BIAS
$I
= 100mA TO 5A
OUT
V
V
V
= 0.8V
= 1.2V
= 1.8V
OUT
OUT
OUT
–10
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3070 G32
3070 G34
3070 G33
3070fa
ꢈ
LT3070
typicAl perFormAnce chArActeristics
Output Voltage Start-Up Time
vs CREF/BYP
Input Voltage Line Regulation
Input Voltage Line Regulation
300
250
20
18
16
14
12
10
8
300
250
V
V
V
I
= 3.3V
V
I
= 2.5V TO 3.3V
BIAS
V
V
V
I
= 3.3V
BIAS
IN
OUT
BIAS
IN
OUT
= 2.05V TO 2.7V
= 1.8V
= 10mA
= 1.05V TO 2.7V
= 0.8V
OUT
C
= 10µF + 4.7µF + 2.2µF
OUT
= 10mA
T = 25°C
J
= 10mA
OUT
OUT
SEE APPLICATIONS
INFORMATION FOR
START-UP DETAILS
200
150
200
150
100
50
0
100
50
0
6
4
2
0
–75 –50 –25
0
25 50 75 100 125 150 175
0
0.1
0.3
0.4
0.5
–75 –50 –25
0
25 50 75 100 125 150 175
0.2
TEMPERATURE (°C)
TEMPERATURE (°C)
REF/BYP CAPACITANCE (µF)
3070 G36
3070 G37
3070 G35
RMS Output Noise
vs Output Current
Nap Mode Recovery Time vs IOUT
Output Noise Spectral Density
400
350
300
250
1.0
0.1
80
70
60
50
40
30
20
10
0
V
V
= 3.3V
OUT(NOM)
EN = LOW TO HIGH
BIAS
IN
V
V
OUT
C
C
= 2.5V
= 1V
V
V
C
= V
+ 300mV
OUT(NOMINAL)
BIAS
OUT
IN
= V
+ 300mV
= 3.3V
BIAS
OUT
I
= 5A
= 16.9µF
I
= 5A (SET BY A RESISTOR LOAD)
OUT
= 16.9µF
OUT
REF/BYP
T = 25°C
J
= 0.01µF
V
C
V
C
V
C
= 1.8V,
= 117µF
= 1.2V,
= 117µF
= 0.8V,
= 117µF
OUT
OUT
OUT
OUT
OUT
OUT
200
150
0.01
0.001
100
50
0
V
V
V
= 1.8V
= 1.2V
= 0.8V
OUT
OUT
OUT
1
2
4
0
5
3
0.01
0.1
1
10
10
100
1k
FREQUENCY (Hz)
10k
100k
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
3070 G38
3070 G39
3070 G40
Input Voltage Line Transient
Response
Output Noise (10Hz to 100kHz)
V
OUT
1mV/DIV
V
OUT
100µV/DIV
V
IN
50mV/DIV
3070 G42
3070 G41
V
V
I
= 1.3V
= 1V
20µs/DIV
V
I
= 1V
1ms/DIV
IN
OUT
OUT
OUT
OUT
= 5A
= 5A
C
= 16.9µF
OUT
C
= 16.9µF
OUT
3070fa
ꢀ0
LT3070
typicAl perFormAnce chArActeristics
Bias Voltage Line Transient
Response
VIOC Amplifier IN-to-OUT Servo
Voltage
VIOC Amplifier Output Current
vs Temperature
350
340
330
320
310
300
290
280
270
260
250
300
275
V
= 2.5V
BIAS
V
OUT
10mV/DIV
I
SOURCING
VIOC
250
225
I
SINKING
VIOC
V
BIAS
200mV/DIV
200
175
150
3070 G43
V
V
V
I
= 1.3V
20µs/DIV
IN
= 2.5V
= 1V
BIAS
OUT
OUT
= 5A
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
C
= 16.9µF
OUT
TEMPERATURE (°C)
TEMPERATURE (°C)
3070 G44
3070 G45
Transient Load Response
Transient Load Response
V
V
OUT
OUT
50mV/DIV
AC-COUPLED
50mV/DIV
AC-COUPLED
I
OUT
I
OUT
2A/DIV
∆I = 500mA
TO 5A
2A/DIV
∆I = 500mA
TO 5A
3070 G46
3070 G47
V
C
I
= 1V
20µs/DIV
= 10µF + 4.7µF + 2.2µF
/t = 100ns
V
C
I
= 1V
= 117µF
/t
20µs/DIV
= 100ns
OUT
OUT
OUT
OUT
t
t
OUT RISE FALL
OUT RISE FALL
Transient Load Response
Transient Load Response
V
V
OUT
OUT
50mV/DIV
50mV/DIV
AC-COUPLED
AC-COUPLED
I
I
OUT
OUT
2A/DIV
∆I = 500mA
TO 5A
2A/DIV
∆I = 500mA
TO 5A
3070 G48
3070 G49
V
C
= 1V
20µs/DIV
= 10µF + 4.7µF + 2.2µF
/t = 1µs
V
C
= 1V
20µs/DIV
= 1µs
OUT
OUT
OUT
OUT
= 117µF
I
t
I
t
/t
OUT RISE FALL
OUT RISE FALL
3070fa
ꢀꢀ
SENSE (Pin 19):ꢀKelvinꢀSenseꢀforꢀOUT
.ꢀTheꢀSENSEꢀpinꢀisꢀ
theꢀinvertingꢀinputꢀtoꢀtheꢀerrorꢀamplifier.ꢀOptimumꢀregulationꢀ
isꢀobtainedꢀwhenꢀtheꢀSENSEꢀpinꢀisꢀconnectedꢀtoꢀtheꢀOUTꢀ
pinsꢀofꢀtheꢀregulator.ꢀInꢀcriticalꢀapplications,ꢀtheꢀresistanceꢀ
LT3070
pin Functions
VIOC (Pin 1):ꢀVoltageꢀforꢀIn-to-OutꢀControl.ꢀTheꢀICꢀin-
IN (Pins 5, 6, 7, 8):ꢀInputꢀSupply.ꢀTheseꢀpinsꢀsupplyꢀ
corporatesꢀaꢀuniqueꢀtrackingꢀfunctionꢀtoꢀcontrolꢀaꢀbuckꢀ powerꢀtoꢀtheꢀhighꢀcurrentꢀpassꢀtransistor.ꢀTieꢀallꢀINꢀpinsꢀ
regulatorꢀpoweringꢀtheꢀLT3070’sꢀinput.ꢀTheꢀVIOCꢀpinꢀisꢀ togetherꢀforꢀproperꢀperformance.ꢀTheꢀLT3070ꢀrequiresꢀaꢀ
theꢀoutputꢀofꢀthisꢀtrackingꢀfunctionꢀthatꢀdrivesꢀtheꢀbuckꢀ bypassꢀcapacitorꢀatꢀINꢀtoꢀmaintainꢀstabilityꢀandꢀlowꢀinputꢀ
regulatorꢀtoꢀmaintainꢀtheꢀLT3070’sꢀinputꢀvoltageꢀatꢀV ꢀ+ꢀ impedanceꢀoverꢀfrequency.ꢀAꢀ47µFꢀinputꢀbypassꢀcapacitorꢀ
OUT
300mV.ꢀThisꢀfunctionꢀmaximizesꢀefficiencyꢀandꢀminimizesꢀ sufficesꢀforꢀmostꢀbatteryꢀandꢀpowerꢀplaneꢀimpedances.ꢀ
powerꢀdissipation.ꢀSeeꢀtheꢀApplicationsꢀInformationꢀsec-
Minimizingꢀinputꢀtraceꢀinductanceꢀoptimizesꢀperformance.ꢀ
tionꢀforꢀmoreꢀinformationꢀonꢀproperꢀcontrolꢀofꢀtheꢀbuckꢀ ApplicationsꢀthatꢀoperateꢀwithꢀlowꢀV -V ꢀdifferentialꢀ
IN OUT
regulator.
voltagesꢀandꢀthatꢀhaveꢀlarge,ꢀfastꢀloadꢀtransientsꢀmayꢀrequireꢀ
muchꢀhigherꢀinputꢀcapacitorꢀrequirementsꢀtoꢀpreventꢀtheꢀ
inputꢀsupplyꢀfromꢀdroopingꢀandꢀallowingꢀtheꢀregulatorꢀtoꢀ
enterꢀdropout.ꢀSeeꢀtheꢀApplicationsꢀInformationꢀsectionꢀ
forꢀmoreꢀinformationꢀonꢀinputꢀcapacitorꢀrequirements.ꢀ
PWRGD (Pin 2):ꢀPowerꢀGood.ꢀTheꢀPWRGDꢀpinꢀisꢀanꢀopen-
drainꢀNMOSꢀoutputꢀthatꢀactivelyꢀpullsꢀlowꢀifꢀanyꢀoneꢀofꢀ
theseꢀfaultꢀmodesꢀisꢀdetected:
•ꢀ V ꢀisꢀlessꢀthanꢀ90ꢁꢀofꢀV
ꢀonꢀtheꢀrisingꢀ
OUT(NOMINAL)
OUT
edgeꢀofꢀV
OUT (Pins 15, 16, 17, 18):ꢀOutput.ꢀTheseꢀpinsꢀsupplyꢀ
powerꢀtoꢀtheꢀload.ꢀTieꢀallꢀOUTꢀpinsꢀtogetherꢀforꢀproperꢀ
performance.ꢀAꢀminimumꢀoutputꢀcapacitanceꢀofꢀ15µFꢀisꢀ
requiredꢀforꢀstability.ꢀLTCꢀrecommendsꢀlowꢀESR,ꢀX5Rꢀorꢀ
X7Rꢀdielectricꢀceramicꢀcapacitorsꢀforꢀbestꢀperformance.ꢀ
Aꢀparallelꢀceramicꢀcapacitorꢀcombinationꢀofꢀ10µFꢀ+ꢀ4.7µFꢀ
+ꢀ2.2µFꢀorꢀ15ꢀ1µFꢀceramicꢀcapacitorsꢀinꢀparallelꢀprovideꢀ
excellentꢀstabilityꢀandꢀloadꢀtransientꢀresponse.ꢀLargeꢀloadꢀ
transientꢀapplicationsꢀrequireꢀlargerꢀoutputꢀcapacitorsꢀtoꢀ
limitꢀpeakꢀvoltageꢀtransients.ꢀSeeꢀtheꢀApplicationsꢀInfor-
mationꢀsectionꢀforꢀmoreꢀinformationꢀonꢀoutputꢀcapacitorꢀ
.
OUTꢀ
•ꢀ V ꢀdropsꢀbelowꢀ85ꢁꢀofꢀV
ꢀforꢀmoreꢀthanꢀ
OUT(NOMINAL)
OUT
25µs.
•ꢀ Junctionꢀtemperatureꢀtypicallyꢀexceedsꢀ145°C.
•ꢀ V ꢀisꢀlessꢀthanꢀitsꢀundervoltageꢀlockoutꢀthreshold.
BIAS
•ꢀ TheꢀOUT-to-INꢀreverse-currentꢀdetectorꢀactivates.
SeeꢀtheꢀApplicationsꢀInformationꢀsectionꢀforꢀmoreꢀinfor-
mationꢀonꢀPWRGDꢀfaultꢀmodes.
REF/BYP (Pin ꢁ):ꢀReferenceꢀFilter.ꢀTheꢀpinꢀisꢀtheꢀoutputꢀ requirements.ꢀ
ofꢀtheꢀbandgapꢀreferenceꢀandꢀhasꢀanꢀimpedanceꢀofꢀap-
proximatelyꢀ19kΩ.ꢀThisꢀpinꢀmustꢀnotꢀbeꢀexternallyꢀloaded.ꢀ
BypassingꢀtheꢀREF/BYPꢀpinꢀtoꢀGNDꢀwithꢀaꢀ10nFꢀcapacitorꢀ
decreasesꢀoutputꢀvoltageꢀnoiseꢀandꢀprovidesꢀaꢀsoft-startꢀ
functionꢀtoꢀtheꢀreference.ꢀLTCꢀrecommendsꢀtheꢀuseꢀofꢀaꢀ
highꢀquality,ꢀlowꢀleakageꢀcapacitor.ꢀSeeꢀtheꢀApplicationsꢀ
Informationꢀsectionꢀforꢀmoreꢀinformationꢀonꢀnoiseꢀandꢀ
outputꢀvoltageꢀmarginingꢀconsiderations.
(R )ꢀofꢀPCBꢀtracesꢀbetweenꢀtheꢀregulatorꢀandꢀtheꢀloadꢀcauseꢀ
P
smallꢀvoltageꢀdrops,ꢀcreatingꢀaꢀloadꢀregulationꢀerrorꢀatꢀtheꢀ
pointꢀofꢀload.ꢀConnectingꢀtheꢀSENSEꢀpinꢀatꢀtheꢀloadꢀinsteadꢀ
ofꢀdirectlyꢀtoꢀOUTꢀeliminatesꢀthisꢀvoltageꢀerror.ꢀFigureꢀ1ꢀ
GND (Pins 4, 9-14, 20, 26, 29):ꢀGround.ꢀTheꢀexposedꢀpadꢀ illustratesꢀthisꢀKelvin-Senseꢀconnectionꢀmethod.ꢀNoteꢀthatꢀ
(Pinꢀ29)ꢀofꢀtheꢀQFNꢀpackageꢀisꢀanꢀelectricalꢀconnectionꢀtoꢀ theꢀvoltageꢀdropꢀacrossꢀtheꢀexternalꢀPCBꢀtracesꢀaddsꢀtoꢀtheꢀ
GND.ꢀToꢀensureꢀproperꢀelectricalꢀandꢀthermalꢀperformance,ꢀ dropoutꢀvoltageꢀofꢀtheꢀregulator.ꢀTheꢀSENSEꢀpinꢀinputꢀbiasꢀ
solderꢀPinꢀ29ꢀtoꢀtheꢀPCBꢀgroundꢀandꢀtieꢀtoꢀallꢀGNDꢀpinsꢀ currentꢀdependsꢀonꢀtheꢀselectedꢀoutputꢀvoltage.ꢀSENSEꢀ
ofꢀtheꢀpackage.ꢀTheseꢀGNDꢀpinsꢀareꢀfusedꢀtoꢀtheꢀinternalꢀ pinꢀinputꢀcurrentꢀvariesꢀfromꢀ50µAꢀtypicallyꢀatꢀV ꢀ=ꢀ0.8Vꢀ
OUT
dieꢀattachꢀpaddleꢀandꢀtheꢀexposedꢀpadꢀtoꢀoptimizeꢀheatꢀ toꢀ300µAꢀtypicallyꢀatꢀV ꢀ=ꢀ1.8V.
OUT
sinkingꢀandꢀthermalꢀresistanceꢀcharacteristics.ꢀSeeꢀtheꢀAp-
plicationsꢀInformationꢀsectionꢀforꢀthermalꢀconsiderationsꢀ
andꢀcalculatingꢀjunctionꢀtemperature.ꢀ
3070fa
ꢀꢁ
ablesꢀnegativeꢀvoltageꢀmargining.ꢀTheꢀlogicꢀhighꢀ
thresholdꢀ
LT3070
pin Functions
V , V and V (Pins 2ꢁ, 24, 25):ꢀOutputꢀVoltageꢀSe-
+
O0 O1
O2
V
BIAS
lect.ꢀTheseꢀthree-stateꢀpinsꢀcombineꢀtoꢀselectꢀaꢀnominalꢀ
outputꢀvoltageꢀfromꢀ0.8Vꢀtoꢀ1.8Vꢀinꢀincrementsꢀofꢀ50mV.ꢀ
Outputꢀvoltageꢀisꢀlimitedꢀtoꢀ1.8Vꢀmaximumꢀbyꢀanꢀinternalꢀ
overrideꢀofꢀV ꢀwhenꢀV ꢀ=ꢀhigh.ꢀTheꢀinputꢀlogicꢀlowꢀ
BIAS
EN
IN
SENSE
OUT
R
P
LT3070
V
V
V
O2
O1
O0
PWRGD
O1
O2
+
thresholdꢀisꢀlessꢀthanꢀ250mVꢀreferencedꢀtoꢀGNDꢀandꢀtheꢀ
LOAD
V
IN
MARGSEL
MARGTOL
VIOC
logicꢀhighꢀthresholdꢀisꢀgreaterꢀthanꢀV
ꢀ–ꢀ250mV.ꢀTheꢀ
BIAS
rangeꢀbetweenꢀtheseꢀtwoꢀthresholdsꢀasꢀsetꢀbyꢀaꢀwindowꢀ
REF/BYP
GND
comparatorꢀdefinesꢀtheꢀlogicꢀHi-Zꢀstate.ꢀSeeꢀTableꢀ1ꢀinꢀtheꢀ
ApplicationsꢀInformationꢀsectionꢀthatꢀdefinesꢀtheꢀV ,ꢀV ꢀ
O2 O1
R
P
3070 F01
andꢀV ꢀsettingsꢀversusꢀV
.
O0
OUTꢀ
BIAS (Pin 27):ꢀBiasꢀSupply.ꢀThisꢀpinꢀsuppliesꢀcurrentꢀtoꢀ
theꢀinternalꢀcontrolꢀcircuitryꢀandꢀtheꢀoutputꢀstageꢀdrivingꢀ
theꢀpassꢀtransistor.ꢀTheꢀLT3070ꢀrequiresꢀaꢀminimumꢀ2.2µFꢀ
bypassꢀcapacitorꢀforꢀstabilityꢀandꢀproperꢀoperation.ꢀToꢀ
ensureꢀproperꢀoperation,ꢀtheꢀBIASꢀvoltageꢀmustꢀsatisfyꢀ
Figure 1. Kelvin Sense Connection
MARGSEL (Pin 21):ꢀMarginingꢀEnableꢀandꢀPolarityꢀSelec-
tion.ꢀThisꢀthree-stateꢀpinꢀdeterminesꢀbothꢀtheꢀpolarityꢀandꢀ
theꢀactiveꢀstateꢀofꢀtheꢀmarginingꢀfunction.ꢀTheꢀlogicꢀlowꢀ
thresholdꢀisꢀlessꢀthanꢀ250mVꢀreferencedꢀtoꢀGNDꢀandꢀen-
theꢀfollowingꢀconditions:ꢀ2.2Vꢀ≤ꢀV
ꢀ≤ꢀ3.6VꢀandꢀV
ꢀ≥ꢀ
BIAS
BIAS
(1.25ꢀ•ꢀV ꢀ+ꢀ1V).ꢀForꢀV ꢀ≤ꢀ0.95V,ꢀtheꢀminimumꢀBIASꢀ
OUT
OUT
voltageꢀisꢀlimitedꢀtoꢀ2.2V.
isꢀgreaterꢀthanꢀV ꢀ–ꢀ250mVꢀandꢀenablesꢀpositiveꢀvoltageꢀ
BIAS
EN (Pin 28):ꢀEnable.ꢀThisꢀpinꢀenables/disablesꢀtheꢀoutputꢀ
margining.ꢀTheꢀvoltageꢀrangeꢀbetweenꢀtheseꢀtwoꢀlogicꢀ
thresholdsꢀasꢀsetꢀbyꢀaꢀwindowꢀcomparatorꢀdefinesꢀtheꢀ
logicꢀHi-Zꢀstateꢀandꢀdisablesꢀtheꢀmarginingꢀfunction.ꢀ
deviceꢀonly.ꢀTheꢀinternalꢀreferenceꢀandꢀallꢀsupportꢀfunctionsꢀ
areꢀactiveꢀifꢀV
ꢀisꢀaboveꢀitsꢀUVLOꢀthreshold.ꢀPullingꢀ
BIAS
ENꢀlowꢀkeepsꢀtheꢀreferenceꢀcircuitꢀactive,ꢀbutꢀdisablesꢀ
theꢀoutputꢀpassꢀtransistorꢀandꢀputsꢀtheꢀLT3070ꢀintoꢀaꢀlowꢀ
powerꢀnapꢀmode.ꢀDriveꢀtheꢀENꢀpinꢀwithꢀeitherꢀaꢀdigitalꢀlogicꢀ
portꢀorꢀanꢀopen-collectorꢀNPNꢀorꢀanꢀopen-drainꢀNMOSꢀ
MARGTOL (Pin 22):ꢀ Marginingꢀ Tolerance.ꢀ Thisꢀ three-
stateꢀpinꢀselectsꢀtheꢀabsoluteꢀvalueꢀofꢀmarginingꢀ(1ꢁ,ꢀ
3ꢁꢀorꢀ5ꢁ)ꢀifꢀenabledꢀbyꢀtheꢀMARGSELꢀinput.ꢀTheꢀlogicꢀ
lowꢀthresholdꢀisꢀlessꢀthanꢀ250mVꢀreferencedꢀtoꢀGNDꢀandꢀ
terminatedꢀwithꢀaꢀpull-upꢀresistorꢀtoꢀV
.ꢀTheꢀpull-upꢀ
BIAS
enablesꢀeitherꢀ 1ꢁꢀchangeꢀinꢀV ꢀdependingꢀonꢀtheꢀstateꢀ
OUT
resistorꢀmustꢀbeꢀlessꢀthanꢀ35kꢀtoꢀmeetꢀtheꢀV ꢀconditionꢀ
IH
ofꢀtheꢀMARGSELꢀpin.ꢀTheꢀlogicꢀhighꢀthresholdꢀisꢀgreaterꢀ
ofꢀtheꢀENꢀpin.ꢀIfꢀunused,ꢀconnectꢀENꢀtoꢀBIAS.
thanꢀV
OUT
ꢀ–ꢀ250mVꢀandꢀenablesꢀeitherꢀ 5ꢁꢀchangeꢀinꢀ
BIAS
V
ꢀdependingꢀonꢀtheꢀstateꢀofꢀtheꢀMARGSELꢀpin.ꢀTheꢀ
voltageꢀrangeꢀbetweenꢀtheseꢀtwoꢀlogicꢀthresholdsꢀasꢀsetꢀ
byꢀaꢀwindowꢀcomparatorꢀdefinesꢀtheꢀlogicꢀHi-Zꢀstateꢀandꢀ
enablesꢀeitherꢀ 3ꢁꢀchangeꢀinꢀV ꢀdependingꢀonꢀtheꢀstateꢀ
OUT
ofꢀtheꢀMARGSELꢀpin.ꢀ
3070fa
ꢀꢂ
LT3070
block DiAgrAm
UVLO AND
BIAS
27
THERMAL
SHUTDOWN
IN
5-8
+
–
I
SENSE
REF/BYP
+
–
EAMP
BUF
OUT
15-18
LDO CORE
SENSE
19
2
PWRGD
DETECT
–
+
VIOC
GND
V
+ 300mV
1
OUT(NOM)
REF/BYP
600mV
V
3
REF
4,9-14,20,26,29
PROGRAM CONTROL
EN
28
V
V
V
O0
MARGSEL MARGTOL
22
O2
O1
25 24 23 21
3070 BD
LOGIC HIGH STATE
–
V
– 0.25V
BIAS
+
LOGIC Hi-Z STATE
V
BIAS
HIGH IF IN > V
HIGH IF IN < V
– 0.25V
– 0.9V
BIAS
V
– 0.9V
+
–
+
–
BIAS
100k
V
, V , VO0
O2 O1
BIAS
AND IN > 0.75V
TO LOGIC
MARGSEL OR
MARGTOL
0.75V
100k
HIGH IF IN < 0.25V
LOGIC LOW STATE
–
+
0.25V
3070fa
ꢀꢃ
LT3070
ApplicAtions inFormAtion
Introduction
Thisꢀ combinesꢀ theꢀ efficiencyꢀ ofꢀ aꢀ switchingꢀ regulatorꢀ
withꢀsuperiorꢀlinearꢀregulatorꢀresponse.ꢀItꢀalsoꢀpermitsꢀ
thermalꢀmanagementꢀofꢀtheꢀsystemꢀevenꢀwithꢀaꢀmaximumꢀ
5Aꢀoutputꢀload.ꢀ
Currentꢀ generationꢀ FPGAꢀ andꢀ ASICꢀ processorsꢀ placeꢀ
stringentꢀdemandsꢀonꢀtheꢀpowerꢀsuppliesꢀthatꢀpowerꢀtheꢀ
core,ꢀI/Oꢀandꢀtransceiverꢀchannels.ꢀTheseꢀmicroprocessorsꢀ
mayꢀcycleꢀloadꢀcurrentꢀfromꢀnearꢀzeroꢀtoꢀampsꢀinꢀtensꢀofꢀ LT3070ꢀinternalꢀprotectionꢀincludesꢀinputꢀundervoltageꢀ
nanoseconds.ꢀOutputꢀvoltageꢀspecifications,ꢀespeciallyꢀinꢀ lockoutꢀ(UVLO),ꢀreverse-currentꢀprotection,ꢀprecisionꢀcur-
theꢀ1Vꢀrange,ꢀrequireꢀtightꢀtolerancesꢀincludingꢀtransientꢀ rentꢀlimitingꢀwithꢀpowerꢀfoldbackꢀandꢀthermalꢀshutdown.ꢀ
responseꢀasꢀpartꢀofꢀtheꢀrequirement.ꢀSomeꢀASICꢀprocessorsꢀ TheꢀLT3070ꢀregulatorꢀisꢀavailableꢀinꢀaꢀthermallyꢀenhancedꢀ
requireꢀonlyꢀaꢀsingleꢀoutputꢀvoltageꢀfromꢀwhichꢀtheꢀcoreꢀ 28-lead,ꢀ4mmꢀ×ꢀ5mmꢀQFNꢀpackage.
andꢀI/Oꢀcircuitryꢀoperate.ꢀSomeꢀhighꢀperformanceꢀFPGAꢀ
TheꢀLT3070’sꢀarchitectureꢀdrivesꢀanꢀinternalꢀN-channelꢀ
processorsꢀrequireꢀseparateꢀpowerꢀsupplyꢀvoltagesꢀforꢀtheꢀ
powerꢀMOSFETꢀasꢀaꢀsourceꢀfollower.ꢀThisꢀconfigurationꢀ
processorꢀcore,ꢀtheꢀI/O,ꢀandꢀtheꢀtransceivers.ꢀOften,ꢀtheseꢀ
permitsꢀaꢀuserꢀtoꢀobtainꢀanꢀextremelyꢀlowꢀdropout,ꢀUltra-
supplyꢀvoltagesꢀmustꢀbeꢀlowꢀnoiseꢀandꢀhighꢀbandwidthꢀ
Fastꢀtransientꢀresponseꢀregulatorꢀwithꢀexcellentꢀhighꢀfre-
toꢀachieveꢀtheꢀlowestꢀbit-errorꢀrates.ꢀTheseꢀrequirementsꢀ
quencyꢀPSRRꢀperformance.ꢀTheꢀLT3070ꢀachievesꢀsuperiorꢀ
mandateꢀtheꢀneedꢀforꢀveryꢀaccurate,ꢀlowꢀnoise,ꢀhighꢀcur-
regulatorꢀbandwidthꢀandꢀtransientꢀloadꢀperformanceꢀbyꢀ
rent,ꢀveryꢀhighꢀspeedꢀregulatorꢀcircuitsꢀthatꢀoperateꢀatꢀlowꢀ
eliminatingꢀexpensiveꢀbulkꢀtantalumꢀorꢀelectrolyticꢀcapaci-
inputꢀandꢀoutputꢀvoltages.
torsꢀinꢀtheꢀmostꢀmodernꢀandꢀdemandingꢀmicroprocessorꢀ
TheꢀLT3070ꢀisꢀaꢀlowꢀvoltage,ꢀUltraFastꢀtransientꢀresponseꢀ applications.ꢀUsersꢀrealizeꢀsignificantꢀcostꢀsavingsꢀasꢀallꢀ
linearꢀregulator.ꢀTheꢀdeviceꢀsuppliesꢀupꢀtoꢀ5Aꢀofꢀoutputꢀ additionalꢀbulkꢀcapacitanceꢀisꢀremoved.ꢀTheꢀadditionalꢀ
currentꢀwithꢀaꢀtypicalꢀdropoutꢀvoltageꢀofꢀ85mV.ꢀAꢀ0.01µFꢀ savingsꢀofꢀinsertionꢀcost,ꢀpurchasing/inventoryꢀcostꢀandꢀ
referenceꢀbypassꢀcapacitorꢀdecreasesꢀoutputꢀvoltageꢀnoiseꢀ boardꢀspaceꢀareꢀreadilyꢀapparent.ꢀPrecisionꢀincrementalꢀ
toꢀ25µV
ꢀ(BWꢀ=ꢀ10Hzꢀtoꢀ100kHz).ꢀTheꢀLT3070’sꢀhighꢀ outputꢀvoltageꢀcontrolꢀaccommodatesꢀlegacyꢀandꢀfutureꢀ
RMS
bandwidthꢀprovidesꢀUltraFastꢀtransientꢀresponseꢀusingꢀlowꢀ microprocessorꢀpowerꢀsupplyꢀvoltages.ꢀ
ESRꢀceramicꢀoutputꢀcapacitorsꢀ(15µFꢀminimum),ꢀsavingꢀ
Outputꢀcapacitorꢀnetworksꢀsimplifyꢀtoꢀdirectꢀparallelꢀcom-
binationsꢀofꢀceramicꢀcapacitors.ꢀOften,ꢀtheꢀhighꢀfrequencyꢀ
ceramicꢀdecouplingꢀcapacitorsꢀrequiredꢀbyꢀtheseꢀvariousꢀ
bulkꢀcapacitance,ꢀPCBꢀareaꢀandꢀcost.ꢀ
TheꢀLT3070’sꢀfeaturesꢀpermitꢀstate-of-the-artꢀlinearꢀregula-
torꢀperformance.ꢀTheꢀLT3070ꢀisꢀidealꢀforꢀhighꢀperformanceꢀ FPGAꢀandꢀASICꢀprocessorsꢀareꢀsufficientꢀtoꢀstabilizeꢀtheꢀ
FPGAs,ꢀmicroprocessors,ꢀsensitiveꢀcommunicationꢀsup-
systemꢀ(seeꢀStabilityꢀandꢀOutputꢀCapacitanceꢀsection).ꢀThisꢀ
plies,ꢀandꢀhighꢀcurrentꢀlogicꢀapplicationsꢀthatꢀalsoꢀoperateꢀ regulatorꢀdesignꢀprovidesꢀampleꢀbandwidthꢀandꢀrespondsꢀ
overꢀlowꢀinputꢀandꢀoutputꢀvoltages.ꢀ
toꢀtransientꢀloadꢀchangesꢀinꢀaꢀfewꢀhundredꢀnanosecondsꢀ
versusꢀregulatorsꢀthatꢀrespondꢀinꢀmanyꢀmicroseconds.ꢀ
OutputꢀvoltageꢀforꢀtheꢀLT3070ꢀisꢀdigitallyꢀselectableꢀinꢀ
50mVꢀincrementsꢀoverꢀaꢀ0.8Vꢀtoꢀ1.8Vꢀrange.ꢀAꢀmarginingꢀ TheꢀLT3070ꢀalsoꢀincorporatesꢀprecisionꢀcurrentꢀlimiting,ꢀ
functionꢀallowsꢀtheꢀuserꢀtoꢀadjustꢀsystemꢀoutputꢀvoltageꢀ enable/disableꢀcontrolꢀofꢀoutputꢀvoltageꢀandꢀintegratedꢀ
inꢀincrementsꢀofꢀ 1ꢁ,ꢀ 3ꢁꢀorꢀ 5ꢁ.ꢀ
overvoltageꢀ andꢀ thermalꢀ shutdownꢀ protection.ꢀ Theꢀ
LT3070’sꢀ uniqueꢀ designꢀ combinesꢀ theꢀ benefitsꢀ ofꢀ lowꢀ
dropoutꢀ voltage,ꢀ highꢀ functionalꢀ integration,ꢀ precisionꢀ
performanceꢀandꢀUltraFastꢀtransientꢀresponse,ꢀasꢀwellꢀasꢀ
providingꢀsignificantꢀcostꢀsavingsꢀonꢀtheꢀoutputꢀcapacitanceꢀ
neededꢀinꢀfastꢀloadꢀtransientꢀapplications.ꢀ
TheꢀICꢀincorporatesꢀaꢀuniqueꢀtrackingꢀfunction,ꢀwhichꢀifꢀ
enabledꢀbyꢀtheꢀuser,ꢀcontrolsꢀanꢀupsteamꢀregulatorꢀpower-
ingꢀtheꢀLT3070’sꢀinputꢀ(seeꢀFigureꢀ8).ꢀThisꢀtrackingꢀfunctionꢀ
drivesꢀtheꢀbuckꢀregulatorꢀtoꢀmaintainꢀtheꢀLT3070’sꢀinputꢀ
voltageꢀtoꢀV ꢀ+ꢀ300mV.ꢀThisꢀinput-to-outputꢀvoltageꢀ
OUT
controlꢀallowsꢀtheꢀuserꢀtoꢀchangeꢀtheꢀregulatorꢀoutputꢀ Asꢀlowerꢀvoltageꢀapplicationsꢀbecomeꢀincreasinglyꢀpreva-
voltage,ꢀandꢀhaveꢀtheꢀswitchingꢀregulatorꢀpoweringꢀtheꢀ lentꢀwithꢀhigherꢀfrequencyꢀswitchingꢀpowerꢀsupplies,ꢀtheꢀ
LT3070’sꢀinputꢀtoꢀtrackꢀtoꢀtheꢀoptimumꢀinputꢀvoltageꢀwithꢀ LT3070ꢀ offersꢀ superiorꢀ regulationꢀ andꢀ anꢀ appreciableꢀ
noꢀcomponentꢀchanges.
3070fa
ꢀꢄ
tiveꢀstateꢀofꢀtheꢀmarginingꢀfunction.ꢀTheꢀlogicꢀlowꢀthresholdꢀ
LT3070
ApplicAtions inFormAtion
componentꢀcostꢀsavings.ꢀTheꢀLT3070ꢀstepsꢀtoꢀtheꢀnextꢀ REF/BYP—Voltage Reference
levelꢀofꢀperformanceꢀforꢀtheꢀlatestꢀgenerationꢀFPGAs,ꢀDSPsꢀ
Thisꢀpinꢀisꢀtheꢀbufferedꢀoutputꢀofꢀtheꢀinternalꢀbandgapꢀ
andꢀmicroprocessors.ꢀTheꢀsimpleꢀversatilityꢀandꢀbenefitsꢀ
derivedꢀfromꢀtheseꢀcircuitsꢀexceedꢀtheꢀpowerꢀsupplyꢀneedsꢀ
ofꢀtoday’sꢀhighꢀperformanceꢀmicroprocessors.
referenceꢀandꢀhasꢀanꢀoutputꢀimpedanceꢀofꢀ≅19kΩ.ꢀTheꢀ
designꢀincludesꢀanꢀinternalꢀcompensationꢀpoleꢀatꢀf ꢀ=ꢀ4kHz.ꢀ
C
Aꢀ10nFꢀREF/BYPꢀcapacitorꢀtoꢀGNDꢀcreatesꢀaꢀlowpassꢀpoleꢀ
atꢀf ꢀ=ꢀ840Hz.ꢀTheꢀ10nFꢀcapacitorꢀdecreasesꢀreferenceꢀ
LP
Programming Output Voltage
voltageꢀnoiseꢀtoꢀaboutꢀ10µV
ꢀandꢀsoft-startsꢀtheꢀrefer-
RMS
Threeꢀtri-levelꢀinputꢀpins,ꢀV ,ꢀV ꢀandꢀV ,ꢀselectꢀtheꢀ
ence.ꢀTheꢀLT3070ꢀonlyꢀsoft-startsꢀtheꢀreferenceꢀvoltageꢀ
duringꢀanꢀinitialꢀturn-onꢀsequence.ꢀIfꢀtheꢀENꢀpinꢀisꢀtoggledꢀ
lowꢀafterꢀinitialꢀturn-on,ꢀtheꢀreferenceꢀremainsꢀpowered-up.ꢀ
Therefore,ꢀtogglingꢀtheꢀENꢀpinꢀfromꢀlowꢀtoꢀhighꢀdoesꢀnotꢀ
soft-startꢀtheꢀreference.ꢀOnlyꢀbyꢀturningꢀtheꢀBIASꢀsupplyꢀ
voltageꢀonꢀandꢀoffꢀwillꢀtheꢀreferenceꢀbeꢀsoft-started.ꢀOutputꢀ
voltageꢀnoiseꢀisꢀtheꢀRMSꢀsumꢀofꢀtheꢀreferenceꢀvoltageꢀ
noiseꢀinꢀadditionꢀtoꢀtheꢀamplifierꢀnoise.ꢀ
O2 O1
O0
valueꢀofꢀoutputꢀvoltage.ꢀTableꢀ1ꢀillustratesꢀtheꢀ3-bitꢀdigitalꢀ
wordꢀtoꢀoutputꢀvoltageꢀresultingꢀfromꢀsettingꢀtheseꢀpinsꢀ
high,ꢀlowꢀorꢀallowingꢀthemꢀtoꢀfloat.ꢀ
Theseꢀpinsꢀmayꢀbeꢀtiedꢀhighꢀorꢀlowꢀbyꢀeitherꢀpin-strappingꢀ
themꢀtoꢀV ꢀorꢀdrivingꢀthemꢀwithꢀdigitalꢀports.ꢀPinsꢀthatꢀ
BIAS
floatꢀmayꢀeitherꢀactuallyꢀfloatꢀorꢀrequireꢀlogicꢀthatꢀhasꢀ
Hi-Zꢀoutputꢀcapability.ꢀThisꢀallowsꢀoutputꢀvoltageꢀtoꢀbeꢀ
dynamicallyꢀchangedꢀifꢀnecessary.
TheꢀREF/BYPꢀpinꢀmustꢀnotꢀbeꢀDCꢀloadedꢀbyꢀanythingꢀexceptꢀ
forꢀapplicationsꢀthatꢀparallelꢀotherꢀLT3070ꢀregulatorsꢀforꢀ
higherꢀoutputꢀcurrents.ꢀConsultꢀtheꢀApplicationsꢀSectionꢀ
onꢀParallelingꢀforꢀfurtherꢀdetails.ꢀ
Outputꢀvoltageꢀisꢀselectableꢀfromꢀaꢀminimumꢀofꢀ0.8Vꢀtoꢀ
aꢀmaximumꢀofꢀ1.8Vꢀinꢀincrementsꢀofꢀ50mV.ꢀTheꢀMSB,ꢀ
V ,ꢀsetsꢀtheꢀpedestalꢀvoltage,ꢀandꢀtheꢀLSB’s,ꢀV andꢀ
O2
O1ꢀ
V ꢀincrementꢀV .ꢀ
O0
OUTꢀ
Output Voltage Margining
Outputꢀvoltageꢀisꢀlimitedꢀtoꢀ1.8Vꢀmaximumꢀbyꢀanꢀinternalꢀ
overrideꢀofꢀV ꢀ(defaultꢀtoꢀlow)ꢀwhenꢀV ꢀ=ꢀhigh.ꢀ
Twoꢀtri-levelꢀinputꢀpins,ꢀMARGSELꢀ(polarity)ꢀandꢀMARGTOLꢀ
(scale),ꢀselectꢀtheꢀpolarityꢀandꢀamountꢀofꢀoutputꢀvoltageꢀ
margining.ꢀMarginingꢀisꢀprogrammableꢀinꢀincrementsꢀofꢀ
1ꢁ,ꢀ 3ꢁꢀandꢀ 5ꢁ.ꢀMarginingꢀisꢀinternallyꢀimplementedꢀ
asꢀaꢀscalingꢀofꢀtheꢀreferenceꢀvoltage.ꢀ
O1
O2
Table 1: VO2 to VO0 Settings vs Output Voltage
V
V
V
V
V
V
V
V
OUT(NOM)
O2
O1
O0
OUT(NOM)
O2
O1
O0
0
0
0
0
0
0
0
0
0
Z
Z
0
0
0
Z
Z
Z
1
1
1
0
0
0
Z
1
0
Z
1
0
Z
1
0
Z
0.80V
Z
Z
Z
Z
Z
Z
Z
1
1
1
0
Z
Z
Z
1
1
1
X
X
X
1
0
Z
1
0
Z
1
0
Z
1
1.35V
0.85V
0.90V
0.95V
1.00V
1.05V
1.10V
1.15V
1.20V
1.25V
1.30V
1.40V
1.45V
1.50V
1.55V
1.60V
1.65V
1.70V
1.75V
1.80V
Tableꢀ2ꢀillustratesꢀtheꢀ2-bitꢀdigitalꢀwordꢀtoꢀoutputꢀvoltageꢀ
marginingꢀresultingꢀfromꢀsettingꢀtheseꢀpinsꢀhigh,ꢀlowꢀorꢀ
allowingꢀthemꢀtoꢀfloat.ꢀ
Theseꢀpinsꢀmayꢀbeꢀsetꢀhighꢀorꢀlowꢀbyꢀeitherꢀpin-strappingꢀ
themꢀtoꢀV
ꢀorꢀdrivingꢀthemꢀwithꢀdigitalꢀports.ꢀPinsꢀthatꢀ
BIAS
floatꢀmayꢀeitherꢀactuallyꢀfloatꢀorꢀrequireꢀlogicꢀthatꢀhasꢀ
“Hi-Z”ꢀoutputꢀcapability.ꢀThisꢀallowsꢀoutputꢀvoltageꢀtoꢀbeꢀ
dynamicallyꢀmarginedꢀifꢀnecessary.
TheꢀMARGSELꢀpinꢀdeterminesꢀbothꢀtheꢀpolarityꢀandꢀtheꢀac-
Xꢀ=ꢀDon’tꢀCare,ꢀ0ꢀ=ꢀLow,ꢀZꢀ=ꢀFloat,ꢀ1ꢀ=ꢀHigh
isꢀlessꢀthanꢀ250mVꢀreferencedꢀtoꢀGNDꢀandꢀenablesꢀnegativeꢀ
Theꢀinputꢀlogicꢀlowꢀthresholdꢀisꢀlessꢀthanꢀ250mVꢀrefer-
encedꢀtoꢀGNDꢀandꢀtheꢀlogicꢀhighꢀthresholdꢀisꢀgreaterꢀthanꢀ
voltageꢀmargining.ꢀTheꢀlogicꢀhighꢀthresholdꢀisꢀgreaterꢀthanꢀ
V
ꢀ–ꢀ250mVꢀandꢀenablesꢀpositiveꢀvoltageꢀmargining.ꢀ
BIAS
V
–ꢀ250mV.ꢀTheꢀrangeꢀbetweenꢀtheseꢀtwoꢀthresholdsꢀ
Theꢀvoltageꢀrangeꢀbetweenꢀtheseꢀtwoꢀlogicꢀthresholdsꢀasꢀ
setꢀbyꢀaꢀwindowꢀcomparatorꢀdefinesꢀtheꢀlogicꢀHi-Zꢀstateꢀ
andꢀdisablesꢀtheꢀmarginingꢀfunction.
3070fa
BIASꢀ
asꢀsetꢀbyꢀaꢀwindowꢀcomparatorꢀdefinesꢀtheꢀlogicꢀHi-Zꢀ
state.
ꢀꢅ
LT3070
ApplicAtions inFormAtion
TheꢀMARGTOLꢀpinꢀselectsꢀtheꢀabsoluteꢀvalueꢀofꢀmargin-
ingꢀ(1ꢁ,ꢀ3ꢁꢀorꢀ5ꢁ)ꢀifꢀenabledꢀbyꢀtheꢀMARGSELꢀinput.ꢀ edgeꢀofꢀV
typicalꢀBIASꢀpinꢀUVLOꢀthresholdꢀisꢀ1.55Vꢀonꢀtheꢀrisingꢀ
.ꢀTheꢀUVLOꢀcircuitꢀincorporatesꢀaboutꢀ150mVꢀ
BIAS
Theꢀlogicꢀlowꢀthresholdꢀisꢀlessꢀthanꢀ250mVꢀreferencedꢀtoꢀ ofꢀhysteresisꢀonꢀtheꢀfallingꢀedgeꢀofꢀV
.ꢀ
BIAS
GNDꢀandꢀenablesꢀeitherꢀ 1ꢁꢀchangeꢀinꢀV ꢀdependingꢀ
OUT
High Efficiency Linear Regulator—Input-to-Output
Voltage Control
onꢀtheꢀstateꢀofꢀtheꢀMARGSELꢀpin.ꢀTheꢀlogicꢀhighꢀthresholdꢀ
isꢀgreaterꢀthanꢀV
ꢀ–ꢀ250mVꢀandꢀenablesꢀeitherꢀ 5ꢁꢀ
BIAS
changeꢀinꢀV ꢀdependingꢀonꢀtheꢀstateꢀofꢀtheꢀMARGSELꢀ
OUT
TheꢀVIOCꢀ(voltageꢀinput-to-outputꢀcontrol)ꢀpinꢀisꢀaꢀfunctionꢀ
toꢀcontrolꢀaꢀswitchingꢀregulatorꢀandꢀfacilitateꢀaꢀdesignꢀsolu-
tionꢀthatꢀmaximizesꢀsystemꢀefficiencyꢀatꢀhighꢀloadꢀcurrentsꢀ
andꢀstillꢀprovidesꢀlowꢀdropoutꢀvoltageꢀperformance.
pin.ꢀTheꢀvoltageꢀrangeꢀbetweenꢀtheseꢀtwoꢀlogicꢀthresholdsꢀ
asꢀsetꢀbyꢀaꢀwindowꢀcomparatorꢀdefinesꢀtheꢀlogicꢀHi-Zꢀstateꢀ
andꢀenablesꢀeitherꢀ 3ꢁꢀchangeꢀinꢀV ꢀdependingꢀonꢀtheꢀ
OUT
stateꢀofꢀtheꢀMARGSELꢀpin.
TheꢀVIOCꢀpinꢀisꢀtheꢀoutputꢀofꢀanꢀintegratedꢀtranscon-
ductanceꢀamplifierꢀthatꢀsourcesꢀandꢀsinksꢀaboutꢀ250µAꢀ
ofꢀcurrent.ꢀItꢀtypicallyꢀregulatesꢀtheꢀoutputꢀofꢀmostꢀLTC®ꢀ
switchingꢀregulatorsꢀorꢀLTM®ꢀpowerꢀmodules,ꢀbyꢀsinkingꢀ
currentꢀfromꢀtheꢀITHꢀcompensationꢀnode.ꢀTheꢀVIOCꢀfunctionꢀ
controlsꢀaꢀbuckꢀregulatorꢀpoweringꢀtheꢀLT3070’sꢀinputꢀbyꢀ
Table 2: Programming Margining
MARGSEL
MARGTOL
ꢀ OF V
OUT(NOM)
0
0
0
Z
Z
Z
1
1
1
0
Z
1
0
Z
1
0
Z
1
–1
–3
–5
0
maintainingꢀtheꢀLT3070’sꢀinputꢀvoltageꢀtoꢀV ꢀ+ꢀ300mV.ꢀ
OUT
0
Thisꢀ300mVꢀV -V ꢀdifferentialꢀvoltageꢀisꢀchosenꢀtoꢀ
IN OUT
0
provideꢀfastꢀtransientꢀresponseꢀandꢀgoodꢀhighꢀfrequencyꢀ
PSRRꢀwhileꢀminimizingꢀpowerꢀdissipationꢀandꢀmaximizingꢀ
efficiency.ꢀForꢀexample,ꢀ1.5Vꢀtoꢀ1.2Vꢀconversionꢀandꢀ1.3Vꢀ
toꢀ1Vꢀconversionꢀyieldꢀ1.5Wꢀmaximumꢀpowerꢀdissipationꢀ
atꢀ5Aꢀfullꢀoutputꢀcurrent.
1
3
5
Enable Function—Turning On and Off
Figureꢀ2ꢀdepictsꢀthatꢀtheꢀswitcher’sꢀfeedbackꢀresistorꢀnet-
workꢀsetsꢀtheꢀmaximumꢀswitchingꢀregulatorꢀoutputꢀvoltageꢀ
ifꢀtheꢀlinearꢀregulatorꢀisꢀdisabled.ꢀHowever,ꢀonceꢀtheꢀLT3070ꢀ
isꢀenabled,ꢀtheꢀVIOCꢀfeedbackꢀloopꢀdecreasesꢀtheꢀswitchingꢀ
TheꢀENꢀpinꢀenables/disablesꢀtheꢀoutputꢀdeviceꢀonly.ꢀTheꢀ
LT3070ꢀreferenceꢀandꢀallꢀsupportꢀfunctionsꢀremainꢀactiveꢀ
ifꢀV
ꢀisꢀaboveꢀitsꢀUVLOꢀthreshold.ꢀPullingꢀtheꢀENꢀpinꢀ
BIAS
lowꢀputsꢀtheꢀLT3070ꢀintoꢀnapꢀmode.ꢀInꢀnapꢀmode,ꢀtheꢀ
referenceꢀcircuitꢀisꢀactive,ꢀbutꢀtheꢀoutputꢀisꢀdisabledꢀandꢀ
quiescentꢀcurrentꢀdecreases.
regulatorꢀoutputꢀvoltageꢀbackꢀtoꢀV ꢀ+ꢀ300mV.
OUT
UsingꢀtheꢀVIOCꢀfunctionꢀcreatesꢀaꢀfeedbackꢀloopꢀbetweenꢀ
theꢀLT3070ꢀandꢀtheꢀswitchingꢀregulator.ꢀAsꢀsuch,ꢀtheꢀfeed-
backꢀloopꢀmustꢀbeꢀfrequencyꢀcompensatedꢀforꢀstability.ꢀ
Fortunately,ꢀtheꢀconnectionꢀofꢀVIOCꢀtoꢀmanyꢀLTCꢀswitchingꢀ
regulatorꢀITHꢀpinsꢀrepresentsꢀaꢀhighꢀimpedanceꢀcharac-
teristicꢀwhichꢀisꢀtheꢀoptimumꢀcircuitꢀnodeꢀtoꢀfrequencyꢀ
compensateꢀtheꢀfeedbackꢀloop.ꢀFigureꢀ2ꢀillustratesꢀtheꢀ
typicalꢀfrequencyꢀcompensationꢀnetworkꢀusedꢀatꢀtheꢀVIOCꢀ
nodeꢀtoꢀGND.
DriveꢀtheꢀENꢀpinꢀwithꢀeitherꢀaꢀdigitalꢀlogicꢀportꢀorꢀanꢀopen-
collectorꢀNPNꢀorꢀanꢀopen-drainꢀNMOSꢀterminatedꢀwithꢀ
aꢀpull-upꢀresistorꢀtoꢀV
.ꢀTheꢀpull-upꢀresistorꢀmustꢀbeꢀ
IH
BIAS
lessꢀthanꢀ35kꢀtoꢀmeetꢀtheꢀV ꢀconditionꢀofꢀtheꢀENꢀpin.ꢀIfꢀ
unused,ꢀconnectꢀENꢀtoꢀBIAS.
Input Undervoltage Lockout on BIAS Pin
Anꢀ internalꢀ undervoltageꢀ lockoutꢀ (UVLO)ꢀ comparatorꢀ
TheꢀVIOCꢀamplifierꢀcharacteristicsꢀare:
monitorsꢀtheꢀBIASꢀsupplyꢀvoltage.ꢀIfꢀV
ꢀdropsꢀbelowꢀ
BIAS
ꢀ g ꢀ=ꢀ3.2mS,ꢀI
=ꢀ 250µA,ꢀBWꢀ=ꢀ10MHz.
OUTꢀ
theꢀUVLOꢀthreshold,ꢀallꢀfunctionsꢀshutꢀdown,ꢀtheꢀpassꢀ
m
transistorꢀisꢀgatedꢀoffꢀandꢀoutputꢀcurrentꢀfallsꢀtoꢀzero.ꢀTheꢀ
IfꢀtheꢀVIOCꢀfunctionꢀisꢀnotꢀused,ꢀterminateꢀtheꢀVIOCꢀpinꢀtoꢀGNDꢀ
withꢀaꢀsmallꢀcapacitorꢀ(1000pF)ꢀtoꢀpreventꢀoscillations.
3070fa
ꢀꢆ
LT3070
ApplicAtions inFormAtion
LT3070
IN
OUT
LOAD
SWITCHING REGULATOR
REF
+
–
–
+
PWM
FB
VIOC
V
+
OUT
V
300mV
REF
REFERENCE
I
TH
3070 F02
Figure 2. VIOC Control Block Diagram
PWRGD—Power Good
LowꢀESR,ꢀX5RꢀorꢀX7Rꢀceramicꢀchipꢀcapacitorsꢀareꢀtheꢀ
LTCꢀrecommendedꢀchoiceꢀforꢀstabilizingꢀtheꢀLT3070.ꢀAd-
ditionalꢀbulkꢀcapacitorsꢀdistributedꢀbeyondꢀtheꢀimmediateꢀ
decouplingꢀcapacitorsꢀareꢀacceptableꢀasꢀtheirꢀparasiticꢀESLꢀ
andꢀESR,ꢀcombinedꢀwithꢀtheꢀdistributedꢀPCBꢀinductanceꢀ
isolatesꢀthemꢀfromꢀtheꢀprimaryꢀcompensationꢀpoleꢀprovidedꢀ
byꢀtheꢀlocalꢀsurfaceꢀmountꢀceramicꢀcapacitors.ꢀ
PWRGDꢀpinꢀisꢀanꢀopen-drainꢀNMOSꢀdigitalꢀoutputꢀthatꢀ
activelyꢀpullsꢀlowꢀifꢀanyꢀoneꢀofꢀtheseꢀfaultꢀmodesꢀisꢀde-
tected:
•ꢀ V ꢀisꢀlessꢀthanꢀ90ꢁꢀofꢀV
ꢀonꢀtheꢀrisingꢀ
OUT
edgeꢀofꢀV
OUT(NOMINAL)
.
OUTꢀ
•ꢀ V ꢀdropsꢀbelowꢀ85ꢁꢀofꢀV
ꢀforꢀmoreꢀthanꢀ
TheꢀLT3070ꢀrequiresꢀaꢀminimumꢀoutputꢀcapacitanceꢀofꢀ
15µFꢀforꢀstability.ꢀLTCꢀstronglyꢀrecommendsꢀthatꢀtheꢀoutputꢀ
capacitorꢀnetworkꢀconsistꢀofꢀseveralꢀlowꢀvalueꢀceramicꢀ
capacitorsꢀinꢀparallel.ꢀ
OUT
25µs.
OUT(NOMINAL)
•ꢀ V ꢀisꢀlessꢀthanꢀitsꢀundervoltageꢀlockoutꢀthreshold.
BIAS
•ꢀ TheꢀOUT-to-INꢀreverse-currentꢀdetectorꢀactivates.
•ꢀ Junctionꢀtemperatureꢀexceedsꢀ145°Cꢀtypically.*
Why Do Multiple, Small-Value Output Capacitors
Connected in Parallel Work Better?
ꢀ *Theꢀjunctionꢀtemperatureꢀdetectorꢀisꢀanꢀearlyꢀwarningꢀ
indicatorꢀthatꢀtripsꢀapproximatelyꢀ20°Cꢀbeforeꢀthermalꢀ
shutdownꢀengages.ꢀ
TheꢀLT3070’sꢀunity-gainꢀbandwidthꢀwithꢀC ꢀofꢀ15µFꢀisꢀ
OUT
aboutꢀ1MHzꢀatꢀitsꢀfull-loadꢀcurrentꢀofꢀ5A.ꢀSurfaceꢀmountedꢀ
MLCCꢀ capacitorsꢀ haveꢀ aꢀ self-resonanceꢀ frequencyꢀ ofꢀ
f ꢀ=ꢀ1/(2π√LC),ꢀwhichꢀmustꢀbeꢀpushedꢀtoꢀaꢀfrequencyꢀhigherꢀ
Stability and Output Capacitance
R
thanꢀtheꢀregulatorꢀbandwidth.ꢀStandardꢀMLCCꢀcapacitorsꢀ
areꢀacceptable.ꢀToꢀkeepꢀtheꢀresonantꢀfrequencyꢀgreaterꢀ
thanꢀ1MHz,ꢀtheꢀproductꢀ1/(2π√LC)ꢀmustꢀbeꢀgreaterꢀthanꢀ
1MHz.ꢀAtꢀthisꢀbandwidth,ꢀPCBꢀviasꢀcanꢀaddꢀsignificantꢀ
inductance,ꢀthusꢀtheꢀfundamentalꢀdecouplingꢀcapacitorsꢀ
mustꢀbeꢀmountedꢀonꢀtheꢀsameꢀplaneꢀasꢀtheꢀLT3070.
TheꢀLT3070’sꢀfeedbackꢀloopꢀrequiresꢀanꢀoutputꢀcapacitorꢀ
forꢀstability.ꢀChooseꢀC ꢀcarefullyꢀandꢀmountꢀitꢀinꢀcloseꢀ
OUT
proximityꢀtoꢀtheꢀLT3070’sꢀOUTꢀandꢀGNDꢀpins.ꢀIncludeꢀwideꢀ
routingꢀplanesꢀforꢀOUTꢀandꢀGNDꢀtoꢀminimizeꢀinductance.ꢀ
Ifꢀpossible,ꢀmountꢀtheꢀregulatorꢀimmediatelyꢀadjacentꢀtoꢀ
theꢀapplicationꢀloadꢀtoꢀminimizeꢀdistributedꢀinductanceꢀ
forꢀ optimalꢀ loadꢀ transientꢀ performance.ꢀ Point-of-Loadꢀ
applicationsꢀ presentꢀ theꢀ bestꢀ caseꢀ layoutꢀ scenarioꢀ forꢀ
extractingꢀfullꢀLT3070ꢀperformance.ꢀ
Typicalꢀ0603ꢀorꢀ0805ꢀcase-sizeꢀcapacitorsꢀhaveꢀanꢀESLꢀofꢀ
~800pHꢀandꢀPCBꢀmountingꢀcanꢀcontributeꢀupꢀtoꢀ~200pH.ꢀ
Thus,ꢀ itꢀ becomesꢀ necessaryꢀ toꢀ reduceꢀ theꢀ parasiticꢀ
3070fa
ꢀꢇ
LT3070
ApplicAtions inFormAtion
inductanceꢀbyꢀusingꢀaꢀparallelꢀcapacitorꢀcombination.ꢀ applications,ꢀthisꢀtotalꢀvalueꢀofꢀcapacitanceꢀmayꢀbeꢀcloseꢀ
Aꢀsuitableꢀmethodologyꢀmustꢀcontrolꢀthisꢀparallelingꢀasꢀ toꢀtheꢀLT3070’sꢀminimumꢀ15µFꢀcapacitanceꢀrequirement.ꢀ
capacitorsꢀwithꢀtheꢀsameꢀself-resonantꢀfrequency,ꢀf ,ꢀwillꢀ Thisꢀmayꢀreduceꢀtheꢀrequiredꢀvalueꢀofꢀcapacitanceꢀdirectlyꢀ
R
formꢀaꢀtankꢀcircuitꢀthatꢀcanꢀinduceꢀringingꢀofꢀtheirꢀownꢀ atꢀtheꢀLT3070’sꢀoutput.ꢀMultipleꢀlowꢀvalueꢀcapacitorsꢀinꢀ
accord.ꢀSmallꢀamountsꢀofꢀESRꢀ(5mΩꢀtoꢀ20mΩ)ꢀhaveꢀsomeꢀ parallelꢀpresentꢀaꢀfavorableꢀfrequencyꢀcharacteristicꢀthatꢀ
benefitꢀinꢀdampeningꢀtheꢀresonantꢀloop,ꢀbutꢀhigherꢀESRsꢀ pushesꢀmanyꢀofꢀtheꢀparasiticꢀpoles/zeroesꢀbeyondꢀtheꢀ
degradeꢀtheꢀcapacitorꢀresponseꢀtoꢀtransientꢀloadꢀstepsꢀ LT3070’sꢀunity-gainꢀcrossoverꢀfrequency.ꢀThisꢀtechniqueꢀ
withꢀrise/fallꢀtimesꢀlessꢀthanꢀ1µs.ꢀTheꢀmostꢀareaꢀefficientꢀ illustratesꢀtheꢀmethodꢀthatꢀextractsꢀtheꢀfullꢀbandwidthꢀ
parallelꢀcapacitorꢀcombinationꢀisꢀaꢀgraduatedꢀ4/2/1ꢀscaleꢀ performanceꢀofꢀtheꢀLT3070.
ofꢀf ꢀofꢀtheꢀsameꢀcaseꢀsize.ꢀUnderꢀtheseꢀconditions,ꢀtheꢀ
R
Giveꢀadditionalꢀconsiderationꢀtoꢀtheꢀuseꢀofꢀceramicꢀcapaci-
tors.ꢀCeramicꢀcapacitorsꢀareꢀmanufacturedꢀwithꢀaꢀvarietyꢀofꢀ
dielectrics,ꢀeachꢀwithꢀdifferentꢀbehaviorꢀacrossꢀtemperatureꢀ
andꢀappliedꢀvoltage.ꢀTheꢀmostꢀcommonꢀdielectricsꢀusedꢀ
areꢀspecifiedꢀwithꢀEIAꢀtemperatureꢀcharacteristicꢀcodesꢀofꢀ
Z5U,ꢀY5V,ꢀX5RꢀandꢀX7R.ꢀTheꢀZ5UꢀandꢀY5Vꢀdielectricsꢀareꢀ
goodꢀforꢀprovidingꢀhighꢀcapacitancesꢀinꢀaꢀsmallꢀpackage,ꢀ
butꢀtheyꢀtendꢀtoꢀhaveꢀstrongꢀvoltageꢀandꢀtemperatureꢀ
coefficientsꢀasꢀshownꢀinꢀFiguresꢀ4ꢀandꢀ5.ꢀWhenꢀusedꢀwithꢀ
aꢀ5Vꢀregulator,ꢀaꢀ16Vꢀ10µFꢀY5Vꢀcapacitorꢀcanꢀexhibitꢀanꢀ
effectiveꢀvalueꢀasꢀlowꢀasꢀ1µFꢀtoꢀ2µFꢀforꢀtheꢀDCꢀbiasꢀvoltageꢀ
appliedꢀandꢀoverꢀtheꢀoperatingꢀtemperatureꢀrange.ꢀTheꢀX5Rꢀ
andꢀX7Rꢀdielectricsꢀresultꢀinꢀmoreꢀstableꢀcharacteristicsꢀ
andꢀareꢀmoreꢀsuitableꢀforꢀuseꢀasꢀtheꢀoutputꢀcapacitor.ꢀ
TheꢀX7Rꢀtypeꢀhasꢀbetterꢀstabilityꢀacrossꢀtemperature,ꢀ
whileꢀtheꢀX5Rꢀisꢀlessꢀexpensiveꢀandꢀisꢀavailableꢀinꢀhigherꢀ
values.ꢀCareꢀstillꢀmustꢀbeꢀexercisedꢀwhenꢀusingꢀX5Rꢀandꢀ
individualꢀESLsꢀareꢀrelativelyꢀuniform,ꢀandꢀtheꢀresonanceꢀ
peaksꢀareꢀdeconstructivelyꢀspreadꢀbeyondꢀtheꢀregulatorꢀ
bandwidth.ꢀTheꢀrecommendedꢀparallelꢀcombinationꢀthatꢀ
approximatesꢀ15µFꢀisꢀ10µFꢀ+ꢀ4.7µFꢀ+ꢀ2.2µF.ꢀCapacitorsꢀ
withꢀcaseꢀsizesꢀlargerꢀthanꢀ0805ꢀhaveꢀhigherꢀESLꢀandꢀ
lowerꢀ ESRꢀ (<5mΩ).ꢀ Therefore,ꢀ moreꢀ capacitorsꢀ withꢀ
smallerꢀvaluesꢀ(<10µF)ꢀmustꢀbeꢀchosen.ꢀUsersꢀshouldꢀ
considerꢀnewꢀgeneration,ꢀlowꢀinductanceꢀcapacitorsꢀtoꢀ
pushꢀoutꢀf ꢀandꢀmaximizeꢀstability.ꢀReferꢀtoꢀtheꢀsurfaceꢀ
R
mountꢀceramicꢀcapacitorꢀmanufacturer’sꢀdataꢀsheetsꢀforꢀ
capacitorꢀspecifications.ꢀFigureꢀ3ꢀillustratesꢀanꢀoptimumꢀ
PCBꢀlayoutꢀforꢀtheꢀparallelꢀoutputꢀcapacitorꢀcombination,ꢀ
butꢀalsoꢀillustratesꢀtheꢀGNDꢀconnectionꢀbetweenꢀtheꢀINꢀ
capacitorꢀandꢀtheꢀOUTꢀcapacitorsꢀtoꢀminimizeꢀtheꢀACꢀ
GNDꢀloopꢀforꢀfastꢀloadꢀtransients.ꢀThisꢀtightꢀbypassingꢀ
connectionꢀminimizesꢀEMIꢀandꢀoptimizesꢀbypassing.ꢀ
ManyꢀofꢀtheꢀapplicationsꢀinꢀwhichꢀtheꢀLT3070ꢀexcels,ꢀ X7Rꢀcapacitors;ꢀtheꢀX5RꢀandꢀX7Rꢀcodesꢀonlyꢀspecifyꢀ
suchꢀasꢀFPGA,ꢀASICꢀprocessorꢀorꢀDSPꢀsupplies,ꢀtypicallyꢀ operatingꢀtemperatureꢀrangeꢀandꢀmaximumꢀcapacitanceꢀ
requireꢀaꢀhighꢀfrequencyꢀdecouplingꢀcapacitorꢀnetworkꢀforꢀ changeꢀ overꢀ temperature.ꢀ Capacitanceꢀ changeꢀ dueꢀ toꢀ
theꢀdeviceꢀbeingꢀpowered.ꢀThisꢀnetworkꢀgenerallyꢀconsistsꢀ DCꢀbiasꢀwithꢀX5RꢀandꢀX7RꢀcapacitorsꢀisꢀbetterꢀthanꢀY5Vꢀ
ofꢀmanyꢀlowꢀvalueꢀceramicꢀcapacitorsꢀinꢀparallel.ꢀInꢀsomeꢀ andꢀZ5Uꢀcapacitors,ꢀbutꢀcanꢀstillꢀbeꢀsignificantꢀenoughꢀtoꢀ
dropꢀcapacitorꢀvaluesꢀbelowꢀappropriateꢀlevels.ꢀCapacitorꢀ
DCꢀbiasꢀcharacteristicsꢀtendꢀtoꢀimproveꢀasꢀcomponentꢀ
caseꢀsizeꢀincreases,ꢀbutꢀexpectedꢀcapacitanceꢀatꢀoperat-
LT3070
SENSE
IN OUT
GND
ingꢀvoltageꢀshouldꢀbeꢀverified.ꢀVoltageꢀandꢀtemperatureꢀ
coefficientsꢀareꢀnotꢀtheꢀonlyꢀsourcesꢀofꢀproblems.ꢀSomeꢀ
ceramicꢀcapacitorsꢀhaveꢀaꢀpiezoelectricꢀresponse.ꢀAꢀpiezo-
electricꢀdeviceꢀgeneratesꢀvoltageꢀacrossꢀitsꢀterminalsꢀdueꢀ
toꢀmechanicalꢀstress,ꢀsimilarꢀtoꢀtheꢀwayꢀaꢀpiezoelectricꢀ
microphoneꢀworks.ꢀForꢀaꢀceramicꢀcapacitorꢀtheꢀstressꢀ
canꢀbeꢀinducedꢀbyꢀvibrationsꢀinꢀtheꢀsystemꢀorꢀthermalꢀ
transients.ꢀ
Lo-Z
INPUT
LOAD PLANE
2.2µF
4.7µF
10µF
47µF
3070 F03
Figure ꢁ. Example PCB Layout
3070fa
ꢀꢈ
LT3070
ApplicAtions inFormAtion
20
theꢀLT3070ꢀbackꢀtoꢀtheꢀpowerꢀsupplyꢀground),ꢀlargeꢀinputꢀ
capacitorsꢀareꢀrequiredꢀtoꢀavoidꢀanꢀunstableꢀapplication.ꢀ
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
0
X5R
ThisꢀisꢀdueꢀtoꢀtheꢀinductanceꢀofꢀtheꢀwireꢀformingꢀanꢀLCꢀ
tankꢀcircuitꢀwithꢀtheꢀinputꢀcapacitorꢀandꢀnotꢀaꢀresultꢀofꢀtheꢀ
LT3070ꢀbeingꢀunstable.ꢀTheꢀselfꢀinductance,ꢀorꢀisolatedꢀ
inductance,ꢀofꢀaꢀwireꢀisꢀdirectlyꢀproportionalꢀtoꢀitsꢀlength.ꢀ
However,ꢀtheꢀdiameterꢀofꢀaꢀwireꢀdoesꢀnotꢀhaveꢀaꢀmajorꢀ
influenceꢀonꢀitsꢀselfꢀinductance.ꢀForꢀexample,ꢀoneꢀinchꢀofꢀ
18-AWG,ꢀ0.04ꢀinchꢀdiameterꢀwireꢀhasꢀ28nHꢀofꢀselfꢀinduc-
tance.ꢀTheꢀselfꢀinductanceꢀofꢀaꢀ2-AWGꢀisolatedꢀwireꢀwithꢀ
aꢀdiameterꢀofꢀ0.26ꢀinchꢀisꢀaboutꢀhalfꢀtheꢀinductanceꢀofꢀaꢀ
18-AWGꢀwire.ꢀTheꢀoverallꢀselfꢀinductanceꢀofꢀaꢀwireꢀcanꢀ
beꢀreducedꢀinꢀtwoꢀways.ꢀOneꢀisꢀtoꢀdivideꢀtheꢀcurrentꢀflow-
ingꢀtowardsꢀtheꢀLT3070ꢀbetweenꢀtwoꢀparallelꢀconductorsꢀ
whichꢀflowsꢀinꢀtheꢀsameꢀdirectionꢀinꢀeach.ꢀInꢀthisꢀcase,ꢀ
theꢀfartherꢀtheꢀwiresꢀareꢀplacedꢀapartꢀfromꢀeachꢀother,ꢀtheꢀ
moreꢀinductanceꢀwillꢀbeꢀreduced,ꢀupꢀtoꢀaꢀ50ꢁꢀreductionꢀ
whenꢀplacedꢀaꢀfewꢀinchesꢀapart.ꢀSplittingꢀtheꢀwiresꢀbasi-
callyꢀconnectsꢀtwoꢀequalꢀinductorsꢀinꢀparallel.ꢀHowever,ꢀ
whenꢀplacedꢀinꢀcloseꢀproximityꢀfromꢀeachꢀother,ꢀmutualꢀ
inductanceꢀisꢀaddedꢀtoꢀtheꢀoverallꢀselfꢀinductanceꢀofꢀtheꢀ
wires.ꢀTheꢀmostꢀeffectiveꢀwayꢀtoꢀreduceꢀoverallꢀinductanceꢀ
isꢀtoꢀplaceꢀtheꢀforwardꢀandꢀreturn-currentꢀconductorsꢀ(theꢀ
wireꢀforꢀtheꢀinputꢀandꢀtheꢀwireꢀforꢀtheꢀreturnꢀground)ꢀinꢀ
veryꢀcloseꢀproximity.ꢀTwoꢀ18-AWGꢀwiresꢀseparatedꢀbyꢀ
0.05ꢀinchꢀreduceꢀtheꢀoverallꢀselfꢀinductanceꢀtoꢀaboutꢀone-
fourthꢀofꢀaꢀsingleꢀisolatedꢀwire.ꢀIfꢀtheꢀLT3070ꢀisꢀpoweredꢀ
byꢀaꢀbatteryꢀmountedꢀinꢀcloseꢀproximityꢀwithꢀgroundꢀandꢀ
powerꢀplanesꢀonꢀtheꢀsameꢀcircuitꢀboard,ꢀaꢀ47µFꢀinputꢀ
capacitorꢀisꢀsufficientꢀforꢀstability.ꢀHowever,ꢀifꢀtheꢀLT3070ꢀ
isꢀpoweredꢀbyꢀaꢀdistantꢀsupply,ꢀuseꢀaꢀlowꢀESR,ꢀlargeꢀvalueꢀ
inputꢀcapacitorꢀonꢀtheꢀorderꢀofꢀ330µF.ꢀAsꢀpowerꢀsupplyꢀ
outputꢀimpedanceꢀvaries,ꢀtheꢀminimumꢀinputꢀcapacitanceꢀ
neededꢀforꢀapplicationꢀstabilityꢀalsoꢀvaries.
–20
–40
–60
Y5V
–80
–100
10 12
DC BIAS VOLTAGE (V)
0
2
4
6
8
14 16
3070 F04
Figure 4. Ceramic Capacitor DC Bias Characteristics
40
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
20
X5R
0
–20
Y5V
–40
–60
–80
–100
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
3070 F05
Figure 5. Ceramic Capacitor Temperature Characteristics
Stability and Input Capacitance
Theꢀ LT3070ꢀ isꢀ stableꢀ withꢀ aꢀ minimumꢀ capacitanceꢀ ofꢀ
47µFꢀconnectedꢀtoꢀitsꢀINꢀpins.ꢀUseꢀlowꢀESRꢀcapacitorsꢀtoꢀ
minimizeꢀinstantaneousꢀvoltageꢀdropsꢀunderꢀlargeꢀloadꢀ
transientꢀconditions.ꢀLargeꢀV ꢀdroopsꢀduringꢀlargeꢀloadꢀ
IN
transientsꢀmayꢀcauseꢀtheꢀregulatorꢀtoꢀenterꢀdropoutꢀwithꢀ
correspondingꢀ degradationꢀ inꢀ loadꢀ transientꢀ response.ꢀ
Increasedꢀvaluesꢀofꢀinputꢀandꢀoutputꢀcapacitanceꢀmayꢀbeꢀ
necessaryꢀdependingꢀonꢀanꢀapplication’sꢀrequirements.ꢀ
Sufficientꢀ inputꢀ capacitanceꢀ isꢀ criticalꢀ asꢀ theꢀ circuitꢀ isꢀ
intentionallyꢀoperatedꢀcloseꢀtoꢀdropoutꢀtoꢀminimizeꢀpower.ꢀ
Ideally,ꢀtheꢀoutputꢀimpedanceꢀofꢀtheꢀsupplyꢀthatꢀpowersꢀ
INꢀshouldꢀbeꢀlessꢀthanꢀ10mΩꢀtoꢀsupportꢀaꢀ5Aꢀloadꢀwithꢀ
largeꢀtransients.
Bias Pin Capacitance Requirements
TheꢀBIASꢀpinꢀsuppliesꢀcurrentꢀtoꢀmostꢀofꢀtheꢀinternalꢀ
controlꢀcircuitryꢀandꢀtheꢀoutputꢀstageꢀdrivingꢀtheꢀpassꢀ
transistor.ꢀTheꢀLT3070ꢀrequiresꢀaꢀminimumꢀ2.2µFꢀby-
passꢀ capacitorꢀ forꢀ stabilityꢀ andꢀ properꢀ operation.ꢀ Toꢀ
ensureꢀ properꢀ operation,ꢀ theꢀ BIASꢀ voltageꢀ mustꢀ sat-
isfyꢀtheꢀfollowingꢀconditions:ꢀ2.2Vꢀ≤ꢀV
ꢀ≤ꢀ3.6Vꢀandꢀ
BIAS
V
ꢀ ≥ꢀ (1.25ꢀ •ꢀ V ꢀ +ꢀ 1V).ꢀ Forꢀ V ꢀ ≤ꢀ 0.95V,ꢀ theꢀ
Inꢀcasesꢀwhereꢀwireꢀisꢀusedꢀtoꢀconnectꢀaꢀpowerꢀsupplyꢀ
toꢀtheꢀinputꢀofꢀtheꢀLT3070ꢀ(andꢀalsoꢀfromꢀtheꢀgroundꢀofꢀ
BIAS
OUT OUT
minimumꢀBIASꢀvoltageꢀisꢀlimitedꢀtoꢀ2.2V.ꢀ
3070fa
ꢁ0
TheꢀLT3070ꢀprovidesꢀaꢀKelvinꢀsenseꢀpinꢀforꢀV
,ꢀallowingꢀ
OUT
LT3070
ApplicAtions inFormAtion
Load Regulation
valuesꢀofꢀinput-to-outputꢀvoltageꢀupꢀtoꢀtheꢀabsoluteꢀmaxi-
mumꢀvoltageꢀrating.ꢀSeeꢀtheꢀCurrentꢀLimitꢀvsꢀV ꢀcurveꢀinꢀ
IN
theꢀTypicalꢀPerformanceꢀCharacteristics.ꢀ
theꢀapplicationꢀtoꢀcorrectꢀforꢀparasiticꢀpackageꢀandꢀPCBꢀ
I-Rꢀdrops.ꢀHowever,ꢀLTCꢀrecommendsꢀthatꢀtheꢀSENSEꢀpinꢀ Duringꢀstart-up,ꢀafterꢀtheꢀBIASꢀvoltageꢀhasꢀclearedꢀitsꢀUVLOꢀ
terminateꢀinꢀcloseꢀproximityꢀtoꢀtheꢀLT3070’sꢀOUTꢀpins.ꢀ thresholdꢀandꢀV ꢀisꢀincreasing,ꢀoutputꢀvoltageꢀincreasesꢀ
IN
Thisꢀminimizesꢀparasiticꢀinductanceꢀandꢀoptimizesꢀregula-
tion.ꢀTheꢀLT3070ꢀhandlesꢀmoderateꢀlevelsꢀofꢀoutputꢀlineꢀ
atꢀtheꢀrateꢀofꢀcurrentꢀlimitꢀchargingꢀC .ꢀ
OUTꢀ
Withꢀaꢀhighꢀinputꢀvoltage,ꢀaꢀproblemꢀcanꢀoccurꢀwhereꢀtheꢀ
removalꢀofꢀanꢀoutputꢀshortꢀwillꢀnotꢀallowꢀtheꢀoutputꢀvolt-
ageꢀtoꢀrecover.ꢀOtherꢀregulatorsꢀwithꢀcurrentꢀlimitꢀfoldbackꢀ
alsoꢀexhibitꢀthisꢀphenomenon,ꢀsoꢀitꢀisꢀnotꢀuniqueꢀtoꢀtheꢀ
LT3070.ꢀTheꢀloadꢀlineꢀforꢀsuchꢀaꢀloadꢀmayꢀintersectꢀtheꢀ
impedance,ꢀbutꢀexcessiveꢀimpedanceꢀbetweenꢀV ꢀandꢀ
OUT
C
ꢀcausesꢀexcessiveꢀphaseꢀshiftꢀinꢀtheꢀfeedbackꢀloopꢀ
OUT
andꢀadverselyꢀaffectsꢀstability.
Figureꢀ1ꢀinꢀtheꢀPinꢀFunctionsꢀsectionꢀillustratesꢀtheꢀKelvin-
Senseꢀconnectionꢀmethodꢀthatꢀeliminatesꢀvoltageꢀdropsꢀ outputꢀcurrentꢀcurveꢀatꢀtwoꢀpoints:ꢀnormalꢀoperationꢀandꢀ
dueꢀtoꢀPCBꢀtraceꢀresistance.ꢀHowever,ꢀnoteꢀthatꢀtheꢀvoltageꢀ theꢀSOAꢀrestrictedꢀloadꢀcurrentꢀsettings.ꢀAꢀcommonꢀsitu-
dropꢀacrossꢀtheꢀexternalꢀPCBꢀtracesꢀaddsꢀtoꢀtheꢀdropoutꢀ ationꢀisꢀimmediatelyꢀafterꢀtheꢀremovalꢀofꢀaꢀshortꢀcircuit,ꢀ
voltageꢀofꢀtheꢀregulator.ꢀTheꢀSENSEꢀpinꢀinputꢀbiasꢀcurrentꢀ butꢀwithꢀaꢀstaticꢀloadꢀ≥ꢀ1A.ꢀInꢀthisꢀsituation,ꢀremovalꢀofꢀtheꢀ
dependsꢀonꢀtheꢀselectedꢀoutputꢀvoltage.ꢀSENSEꢀpinꢀinputꢀ loadꢀorꢀreductionꢀofꢀI ꢀtoꢀ<1Aꢀwillꢀclearꢀthisꢀconditionꢀ
OUT
currentꢀvariesꢀfromꢀ50µAꢀtypicallyꢀatꢀV ꢀ=ꢀ0.8Vꢀtoꢀ300µAꢀ andꢀallowꢀV ꢀtoꢀreturnꢀtoꢀnormalꢀregulation.
OUT
OUT
typicallyꢀatꢀV ꢀ=ꢀ1.8V.
OUT
Reverse Voltage
Short-Circuit and Overload Recovery
TheꢀLT3070ꢀincorporatesꢀaꢀcircuitꢀthatꢀdetectsꢀifꢀV ꢀde-
creasesꢀbelowꢀV .ꢀThisꢀreverse-voltageꢀdetectorꢀhasꢀ
IN
LikeꢀmanyꢀICꢀpowerꢀregulators,ꢀtheꢀLT3070ꢀhasꢀsafeꢀop-
eratingꢀareaꢀ(SOA)ꢀprotection.ꢀTheꢀsafeꢀareaꢀprotectionꢀ aꢀtypicalꢀthresholdꢀofꢀaboutꢀ(V ꢀ–ꢀV )ꢀ=ꢀ–6mV.ꢀIfꢀtheꢀ
OUTꢀ
IN
OUT
decreasesꢀcurrentꢀlimitꢀasꢀinput-to-outputꢀvoltageꢀincreasesꢀ thresholdꢀisꢀexceeded,ꢀthisꢀdetectorꢀcircuitꢀturnsꢀoffꢀtheꢀ
andꢀkeepsꢀtheꢀpowerꢀtransistorꢀinsideꢀaꢀsafeꢀoperatingꢀ driveꢀtoꢀtheꢀinternalꢀNMOSꢀpassꢀtransistor,ꢀtherebyꢀturningꢀ
regionꢀforꢀallꢀvaluesꢀofꢀinput-to-outputꢀvoltageꢀupꢀtoꢀtheꢀ offꢀtheꢀoutput.ꢀTheꢀoutputꢀpullsꢀlowꢀwithꢀtheꢀloadꢀcurrentꢀ
absoluteꢀmaximumꢀvoltageꢀrating.ꢀV
ꢀmustꢀbeꢀaboveꢀ dischargingꢀtheꢀoutputꢀcapacitance.ꢀThisꢀcircuit’sꢀintentꢀ
BIAS
theꢀUVLOꢀthresholdꢀforꢀanyꢀfunction.ꢀTheꢀLT3070ꢀhasꢀaꢀ isꢀtoꢀlimitꢀandꢀpreventꢀback-feedꢀcurrentꢀfromꢀOUTꢀtoꢀINꢀ
precisionꢀcurrentꢀlimitꢀspecifiedꢀatꢀ 20ꢁꢀthatꢀisꢀactiveꢀifꢀ ifꢀtheꢀinputꢀvoltageꢀcollapsesꢀdueꢀtoꢀaꢀfaultꢀorꢀoverloadꢀ
V ꢀisꢀaboveꢀUVLO.ꢀ
BIAS
condition.
Underꢀ conditionsꢀ ofꢀ maximumꢀ I
IN OUT
ꢀ andꢀ maximumꢀ
LOAD
Thermal Considerations
V -V ꢀtheꢀdevice’sꢀpowerꢀdissipationꢀpeaksꢀatꢀaboutꢀ
Theꢀ LT3070’sꢀ maximumꢀ ratedꢀ junctionꢀ temperatureꢀ ofꢀ
125°Cꢀlimitsꢀitsꢀpowerꢀhandlingꢀcapabilityꢀandꢀisꢀdomi-
natedꢀbyꢀtheꢀoutputꢀcurrentꢀmultipliedꢀbyꢀtheꢀinput/outputꢀ
voltageꢀdifferential:ꢀ
3W.ꢀIfꢀambientꢀtemperatureꢀisꢀhighꢀenough,ꢀdieꢀjunctionꢀ
temperatureꢀwillꢀexceedꢀtheꢀ125°Cꢀmaximumꢀoperatingꢀ
temperature.ꢀ Ifꢀ thisꢀ occurs,ꢀ theꢀ LT3070ꢀ reliesꢀ onꢀ twoꢀ
additionalꢀthermalꢀsafetyꢀfeatures.ꢀAtꢀaboutꢀ145°C,ꢀtheꢀ
PWRGDꢀoutputꢀpullsꢀlowꢀprovidingꢀanꢀearlyꢀwarningꢀofꢀanꢀ
impendingꢀthermalꢀshutdownꢀcondition.ꢀAtꢀ165°Cꢀtypically,ꢀ
theꢀLT3070’sꢀthermalꢀshutdownꢀengagesꢀandꢀtheꢀoutputꢀisꢀ
shutꢀdownꢀuntilꢀtheꢀICꢀtemperatureꢀfallsꢀbelowꢀtheꢀthermalꢀ
hysteresisꢀlimit.ꢀTheꢀSOAꢀprotectionꢀdecreasesꢀcurrentꢀlimitꢀ
asꢀtheꢀIN-to-OUTꢀvoltageꢀincreasesꢀandꢀkeepsꢀtheꢀpowerꢀ
dissipationꢀatꢀsafeꢀlevelsꢀforꢀallꢀvaluesꢀofꢀinput-to-outputꢀ
voltage.ꢀTheꢀLT3070ꢀprovidesꢀsomeꢀoutputꢀcurrentꢀatꢀallꢀ
ꢀ I ꢀ•ꢀ(V ꢀ–ꢀV )ꢀ
OUT
IN
OUT
TheꢀLT3070’sꢀinternalꢀpowerꢀandꢀthermalꢀlimitingꢀcircuitryꢀ
protectꢀitꢀunderꢀoverloadꢀconditions.ꢀForꢀcontinuousꢀnor-
malꢀloadꢀconditions,ꢀdoꢀnotꢀexceedꢀtheꢀmaximumꢀjunctionꢀ
temperatureꢀofꢀ125°C.ꢀGiveꢀcarefulꢀconsiderationꢀtoꢀallꢀ
sourcesꢀofꢀthermalꢀresistanceꢀfromꢀjunctionꢀtoꢀambient.ꢀ
Thisꢀincludesꢀjunctionꢀtoꢀcase,ꢀcase-to-heatꢀsinkꢀinterface,ꢀ
3070fa
ꢁꢀ
LT3070
ApplicAtions inFormAtion
heatꢀsinkꢀresistanceꢀorꢀcircuitꢀboardꢀtoꢀambientꢀasꢀtheꢀ where:
applicationꢀdictates.ꢀAlso,ꢀconsiderꢀadditionalꢀheatꢀsourcesꢀ
ꢀ I
ꢀ=ꢀ4A
OUT(MAX)
mountedꢀinꢀproximityꢀtoꢀtheꢀLT3070.ꢀTheꢀLT3070ꢀisꢀaꢀsurfaceꢀ
mountꢀdeviceꢀandꢀasꢀsuch,ꢀheatꢀsinkingꢀisꢀaccomplishedꢀ
byꢀusingꢀtheꢀheatꢀspreadingꢀcapabilitiesꢀofꢀtheꢀPCꢀboardꢀ
andꢀ itsꢀ copperꢀ traces.ꢀ Surfaceꢀ mountꢀ heatꢀ sinksꢀ andꢀ
platedꢀthrough-holesꢀcanꢀalsoꢀbeꢀusedꢀtoꢀspreadꢀtheꢀheatꢀ
generatedꢀ byꢀ powerꢀ devices.ꢀ Junction-to-caseꢀ thermalꢀ
resistanceꢀisꢀspecifiedꢀfromꢀtheꢀICꢀjunctionꢀtoꢀtheꢀbottomꢀ
ofꢀtheꢀcaseꢀdirectlyꢀbelowꢀtheꢀdie.ꢀThisꢀisꢀtheꢀlowestꢀresis-
tanceꢀpathꢀforꢀheatꢀflow.ꢀProperꢀmountingꢀisꢀrequiredꢀtoꢀ
ꢀ V
ꢀ=ꢀ1.26V
IN(MAX)
ꢀ I
ꢀatꢀ(I ꢀ=ꢀ4A,ꢀV
ꢀ=ꢀ2.5V)ꢀ=ꢀ6.91mA
BIAS
OUT
BIAS
ꢀ I ꢀatꢀ(I ꢀ=ꢀ4A,ꢀV ꢀ=ꢀ2.5V)ꢀ=ꢀ0.87mA
BIAS
GND
OUT
thus:
Pꢀ=ꢀ4A(1.26Vꢀ–ꢀ0.9V)ꢀ+ꢀ(6.91mAꢀ–ꢀ0.87mA)0.9Vꢀ+ꢀ
0.87mA(2.5V)ꢀ=ꢀ1.448W
ensureꢀtheꢀbestꢀpossibleꢀthermalꢀflowꢀfromꢀthisꢀareaꢀofꢀtheꢀ Withꢀ theꢀ QFNꢀ packageꢀ solderedꢀ toꢀ maximumꢀ copperꢀ
packageꢀtoꢀtheꢀheatꢀsinkingꢀmaterial.ꢀNoteꢀthatꢀtheꢀexposedꢀ area,ꢀtheꢀthermalꢀresistanceꢀisꢀ30°C/W.ꢀSoꢀtheꢀjunctionꢀ
padꢀisꢀelectricallyꢀconnectedꢀtoꢀGND.ꢀ
temperatureꢀriseꢀaboveꢀambientꢀequals:
Tableꢀ3ꢀlistsꢀthermalꢀresistanceꢀasꢀaꢀfunctionꢀofꢀcopperꢀ ꢀ 1.448Wꢀatꢀ30°C/Wꢀ=ꢀ43.44°C
areaꢀinꢀaꢀfixedꢀboardꢀsize.ꢀAllꢀmeasurementsꢀwereꢀtakenꢀ
Theꢀmaximumꢀjunctionꢀtemperatureꢀequalsꢀtheꢀmaximumꢀ
ambientꢀtemperatureꢀplusꢀtheꢀmaximumꢀjunctionꢀtempera-
tureꢀriseꢀaboveꢀambientꢀor:ꢀ
inꢀstillꢀairꢀonꢀaꢀ4-layerꢀFR-4ꢀboardꢀwithꢀ1ꢀozꢀsolidꢀinternalꢀ
planesꢀandꢀ2ꢀozꢀtop/bottomꢀexternalꢀtraceꢀplanesꢀwithꢀaꢀ
totalꢀboardꢀthicknessꢀofꢀ1.6mm.ꢀPCBꢀlayers,ꢀcopperꢀweight,ꢀ
boardꢀlayoutꢀandꢀthermalꢀviasꢀaffectꢀtheꢀresultantꢀthermalꢀ
resistance.ꢀForꢀfurtherꢀinformationꢀonꢀthermalꢀresistanceꢀ
andꢀhighꢀthermalꢀꢀconductivityꢀtestꢀboards,ꢀreferꢀtoꢀJEDECꢀ
standardꢀ JESD51,ꢀ notablyꢀ JESD51-12ꢀ andꢀ JESD51-7.ꢀ
Achievingꢀlowꢀthermalꢀresistanceꢀnecessitatesꢀattentionꢀ
toꢀdetailꢀandꢀcarefulꢀPCBꢀlayout.
ꢀ T ꢀ=ꢀ50°Cꢀ+ꢀ43.44°Cꢀ=ꢀ93.44°C
JMAX
Applicationsꢀ thatꢀ cannotꢀ supportꢀ extensiveꢀ PCBꢀ spaceꢀ
forꢀheatꢀsinkingꢀtheꢀLT3070ꢀrequireꢀaꢀderatingꢀofꢀoutputꢀ
currentꢀorꢀincreasedꢀairflow.ꢀ
Paralleling Devices for Higher I
OUT
Table ꢁ, UFD Plastic Package, 28-Lead QFN
MultipleꢀLT3070sꢀmayꢀbeꢀparalleledꢀtoꢀobtainꢀhigherꢀoutputꢀ
current.ꢀThisꢀparallelingꢀconceptꢀborrowsꢀfromꢀtheꢀschemeꢀ
employedꢀbyꢀtheꢀLT3080.
COPPER AREA
THERMAL RESISTANCE
TOPSIDE* BACK SIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2
2
2
2
2
2
2
2
2
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
30°C/W
32°C/W
33°C/W
35°C/W
Toꢀaccomplishꢀthisꢀparalleling,ꢀtieꢀtheꢀREF/BYPꢀpinsꢀofꢀ
theꢀparalleledꢀregulatorsꢀtogether.ꢀThisꢀeffectivelyꢀgivesꢀ
anꢀaveragedꢀvalueꢀofꢀmultipleꢀ600mVꢀreferenceꢀvoltageꢀ
sources.ꢀTieꢀtheꢀOUTꢀpinsꢀofꢀtheꢀparalleledꢀregulatorsꢀtoꢀ
theꢀcommonꢀloadꢀplaneꢀthroughꢀaꢀsmallꢀpieceꢀofꢀPCꢀtraceꢀ
ballastꢀorꢀanꢀactualꢀsurfaceꢀmountꢀsenseꢀresistorꢀbeyondꢀ
theꢀprimaryꢀoutputꢀcapacitorsꢀofꢀeachꢀregulator.ꢀTheꢀre-
quiredꢀballastꢀisꢀdependentꢀuponꢀtheꢀapplicationꢀoutputꢀ
voltageꢀandꢀpeakꢀloadꢀcurrent.ꢀTheꢀrecommendedꢀballastꢀ
isꢀthatꢀvalueꢀwhichꢀcontributesꢀ1ꢁꢀtoꢀloadꢀregulation.ꢀForꢀ
example,ꢀtwoꢀLT3070ꢀregulatorsꢀconfiguredꢀtoꢀoutputꢀ1V,ꢀ
sharingꢀaꢀ10Aꢀloadꢀrequireꢀ2mΩꢀofꢀballastꢀatꢀeachꢀoutput.ꢀ
TheꢀKelvinꢀSENSEꢀpinsꢀconnectꢀtoꢀtheꢀregulatorꢀsideꢀofꢀ
theꢀballastꢀresistorsꢀtoꢀkeepꢀtheꢀindividualꢀcontrolꢀloopsꢀ
fromꢀconflictingꢀwithꢀeachꢀotherꢀ(seeꢀFiguresꢀ8ꢀandꢀ9).ꢀ
3070fa
2
1000mm
2
225mm
100mm
2
*Deviceꢀisꢀmountedꢀonꢀtopside
Calculating Junction Temperature
Example:ꢀGivenꢀanꢀoutputꢀvoltageꢀofꢀ0.9V,ꢀanꢀinputꢀvoltageꢀ
rangeꢀofꢀ1.2Vꢀ ꢀ5ꢁ,ꢀaꢀBIASꢀvoltageꢀofꢀ2.5V,ꢀaꢀmaximumꢀout-
putꢀcurrentꢀofꢀ4Aꢀandꢀaꢀmaximumꢀambientꢀtemperatureꢀofꢀ
50°C,ꢀwhatꢀwillꢀtheꢀmaximumꢀjunctionꢀtemperatureꢀbe?
Theꢀpowerꢀdissipatedꢀbyꢀtheꢀdeviceꢀequals:
I
ꢀ•ꢀ(V
BIAS
ꢀ–ꢀV )ꢀ+ꢀ(I
–ꢀI )ꢀ•ꢀV
ꢀ
OUT(MAX)
IN(MAX)
OUT
BIASꢀ GND
OUT
+ꢀI ꢀ•ꢀV
GND
ꢁꢁ
LT3070
ApplicAtions inFormAtion
Keepꢀthisꢀballastꢀtraceꢀareaꢀfreeꢀofꢀsolderꢀtoꢀmaintainꢀaꢀ noiseꢀreductionꢀofꢀreferenceꢀnoise.ꢀTheꢀLT3070ꢀdeviatesꢀ
controlledꢀresistance.
fromꢀtheꢀtraditionalꢀvoltageꢀreferenceꢀbyꢀgeneratingꢀaꢀ
lowꢀvoltageꢀV ꢀfromꢀaꢀreferenceꢀcurrentꢀintoꢀanꢀinter-
REF
Tableꢀ4ꢀshowsꢀaꢀsimpleꢀguidelineꢀforꢀPCBꢀtraceꢀresistanceꢀ
asꢀaꢀfunctionꢀofꢀweightꢀandꢀtraceꢀwidth.
nalꢀ resistorꢀ ≅19k.ꢀ Thisꢀ intermediateꢀ impedanceꢀ nodeꢀ
(REF/BYP)ꢀfacilitatesꢀexternalꢀfilteringꢀdirectly.ꢀAꢀ10nFꢀfilterꢀ
Table 4. PC Board Trace Resistance
capacitorꢀminimizesꢀreferenceꢀnoiseꢀtoꢀ10µV
ꢀatꢀtheꢀ
RMS
WEIGHT (Oz)
100 MIL WIDTH*
200 MIL WIDTH*
600mVꢀREF/BYPꢀpin,ꢀequivalentlyꢀaꢀ17µVꢀcontributionꢀtoꢀ
1
2
5.43
2.71
2.71
1.36
outputꢀnoiseꢀatꢀV ꢀ=ꢀ1V.ꢀSeeꢀtheꢀTypicalꢀPerformanceꢀ
OUT
CharacteristicsꢀforꢀNoiseꢀvsꢀOutputꢀVoltageꢀperformanceꢀ
asꢀaꢀfunctionꢀofꢀC
.
*Traceꢀresistanceꢀisꢀmeasuredꢀinꢀmilliohms/in
REF/BYPꢀ
Thisꢀ approachꢀ alsoꢀ accommodatesꢀ referenceꢀ sharingꢀ
betweenꢀLT3070ꢀregulatorsꢀthatꢀareꢀhookedꢀupꢀinꢀcur-
rentꢀsharingꢀapplications.ꢀTheꢀREF/BYPꢀfilterꢀcapacitorꢀ
delaysꢀtheꢀinitialꢀpower-upꢀtimeꢀbyꢀaꢀfactorꢀofꢀtheꢀRCꢀtimeꢀ
Quieting the Noise
TheꢀLT3070ꢀoffersꢀnumerousꢀnoiseꢀperformanceꢀadvan-
tages.ꢀEachꢀLDOꢀhasꢀseveralꢀsourcesꢀofꢀnoise.ꢀAnꢀLDO’sꢀ
mostꢀcriticalꢀnoiseꢀsourceꢀisꢀtheꢀreference,ꢀfollowedꢀbyꢀ
theꢀLDOꢀerrorꢀamplifier.ꢀTraditionalꢀlowꢀnoiseꢀregulatorsꢀ
bufferꢀtheꢀvoltageꢀreferenceꢀoutꢀtoꢀanꢀexternalꢀpinꢀ(usuallyꢀ
throughꢀaꢀlargeꢀvalueꢀresistor)ꢀtoꢀallowꢀforꢀbypassingꢀandꢀ
constant.ꢀV ꢀremainsꢀactiveꢀinꢀnapꢀmode,ꢀthusꢀstart-upꢀ
REF
timeꢀisꢀsignificantlyꢀreducedꢀandꢀwellꢀcontrolledꢀcomingꢀ
outꢀofꢀnapꢀmodeꢀ(EN:LO↑HI).
50k
V
BIAS
PWRGD
2.5V TO 3.6V
2.2µF
BIAS
V
IN
IN
PWRGD
SENSE
1.5V
330µF
EN
V
1.2V
5A
OUT
LT3070
OUT
V
O0
V
O1
V
O2
2.2µF*
4.7µF*
10µF*
NC
NC
MARGSEL
MARGTOL
VIOC
*X5R OR X7R CAPACITORS
REF/BYP
GND
1nF
0.01µF
3070 F06
Figure 6. 1.5V to 1.2V Linear Regulator
3070fa
ꢁꢂ
LT3070
ApplicAtions inFormAtion
V
BIAS
3.3V
47µF
6.3V
s3
1Ω
50k
SV
IN
PWRGD
2.2µF*
NC
2.2µF
0.1µF
BIAS
PGOOD RUN PV
PV
SV TRACK
IN
IN
IN
0.2µH
EN
IN
PWRGD
SENSE
OUT
1.3V/5A
SGND
SW
SW
SW
SW
V
1V
5A
OUT
47µF
PV
PV
IN
IN
LT3070
NC
NC
V
O0
V
O1
V
O2
4.7µF*
10µF*
20k
10k
PLLLPF
*X5R OR X7R CAPACITORS
I
TH
NC
NC
MARGTOL
MARGSEL
LTC3415EUHF
MGN
BSEL
100µF
6.3V
s2
NC
NC
NC
CLKOUT
PHMODE
CLKIN
VIOC
REF/BYP
GND
V
FB
SV
IN
2k
4.7nF
PGND
0.01µF
1nF
I
THM
SGND
PGND PGND
MODE
3070 F07
PGND PGND PGND PGND
NOTE: LTC3415 SWITCHER, 2MHz INTERNAL OSCILLATOR
LTC3415 AND LT3070 ON SAME PCB POWER PLANE
Figure 7. Regulator with VIOC Buck Control
V
BIAS
3.3V
50k
47µF
6.3V
s3
PWRGD
1Ω
2.2µF
SV
IN
NC
PGOOD RUN PV
0.1µF
BIAS
PV
SV TRACK
IN
IN
IN
0.2µH
EN
IN
PWRGD
SENSE
OUT
1.3V/7A
SGND
SW
SW
SW
SW
V
OUT
47µF
1V
PV
IN
PV
IN
LT3070
3.5A
2.2µF*
4.7µF*
10µF*
NC
NC
V
O0
V
O1
V
O2
R
TRACE
PLLLPF
3mΩ
*X5R OR X7R CAPACITORS
CONTROLLED
I
TH
NC
NC
MARGTOL
MARGSEL
MGN
BSEL
P.O.L. 1
LTC3415EUHF
NC
NC
CLKOUT
PHMODE
VIOC
REF/BYP
GND
17.5k
1%
POWER
PLANE
1V/8A
1nF
0.01µF
V
FB
15k
1%
100µF
6.3V
s2
P.O.L. 2
PGND
2.2µF
NC
CLKIN
MODE
I
THM
SGND
PGND PGND
R
TRACE
3mΩ
BIAS
PGND PGND PGND PGND
CONTROLLED
EN
IN
PWRGD
SENSE
OUT
V
OUT
47µF
1V
NOTE: LTC3415 SWITCHER, 2MHz INTERNAL OSCILLATOR
LTC3415 AND LT3070 s2 ON SAME PCB POWER PLANE
LT3070
3.5A
2.2µF*
4.7µF*
10µF*
NC
NC
V
V
V
O0
O1
O2
*X5R OR X7R CAPACITORS
NC
NC
MARGTOL
MARGSEL
VIOC
REF/BYP
1nF
GND
0.01µF
3070 F08
Figure 8. 1V, 7A Point-of-Load Current Sharing Regulators
3070fa
ꢁꢃ
LT3070
typicAl ApplicAtions
50k
V
IN
3.3V
PWRGD
2.2µF
BIAS
EN
IN
PWRGD
SENSE
OUT
V
1V
4A
OUT
47µF
NC
NC
V
O0
V
O1
V
O2
LT3070
2.2µF*
4.7µF*
10µF*
R
TRACE
2.5mΩ
CONTROLLED
NC
NC
MARGTOL
MARGSEL
VIOC
*X5R OR X7R CAPACITORS
0.01µF
P.O.L. 1
REF/BYP
POWER
PLANE
1V/7A
1nF
GND
V
IN
3.3V
V
IN
3.3V
P.O.L. 2
2.2µF
NC
NC
NC
NC
NC
R
TRACE
BIAS
2.5mΩ
EN
IN
V
PWRGD
SENSE
OUT
SW1 CLKIN1 CLKOUT1 CLKIN2 CLKOUT2
CONTROLLED
V
1.3V/8A
BUCK1
V
V
OUT1
MGN1
FB1
IN1
SV
V
1V
4A
OUT
100µF
6.3V
X5R
47µF
10µF
NC
NC
IN1
O0
20k
LT3070
RUN1
2.2µF*
10µF*
10µF*
10µF*
4.7µF*
V
V
O1
PLLLPF1
MODE1
PHMODE1
TRACK1
ITH1
O2
ITHM1
BSEL1
PGOOD1
10k
2k
4.7nF
NC
NC
MARGTOL
MARGSEL
VIOC
*X5R OR X7R CAPACITORS
0.01µF
NC
NC
REF/BYP
GND
LTM4616
V
2.1V/8A
BUCK2
1nF
V
V
OUT2
MGN2
FB2
IN2
SV
100µF
6.3V
X5R
10µF
IN2
RUN2
V
IN
3.3V
PLLLPF2
MODE2
PHMODE2
TRACK2
ITH2
2.2µF
ITHM2
BSEL2
PGOOD2
BIAS
NC
NC
EN
IN
PWRGD
SENSE
OUT
V
1.8V
5A
OUT
SW2 SGND1 GND1 SGND2 GND2
47µF
V
O0
V
O1
V
O2
LT3070
2.2µF*
4.7µF*
NC
NC
NC
NC
MARGTOL
MARGSEL
VIOC
*X5R OR X7R CAPACITORS
0.01µF
20k
NOTE: THE TWO LTM4616 MODULE CHANNELS ARE
INDEPENDENTLY CONTROLLED BY THE VIOC
CONTROLS FROM THE LINEAR REGULATORS
REF/BYP
GND
1nF
2k
4.7nF
10k
V
IN
3.3V
2.2µF
BIAS
EN
IN
PWRGD
SENSE
OUT
V
1.5V
3A
OUT
47µF
V
O0
V
O1
V
O2
LT3070
2.2µF*
4.7µF*
NC
NC
NC
NC
MARGTOL
MARGSEL
VIOC
*X5R OR X7R CAPACITORS
REF/BYP
1nF
GND
0.01µF
3070 F09
Figure 9. Triple Output Supply Providing 1V, 8A and 1.8V, 5A and 1.5V, ꢁA
3070fa
ꢁꢄ
LT3070
pAckAge Description
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(ReferenceꢀLTCꢀDWGꢀ#ꢀ05-08-1712ꢀRevꢀB)
0.70 p0.05
4.50 p 0.05
3.10 p 0.05
2.50 REF
2.65 p 0.05
3.65 p 0.05
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
3.50 REF
4.10 p 0.05
5.50 p 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.35
s 45o CHAMFER
2.50 REF
R = 0.115
TYP
R = 0.05
TYP
0.75 p 0.05
4.00 p 0.10
(2 SIDES)
27
28
0.40 p 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 p 0.10
(2 SIDES)
3.50 REF
3.65 p 0.10
2.65 p 0.10
(UFD28) QFN 0506 REV B
0.25 p 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3070fa
ꢁꢅ
LT3070
revision history
REV
DATE
DESCRIPTION
PAGE NUMBER
A
5/10
Entireꢀdataꢀsheetꢀrevised
1ꢀtoꢀ28
3070fa
InformationꢀfurnishedꢀbyꢀLinearꢀTechnologyꢀCorporationꢀisꢀbelievedꢀtoꢀbeꢀaccurateꢀandꢀreliable.ꢀ
However,ꢀnoꢀresponsibilityꢀisꢀassumedꢀforꢀitsꢀuse.ꢀLinearꢀTechnologyꢀCorporationꢀmakesꢀnoꢀrepresenta-
tionꢀthatꢀtheꢀinterconnectionꢀofꢀitsꢀcircuitsꢀasꢀdescribedꢀhereinꢀwillꢀnotꢀinfringeꢀonꢀexistingꢀpatentꢀrights.
ꢁꢆ
LT3070
typicAl ApplicAtion
50k
V
BIAS
PWRGD
2.5V TO 3.6V
2.2µF
BIAS
V
IN
IN
PWRGD
SENSE
1.5V
330µF
EN
V
1.2V
5A
OUT
LT3070
OUT
V
O0
V
O1
V
O2
2.2µF*
4.7µF*
10µF*
NC
NC
MARGSEL
MARGTOL
VIOC
*X5R OR X7R CAPACITORS
REF/BYP
GND
1nF
0.01µF
3070 TA02
1.5V to 1.2V Linear Regulator
relAteD pArts
PART
DESCRIPTION
COMMENTS
LT1763
500mA,ꢀLowꢀNoiseꢀLDO
300mVꢀDropoutꢀVoltage,ꢀLowꢀNoise:ꢀ20µV
,ꢀV :ꢀ1.8Vꢀtoꢀ20V,ꢀ
RMS IN
SO-8ꢀPackage
LT1764/LT1764A
LT1963/LT1963A
3A,ꢀFastꢀTransientꢀResponse,ꢀLowꢀNoiseꢀLDO
1.5AꢀLowꢀNoise,ꢀFastꢀTransientꢀResponseꢀLDO
340mVꢀDropoutꢀVoltage,ꢀLowꢀNoise:ꢀ40µV
,ꢀV :ꢀ2.7Vꢀtoꢀ20V,ꢀꢀ
RMS IN
TO-220ꢀandꢀDDꢀPackagesꢀ“A”ꢀVersionꢀStableꢀAlsoꢀwithꢀCeramicꢀCaps
340mVꢀDropoutꢀVoltage,ꢀLowꢀNoise:ꢀ40µV
,ꢀV :ꢀ2.5Vꢀtoꢀ20V,ꢀꢀ
RMS IN
“A”ꢀVersionꢀStableꢀwithꢀCeramicꢀCaps,ꢀTO-220,ꢀDD,ꢀSOT-223ꢀandꢀ
SO-8ꢀPackages
LT1965
LT3021
1.1A,ꢀLowꢀNoise,ꢀLowꢀDropoutꢀLinearꢀRegulator
500mA,ꢀLowꢀVoltage,ꢀVLDO™ꢀLinearꢀRegulator
290mVꢀDropoutꢀVoltage,ꢀLowꢀNoise:ꢀ40µV
,ꢀV :ꢀ1.8Vꢀtoꢀ20V,ꢀ
RMS IN
V
:ꢀ1.2Vꢀtoꢀ19.5V,ꢀStableꢀwithꢀCeramicꢀCaps,ꢀTO-220,ꢀDD-Pak,ꢀ
OUTꢀ
MSOPꢀandꢀ3mmꢀ×ꢀ3mmꢀDFNꢀPackages
V :ꢀ0.9Vꢀtoꢀ10V,ꢀDropoutꢀVoltageꢀ=ꢀ160mVꢀ(Typ),ꢀAdjustableꢀOutputꢀ
IN
REF
(V ꢀ=ꢀV
ꢀ=ꢀ200mV),ꢀFixedꢀOutputꢀVoltages:ꢀ1.2V,ꢀ1.5V,ꢀ1.8V,ꢀ
OUT(MIN)
StableꢀwithꢀLowꢀESR,ꢀCeramicꢀOutputꢀCapacitorsꢀ16-PinꢀDFNꢀꢀ
(5mmꢀ×ꢀ5mm)ꢀandꢀ8-LeadꢀSOꢀPackages
LT3080/LT3080-1
LT3085
1.1A,ꢀParallelable,ꢀLowꢀNoise,ꢀLowꢀDropoutꢀLinearꢀRegulator 300mVꢀDropoutꢀVoltageꢀ(2-SupplyꢀOperation),ꢀLowꢀNoise:ꢀ40µV
,ꢀ
,ꢀ
RMS
V :ꢀ1.2Vꢀtoꢀ36V,ꢀV :ꢀ0Vꢀtoꢀ35.7V,ꢀCurrent-BasedꢀReferenceꢀwithꢀ
IN
OUTꢀ
1ꢀResistorꢀV ꢀSet;ꢀDirectlyꢀParallelableꢀ(NoꢀOpꢀAmpꢀRequired),ꢀ
OUT
StableꢀwithꢀCeramicꢀCaps,ꢀTO-220,ꢀSOT-223,ꢀMSOP-8ꢀandꢀ3mmꢀ
×ꢀ3mmꢀDFN-8ꢀPackages;ꢀLT3080-1ꢀhasꢀIntegratedꢀInternalꢀBallastꢀ
Resistor
500mA,ꢀParallelable,ꢀLowꢀNoise,ꢀLowꢀDropoutꢀꢀ
LinearꢀRegulator
275mVꢀDropoutꢀVoltageꢀ(2-SupplyꢀOperation),ꢀLowꢀNoise:ꢀ40µV
RMS
V :ꢀ1.2Vꢀtoꢀ36V,ꢀV :ꢀ0Vꢀtoꢀ35.7V,ꢀCurrent-BasedꢀReferenceꢀwithꢀ
IN
OUTꢀ
1ꢀResistorꢀV ꢀSet;ꢀDirectlyꢀParallelableꢀ(NoꢀOpꢀAmpꢀRequired),ꢀ
OUT
StableꢀwithꢀCeramicꢀCaps,ꢀMSOP-8ꢀandꢀ2mmꢀ×ꢀ3mmꢀDFN-6ꢀ
Packages
LTC3025-1/ꢀ
LTC3025-2
500mAꢀMicropowerꢀVLDOꢀLinearꢀRegulatorꢀꢀ
inꢀ2mmꢀ×ꢀ2mmꢀDFNꢀ
V ꢀ=ꢀ0.9Vꢀtoꢀ5.5V,ꢀDropoutꢀVoltage:ꢀ75mV,ꢀLowꢀNoiseꢀ80µV
,ꢀ
IN
RMS
LowꢀI :ꢀ54µA,ꢀFixedꢀOutput:ꢀ1.2Vꢀ(LTC3025-2);ꢀAdjustableꢀOutputꢀ
Q
Range:ꢀ0.4Vꢀtoꢀ3.6Vꢀ(LTC3025-1)ꢀ2mmꢀ×ꢀ2mmꢀ6-LeadꢀDFNꢀPackage
LTC3026ꢀ
1.5A,ꢀLowꢀInputꢀVoltageꢀVLDOꢀRegulatorꢀ
V :ꢀ1.14Vꢀtoꢀ3.5Vꢀ(BoostꢀEnabled),ꢀ1.14Vꢀtoꢀ5.5Vꢀ(withꢀExternalꢀ
IN
5V),ꢀV ꢀ=ꢀ0.1V,ꢀI ꢀ=ꢀ950µA,ꢀStableꢀwithꢀ10µFꢀCeramicꢀCapacitors,ꢀ
DO
Q
10-LeadꢀMSOPꢀandꢀDFN-10ꢀPackages
3070fa
LT 0510 REV A • PRINTED IN USA
Linear Technology Corporation
1630ꢀ McCarthyꢀ Blvd.,ꢀ Milpitas,ꢀ CAꢀ 95035-7417
ꢀ
ꢁꢇ
●
●ꢀ
LINEAR TECHNOLOGY CORPORATION 2009
(408)ꢀ432-1900ꢀ ꢀFAX:ꢀ(408)ꢀ434-0507ꢀ www.linear.com
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