LT3407IMSE-2#TRPBF_技术文档

LTC3407-2

Dual Synchronous, 800mA,

2.25MHz Step-Down

DC/DC Regulator

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DESCRIPTIO

FEATURES

The LTC^®3407-2 is a dual, constant frequency, synchro-

nous step down DC/DC converter. Intended for low power

applications, it operates from 2.5V to 5.5V input voltage

range and has a constant 2.25MHz switching frequency,

allowing the use of tiny, low cost capacitors and inductors

with a profile ≤1.2mm. Each output voltage is adjustable

from 0.6V to 5V. Internal synchronous 0.35Ω, 1.2A power

switches provide high efficiency without the need for

external Schottky diodes.

■

High Efficiency: Up to 95%

Very Low Quiescent Current: Only 40μA

2.25MHz Constant Frequency Operation

High Switch Current: 1.2A on Each Channel

No Schottky Diodes Required

Low R_DS(ON)Internal Switches: 0.35Ω

Current Mode Operation for Excellent Line

■

and Load Transient Response

Short-Circuit Protected

Low Dropout Operation: 100% Duty Cycle

Ultralow Shutdown Current: I_Q< 1μA

Output Voltages from 5V down to 0.6V

Power-On Reset Output

Externally Synchronizable Oscillator

■

A user selectable mode input is provided to allow the user

to trade-off noise ripple for low power efficiency. Burst

Mode^®operation provides high efficiency at light loads,

while Pulse Skip Mode provides low noise ripple at light

loads.

■

Small Thermally Enhanced MSOP and 3mm × 3mm

To further maximize battery life, the P-channel MOSFETs

are turned on continuously in dropout (100% duty cycle),

and both channels draw a total quiescent current of only

40μA. In shutdown, the device draws <1μA.

DFN Packages

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APPLICATIO S

■

PDAs/Palmtop PCs

■

, LT, LTC, LTM, and Burst Mode are registered trademarks of Linear Technology

Corporation. All other trademarks are the property of their respective owners.

Digital Cameras

Cellular Phones

Portable Media Players

PC Cards

■

Wireless and DSL Modems

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TYPICAL APPLICATIO

V

= 2.5V*

TO 5.5V

LTC3407-2 Efficiency Curve

IN

R5

100

C1

100k

10μF

RUN2

V

RUN1

POR

IN

95

90

85

80

75

70

65

60

2.5V

MODE/SYNC

RESET

1.8V

LTC3407-2

L2

L1

2.2μH

V

= 2.5V

OUT2

AT 800mA

V

= 1.8V

OUT1

SW2

SW1

AT 800mA

C5, 22pF

C4, 22pF

V

FB1

FB2

R4

887k

R2

604k

GND

C3

10μF

C2

10μF

V

= 3.3V

R3

280k

R1

301k

IN

Burst Mode OPERATION

NO LOAD ON OTHER CHANNEL

1

10

100

1000

3407 TA01

C1, C2, C3: TAIYO YUDEN JMK316BJ106ML

L1, L2: MURATA LQH32CN2R2M33

LOAD CURRENT (mA)

*V CONNECTED TO V FOR V ≤ 2.8V

OUT

IN IN

3407 TA02

Figure 1. 2.5V/1.8V at 800mA Step-Down Regulators

34072fa

1

LTC3407-2

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ABSOLUTE AXI U RATI GS

(Note 1)

Ambient Operating Temperature Range (Note 2)

LTC3407E-2........................................ –40°C to 85°C

LTC3407I-2 ...................................... –40°C to 125°C

Junction Temperature (Note 5)............................. 125°C

Storage Temperature Range ................. – 65°C to 150°C

Lead Temperature (Soldering, 10 sec)

V_INVoltages.................................................–0.3V to 6V

V_FB1, V_FB2, RUN1, RUN2

Voltages ..................................... –0.3V to V_IN+ 0.3V

MODE/SYNC Voltage ...................... –0.3V to V_IN+ 0.3V

SW1, SW2 Voltage ......................... –0.3V to V_IN+ 0.3V

POR Voltage ................................................–0.3V to 6V

MSE Package Only ........................................... 300°C

Reflow Peak Body Temperature............................ 260°C

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PI CO FIGURATIO

TOP VIEW

V

1

2

3

4

5

10

9

V

FB2

RUN2

POR

SW2

MODE/

SYNC

V

1

2

3

4

5

10

9

V

FB2

FB1

RUN1

RUN2

V

SW1

GND

11

8

IN

11

V

8

POR

SW2

7

6

IN

SW1

GND

7

6

MODE/

SYNC

MSE PACKAGE

10-LEAD PLASTIC MSOP

DD PACKAGE

10-LEAD (3mm × 3mm) PLASTIC DFN

MSE PIN 11, EXPOSED PAD: PGND

MUST BE CONNECTED TO GND

DD PIN 11, EXPOSED PAD: PGND

MUST BE CONNECTED TO GND

T_JMAX= 125°C, θ_JA= 45°C/W, θ_JC= 10°C/W

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ORDER I FOR ATIO

LEAD FREE FINISH

LT3407EDD-2#PBF

LT3407IDD-2#PBF

LT3407EMSE-2#PBF

LT3407IMSE-2#PBF

LEAD BASED FINISH

LT3407EDD-2

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

TEMPERATURE RANGE

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

LT3407EDD-2#TRPBF

LT3407IDD-2#TRPBF

LT3407EMSE-2#TRPBF

LT3407IMSE-2#TRPBF

TAPE AND REEL

LBFB

10-Lead (3mm x 3mm) Plastic DFN

10-Lead Plastic MSOP

LBFB

LTBDZ

PART MARKING*

LBFB

10-Lead Plastic MSOP

PACKAGE DESCRIPTION

LT3407EDD-2#TR

LT3407IDD-2#TR

10-Lead (3mm x 3mm) Plastic DFN

10-Lead Plastic MSOP

LT3407IDD-2

LBFB

LT3407EMSE-2

LT3407IMSE-2

LT3407EMSE-2#TR

LT3407IMSE-2#TR

LTBDZ

10-Lead Plastic MSOP

–40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is indicated by a label on the shipping container

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

34072fa

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LTC3407-2

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 3.6V, unless otherwise specified. (Note 2)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

5.5

UNITS

V

IN

Operating Voltage Range

Feedback Pin Input Current

Feedback Voltage (Note 3)

●

2.5

I

30

nA

FB

V

FB

0°C ≤ T ≤ 85°C

0.588

0.585

0.6

0.612

V

A

–40°C ≤ T ≤ 85°C

●

A

–40°C ≤ T ≤ 125°C (Note 2)

A

ΔV

Reference Voltage Line Regulation

Output Voltage Load Regulation

V

= 2.5V to 5.5V (Note 3)

0.3

0.5

%/V

%

LINE REG

IN

(Note 3)

LOAD REG

I

Input DC Supply Current

Active Mode

S

V

= V = 0.5V

700

40

0.1

950

60

1

μA

FB1

FB2

Sleep Mode

Shutdown

= V = 0.63V, MODE/SYNC = 3.6V

FB1

FB2

RUN = 0V, V = 5.5V, MODE/SYNC = 0V

IN

f

I

Oscillator Frequency

V

= 0.6V

FBX

●

1.8

2.25

1.2

2.7

MHz

A

OSC

SYNC

LIM

Synchronization Frequency

Peak Switch Current Limit

V

IN

= 3V, V

= 0.5V, Duty Cycle <35%

0.95

1.6

FBX

R

Top Switch On-Resistance

Bottom Switch On-Resistance

(Note 6)

0.35

0.30

0.45

Ω

DS(ON)

I

Switch Leakage Current

V

IN

= 5V, V

= 0V, V = 0V

FBX

0.01

1

μA

SW(LKG)

RUN

POR

Power-On Reset Threshold

V

FBX

V

FBX

Ramping Up, MODE/SYNC = 0V

Ramping Down, MODE/SYNC = 0V

8.5

–8.5

%

Power-On Reset On-Resistance

Power-On Reset Delay

RUN Threshold

100

262,144

1

200

Ω

Cycles

V

I

●

0.3

1.5

1

RUN

RUN Leakage Current

0.01

μA

RUN

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: The LTC3407-2 is tested in a proprietary test mode that connects

to the output of the error amplifier.

Note 4: Dynamic supply current is higher due to the internal gate charge

V

FB

being delivered at the switching frequency.

Note 2: The 5LTC3407E-2 is guaranteed to meet specified performance

from 0°C to 70°C. Specifications over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls. The LTC3407I-2 is guaranteed over the

full –40°C to 125°C operating temperature range.

Note 5: T is calculated from the ambient T and power dissipation P

D

J

A

according to the following formula: T = T + (P • θ ).

J

A

D

JA

Note 6: The DFN switch on-resistance is guaranteed by correlation to

wafer level measurements.

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TYPICAL PERFOR A CE CHARACTERISTICS ^T_A^{= 25°C unless other wise specified.}

Load Step

Burst Mode Operation

Pulse Skipping Mode

SW

5V/DIV

SW

5V/DIV

V

OUT

200mV/DIV

V

I

L

OUT

100mV/DIV

10mV/DIV

500mA/DIV

I

L

I

LOAD

500mA/DIV

L

200mA/DIV

3407 G01

3407 G02

3407 G03

V

LOAD

= 3.6V

V

LOAD

= 3.6V

V

= 3.6V

IN

2μs/DIV

1μs/DIV

20μs/DIV

IN

= 1.8V

V

= 1.8V

OUT

I

= 100mA

I

= 20mA

I

LOAD

CIRCUIT OF FIGURE 1

= 80mA TO 800mA

CIRCUIT OF FIGURE 1

34072fa

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LTC3407-2

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TYPICAL PERFOR A CE CHARACTERISTICS ^T_A^{= 25°C unless other wise specified.}

Oscillator Frequency vs Supply

Voltage

Oscillator Frequency vs

Temperature

Efficiency vs Input Voltage

100

95

90

85

80

75

70

65

60

2.5

2.4

2.3

2.2

2.1

2.0

10

8

V

= 3.6V

IN

6

100mA

10mA

1mA

4

2

800mA

0

–2

–4

–6

–8

–10

V

= 1.8V

OUT

Burst Mode OPERATION

CIRCUIT OF FIGURE 1

4

5

6

50

TEMPERATURE (°C)

100 125

4

5

6

2

3

–50 –25

0

25

75

2

3

INPUT VOLTAGE (V)

SUPPLY VOLTAGE (V)

3407 G04

3407 G05

3407 G06

Reference Voltage vs

Temperature

R_DS(ON)vs Input Voltage

R_DS(ON)vs Temperature

0.615

0.610

0.605

0.600

0.595

0.590

0.585

500

450

400

350

300

250

200

550

500

450

400

350

300

250

200

150

100

V

= 3.6V

V

= 2.7V

IN

T

= 25°C

IN

A

V

= 3.6V

IN

V

= 4.2V

IN

MAIN

SWITCH

SYNCHRONOUS

SWITCH

MAIN SWITCH

SYNCHRONOUS SWITCH

3

2

50

TEMPERATURE (°C)

100 125

5

7

50

TEMPERATURE (°C)

100 125 150

–50 –25

0

25

75

1

4

6

–50 –25

0

25

75

V

(V)

IN

3407 G07

3407 G08

3407 G09

Load Regulation

Efficiency vs Load Current

4

3

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

2.7V

3.6V

4.2V

Burst Mode OPERATION

2

1

0

PULSE SKIP MODE

–1

–2

–3

–4

PULSE SKIP MODE

V

= 2.5V

OUT

Burst Mode OPERATION

NO LOAD ON OTHER CHANNEL

CIRCUIT OF FIGURE 1

V

= 3.6V, V

= 1.8V

OUT

IN

V

= 3.6V, V

= 1.8V

OUT

IN

NO LOAD ON OTHER CHANNEL

1

10

100

1000

1

10

100

1000

1

10

100

1000

LOAD CURRENT (mA)

3407 G12

3407 G10

3407 G11

34072fa

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LTC3407-2

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TYPICAL PERFOR A CE CHARACTERISTICS ^T_A^{= 25°C unless other wise specified.}

Efficiency vs Load Current

Line Regulation

Efficiency vs Load Current

0.5

0.4

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

V

= 1.8V

OUT

I

= 200mA

3.6V

T

= 25°C

A

0.3

3.6V

2.7V

4.2V

0.2

0.1

0

4.2V

–0.1

–0.2

–0.3

–0.4

–0.5

V

= 1.2V

V

= 1.5V

OUT

Burst Mode OPERATION

NO LOAD ON OTHER CHANNEL

CIRCUIT OF FIGURE 1

Burst Mode OPERATION

NO LOAD ON OTHER CHANNEL

CIRCUIT OF FIGURE 1

2

6

1

10

100

1000

1

10

100

1000

3

4

5

V

(V)

LOAD CURRENT (mA)

IN

3407 G15

3407 G13

3407 G14

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PI FU CTIO S

V_FB1(Pin 1): Output Feedback. Receives the feedback

voltage from the external resistive divider across the

output. Nominal voltage for this pin is 0.6V.

be syncronized to an external oscillator applied to this pin

and pulse skipping mode is automatically selected.

SW2 (Pin 7): Regulator 2 Switch Node Connection to the

RUN1 (Pin 2): Regulator 1 Enable. Forcing this pin to V_IN

enables regulator 1, while forcing it to GND causes regu-

lator 1 to shut down.

Inductor. This pin swings from V_INto GND.

POR (Pin 8): Power-On Reset . This common-drain logic

output is pulled to GND when the output voltage is not

within 8.5% of regulation and goes high after 117ms

when both channels are within regulation.

V_IN(Pin3):MainPowerSupply.Mustbecloselydecoupled

to GND.

SW1 (Pin 4): Regulator 1 Switch Node Connection to the

Inductor. This pin swings from V_INto GND.

RUN2 (Pin 9): Output Feedback. Forcing this pin to V_IN

enables regulator 2, while forcing it to GND causes regu-

lator 2 to shut down.

GND (Pin 5): Main Ground. Connect to the (–) terminal of

C

_OUT, and (–) terminal of C_IN.

V_FB2(Pin 10): Output Feedback. Receives the feedback

voltage from the external resistive divider across the

output. Nominal voltage for this pin is 0.6V.

MODE/SYNC (Pin 6): Combination Mode Selection and

OscillatorSynchronization.Thispincontrolstheoperation

of the device. When tied to V_INor GND, Burst Mode

operation or pulse skipping mode is selected, respec-

tively. Do not float this pin. The oscillation frequency can

Exposed Pad (GND) (Pin 11): Power Ground. Connect to

the (–) terminal of C_OUT, and (–) terminal of C_IN. Must be

connected to electrical ground on PCB.

34072fa

5

LTC3407-2

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BLOCK DIAGRA

REGULATOR 1

MODE/SYNC

6

BURST

CLAMP

V

IN

SLOPE

COMP

EN

–

+

–

0.6V

SLEEP

–

+

I

TH

5Ω

EA

I

COMP

0.35V

V

FB1

1

BURST

Q

S

R

RS

LATCH

Q

0.55V

–

+

SWITCHING

LOGIC

UV

OV

UVDET

OVDET

AND

BLANKING

CIRCUIT

ANTI

SHOOT-

THRU

4

SW1

+

–

0.65V

+

–

I

RCMP

SHUTDOWN

11 GND

V

IN

3

8

V

IN

PGOOD1

POR

2

9

RUN1

RUN2

POR

COUNTER

0.6V REF

OSC

5

7

GND

PGOOD2

REGULATOR 2 (IDENTICAL TO REGULATOR 1)

10

SW2

V

FB2

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OPERATIO

Main Control Loop

The LTC3407-2 uses a constant frequency, current mode

architecture. The operating frequency is set at 2.25MHz

and can be synchronized to an external oscillator. Both

channels share the same clock and run in-phase. To suit

a variety of applications, the selectable Mode pin allows

the user to choose between low noise and high efficiency.

Duringnormaloperation,thetoppowerswitch(P-channel

MOSFET) is turned on at the beginning of a clock cycle

when the V_FBvoltage is below the the reference voltage.

The current into the inductor and the load increases until

the current limit is reached. The switch turns off and

energy stored in the inductor flows through the bottom

switch (N-channel MOSFET) into the load until the next

clock cycle.

The output voltage is set by an external divider returned to

the V_FBpins. An error amplfier compares the divided

outputvoltagewithareferencevoltageof0.6Vandadjusts

the peak inductor current accordingly. Overvoltage and

undervoltage comparators will pull the POR output low if

the output voltage is not within 8.5%. The POR output

will go high after 262,144 clock cycles (about 117ms) of

achieving regulation.

The peak inductor current is controlled by the internally

compensated I_THvoltage, which is the output of the error

amplifier.This amplifier compares the V_FBpin to the 0.6V

reference. When the load current increases, the V_FBvolt-

age decreases slightly below the reference. This

34072fa

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LTC3407-2

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OPERATIO

decrease causes the error amplifier to increase the I_THFor lower ripple noise at low currents, the pulse skipping

voltageuntiltheaverageinductorcurrentmatchesthenew modecanbeused. Inthismode, theLTC3407-2continues

to switch at a constant frequency down to very low

currents, where it will begin skipping pulses. The effi-

ciency in pulse skip mode can be improved slightly by

connecting the SW node to the MODE/SYNC input which

reduces the clock frequency by approximately 30%.

load current.

The main control loop is shut down by pulling the RUN pin

to ground.

Low Current Operation

Two modes are available to control the operation of the

LTC3407-2 at low currents. Both modes automatically

switch from continuous operation to the selected mode

when the load current is low.

Dropout Operation

When the input supply voltage decreases toward the

output voltage, the duty cycle increases to 100% which is

the dropout condition. In dropout, the PMOS switch is

turned on continuously with the output voltage being

equal to the input voltage minus the voltage drops across

the internal p-channel MOSFET and the inductor.

To optimize efficiency, the Burst Mode operation can be

selected. When the load is relatively light, the LTC3407-2

automatically switches into Burst Mode operation, in

which the PMOS switch operates intermittently based on

load demand with a fixed peak inductor current. By run-

ning cycles periodically, the switching losses which are

dominatedbythegatechargelossesofthepowerMOSFETs

are minimized. The main control loop is interrupted when

the output voltage reaches the desired regulated value. A

hysteretic voltage comparator trips when I_THis below

0.35V, shuttingofftheswitchandreducingthepower. The

output capacitor and the inductor supply the power to the

load until I_THexceeds 0.65V, turning on the switch and the

main control loop which starts another cycle.

An important design consideration is that the R_DS(ON)of

the P-channel switch increases with decreasing input

supplyvoltage(SeeTypicalPerformanceCharacteristics).

Therefore, the user should calculate the power dissipation

when the LTC3407-2 is used at 100% duty cycle with low

input voltage (See Thermal Considerations in the Applica-

tions Information Section).

Low Supply Operation

To prevent unstable operation, the LTC3407-2 incorpo-

rates an Under-Voltage Lockout circuit which shuts down

the part when the input voltage drops below about 1.65V.

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APPLICATIO S I FOR ATIO

Accepting larger values of ΔI_Lallows the use of low

inductances, but results in higher output voltage ripple,

greater core losses, and lower output current capability.

A reasonable starting point for setting ripple current is

ΔI_L= 0.3 • I_LIM, where I_LIMis the peak switch current limit.

The largest ripple current ΔI_Loccurs at the maximum

input voltage. To guarantee that the ripple current stays

below a specified maximum, the inductor value should be

chosen according to the following equation:

A general LTC3407-2 application circuit is shown in

Figure 2. External component selection is driven by the

load requirement, and begins with the selection of the

inductor L. Once the inductor is chosen, C_INand C_OUTcan

be selected.

Inductor Selection

Although the inductor does not influence the operating

frequency, the inductor value has a direct effect on ripple

current. The inductor ripple current ΔI_Ldecreases with

⎛

⎞

V_OUT

higher inductance and increases with higher V_INor V_OUT

:

L =

• 1–

⎜

⎟

f_O• ΔI_L

V

IN(MAX)

⎝

⎠

⎛

⎞

V_OUT

f_O•L

V_OUT

ΔI_L=

• 1–

⎜

⎟

The inductor value will also have an effect on Burst Mode

V

IN

⎝

⎠

operation. The transition from low current operation

34072fa

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LTC3407-2

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APPLICATIO S I FOR ATIO

Table 1. Representative Surface Mount Inductors

begins when the peak inductor current falls below a level

set by the burst clamp. Lower inductor values result in

higher ripple current which causes this to occur at lower

load currents. This causes a dip in efficiency in the upper

range of low current operation. In Burst Mode operation,

lower inductance values will cause the burst frequency to

increase.

PART

VALUE

DCR

MAX DC

SIZE

3

NUMBER

(μH)

(Ω MAX) CURRENT (A) W × L × H (mm )

Sumida

CDRH3D16

2.2

3.3

4.7

0.075

0.110

0.162

1.20

1.10

0.90

3.8 × 3.8 × 1.8

Sumida

CDRH2D11

1.5

2.2

0.068

0.170

0.900

0.780

3.2 × 3.2 × 1.2

4.4 × 5.8 × 1.2

2.5 × 3.2 × 2.0

4.5 × 5.4 × 1.2

Inductor Core Selection

Sumida

CMD4D11

2.2

3.3

0.116

0.174

0.950

0.770

Different core materials and shapes will change the size/

current and price/current relationship of an inductor.

Toroid or shielded pot cores in ferrite or permalloy mate-

rials are small and don’t radiate much energy, but gener-

ally cost more than powdered iron core inductors with

similar electrical characterisitics. The choice of which

style inductor to use often depends more on the price vs

size requirements and any radiated field/EMI require-

ments than on what the LTC3407-2 requires to operate.

Table 1 shows some typical surface mount inductors that

work well in LTC3407-2 applications.

Murata

LQH32CN

1.0

2.2

0.060

0.097

1.00

0.79

Toko

D312F

2.2

3.3

0.060

0.260

1.08

0.92

Panasonic

ELT5KT

3.3

4.7

0.17

0.20

1.00

0.95

Output Capacitor (C_OUT) Selection

The selection of C_OUTis driven by the required ESR to

minimizevoltagerippleandloadsteptransients.Typically,

once the ESR requirement is satisfied, the capacitance is

adequate for filtering. The output ripple (ΔV_OUT) is deter-

mined by:

Input Capacitor (C_IN) Selection

In continuous mode, the input current of the converter is

a square wave with a duty cycle of approximately V_OUT

/

V_IN. To prevent large voltage transients, a low equivalent

series resistance (ESR) input capacitor sized for the maxi-

mum RMS current must be used. The maximum RMS

capacitor current is given by:

⎛

⎞

1

ΔV_OUT≈ ΔI_LESR +

⎜

⎟

8f_OC_OUT

⎝

⎠

where f = operating frequency, C_OUT= output capacitance

and ΔI_L= ripple current in the inductor. The output ripple

is highest at maximum input voltage since ΔI_Lincreases

with input voltage. With ΔI_L= 0.3 • I_LIMthe output ripple

willbelessthan100mVatmaximumV_INandf_O=2.25MHz

with:

V_OUT(V – V_OUT

)

IN

I_RMS≈ I_MAX

V

IN

where the maximum average output current I_MAXequals

the peak current minus half the peak-to-peak ripple cur-

rent, I_MAX= I_LIM– ΔI_L/2.

ESR_COUT< 150mΩ

This formula has a maximum at V_IN= 2V_OUT, where I_RMS

= I_OUT/2. This simple worst-case is commonly used to

design because even significant deviations do not offer

much relief. Note that capacitor manufacturer’s ripple

current ratings are often based on only 2000 hours life-

time. This makes it advisable to further derate the capaci-

tor, or choose a capacitor rated at a higher temperature

thanrequired. Severalcapacitorsmayalsobeparalleledto

meet the size or height requirements of the design. An

additional 0.1μF to 1μF ceramic capacitor is also recom-

mended on V_INfor high frequency decoupling, when not

using an all ceramic capacitor solution.

Once the ESR requirements for C_OUThave been met, the

RMS current rating generally far exceeds the I_RIPPLE(P-P)

requirement, except for an all ceramic solution.

In surface mount applications, multiple capacitors may

have to be paralleled to meet the capacitance, ESR or RMS

current handling requirement of the application. Alumi-

numelectrolytic,specialpolymer,ceramicanddrytantulum

capacitorsareallavailableinsurfacemountpackages.The

OS-CONsemiconductordielectriccapacitoravailablefrom

Sanyo has the lowest ESR(size) product of any aluminum

electrolytic at a somewhat higher price. Special polymer

34072fa

8

LTC3407-2

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APPLICATIO S I FOR ATIO

capacitors, such as Sanyo POSCAP, Panasonic Special

Polymer (SP), and Kemet A700, offer very low ESR, but

have a lower capacitance density than other types. Tanta-

lum capacitors have the highest capacitance density, but

they have a larger ESR and it is critical that the capacitors

are surge tested for use in switching power supplies. An

excellent choice is the AVX TPS series of surface mount

tantalums, available in case heights ranging from 2mm to

4mm. Aluminum electrolytic capacitors have a signifi-

cantly larger ESR, and are often used in extremely cost-

sensitiveapplicationsprovidedthatconsiderationisgiven

to ripple current ratings and long term reliability. Ceramic

capacitorshavethelowestESRandcost, butalsohavethe

lowest capacitance density, a high voltage and tempera-

ture coefficient, and exhibit audible piezoelectric effects.

In addition, the high Q of ceramic capacitors along with

trace inductance can lead to significant ringing.

requires the designer to check loop stability over the

operating temperature range. To minimize their large

temperature and voltage coefficients, only X5R or X7R

ceramic capacitors should be used. A good selection of

ceramic capacitors is available from Taiyo Yuden, AVX,

Kemet, TDK, and Murata.

Great care must be taken when using only ceramic input

and output capacitors. When a ceramic capacitor is used

at the input and the power is being supplied through long

wires,suchasfromawalladapter,aloadstepattheoutput

can induce ringing at the V_INpin. At best, this ringing can

couple to the output and be mistaken as loop instability. At

worst, the ringing at the input can be large enough to

damage the part.

Since the ESR of a ceramic capacitor is so low, the input

and output capacitor must instead fulfill a charge storage

requirement.Duringaloadstep,theoutputcapacitormust

instantaneously supply the current to support the load

untilthefeedbackloopraisestheswitchcurrentenoughto

support the load. The time required for the feedback loop

to respond is dependent on the compensation and the

output capacitor size. Typically, 3-4 cycles are required to

respond to a load step, but only in the first cycle does the

output drop linearly. The output droop, V_DROOP, is usually

about 2-3 times the linear drop of the first cycle. Thus, a

good place to start is with the output capacitor size of

approximately:

In most cases, 0.1μF to 1μF of ceramic capacitors should

also be placed close to the LTC3407-2 in parallel with the

main capacitors for high frequency decoupling.

V = 2.5V

IN

TO 5.5V

C

R5

IN

RUN2

V

RUN1

POR

IN

BM*

POWER-ON

RESET

MODE/SYNC

PS*

LTC3407-2

L1

L2

V

OUT2

SW2

SW1

V

OUT1

C5

R4

C4

R2

V

FB1

V

FB2

GND

R1

C

OUT1

C

R3

OUT2

ΔI_OUT

f_O•V_DROOP

C_OUT≈ 2.5

3407 F02

*MODE/SYNC = 0V: PULSE SKIP

MODE/SYNC = V : Burst Mode

IN

More capacitance may be required depending on the duty

cycle and load step requirements.

Figure 2. LTC3407-2 General Schematic

Ceramic Input and Output Capacitors

In most applications, the input capacitor is merely re-

quired to supply high frequency bypassing, since the

impedance to the supply is very low. A 10μF ceramic

capacitor is usually enough for these conditions.

Higher value, lower cost ceramic capacitors are now

becomingavailableinsmallercasesizes.Thesearetempt-

ing for switching regulator use because of their very low

ESR. Unfortunately, the ESR is so low that it can cause

loop stability problems. Solid tantalum capacitor ESR

generatesaloop“zero”at5kHzto50kHzthatisinstrumen-

tal in giving acceptable loop phase margin. Ceramic ca-

pacitors remain capacitive to beyond 300kHz and usually

resonate with their ESL before ESR becomes effective.

Also, ceramic caps are prone to temperature effects which

Setting the Output Voltage

The LTC3407-2 develops a 0.6V reference voltage be-

tween the feedback pin, V_FB, and the ground as shown in

Figure 2. The output voltage is set by a resistive divider

according to the following formula:

34072fa

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LTC3407-2

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APPLICATIO S I FOR ATIO

Checking Transient Response

⎛

⎞

R2

R1

V_OUT= 0.6V 1+

⎜

⎟

The regulator loop response can be checked by looking at

the load transient response. Switching regulators take

several cycles to respond to a step in load current. When

a load step occurs, V_OUTimmediately shifts by an amount

equal to ΔI_LOAD• ESR, where ESR is the effective series

resistance of C_OUT. ΔI_LOADalso begins to charge or

discharge C_OUT, generating a feedback error signal used

by the regulator to return V_OUTto its steady-state value.

During this recovery time, V_OUTcan be monitored for

overshoot or ringing that would indicate a stability

problem.

⎝

⎠

Keeping the current small (<5μA) in these resistors maxi-

mizes efficiency, but making them too small may allow

stray capacitance to cause noise problems and reduce the

phase margin of the error amp loop.

To improve the frequency response, a feed-forward ca-

pacitor C_Fmay also be used. Great care should be taken to

route the V_FBline away from noise sources, such as the

inductor or the SW line.

The initial output voltage step may not be within the

bandwidth of the feedback loop, so the standard second-

order overshoot/DC ratio cannot be used to determine

phase margin. In addition, a feed-forward capacitor, C_F,

can be added to improve the high frequency response, as

shown in Figure 2. Capacitor C_Fprovides phase lead by

creating a high frequency zero with R2, which improves

the phase margin.

Power-On Reset

The POR pin is an open-drain output which pulls low when

either regulator is out of regulation. When both output

voltages are within 8.5% of regulation, a timer is started

which releases POR after 2¹⁸clock cycles (about 117ms).

This delay can be significantly longer in Burst Mode

operation with low load currents, since the clock cycles

only occur during a burst and there could be milliseconds

of time between bursts. This can be bypassed by tying the

POR output to the MODE/SYNC input, to force pulse

skipping mode during a reset. In addition, if the output

voltage faults during Burst Mode sleep, POR could have a

slight delay for an undervoltage output condition and may

notrespondtoanovervoltageoutput. Thiscanbeavoided

by using pulse skipping mode instead. When either chan-

nel is shut down, the POR output is pulled low, since one

or both of the channels are not in regulation.

The output voltage settling behavior is related to the

stability of the closed-loop system and will demonstrate

the actual overall supply performance. For a detailed

explanation of optimizing the compensation components,

including a review of control loop theory, refer to Applica-

tion Note 76.

In some applications, a more severe transient can be

caused by switching in loads with large (>1μF) input

capacitors.Thedischargedinputcapacitorsareeffectively

put in parallel with C_OUT, causing a rapid drop in V_OUT. No

regulator can deliver enough current to prevent this prob-

Mode Selection & Frequency Synchronization

TheMODE/SYNCpinisamultipurposepinwhichprovides lem, if the switch connecting the load has low resistance

mode selection and frequency synchronization. Connect- and is driven quickly. The solution is to limit the turn-on

ing this pin to V_INenables Burst Mode operation, which speed of the load switch driver. A Hot Swap^TMcontroller is

provides the best low current efficiency at the cost of a designedspecificallyforthispurposeandusuallyincorpo-

higheroutputvoltageripple.Connectingthispintoground rates current limiting, short-circuit protection, and soft-

selects pulse skipping mode, which provides the lowest starting.

output ripple, at the cost of low current efficiency.

Efficiency Considerations

The LTC3407-2 can also be synchronized to an external

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

2.25MHz clock signal by the MODE/SYNC pin. During

synchronization, the mode is set to pulse skipping and the

topswitchturn-onissynchronizedtotherisingedgeofthe

external clock.

Hot Swap is registered trademark of Linear Technology Corporation.

34072fa

10

LTC3407-2

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APPLICATIO S I FOR ATIO

produce the most improvement. Percent efficiency can be

expressed as:

include these “system” level losses in the design of a

system. The internal battery and fuse resistance losses

can be minimized by making sure that C_INhas adequate

charge storage and very low ESR at the switching fre-

quency. Other losses including diode conduction losses

during dead-time and inductor core losses generally ac-

count for less than 2% total additional loss.

%Efficiency = 100% - (L1 + L2 + L3 + ...)

whereL1, L2, etc. aretheindividuallossesasapercentage

of input power.

Although all dissipative elements in the circuit produce

losses, 4 main sources usually account for most of the

losses in LTC3407-2 circuits: 1)V_INquiescent current, 2)

switching losses, 3) I²R losses, 4) other losses.

Thermal Considerations

In a majority of applications, the LTC3407-2 does not

dissipate much heat due to its high efficiency. However, in

applications where the LTC3407-2 is running at high

ambient temperature with low supply voltage and high

duty cycles, such as in dropout, the heat dissipated may

exceed the maximum junction temperature of the part. If

the junction temperature reaches approximately 150°C,

both power switches will turn off and the SW node will

become high impedance.

1) The V_INcurrent is the DC supply current given in the

Electrical Characteristics which excludes MOSFET driver

andcontrolcurrents.V_INcurrentresultsinasmall(<0.1%)

loss that increases with V_IN, even at no load.

2) The switching current is the sum of the MOSFET driver

and control currents. The MOSFET driver current results

fromswitchingthegatecapacitanceofthepowerMOSFETs.

Each time a MOSFET gate is switched from low to high to

low again, a packet of charge dQ moves from V_INto

ground. The resulting dQ/dt is a current out of V_INthat is

typically much larger than the DC bias current. In continu-

ousmode, I_GATECHG=f_O(Q_T+Q_B), whereQ_TandQ_Barethe

gate charges of the internal top and bottom MOSFET

switches. The gate charge losses are proportional to V_IN

and thus their effects will be more pronounced at higher

supply voltages.

3) I²R losses are calculated from the DC resistances of the

internal switches, R_SW, and external inductor, R_L. In

continuousmode,theaverageoutputcurrentflowsthrough

inductor L, but is “chopped” between the internal top and

bottom switches. Thus, the series resistance looking into

the SW pin is a function of both top and bottom MOSFET

R_DS(ON)and the duty cycle (DC) as follows:

To prevent the LTC3407-2 from exceeding the maximum

junction temperature, the user will need to do some

thermal analysis. The goal of the thermal analysis is to

determine whether the power dissipated exceeds the

maximum junction temperature of the part. The tempera-

ture rise is given by:

T_RISE= P_D• θ_JA

where P_Dis the power dissipated by the regulator and θ_JA

is the thermal resistance from the junction of the die to the

ambient temperature.

The junction temperature, T_J, is given by:

T_J= T_RISE+ T_AMBIENT

As an example, consider the case when the LTC3407-2 is

in dropout on both channels at an input voltage of 2.7V

with a load current of 800mA and an ambient temperature

of 70°C. From the Typical Performance Characteristics

graph of Switch Resistance, the R_DS(ON)resistance of the

main switch is 0.425Ω. Therefore, power dissipated by

each channel is:

R_SW= (R_DS(ON)TOP)(DC) + (R_DS(ON)BOT)(1 – DC)

The R_DS(ON)for both the top and bottom MOSFETs can be

obtained from the Typical Performance Characteristics

curves. Thus, to obtain I²R losses:

I²R losses = I_OUT2(R_SW+ R_L)

P_D= I²• R_DS(ON)= 272mW

4) Other ‘hidden’ losses such as copper trace and internal

battery resistances can account for additional efficiency

degradations in portable systems. It is very important to

The MS package junction-to-ambient thermal resistance,

θ_JA, is 45°C/W. Therefore, the junction temperature of the

34072fa

11

LTC3407-2

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APPLICATIO S I FOR ATIO

Board Layout Considerations

regulator operating in a 70°C ambient temperature is

approximately:

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC3407-2. These items are also illustrated graphically in

the layout diagram of Figure 3. Check the following in your

layout:

T_J= 2 • 0.272 • 45 + 70 = 94.5°C

which is below the absolute maximum junction tempera-

ture of 125°C.

Design Example

1. Does the capacitor C_INconnect to the power V_IN(Pin 3)

andGND(exposedpad)ascloseaspossible?Thiscapaci-

torprovidestheACcurrenttotheinternalpowerMOSFETs

and their drivers.

As a design example, consider using the LTC3407-2 in an

portable application with a Li-Ion battery. The battery

provides a V_IN= 2.8V to 4.2V. The load requires a maxi-

mum of 800mA in active mode and 2mA in standby mode.

The output voltage is V_OUT= 2.5V. Since the load still

needs power in standby, Burst Mode operation is selected

for good low load efficiency.

2. Are the C_OUTand L1 closely connected? The (–) plate of

C_OUTreturns current to GND and the (–) plate of C_IN.

3. The resistor divider, R1 and R2, must be connected

between the (+) plate of C_OUTand a ground sense line

terminatednearGND(exposedpad). Thefeedbacksignals

V_FBshould be routed away from noisy components and

traces, such as the SW line (Pins 4 and 7), and its trace

should be minimized.

First, calculate the inductor value for about 30% ripple

current at maximum V_IN:

⎛

⎞

2.5V

4.2V

L =

• 1–

= 1.5μH

⎜

⎟

2.25MHz • 300mA

⎝

⎠

4.KeepsensitivecomponentsawayfromtheSWpins.The

input capacitor C_INand the resistors R1 to R4 should be

routed away from the SW traces and the inductors.

Choosing a vendor’s closest inductor value of 2.2μH,

results in a maximum ripple current of:

5. Agroundplaneispreferred, butifnotavailable, keepthe

signal and power grounds segregated with small signal

components returning to the GND pin at one point and

⎛

⎞

2.5V

4.2V

ΔI_L=

• 1−

= 204mA

⎜

⎟

2.25MHz •2.2μ

⎝

⎠

should not share the high current path of C_INor C_OUT

.

For cost reasons, a ceramic capacitor will be used. C_OUT

selection is then based on load step droop instead of ESR

requirements. For a 5% output droop:

6. Flood all unused areas on all layers with copper.

Flooding with copper will reduce the temperature rise of

power components. These copper areas should be con-

nected to V_INor GND.

800mA

C_OUT≈ 2.5

= 7.1μF

2.25MHz •(5%•2.5V)

V

IN

C

A good standard value is 10μF. Since the output imped-

ance of a Li-Ion battery is very low, C_INis typically 10μF.

The output voltage can now be programmed by choosing

the values of R1 and R2. To maintain high efficiency, the

current in these resistors should be kept small. Choosing

2μA with the 0.6V feedback voltage makes R1~300k. A

close standard 1% resistor is 280k, and R2 is then 887k.

IN

RUN2

V

RUN1

POR

IN

MODE/SYNC

LTC3407-2

L1

C4

L2

V

OUT2

SW2

SW1

V

OUT1

C5

R4

V

FB2

FB1

R2

GND

R1

C

OUT1

C

OUT2

R3

The PGOOD pin is a common drain output and requires a

pull-upresistor.A100kresistorisusedforadequate speed.

3407 F03

BOLD LINES INDICATE HIGH CURRENT PATHS

Figure 1 shows the complete schematic for this design

example.

Figure 3. LTC3407-2 Layout Diagram (See Board Layout Checklist)

34072fa

12

LTC3407-2

U

TYPICAL APPLICATIO S

Low Ripple Buck Regulators Using Ceramic Capacitors

V

= 2.5V

IN

TO 5.5V

R5

100k

C1

10μF

RUN2

V

RUN1

POR

IN

POWER-ON

RESET

LTC3407-2

L2

L1

4.7μH

V

= 1.8V

V

= 1.2V

OUT2

OUT1

SW2

SW1

AT 800mA

C5, 22pF

C4, 22pF

V

FB1

FB2

R4

887k

R2

604k

MODE/SYNC GND

C3

10μF

C2

10μF

R3

442k

R1

604k

3407 TA03

C1, C2, C3: TAIYO YUDEN JMK316BJ106ML

L1, L2: SUMIDA CDRH2D18/HP-4R7NC

Efficiency vs Load Current

100

95

90

85

80

75

70

65

60

55

50

1.8V

1.2V

V

= 3.3V

IN

PULSE SKIP MODE

NO LOAD ON OTHER CHANNEL

10

100

1000

LOAD CURRENT (mA)

3407 TA03b

34072fa

13

LTC3407-2

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TYPICAL APPLICATIO S

2mm Height Core Supply

V

= 3.6V

IN

TO 5.5V

R5

100k

C1*

4.7μF

RUN2

V

RUN1

POR

IN

POWER-ON

RESET

MODE/SYNC

LTC3407-2

L2

L1

2.2μH

V

OUT2

= 3.3V

V

= 1.8V

OUT1

SW2

SW1

AT 800mA

C5, 22pF

C4, 22pF

V

FB2

FB1

R4

887k

R2

604k

C3

C2

GND

R3

196k

R1

301k

4.7μF

×2

3407 TA07

C1, C2, C3: TDK C1608X5ROJ475M

L1, L2: CMD4D11-2R2

*IF C1 IS GREATER THAN 3" FROM POWER SOURCE,

ADDITIONAL CAPACITANCE MAY BE REQUIRED.

Efficiency vs Load Current

100

95

90

85

80

75

70

65

60

3.3V

1.8V

V

= 5V

IN

Burst Mode OPERATION

NO LOAD ON OTHER CHANNEL

1

10

100

1000

LOAD CURRENT (mA)

3407 TA08

34072fa

14

LTC3407-2

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PACKAGE DESCRIPTIO

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699)

R = 0.115

TYP

6

0.38 0.10

10

0.675 0.05

3.50 0.05

2.15 0.05 (2 SIDES)

1.65 0.05

3.00 0.10

(4 SIDES)

1.65 0.10

(2 SIDES)

PIN 1

TOP MARK

(SEE NOTE 6)

PACKAGE

OUTLINE

(DD) DFN 1103

5

1

0.25 0.05

0.50 BSC

0.75 0.05

0.200 REF

0.25 0.05

0.50

BSC

2.38 0.05

(2 SIDES)

2.38 0.10

(2 SIDES)

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

MSE Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1664)

BOTTOM VIEW OF

EXPOSED PAD OPTION

2.06 0.102

3.00 0.102

(.118 .004)

(NOTE 3)

2.794 0.102

(.110 .004)

0.889 0.127

(.035 .005)

0.497 0.076

(.0196 .003)

REF

(.081 .004)

1

10 9

8

7 6

1.83 0.102

(.072 .004)

3.00 0.102

(.118 .004)

(NOTE 4)

5.23

(.206)

MIN

DETAIL “A”

0° – 6° TYP

4.90 0.152

(.193 .006)

2.083 0.102 3.20 – 3.45

(.082 .004) (.126 – .136)

0.254

(.010)

GAUGE PLANE

0.53 0.152

(.021 .006)

1

2

3

4

5

10

0.50

(.0197)

BSC

0.305 0.038

(.0120 .0015)

TYP

0.86

(.034)

REF

1.10

(.043)

MAX

RECOMMENDED SOLDER PAD LAYOUT

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 0.0508

(.004 .002)

0.50

(.0197)

BSC

MSOP (MSE) 0307 REV B

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

34072fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

15

LTC3407-2

U

TYPICAL APPLICATIO

2mm Height Lithium-Ion Single Inductor Buck-Boost Regulator and a Buck Regulator

V

= 2.8V

IN

TO 4.2V

R5

100k

C1

10μF

RUN2

V

RUN1

POR

IN

POWER-ON

RESET

MODE/SYNC

LTC3407-2

L2

10μH

L1

2.2μH

D1

V = 3.3V

OUT2

AT 200mA

V

= 1.8V

OUT1

SW2

SW1

AT 800mA

C5, 22pF

C4, 22pF

M1

+

C6

47μF

V

FB2

FB1

R4

887k

R2

604k

GND

C3

10μF

C2

10μF

R3

196k

R1

301k

3407 TA04

C1, C2, C3: TAIYO YUDEN JMK316BJ106ML

C6: SANYO 6TPB47M

D1: PHILIPS PMEG2010

L1: MURATA LQH32CN2R2M33

L2: TOKO A914BYW-100M (D52LC SERIES)

M1: SILICONIX Si2302

Efficiency vs Load Current

100

95

90

85

80

75

70

65

60

90

80

70

60

50

40

30

2.8V

4.2V

3.6V

4.2V

3.6V

2.8V

V

OUT

= 1.8V

V

OUT

= 3.3V

Burst Mode OPERATION

NO LOAD ON OTHER CHANNEL

NO LOD ON OTHER CHANNEL

1

10

100

1000

1

10

100

1000

LOAD CURRENT (mA)

3407 TA06

3407 TA05

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DESCRIPTION

COMMENTS

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600mA (I ), 550kHz,

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IN

OUT(MIN)

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<1μA, MSOP-8, Package

SD

LT1940

Dual Output 1.4A(I , Constant 1.1MHz,

V : 3V to 25V, V

= 1.2V, I = 2.5mA, I = <1μA,

OUT)

IN

OUT(MIN)

Q

SD

High Efficiency Step-Down DC/DC Converter

TSSOP-16E Package

LTC3252

Dual 250mA (I ), 1MHz, Spread Spectrum

88% Efficiency, V : 2.7V to 5.5V, V

Q SD

= 0.9V to 1.6V,

OUT

IN

OUT(MIN)

Inductorless Step-Down DC/DC Converter

I = 60μA, I < 1μA, DFN-12 Package

LTC3405/LTC3405A

LTC3406/LTC3406B

LT3407

300mA (I ), 1.5MHz,

96% Efficiency, V : 2.5V to 5.5V, V

SD

= 0.8V, I = 20μA,

OUT

IN

OUT(MIN)

Q

Synchronous Step-Down DC/DC Converters

I

<1μA, ThinSOT Package

600mA (I ), 1.5MHz,

96% Efficiency, V : 2.5V to 5.5V, V

= 0.6V, I = 20μA,

OUT

IN

Q

Synchronous Step-Down DC/DC Converters

I

<1μA, ThinSOT Package

SD

600mA, 1.5MHz

Dual Synchronous Step-Down DC/DC Converter

96% Efficiency, V : 2.5V to 5.5V, V

= 0.6V, I = 40μA,

IN

Q

I

<1μA, MSE, DFN Package

SD

LTC3411

1.25A (I ), 4MHz,

95% Efficiency, V : 2.5V to 5.5V, V

= 0.8V, I = 60μA,

OUT

IN

Q

Synchronous Step Down DC/DC Converter

I

<1μA, MSOP-10 Package

SD

LTC3412

2.5A (I ), 4MHz,

95% Efficiency, V : 2.5V to 5.5V, V

= 0.8V, I = 60μA,

OUT

IN

Q

Synchronous Step Down DC/DC Converter

I

<1μA, TSSOP-16E Package

SD

LTC3414

4A (I ), 4MHz,

95% Efficiency, V : 2.25V to 5.5V, V

SD

= 0.8V, I = 64μA,

OUT

IN

OUT(MIN)

Q

Synchronous Step Down DC/DC Converter

I

<1μA, TSSOP-28E Package

LTC3440

600mA (I ), 2MHz,

95% Efficiency, V : 2.5V to 5.5V, V

SD

= 2.5V, I = 25μA,

OUT

IN

OUT(MIN)

Q

Synchronous Buck-Boost DC/DC Converter

I

<1μA, MSOP-10 Package

34072fa

LT 0707 REV A • PRINTED IN USA

16 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT3407IMSE-2#TRPBF
厂家：	Linear
描述：	Dual Switching Controller, Current-mode, 1.6A, 2700kHz Switching Freq-Max, PDSO10 开关光电二极管
文件：	总16页 (文件大小：221K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT3407IMSE-2#TRPBF [Linear]

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