LT3430-1_15_技术文档

LT3430/LT3430-1

High Voltage, 3A,

200kHz/100kHz Step-Down

Switching Regulators

DESCRIPTION

The LT^®3430/LT3430-1 are monolithic buck switching

regulators that accept input voltages up to 60V. A high ef-

ﬁciency 3A, 0.1Ω switch is included on the die along with

all the necessary oscillator, control and logic circuitry. A

currentmodearchitectureprovidesfasttransientresponse

and excellent loop stability.

FEATURES

■

Wide Input Range: 5.5V to 60V

■

3A Peak Switch Current over All Duty Cycles

■

Constant Switching Frequency:

200kHz (LT3430)

100kHz (LT3430-1)

■

0.1Ω Switch Resistance

Current Mode

■

Special design techniques and a new high voltage process

achieve high efﬁciency over a wide input range. Efﬁciency

is maintained over a wide output current range by using

the output to bias the circuitry and by utilizing a supply

boost capacitor to saturate the power switch. Patented

circuitry* maintains peak switch current over the full duty

cycle range. A shutdown pin reduces supply current to

30µA and a SYNC pin can be externally synchronized with

a logic level input from 228kHz to 700kHz for the LT3430

or from 125kHz to 250kHz for the LT3430-1.

■

Effective Supply Current: 2.5mA

■

Shutdown Current: 30µA

■

1.2V Feedback Reference Voltage

■

Easily Synchronizable

■

Cycle-by-Cycle Current Limiting

■

Small, 16-Pin Thermally Enhanced TSSOP Package

APPLICATIONS

■

Industrial and Automotive Power Supplies

■

Portable Computers

TheLT3430/LT3430-1areavailableinathermallyenhanced

16-pin TSSOP package.

■

Battery Chargers

Distributed Power Systems

■

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

*US Patent # 6498466

TYPICAL APPLICATION

5V, 2A Buck Converter

MMSD914TI

Efﬁciency vs Load Current

100

V

= 5V

OUT

V

= 12V

= 42V

IN

90

80

70

60

50

0.68µF

BOOST

22µH

V

5V

2A

IN

OUT

5.5V*

V

IN

SW

TO 60V

30BQ060

4.7µF

LT3430**

100V

+

100µF 10V

SOLID

TANTALUM

OFF ON

SHDN

BIAS

15.4k

SYNC

GND

FB

LT3430-1 L = 68µH

LT3430 L =27µH

V

C

4.99k

0

0.5

1.0

1.5

2.0

2.5

LOAD CURRENT (A)

220pF

3.3k

0.022µF

3430 TA02

3430 TA01

*FOR INPUT VOLTAGES BELOW 7.5V, SOME RESTRICTIONS MAY APPLY

** SEE LT3430-1 CIRCUIT IN APPLICATIONS INFORMATION SECTION

34301fa

1

LT3430/LT3430-1

ABSOLUTE MAXIMUM RATINGS

PACKAGE/ORDER INFORMATION

(Note 1)

TOP VIEW

Input Voltage (V ) .................................................. 60V

IN

GND

SW

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND

SHDN

SYNC

NC

BOOST Pin Above SW (Note 11).............................. 35V

BOOST Pin Voltage ................................................. 68V

SYNC Voltage............................................................. 7V

SHDN Voltage ............................................................ 6V

BIAS Pin Voltage ..................................................... 30V

FB Pin Voltage/Current .................................. 3.5V/2mA

Operating Junction Temperature Range

V

IN

V

IN

17

SW

BOOST

NC

FB

V

C

BIAS

GND

LT3430EFE (Notes 8, 10) .................. –40°C to 125°C

LT3430IFE (Notes 8, 10) .................. –40°C to 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ................ 300°C

FE PACKAGE

16-LEAD PLASTIC TSSOP

T

= 125°C, θ = 45°C/W, θ = 10°C/W

JMAX

JA JC

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

ORDER PART NUMBER

FE PART MARKING

3430EFE

LT3430EFE

LT3430IFE

3430IFE

3430EFE-1

3430IFE-1

LT3430EFE-1

LT3430IFE-1

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS ^The

SW = Open Circuit, unless otherwise noted.

●

denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T = 25°C. V = 15V, V = 1.5V, SHDN = 1V, BOOST = Open Circuit,

J

IN

C

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Reference Voltage (V

)

REF

V

+ 0.2 ≤ V ≤ V – 0.2

1.204

1.195

1.219

1.234

1.243

V

OL

C

OH

●

5.5V ≤ V ≤ 60V

IN

FB Input Bias Current

–0.2

400

–1.5

µA

Error Amp Voltage Gain

(Note 2)

200

V/V

Error Amp g

dl (V ) = 10µA

1650

1000

2200

3300

4200

µMho

m

C

●

V to Switch g

3.4

225

0.9

2.1

A/V

µA

V

C

m

●

EA Source Current

EA Sink Current

FB = 1V

125

100

450

500

FB = 1.4V

V Switching Threshold

C

Duty Cycle = 0

SHDN = 1V

V High Clamp

C

V

Switch Current Limit

Switch On Resistance

V Open, Boost = V + 5V, FB = 1V

C IN

–40°C ≤ T ≤ 25°C

3

2.5

5

4

6.5

5.5

A

J

T = 125°C (Note 9)

J

I

SW

= 2.5A, Boost = V + 5V (Note 7)

0.1

0.14

0.18

Ω

IN

Maximum Switch Duty Cycle (LT3430)

FB = 1V

93

90

96

%

●

34301fa

2

LT3430/LT3430-1

ELECTRICAL CHARACTERISTICS ^The

SW = Open Circuit, unless otherwise noted.

●

denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T = 25°C. V = 15V, V = 1.5V, SHDN = 1V, BOOST = Open Circuit,

J

IN

C

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Maximum Switch Duty Cycle (LT3430-1)

96

94

98

%

●

Switch Frequency (LT3430)

Switch Frequency (LT3430-1)

V Set to Give DC = 50%

184

172

200

216

228

kHz

C

88

85

100

115

120

kHz

●

f

Line Regulation

5.5V ≤ V ≤ 60V

0.05

0.8

0.15

%/V

V

SW

IN

Shifting Threshold

Df = 10kHz

(Note 3)

●

Minimum Input Voltage

Minimum Boost Voltage

Boost Current (Note 5)

4.6

5.5

3

V

(Note 4) I ≤ 2.5A

1.8

V

SW

●

Boost = V + 5V, I = 0.75A

25

75

50

120

mA

IN

SW

Boost = V + 5V, I = 2.5A

IN

SW

Input Supply Current (I

)

(Note 6) V

= 5V

1.5

3.1

30

2.2

4.2

mA

VIN

BIAS

Bias Supply Current (I

(Note 6) V

= 5V

BIAS

Shutdown Supply Current

SHDN = 0V, V ≤ 60V, SW = 0V, V Open

100

200

µA

IN

C

●

Lockout Threshold

V Open

C

2.3

2.42

2.53

V

●

Shutdown Threshold

V Open, Shutting Down

C

0.15

0.25

0.37

0.42

0.58

0.60

V

C

V Open, Starting Up

Minimum SYNC Amplitude

1.5

V

kHz

kΩ

SYNC Frequency Range (LT3430)

SYNC Frequency Range (LT3430-1)

SYNC Input Resistance

228

125

700

250

20

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 7: Switch on resistance is calculated by dividing V to SW voltage

by the forced current (3A). See Typical Performance Characteristics for the

graph of switch voltage at other currents.

Note 8: The LT3430EFE/LT3430EFE-1 are guaranteed to meet performance

speciﬁcations from 0°C to 125°C junction temperature. Speciﬁcations over

the –40°C to 125°C operating junction temperature range are assured by

design, characterization and correlation with statistical process controls.

The LT3430IFE/LT3430IFE-1 are guaranteed over the full –40°C to 125°C

operating junction temperature range.

IN

Note 2: Gain is measured with a V swing equal to 200mV above the low

C

clamp level to 200mV below the upper clamp level.

Note 3: Minimum input voltage is not measured directly, but is guaranteed

by other tests. It is deﬁned as the voltage where internal bias lines are still

regulated so that the reference voltage and oscillator remain constant.

Actual minimum input voltage to maintain a regulated output will depend

upon output voltage and load current. See Applications Information.

Note 9: See Peak Switch Current Limit vs Junction Temperature graph in

the Typical Performance Characteristics section.

Note 4: This is the minimum voltage across the boost capacitor needed to

guarantee full saturation of the internal power switch.

Note 5: Boost current is the current ﬂowing into the BOOST pin with the

pin held 5V above input voltage. It ﬂows only during switch on time.

Note 6: Input supply current is the quiescent current drawn by the input

pin when the BIAS pin is held at 5V with switching disabled. Bias supply

current is the current drawn by the BIAS pin when the BIAS pin is held

at 5V. Total input referred supply current is calculated by summing input

Note 10: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the speciﬁed maximum operating junction

temperature may impair device reliability.

Note 11: The maximum operational Boost-SW voltage is limited by

thermal and load current constraints. See ‘Boost Pin’ and ‘Thermal

Calculations’ in the Applications Information section.

supply current (I ) with a fraction of bias supply current (I

):

BIAS

VIN

I

= I + (I

)(V /V )

BIAS OUT IN

TOTAL

VIN

With V = 15V, V

= 5V, I = 1.4mA, I

= 2.9mA, I

= 2.4mA.

IN

OUT

VIN

BIAS

TOTAL

34301fa

3

LT3430/LT3430-1

TYPICAL PERFORMANCE CHARACTERISTICS

Switch Peak Current Limit

FB Pin Voltage and Current

SHDN Pin Bias Current

1.234

1.229

1.224

1.219

2.0

1.5

250

200

150

100

12

6

5

4

3

2

T

= 25°C

J

CURRENT REQUIRED TO FORCE SHUTDOWN

(FLOWS OUT OF PIN). AFTER SHUTDOWN,

CURRENT DROPS TO A FEW µA

TYPICAL

VOLTAGE

CURRENT

1.0

0.5

0

1.214

1.209

1.204

GUARANTEED MINIMUM

AT 2.38V STANDBY THRESHOLD

(CURRENT FLOWS OUT OF PIN)

6

0

50

100 125

50

100 125

–50 –25

0

25

75

–50 –25

0

25

75

0

20

40

60

80

100

DUTY CYCLE (%)

JUNCTION TEMPERATURE (°C)

3430 G02

3430 G03

3430 G01

Lockout and Shutdown Threshold

Shutdown Supply Current

300

250

2.4

2.0

1.6

1.2

0.8

0.4

0

40

35

30

25

20

15

10

5

T

= 25°C

V

A

= 0V

A

SHDN

T

= 25°C

LOCKOUT

V

= 60V

IN

200

150

V

= 15V

IN

100

50

0

START-UP

SHUTDOWN

0

–25

0

25

50

75

100

125

0

10

20

30

40

50

60

0

0.1

0.2

0.3

0.4

0.5

–50

SHUTDOWN VOLTAGE (V)

JUNCTION TEMPERATURE (°C)

INPUT VOLTAGE (V)

3430 G06

3430 G04

3430 G05

Error Ampliﬁer Transconductance

Frequency Foldback

3000

2500

2000

1500

1000

500

200

150

100

50

600

500

2500

2000

1500

1000

500

T

A

= 25°C

PHASE

GAIN

400

300

200

100

FB PIN

CURRENT

V

C

SWITCHING

FREQUENCY

C

OUT

12pF

R

OUT

200k

–3

V

FB

2 • 10

(

)

3430

ERROR AMPLIFIER EQUIVALENT CIRCUIT

0

3430-1

R

A

= 50Ω

LOAD

T

= 25°C

–50

0

100

1k

10k

100k

1M

10M

–50

–25

0

25

50

75

100

125

0

0.5

1.0

1.5

FREQUENCY (Hz)

JUNCTION TEMPERATURE (°C)

V

(V)

FB

3430 G08

3430 G07

3430 G09

34301fa

4

LT3430/LT3430-1

TYPICAL PERFORMANCE CHARACTERISTICS

Minimum Input Voltage with

Switching Frequency

5V Output

BOOST Pin Current

230

220

210

200

190

180

170

7.5

7.0

6.5

6.0

5.5

5.0

90

(LT3430)

T = 25°C

A

T

= 25°C

A

80

70

60

50

40

30

20

10

0

MINIMUM INPUT

VOLTAGE TO START

MINIMUM INPUT

VOLTAGE TO RUN

–50

–25

0

25

50

75

100

125

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

0

1

2

3

JUNCTION TEMPERATURE (°C)

LOAD CURRENT (A)

SWITCH CURRENT (A)

3430 G10

3430 G11

3430 G12

V Pin Shutdown Threshold

C

Switch Voltage Drop

2.1

1.9

450

400

350

300

250

200

150

100

50

T

= 125°C

J

1.7

1.5

1.3

1.1

0.9

T

= 25°C

J

T

= –40°C

J

0.7

0

50

100 125

–50 –25

0

25

75

0

1

2

3

JUNCTION TEMPERATURE (°C)

SWITCH CURRENT (A)

3430 G13

3430 G14

Switch Minimum ON Time

vs Temperature

Switch Peak Current Limit

600

500

400

300

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

200

100

0

–25

0

25

50

75

100

125

50

–50 –25

JUNCTION TEMPERATURE (°C)

100 125

–50

25

75

0

JUNCTION TEMPERATURE (°C)

3430 G16

3430 G15

34301fa

5

LT3430/LT3430-1

PIN FUNCTIONS

GND (Pins 1, 8, 9, 16, 17): The GND pin connections act

asthereferencefortheregulatedoutput,soloadregulation

will suffer if the “ground” end of the load is not at the same

voltage as the GND pins of the IC. This condition will occur

when load current or other currents ﬂow through metal

pathsbetweentheGNDpinsandtheloadground.Keepthe

pathsbetweentheGNDpinsandtheloadgroundshortand

use a ground plane when possible. The FE package has an

exposed pad that is fused to the GND pins. The pad (Pin

17) should be soldered to the copper ground plane under

the device to reduce thermal resistance. (See Applications

Information—Layout Considerations.)

This architecture increases efﬁciency especially when the

input voltage is much higher than the output. Minimum

output voltage setting for this mode of operation is 3V.

V (Pin 11): The V pin is the output of the error ampliﬁer

C

and the input of the peak switch current comparator. It is

normally used for frequency compensation, but can also

serve as a current clamp or control loop override. V sits

C

at about 0.9V for light loads and 2.1V at maximum load.

It can be driven to ground to shut off the regulator, but if

driven high, current must be limited to 4mA.

FB (Pin 12): The feedback pin is used to set the output

voltage using an external voltage divider that generates

1.22V at the pin for the desired output voltage. Three

additional functions are performed by the FB pin. When

the pin voltage drops below 0.6V, switch current limit is

reducedandtheexternalSYNCfunctionisdisabled.Below

0.8V, switching frequency is also reduced. See Feedback

Pin Functions in Applications Information for details.

SW(Pins2, 5):Theswitchpinistheemitteroftheon-chip

power NPN switch. This pin is driven up to the input pin

voltage during switch on time. Inductor current drives the

switchpinvoltagenegativeduringswitchofftime.Negative

voltageisclampedwiththeexternalcatchdiode.Maximum

negative switch voltage allowed is –0.8V.

V (Pins 3, 4): This is the collector of the on-chip power

IN

SYNC (Pin 14): The SYNC pin is used to synchronize the

internal oscillator to an external signal. It is directly logic

compatibleandcanbedrivenwithanysignalbetween10%

and 90% duty cycle. The synchronizing range is 125kHz

to 250kHz for the LT3430-1 and 228kHz to 700kHz for the

LT3430. See Synchronizing in Applications Information

for details.

NPNswitch.V powerstheinternalcontrolcircuitrywhen

IN

a voltage on the BIAS pin is not present. High dI/dt edges

occur on this pin during switch turn on and off. Keep the

path short from the V pin through the input bypass

IN

capacitor, through the catch diode back to SW. All trace

inductance in this path creates voltage spikes at switch

off, adding to the V voltage across the internal NPN.

CE

SHDN (Pin 15): The SHDN pin is used to turn off the

regulator and to reduce input drain current to a few mi-

croamperes. This pin has two thresholds: one at 2.38V to

disable switching and a second at 0.4V to force complete

micropower shutdown. The 2.38V threshold functions

as an accurate undervoltage lockout (UVLO); sometimes

used to prevent the regulator from delivering power until

the input voltage has reached a predetermined level.

BOOST (Pin 6): The BOOST pin is used to provide a drive

voltage,higherthantheinputvoltage,totheinternalbipolar

NPN power switch. Without this added voltage, the typical

switch voltage loss would be about 1.5V. The additional

BOOST voltage allows the switch to saturate and voltage

loss approximates that of a 0.1Ω FET structure.

NC (Pins 7, 13): No Connection.

BIAS (Pin 10): The BIAS pin is used to improve efﬁciency

when operating at higher input voltages and light load cur-

rent. Connecting this pin to the regulated output voltage

forces most of the internal circuitry to draw its operating

currentfromtheoutputvoltageratherthantheinputsupply.

If the SHDN pin functions are not required, the pin can

either be left open (to allow an internal bias current to lift

the pin to a default high state) or be forced high to a level

not to exceed 6V.

34301fa

6

LT3430/LT3430-1

BLOCK DIAGRAM

itmucheasiertofrequencycompensatethefeedbackloop

and also gives much quicker transient response.

The LT3430/LT3430-1 are constant frequency, current

mode buck converters. This means that there is an in-

ternal clock and two feedback loops that control the duty

cycle of the power switch. In addition to the normal error

ampliﬁer, there is a current sense ampliﬁer that monitors

switch current on a cycle-by-cycle basis. A switch cycle

Most of the circuitry of the LT3430/LT3430-1 operates

fromaninternal2.9Vbiasline.Thebiasregulatornormally

draws power from the regulator input pin, but if the BIAS

pin is connected to an external voltage equal to or higher

than 3V, bias power will be drawn from the external source

(typically the regulated output voltage). This will improve

efﬁciency if the BIAS pin voltage is lower than regulator

input voltage.

starts with an oscillator pulse which sets the R ﬂip-ﬂop

S

to turn the switch on. When switch current reaches a level

set by the inverting input of the comparator, the ﬂip-ﬂop

is reset and the switch turns off. Output voltage control is

obtained by using the output of the error ampliﬁer to set

theswitchcurrenttrippoint.Thistechniquemeansthatthe

error ampliﬁer commands current to be delivered to the

output rather than voltage. A voltage fed system will have

lowphaseshiftuptotheresonantfrequencyoftheinductor

and output capacitor, then an abrupt 180° shift will occur.

The current fed system will have 90° phase shift at a much

lower frequency, but will not have the additional 90° shift

until well beyond the LC resonant frequency. This makes

High switch efﬁciency is attained by using the BOOST pin

to provide a voltage to the switch driver which is higher

than the input voltage, allowing switch to be saturated.

This boosted voltage is generated with an external ca-

pacitor and diode. Two comparators are connected to the

shutdownpin.Onehasa2.38Vthresholdforundervoltage

lockout and the second has a 0.4V threshold for complete

shutdown.

V

IN

3, 4

10

R

SENSE

LIMIT

–

+

2.9V BIAS

REGULATOR

INTERNAL

CC

BIAS

V

CURRENT

COMPARATOR

SLOPE COMP

Σ

SYNC 14

BOOST

6

ANTISLOPE COMP

SHUTDOWN

COMPARATOR

200kHz: LT3430

100kHz: LT3430-1

OSCILLATOR

–

+

S

Q1

POWER

SWITCH

R

DRIVER

CIRCUITRY

S

FLIP-FLOP

R

0.4V

5.5µA

SW

SHDN 15

+

–

2, 5

FREQUENCY

FOLDBACK

LOCKOUT

COMPARATOR

×1

Q2

FOLDBACK

CURRENT

LIMIT

V

C(MAX)

CLAMP

Q3

ERROR

AMPLIFIER

= 2000µMho

CLAMP

–

+

12

FB

g

m

11

1.22V

2.38V

V

C

GND

1, 8, 9, 16, 17

3430 F01

Figure 1. LT3430/LT3430-1 Block Diagram

34301fa

7

LT3430/LT3430-1

APPLICATIONS INFORMATION

FEEDBACK PIN FUNCTIONS

average current through the diode and inductor is equal

to the short-circuit current limit of the switch (typically

4A for the LT3430/LT3430-1, folding back to less than

2A). Minimum switch on time limitations would prevent

the switcher from attaining a sufﬁciently low duty cycle if

switching frequency were maintained at 200kHz (100kHz

LT3430-1), so frequency is reduced by about 5:1 (3:1

LT3430-1) when the feedback pin voltage drops below

0.8V (see Frequency Foldback graph). This does not affect

operation with normal load conditions; one simply sees

a gear shift in switching frequency during start-up as the

output voltage rises.

The feedback (FB) pin on the LT3430/LT3430-1 is used to

setoutputvoltageandprovideseveraloverloadprotection

features. The ﬁrst part of this section deals with selecting

resistors to set output voltage and the second part talks

about foldback frequency and current limiting created by

the FB pin. Please read both parts before committing to

a ﬁnal design.

ThesuggestedvaluefortheLT3430outputdividerresistor

(see Figure 2) from FB to ground (R2) is 5k or less, and a

formula for R1 is shown below. For the LT3430-1, choose

the resistors so that the Thevinin resistance of the divider

at the feedback pin is 7.5kΩ. The output voltage error

caused by ignoring the input bias current on the FB pin

is less than 0.25% with R2 = 5k. A table of standard 1%

values is shown in Table 1 for common output voltages.

Please read the following if divider resistors are increased

above the suggested values.

In addition to lower switching frequency, the LT3430/

LT3430-1 also operate at lower switch current limit when

the feedback pin voltage drops below 0.6V. Q2 in Figure 2

performs this function by clamping the V pin to a voltage

C

less than its normal 2.1V upper clamp level. This foldback

current limit greatly reduces power dissipation in the IC,

diodeandinductorduringshort-circuitconditions.External

synchronization is also disabled to prevent interference

with foldback operation. Again, it is nearly transparent to

the user under normal load conditions. The only loads that

may be affected are current source loads which maintain

full load current with output voltage less than 50% of

ﬁnal value. In these rare situations the feedback pin can

be clamped above 0.6V with an external diode to defeat

foldback current limit. Caution: clamping the feedback

pin means that frequency shifting will also be defeated,

so a combination of high input voltage and dead shorted

output may cause the LT3430/LT3430-1 to lose control

of current limit.

R2 V

−1.22

1.22

(

)

OUT

R1=

Table 1. *LT3430, **LT3430-1

OUTPUT

R1

% ERROR AT OUTPUT

DUE TO DISCREET 1%

RESISTOR STEPS

VOLTAGE

(V)

R2

(NEAREST 1%)

(kΩ)

3*

3.3*

5*

4.99

4.12

12.7

12.1

10

7.32

8.45

15.4

46.4

18.7

20.5

30.9

73.2

+0.32

–0.43

–0.30

–0.27

+0.54

–0.40

–0.20

+0.37

12*

3**

3.3**

5**

12**

The internal circuitry which forces reduced switching

frequency also causes current to ﬂow out of the feedback

pin when output voltage is low. The equivalent circuitry

is shown in Figure 2. Q1 is completely off during normal

operation. If the FB pin falls below 0.8V, Q1 begins to

conduct current and LT3430 reduces frequency at the rate

ofapproximately1.4kHz/µA.Toensureadequatefrequency

foldback (under worst-case short-circuit conditions), the

8.25

More Than Just Voltage Feedback

The feedback pin is used for more than just output voltage

sensing. It also reduces switching frequency and current

limit when output voltage is very low (see the Frequency

Foldback graph in Typical Performance Characteristics).

This is done to control power dissipation in both the IC

and in the external diode and inductor during short-cir-

cuit conditions. A shorted output requires the switching

regulator to operate at very low duty cycles, and the

external divider Thevinin resistance (R

) must be low

THEV

enough to pull 115µA out of the FB pin with 0.44V on

the pin (R

≤ 3.8k)(LT3430-1 R

≈ 7.5k). The net

THEV

result is that reductions in frequency and current limit

are affected by output voltage divider impedance. Cau-

34301fa

8

LT3430/LT3430-1

APPLICATIONS INFORMATION

V

LT3430

SW

L1

TO FREQUENCY

OUTPUT

5V

SHIFTING

1.4V

Q1

ERROR

AMPLIFIER

R1

1.2V

+

–

R4

2k

R3

1k

FB

+

C1

BUFFER

Q2

R2

TO SYNC CIRCUIT

V

GND

C

3430 F02

Figure 2. Frequency and Current Limit Foldback

tion should be used if resistors are increased beyond the

suggested values and short-circuit conditions occur with

high input voltage. High frequency pickup will increase

and the protection accorded by frequency and current

foldback will decrease.

V

USING

OUT

100µF CERAMIC

OUTPUT

20mV/DIV

CAPACITOR

V

OUT

USING

100µF 0.08Ω

TANTALUM

OUTPUT

Choosing the Inductor

CAPACITOR

For most applications, the output inductor will fall into

the range of 5µH to 47µH (10µH to 100µH for LT3430-1).

Lower values are chosen to reduce physical size of the

inductor.Highervaluesallowmoreoutputcurrentbecause

they reduce peak current seen by the LT3430/LT3430-1

switch, which has a 3A limit. Higher values also reduce

output ripple voltage.

3430 F03

V

= 40V

OUT

L = 22µH

2µs/DIV

IN

= 5V

Figure 3. LT3430 Output Ripple Voltage Waveforms.

Ceramic vs Tantalum Output Capacitors

ceramic output capacitor; the signiﬁcant decrease in out-

put ripple voltage is due to the very low ESR of ceramic

capacitors.

When choosing an inductor you will need to consider

output ripple voltage, maximum load current, peak induc-

tor current and fault current in the inductor. In addition,

other factors such as core and copper losses, allowable

component height, EMI, saturation and cost should also

be considered. The following procedure is suggested

as a way of handling these somewhat complicated and

conﬂicting requirements.

Outputripplevoltageisdeterminedbyripplecurrent(I

)

LP-P

throughtheinductorandthehighfrequencyimpedanceof

the output capacitor. At high frequencies, the impedance

of the tantalum capacitor is dominated by its effective

series resistance (ESR).

Tantalum Output Capacitor

Output Ripple Voltage

The typical method for reducing output ripple voltage

when using a tantalum output capacitor is to increase the

inductorvalue(toreducetheripplecurrentintheinductor).

Figure 3 shows a comparison of output ripple voltage for

the LT3430/LT3430-1 using either a tantalum or ceramic

output capacitor. It can be seen from Figure 3 that output

ripple voltage can be signiﬁcantly reduced by using the

The following equations will help in choosing the required

34301fa

9

LT3430/LT3430-1

APPLICATIONS INFORMATION

inductor value to achieve a desirable output ripple volt-

age level. If output ripple voltage is of less importance,

the subsequent suggestions in Peak Inductor and Fault

Current and EMI will additionally help in the selection of

the inductor value.

Ceramic Output Capacitor

An alternative way to further reduce output ripple voltage

is to reduce the ESR of the output capacitor by using a

ceramiccapacitor.AlthoughthisreductionofESRremoves

a useful zero in the overall loop response, this zero can

Peak-to-peak output ripple voltage is the sum of a triwave

be replaced by inserting a resistor (R ) in series with the

C

(created by peak-to-peak ripple current (I

) times ESR)

V pin and the compensation capacitor C . (See Ceramic

LP-P

C

and a square wave (created by parasitic inductance (ESL)

and ripple current slew rate). Capacitive reactance is as-

sumed to be small compared to ESR or ESL.

Capacitors in Applications Information.)

Peak Inductor Current and Fault Current

To ensure that the inductor will not saturate, the peak

inductor current should be calculated knowing the

maximum load current. An appropriate inductor should

then be chosen. In addition, a decision should be made

whether or not the inductor must withstand continuous

fault conditions.

dI

dt

V_RIPPLE= I

ESR + ESL

) (

(

_LP-P)(

)

where:

ESR = equivalent series resistance of the output capaci-

tor

If maximum load current is 1A, for instance, a 1A induc-

tor may not survive a continuous 4A overload condition.

Dead shorts will actually be more gentle on the inductor

becausetheLT3430/LT3430-1havefrequencyandcurrent

limit foldback.

ESL = equivalent series inductance of the output capaci-

tor

dI/dt = slew rate of inductor ripple current = V /L

IN

Peak-to-peak ripple current (I

) through the inductor

LP-P

and into the output capacitor is typically chosen to be

between 20% and 40% of the maximum load current. It

is approximated by:

Table 2

VENDOR/

PART NO.

VALUE

(µH)

I

DCR

(Ohms)

HEIGHT

(mm)

DC

(Amps)

Sumida

V

V – V

IN OUT

(

_OUT)(

)

I_LP-P

=

CDRH104R-150

CDRH104R-220

CDRH104R-330

CDRH124-220

CDRH124-330

CDRH127-330

CDRH127-470

CEI122-220

Coiltronics

15

22

33

22

33

47

22

3.6

2.9

2.3

2.9

2.7

3.0

2.5

2.3

0.050

0.073

0.093

0.066

0.097

0.065

0.100

0.085

4

V

f L

_IN)( )( )

(

Example: with V = 40V, V

= 5V, L = 22µH, ESR =

4

IN

OUT

0.080Ω and ESL = 10nH, output ripple voltage can be

4.5

8

approximated as follows:

5 40 − 5

( )(

)

I_P-P

dI

=

= 0.99A

8

40 22 •10⁻⁶200 •10³

( )

(

)(

)

8

40

=

= 10⁶•1.8

UP3B-330

33

47

68

3

0.069

0.108

0.120

6.8

7.9

22 •10⁻⁶

dt

UP3B-470

2.4

4.3

V_RIPPLE= 0.99A 0.08 + 10 •10⁻⁹10⁶1.8

(

)(

)

(

)

(

)(

UP4B-680

= 0.079 + 0.018 = 97mV_P-P

Coilcraft

DO3316P-153

DO5022p-683

15

68

3

0.046

0.130

5.2

7.1

Toreduceoutputripplevoltagefurtherrequiresanincrease

in the inductor value with the trade-off being a physically

largerinductorwiththepossibilityofincreasedcomponent

height and cost.

3.5

34301fa

10

LT3430/LT3430-1

APPLICATIONS INFORMATION

Peakswitchandinductorcurrentcanbesigniﬁcantlyhigher

than output current, especially with smaller inductors

and lighter loads, so don’t omit this step. Powdered iron

cores are forgiving because they saturate softly, whereas

ferrite cores saturate abruptly. Other core materials fall

somewhere in between. The following formula assumes

continuous mode of operation, but errs only slightly on

the high side for discontinuous mode, so it can be used

for all conditions.

The LT3430/LT3430-1 are able to maintain peak switch

currentlimitoverthefulldutycyclerangebyusingpatented

circuitry* to cancel the effects of slope compensation

on peak switch current without affecting the frequency

compensation it provides.

Maximumloadcurrentwouldbeequaltomaximumswitch

current for an inﬁnitely large inductor, but with ﬁnite

inductor size, maximum load current is reduced by one-

half peak-to-peak inductor current (I

). The following

LP-P

formula assumes continuous mode operation, implying

V

V – V

IN OUT

I_LP-P

2

(

= I_OUT+

_OUT)(

)

I_PEAK= I_OUT

+

that the term on the right is less than one-half of IP.

2 V f L

( )( _IN)( )( )

I

=

OUT(MAX)

EMI

Continuous Mode

Decide if the design can tolerate an “open” core geometry

likearodorbarrel,whichhavehighmagneticﬁeldradiation,

or whether it needs a closed core like a toroid to prevent

EMI problems. This is a tough decision because the rods

or barrels are temptingly cheap and small and there are

no helpful guidelines to calculate when the magnetic ﬁeld

radiation will be a problem.

V

+ V V − V – V

I

(

_F)(

)

OUT

IN

OUT

F

I_P– ^LP-P=I_P−

2

2 L f V

( )( )

(

)

IN

For V

= 5V, V = 12V, V

= 0.52V, f = 200kHz and

F(D1)

OUT

L = 15µH:

IN

5 + 0.52 12 − 5 – 0.52

(

)(

)

I_{OUT MAX}₎= 3 −

(

2 15•10⁻⁶200•10³12

Additional Considerations

( )

)

After making an initial choice, consider additional factors

such as core losses and second sourcing, etc. Use the

experts in Linear Technology’s Applications department

if you feel uncertain about the ﬁnal choice. They have ex-

perience with a wide range of inductor types and can tell

you about the latest developments in low proﬁle, surface

mounting, etc.

= 3 − 0.5 = 2.5A

Note that there is less load current available at the higher

input voltage because inductor ripple current increases.

At V = 24V, duty cycle is 23% and for the same set of

IN

conditions:

5 + 0.52 24 − 5 – 0.52

(

)(

)

I_OUT(MAX)= 3 −

2 15•10⁻⁶200•10³24

Maximum Output Load Current

( )

)

Maximum load current for a buck converter is limited by

= 3 − 0.71= 2.29A

themaximumswitchcurrentrating(I ).Thecurrentrating

P

To calculate actual peak switch current with a given set

of conditions, use:

for the LT3430/LT3430-1 is 3A. Unlike most current mode

converters,theLT3430/LT3430-1maximumswitchcurrent

limit does not fall off at high duty cycles. Most current

mode converters suffer a drop off of peak switch current

for duty cycles above 50%. This is due to the effects of

slope compensation required to prevent subharmonic

oscillations in current mode converters. (For detailed

analysis, see Application Note 19.)

I_LP-P

2

I_{SW PEAK}= I_OUT

+

(

)

(V_OUT+ V ) V − V

– V

F

(

)

F

IN

OUT

= I_OUT

2 L f V

( )( )(

)

IN

*US Patent # 6,498,466

34301fa

11

LT3430/LT3430-1

APPLICATIONS INFORMATION

Reduced Inductor Value and Discontinuous Mode

I

OUT(MAX)

Discontinuous

Mode

3²•(200•10³)(4.7 •10 ⁻⁶)(15)

=

If the smallest inductor value is of most importance to a

converter design, in order to reduce inductor size/cost,

discontinuous mode may yield the smallest inductor solu-

tion. The maximum output load current in discontinuous

mode, however, must be calculated and is deﬁned later

in this section.

2(5 + 0.52)(15 – 5 – 0.52)

I

= 1.21A

OUT(MAX)

Discontinuous Mode

What has been shown here is that if high inductor ripple

currentanddiscontinuousmodeoperationcanbetolerated,

small inductor values can be used. If a higher output load

current is required, the inductor value must be increased.

Discontinuous mode is entered when the output load

current is less than one-half of the inductor ripple current

If I

no longer meets the discontinuous mode

(I ). In this mode, inductor current falls to zero before

LP-P

OUT(MAX)

criteria, use the I

equation for continuous mode;

the next switch turn on (see Figure 8). Buck converters

will be in discontinuous mode for output load current

given by:

OUT(MAX)

the LT3430/LT3430-1 are designed to operate well in both

modes of operation, allowing a large range of inductor

values to be used.

(V_OUT+ V_F)(V – V_OUT– V_F)

I

IN

OUT

<

(2)(V )(f)(L)

IN

Short-Circuit Considerations

Discontinuous Mode

The inductor value in a buck converter is usually chosen

large enough to keep inductor ripple current (I ) low;

The LT3430/LT3430-1 are current mode controllers. They

use the V node voltage as an input to a current compara-

C

LP-P

tor which turns off the output switch on a cycle-by-cycle

thisisdonetominimizeoutputripplevoltageandmaximize

output load current. In the case of large inductor values,

as seen in the equation above, discontinuous mode will

be associated with “light loads.”

basisasthispeakcurrentisreached.Theinternalclampon

the V node, nominally 2V, then acts as an output switch

C

peak current limit. This action becomes the switch current

limit speciﬁcation. The maximum available output power

is then determined by the switch current limit.

Whenchoosingsmallinductorvalues,however,discontinu-

ous mode will occur at much higher output load currents.

The limit to the smallest inductor value that can be chosen

A potential controllability problem could occur under

short-circuit conditions. If the power supply output is

short circuited, the feedback ampliﬁer responds to the

issetbytheLT3430/LT3430-1peakswitchcurrent(I )and

P

the maximum output load current required, given by:

low output voltage by raising the control voltage, V , to its

C

I

I_LP-P

2

OUT(MAX)

peak current limit value. Ideally, the output switch would

= <

Discontinuous Mode

be turned on, and then turned off as its current exceeded

thevalueindicatedbyV . However, thereisﬁniteresponse

C

2

I_P

time involved in both the current comparator and turnoff

=

(2)(I_LP-P

)

of the output switch. These result in a minimum on time

t

. When combined with the large ratio of V to

IN

2

ON(MIN)

I_Pf •L•V

(

)

IN

=

(V + I • R), the diode forward voltage plus inductor I • R

F

2(V_OUT+ V_F)(V – V_OUT– V_F)

IN

voltage drop, the potential exists for a loss of control.

Expressed mathematically the requirement to maintain

control is:

Example: For V = 15V, V

= 5V, V = 0.52V, f = 200kHz

F

IN

OUT

and L = 4.7µH.

V_F+ I•R

f • t_ON

≤

V

IN

34301fa

12

LT3430/LT3430-1

APPLICATIONS INFORMATION

where:

Table 3. Surface Mount Solid Tantalum Capacitor ESR

f = switching frequency

and Ripple Current

E Case Size

t

= switch minimum on time

ESR (Max., Ω)

Ripple Current (A)

ON

V = diode forward voltage

AVX TPS, Sprague 593D

D Case Size

0.1 to 0.3

0.7 to 1.1

F

V = Input voltage

I • R = inductor I • R voltage drop

IN

AVX TPS, Sprague 593D

C Case Size

0.1 to 0.3

0.7 to 1.1

If this condition is not observed, the current will not be

AVX TPS

0.2 (typ)

0.5 (typ)

limited at I , but will cycle-by-cycle ratchet up to some

PK

higher value. Using the nominal LT3430/LT3430-1 clock

from22µFtogreaterthan500µFworkwell, butyoucannot

cheat mother nature on ESR. If you ﬁnd a tiny 22µF solid

tantalum capacitor, it will have high ESR, and output ripple

voltage will be terrible. Table 3 shows some typical solid

tantalum surface mount capacitors.

frequencies of 200KHz/100kHz, a V of 40V and a (V +

IN

ON

F

I • R) of say 0.7V, the maximum t to maintain control

would be approximately 90ns for the LT3430 and 180ns

for the LT3430-1, unacceptably short times.

The solution to this dilemma is to slow down the oscil-

lator when the FB pin voltage is abnormally low thereby

indicatingsomesortofshort-circuitcondition. Oscillator

frequency is unaffected until FB voltage drops to about

2/3 of its normal value. Below this point the oscillator

frequency decreases roughly linearly down to a limit of

about 40kHz. (30kHz for LT3430-1) This lower oscillator

frequencyduringshort-circuitconditionscanthenmaintain

control with the effective minimum on time.

Many engineers have heard that solid tantalum capacitors

arepronetofailureiftheyundergohighsurgecurrents.This

is historically true, and type TPS capacitors are specially

tested for surge capability, but surge ruggedness is not

a critical issue with the output capacitor. Solid tantalum

capacitors fail during very high turn-on surges, which

do not occur at the output of regulators. High discharge

surges,suchaswhentheregulatoroutputisdeadshorted,

do not harm the capacitors.

It is recommended that for [V /(V

+ V )] ratios >

F

IN OUT

Unliketheinputcapacitor,RMSripplecurrentintheoutput

capacitor is normally low enough that ripple current rating

is not an issue. The current waveform is triangular with

10, a soft-start circuit should be used for the LT3430 to

control the output capacitor charge rate during start-up

or during recovery from an output short circuit, thereby

adding additional control over peak inductor current. See

Buck Converter with Adjustable Soft-Start later in this

data sheet.

a typical value of 250mA

this is:

. The formula to calculate

RMS

Output capacitor ripple current (RMS):

0.29 V

_OUT)(

=

V − V

IN OUT

(

)

I_{RIPPLE RMS}

OUTPUT CAPACITOR

(

)

L f V

( )( )(

)

IN

The output capacitor is normally chosen by its effective

series resistance (ESR), because this is what determines

output ripple voltage. To get low ESR takes volume, so

physically smaller capacitors have high ESR. The ESR

range for typical LT3430 applications is 0.05Ω to 0.2Ω.

A typical output capacitor is an AVX type TPS, 100µF at

10V, with a guaranteed ESR less than 0.1Ω (The LT3430-1

will typically use two of these capacitors in parallel). This

is a “D” size surface mount solid tantalum capacitor. TPS

capacitors are specially constructed and tested for low

ESR, so they give the lowest ESR for a given volume. The

value in microfarads is not particularly critical, and values

Ceramic Capacitors

Higher value, lower cost ceramic capacitors are now

becoming available. They are generally chosen for their

good high frequency operation, small size and very low

ESR (effective series resistance). Their low ESR reduces

output ripple voltage but also removes a useful zero in the

loop frequency response, common to tantalum capaci-

tors. To compensate for this, a resistor R_Ccan be placed

in series with the V_Ccompensation capacitor C_C. Care

must be taken however, since this resistor sets the high

34301fa

13

LT3430/LT3430-1

APPLICATIONS INFORMATION

frequency gain of the error ampliﬁer, including the gain at

the switching frequency. If the gain of the error ampliﬁer

is high enough at the switching frequency, output ripple

voltage (although smaller for a ceramic output capacitor)

may still affect the proper operation of the regulator. A

ﬁlter capacitor C_Fin parallel with the R_C/C_Cnetwork is

suggested to control possible ripple at the V_Cpin. An “All

Ceramic” solution is possible for the LT3430/LT3430-1

by choosing the correct compensation components for

the given application.

Theinputvoltagetransientsmaybecausedbyinputvoltage

steps or by connecting the LT3430/LT3430-1 converter to

an already powered up source such as a wall adapter. The

suddenapplicationofinputvoltagewillcausealargesurge

of current in the input leads that will store energy in the

parasiticinductanceoftheleads.Thisenergywillcausethe

input voltage to swing above the DC level of input power

source and it may exceed the maximum voltage rating of

input capacitor and LT3430/LT3430-1.

The easiest way to suppress input voltage transients is

to add a small aluminum electrolytic capacitor in parallel

with the low ESR input capacitor. The selected capacitor

needs to have the right amount of ESR in order to criti-

cally dampen the resonant circuit formed by the input lead

inductance and the input capacitor. The typical values of

ESR will fall in the range of 0.5Ω to 2Ω and capacitance

will fall in the range of 5µF to 50µF.

Example: For V_IN= 8V to 40V, V_OUT= 5V at 2A, the LT3430

can be stabilized, provide good transient response and

maintain very low output ripple voltage using the follow-

ing component values: (refer to the ﬁrst page of this data

sheet for component references) C_IN= 4.7µF, R_C= 3.3k,

C_C= 22nF, C_F= 220pF and C_OUT= 100µF. See Application

Note 19 for further detail on techniques for proper loop

compensation.

If tantalum capacitors are used, values in the 22µF to

470µF range are generally needed to minimize ESR and

meetripplecurrentandsurgeratings.Careshouldbetaken

to ensure the ripple and surge ratings are not exceeded.

The AVX TPS and Kemet T495 series are surge rated. AVX

recommends derating capacitor operating voltage by 2:1

for high surge applications.

INPUT CAPACITOR

Step-down regulators draw current from the input supply

in pulses. The rise and fall times of these pulses are very

fast. The input capacitor is required to reduce the volt-

age ripple this causes at the input of LT3430/LT3430-1

and force the switching current into a tight local loop,

thereby minimizing EMI. The RMS ripple current can be

calculated from:

CATCH DIODE

HighestefﬁciencyoperationrequirestheuseofaSchottky

type diode. DC switching losses are minimized due to its

low forward voltage drop, and AC behavior is benign due

to its lack of a signiﬁcant reverse recovery time.

2

I_{RIPPLE RMS}= I_OUTV_OUTV – V

/V

IN

(

)

IN

OUT

(

)

Ceramic capacitors are ideal for input bypassing. At

200kHz(100kHz)switchingfrequency, theenergystorage

requirement of the input capacitor suggests that values

in the range of 4.7µF to 20µF (10µF to 47µF) are suitable

for most applications. If operation is required close to the

minimum input required by the output of the LT3430, a

larger value may be required. This is to prevent excessive

ripple causing dips below the minimum operating voltage

resulting in erratic operation.

Theuseofso-called“ultrafast”recoverydiodesisgenerally

not recommended. When operating in continuous mode,

the reverse recovery time exhibited by “ultrafast” diodes

will result in a slingshot type effect. The power internal

switch will ramp up V current into the diode in an at-

IN

tempt to get it to recover. Then, when the diode has ﬁnally

turned off, some tens of nanoseconds later, the V node

SW

voltage ramps up at an extremely high dV/dt, perhaps 5 to

even 10V/ns! With real world lead inductances, the V

SW

DependingonhowtheLT3430/LT3430-1circuitispowered

up you may need to check for input voltage transients.

node can easily overshoot the V rail. This can result in

IN

34301fa

14

LT3430/LT3430-1

APPLICATIONS INFORMATION

poor RFI behavior and if the overshoot is severe enough,

less demanding conditions, but this will not improve cir-

cuit operation or efﬁciency. Under low input voltage and

low load conditions, a higher value capacitor will reduce

discharge ripple and improve start-up operation. For the

LT3430-1 a 1.5µF boost capacitor is recommended.

damage the IC itself.

The suggested catch diode (D1) is an International Recti-

ﬁer 30BQ060 Schottky. It is rated at 3A average forward

current and 60V reverse voltage. Typical forward voltage

is 0.52V at 3A. The diode conducts current only during

switch off time. Peak reverse voltage is equal to regulator

inputvoltage.Averageforwardcurrentinnormaloperation

can be calculated from:

SHUTDOWN FUNCTION AND UNDERVOLTAGE

LOCKOUT

Figure 4 shows how to add undervoltage lockout (UVLO)

to the LT3430/LT3430-1. Typically, UVLO is used in situ-

ations where the input supply is current limited, or has

a relatively high source resistance. A switching regulator

draws constant power from the source, so source cur-

rent increases as source voltage drops. This looks like a

negative resistance load to the source and can cause the

sourcetocurrentlimitorlatchlowunderlowsourcevoltage

conditions. UVLOpreventstheregulatorfromoperatingat

source voltages where these problems might occur.

I_OUTV – V

(

)

IN

OUT

I_D(AVG)

=

V

IN

This formula will not yield values higher than 3A with

maximum load current of 3A.

BOOST PIN

For most LT 3430 applications, the boost components are

a 0.68µF capacitor and a MMSD914TI diode. The anode

is typically connected to the regulated output voltage to

Threshold voltage for lockout is about 2.38V. A 5.5µA

bias current ﬂows out of the pin at this threshold. The

internally generated current is used to force a default high

state on the shutdown pin if the pin is left open. When

low shutdown current is not an issue, the error due to this

generate a voltage approximately V

above V to drive

OUT

IN

the output stage. However, the output stage discharges

the boost capacitor during the on time of the switch. The

output driver requires at least 3V of headroom throughout

this period to keep the switch fully saturated. If the output

voltageislessthan3.3V,itisrecommendedthatanalternate

boost supply is used. For output voltages greater than 6V,

it is recommended to place a zener diode (D4; page 20)

in series with the Boost diode to set Boost-to-SW voltage

between 4V to 6V. This minimizes power loss within the

IC, improving maximum ambient temperature operation.

In addition, D4 minimizes Boost current overshoot during

power switch turn on to reduce noise within the regula-

tor loop. For output voltages greater than the standard

demoboard 5V output, a location for D4 is provided.

current can be minimized by making R 10k or less. If

LO

shutdown current is an issue, R can be raised to 100k,

LO

but the error due to initial bias current and changes with

temperature should be considered.

R_LO= 10k to 100k 25k suggested

(

)

R_LOV − 2.38V

(

)

IN

R_HI=

2.38V − R_LO5.5µA

(

)

V = Minimum input voltage

IN

Keep the connections from the resistors to the shutdown

pin short and make sure that interplane or surface capaci-

tancetotheswitchingnodesareminimized.Ifhighresistor

valuesareused,theshutdownpinshouldbebypassedwith

a1000pFcapacitortopreventcouplingproblemsfromthe

switch node. If hysteresis is desired in the undervoltage

lockout point, a resistor R_FBcan be added to the output

node. Resistor values can be calculated from:

A0.68µFboostcapacitorisrecommendedformostLT3430

applications. Almost any type of ﬁlm or ceramic capaci-

tor is suitable, but the ESR should be <1Ω to ensure it

can be fully recharged during the off time of the switch.

The LT3430 capacitor value is derived from conditions of

4800ns on time, 75mA boost current and 0.7V discharge

ripple. The boost capacitor value could be reduced under

34301fa

15

LT3430/LT3430-1

APPLICATIONS INFORMATION

R

FB

L1

LT3430/LTC3430-1

OUTPUT

V

SW

2.38V

+

–

IN

INPUT

STANDBY

R

HI

5.5µA

+

SHDN

C1

+

–

TOTAL

SHUTDOWN

R

C2

LO

0.4V

GND

3430 F04

Figure 4. Undervoltage Lockout

is equal to initial operating frequency up to 700kHz. This

means that minimum practical sync frequency is equal to

theworst-casehighself-oscillatingfrequency(228kHz),not

the typical operating frequency of 200kHz. Caution should

be used when synchronizing above 265kHz because at

highersyncfrequenciestheamplitudeoftheinternalslope

compensation used to prevent subharmonic switching is

reduced. This type of subharmonic switching only occurs

at input voltages less than twice output voltage. Higher

inductor values will tend to eliminate this problem. See

Frequency Compensation section for a discussion of an

entirely different cause of subharmonic switching before

assuming that the cause is insufﬁcient slope compensa-

tion. Application Note 19 has more details on the theory

ofslopecompensation.TheLT3430-1synchronizingrange

is from 125kHz to 250kHz (slope compensation loss oc-

curs above 133kHz).

R_LOV − 2.38 ∆V/V

+ 1 + ∆V

(

)

[

IN

OUT

]

R_HI=

2.38 − R_LO5.5µA

(

)

R = R V /∆V

(

)

(

)

FB

HI

OUT

25k suggested for R

LO

V = Input voltage at which switching stops as input

voltage descends to trip level

∆V = Hysteresis in input voltage level

IN

Example: output voltage is 5V, switching is to stop if

input voltage drops below 12V and should not restart

unless input rises back to 13.5V. ∆V is therefore 1.5V and

V = 12V. Let R = 25k.

IN

LO

25k 12 − 2.38 1.5/5 + 1 + 1.5

(

)

[

]

R_HI=

2.38 – 25k 5.5µA

(

)

25k 10.41

(

)

=

= 116k

2.24

At power-up, when V is being clamped by the FB pin (see

C

R = 116k 5/1.5 = 387k

Figure 2, Q2), the sync function is disabled. This allows

the frequency foldback to operate in the shorted output

condition.Duringnormaloperation,switchingfrequencyis

controlledbytheinternaloscillatoruntiltheFBpinreaches

0.6V, after which the SYNC pin becomes operational. If no

synchronization is required, this pin should be connected

to ground.

(

)

FB

SYNCHRONIZING

The SYNC input must pass from a logic level low, through

the maximum synchronization threshold with a duty cycle

between 10% and 90%. The input can be driven directly

from a logic level output. The LT3430 synchronizing range

34301fa

16

LT3430/LT3430-1

APPLICATIONS INFORMATION

LAYOUT CONSIDERATIONS

ingthispathwillalsoreducetheparasitictraceinductance

of approximately 25nH/inch. At switch off, this parasitic

inductance produces a ﬂyback spike across the LT3430/

LT3430-1 switch. When operating at higher currents and

input voltages, with poor layout, this spike can generate

voltages across the LT3430/LT3430-1 that may exceed its

absolute maximum rating. A ground plane should always

be used under the switcher circuitry to prevent interplane

coupling and overall noise.

As with all high frequency switchers, when considering

layout, care must be taken in order to achieve optimal

electrical, thermal and noise performance. For maximum

efﬁciency, switch rise and fall times are typically in the

nanosecond range. To prevent noise both radiated and

conducted, the high speed switching current path, shown

in Figure 5, must be kept as short as possible. This is

implementedinthesuggestedlayoutofFigure6. Shorten-

LT3430/

LT3430-1

L1

5V

HIGH

FREQUENCY

CIRCULATING

PATH

V

IN

C3

D1 C1

LOAD

3430 F05

Figure 5. High Speed Switching Path

1 GND

2

3

4

5

SW

CONNECT TO

V

IN

LT3430/

LT3430-1

GROUND PLANE

V

IN

GND

SW

L1

6 BOOST

SOLDER THE EXPOSED PAD

(PIN 17) TO THE ENTIRE COPPER

GROUND PLANE UNDERNEATH

THE DEVICE. NOTE: THE BOOST

AND BIAS COPPER TRACES ARE

ON A SEPARATE LAYER FROM

THE GROUND PLANE

MINIMIZE

LT3430/LT3430-1

C3-D1 LOOP

C1

V

PINS 3 AND 4

IN

ARE SHORTED TOGETHER.

D2

SW PINS 2 AND 5 ARE ALSO

SHORTED TOGETHER (USING

AVAILABLE SPACE UNDERNEATH

THE DEVICE BETWEEN PINS AND

GND PLANE)

V

OUT

D1

C2

GND

1

2

3

4

5

6

7

8

GND

SW

GND 16

15

SHDN

SYNC

KELVIN SENSE

V

OUT

V

14

IN

LT3430/

LT3430-1

V

13

IN

C3

SW

FB

12

11

R2

V

C

BOOST

R1

C

FB

BIAS 10

GND

C

F

GND

9

V

IN

R

C

KEEP FB AND V COMPONENTS

C

AWAY FROM HIGH FREQUENCY,

HIGH CURRENT COMPONENTS

C

PLACE FEEDTHROUGH AROUND

GROUND PINS (4 CORNERS) FOR

GOOD THERMAL CONDUCTIVITY

3430 F06

Figure 6. Suggested Layout

34301fa

17

LT3430/LT3430-1

APPLICATIONS INFORMATION

The V and FB components should be kept as far away as

total lead length for the input capacitor, diode and switch

path is 1 inch, the inductance will be approximately 25nH.

At switch off, this will produce a spike across the NPN

output device in addition to the input voltage. At higher

currents this spike can be in the order of 10V to 20V

or higher with a poor layout, potentially exceeding the

absolute max switch voltage. The path around switch,

catch diode and input capacitor must be kept as short as

possibletoensurereliableoperation.Whenlookingatthis,

a >100MHz oscilloscope must be used, and waveforms

should be observed on the leads of the package. This

switch off spike will also cause the SW node to go below

ground.TheLT3430/LT3430-1havespecialcircuitryinside

which mitigates this problem, but negative voltages over

0.8Vlastinglongerthan10nsshouldbeavoided. Notethat

100MHz oscilloscopes are barely fast enough to see the

details of the falling edge overshoot in Figure 7.

C

possible from the switch and boost nodes. The LT3430/

LT3430-1 pinout has been designed to aid in this. The

ground for these components should be separated from

the switch current path. Failure to do so will result in poor

stability or subharmonic like oscillation.

Board layout also has a signiﬁcant effect on thermal

resistance. Pins 1, 8, 9 and 16, GND, should be soldered

to a continuous copper ground plane under the LT3430/

LT3430-1 die. The FE package has an exposed pad (Pin

17) which is the best thermal path for heat out of the

package. Soldering the exposed pad to the copper ground

plane under the device will reduce die temperature and

increasethepowercapabilityoftheLT3430/LT3430-1.Add-

ing multiple solder ﬁlled feedthroughs under and around

the four corner pins to the ground plane will also help.

Similar treatment to the catch diode and coil terminations

will reduce any additional heating effects.

A second, much lower frequency ringing is seen during

switch off time if load current is low enough to allow the

inductor current to fall to zero during part of the switch off

time (see Figure 8). Switch and diode capacitance reso-

nate with the inductor to form damped ringing at 1MHz

to 10MHz. This ringing is not harmful to the regulator

and it has not been shown to contribute signiﬁcantly to

EMI. Any attempt to damp it with a resistive snubber will

degrade efﬁciency.

PARASITIC RESONANCE

Resonance or “ringing” may sometimes be seen on the

switch node (see Figure 7). Very high frequency ringing

followingswitchrisetimeiscausedbyswitch/diode/input

capacitorleadinductanceanddiodecapacitance.Schottky

diodes have very high “Q” junction capacitance that can

ring for many cycles when excited at high frequency. If

LT3430

SWITCH NODE

VOLTAGE

10mV/DIV

SW RISE

SW FALL

2V/DIV

INDUCTOR

CURRENT AT

OUT

0.2A/DIV

I

= 0.1A

3430 F08

V

= 40V

OUT

L = 22µH

1µs/DIV

IN

= 5V

50ns/DIV

3430 F07

Figure 7. Switch Node Resonance

Figure 8. Discontinuous Mode Ringing

34301fa

18

LT3430/LT3430-1

APPLICATIONS INFORMATION

THERMAL CALCULATIONS

ThermalresistancefortheLT3430/LT3430-1packageisin-

ﬂuenced by the presence of internal or backside planes.

Power dissipation in the LT3430/LT3430-1 chip comes

from four sources: switch DC loss, switch AC loss, boost

circuit current, and input quiescent current. The follow-

ing formulas show how to calculate each of these losses.

These formulas assume continuous mode operation, so

they should not be used for calculating efﬁciency at light

load currents.

TSSOP (Exposed Pad) Package: With a full plane under

the TSSOP package, thermal resistance will be about

45°C/W.

To calculate die temperature, use the proper thermal

resistance number for the desired package and add in

worst-case ambient temperature:

Switch loss:

T = T + (θ • P )

TOT

J

A

JA

2

R_{SW OUT}

I

(

V

OUT

) (

)

When estimating ambient, remember the nearby catch

diode and inductor will also be dissipating power:

P

SW

=

+ t_EFF(1/2) I

V

f

(

_OUT)( _IN)( )

V

IN

(V_F)(V – V_OUT)(I_LOAD

)

(Note: Switching losses are less for the LT3430-1 oper-

ating at only 100kHz)

IN

P_DIODE

=

V

IN

Boost current loss:

V = Forward voltage of diode (assume 0.52V at 2A)

F

2

V_OUT

I

/36

(

)

OUT

(0.52)(40 – 5)(2)

P_BOOST

=

P_DIODE

=

= 0.91W

V

IN

40

Quiescent current loss:

2

P

R

P

= (I

) (R

LOAD

)

IND

INDUCTOR

P =V 0.0015 + V 0.003

OUT

(

)

(

)

Q

IN

= Inductor DC resistance (assume 0.1Ω)

IND

2

(2) (0.1) = 0.4W

R

EFF

= Switch resistance (≈0.15) hot

INDUCTOR

SW

t

= Effective switch current/voltage overlap time

Only a portion of the temperature rise in the external

inductor and diode is coupled to the junction of the

LT3430. Based on empirical measurements, the thermal

effect on the LT3430 junction temperature due to power

dissipation in the external inductor and catch diode can

be calculated as:

= (t + t + t + t )

r

f

Ir

If

t = (V /1.2)ns

r

IN

t = (V /1.1)ns

f

t = t = (I /0.2)ns

Ir

If

OUT

f = Switch frequency

Example: with V = 40V, V

= 5V and I

= 2A:

IN

OUT

∆T (LT3430) ≈ (P

+ P

)(5°C/W)

J

DIODE

INDUCTOR

2

0.15 2

5

(

)( ) ( )

P_SW

=

+ 90•10⁻⁹1/2 2 40 200 •10³

UsingtheexamplecalculationsforLT3430dissipation,the

LT3430 die temperature will be estimated as:

(

)

( )( )

(

)

(

)

40

= 0.08 + 0.72 = 0.8W

T = T + (θ • P ) + [5 • (P

+ P

)]

J

A

JA

TOT

DIODE

INDUCTOR

2

5

( )

2 /36

(

)

= 0.04W

P_BOOST

=

With the TSSOP package (θ = 45°C/W), at an ambient

temperature of 50°C:

JA

40

P_Q= 40(0.0015)+ 5(0.003) = 0.08W

T = 50 + (45 • 0.92) + (5 • 1.31) = 98°C

J

Total power dissipation in the IC is given by:

= P + P + P

Die temperature can peak for certain combinations of V_IN,

V_OUTand load current. While higher V_INgives greater

switch AC losses, quiescent and catch diode losses, a

P

TOT

SW

BOOST

Q

= 0.8W + 0.04W + 0.08W = 0.92W

34301fa

19

LT3430/LT3430-1

APPLICATIONS INFORMATION

lower V_INmay generate greater losses due to switch DC

losses. In general, the maximum and minimum V_INlevels

should be checked with maximum typical load current for

calculation of the LT3430/LT3430-1 die temperature. If a

more accurate die temperature is required, a measure-

ment of the SYNC pin resistance (to GND) can be used.

The SYNC pin resistance can be measured by forcing a

voltage no greater than 0.5V at the pin and monitoring the

pin current over temperature in an oven. This should be

donewithminimaldevicepower(lowV_INandnoswitching

(V_C= 0V)) in order to calibrate SYNC pin resistance with

ambient (oven) temperature.

section, the value of C2 was designed for a 0.7V droop in

V =V .Hence,anoutputvoltageaslowas4Vwould

still allow the minimum 3.3V for the boost function using

the C2 capacitor calculated. If a target output voltage of

12V is required, however, an excess of 8V is placed across

the boost capacitor which is not required for the boost

function but still dissipates additional power.

C2

DROOP

What is required is a voltage drop in the path of D2 to

achieve minimal power dissipation while still maintaining

minimum boost voltage across C2. A zener, D4, placed in

series with D2 (see Figure 9), drops voltage to C2.

Example:theBOOSTpinpowerdissipationfora20Vinput

to 12V output conversion at 2A is given by:

Note: Some of the internal power dissipation in the IC,

due to BOOST pin voltage, can be transferred outside

of the IC to reduce junction temperature, by increasing

the voltage drop in the path of the boost diode D2 (see

Figure 9). This reduction of junction temperature inside

the IC will allow higher ambient temperature operation for

a given set of conditions. BOOST pin circuitry dissipates

power given by:

12• 2 /36 •12

(

)

P

=

= 0.4W

BOOST

20

If a 7V zener D4 is placed in series with D2, then power

dissipation becomes :

12• 2 /36 •5

(

)

P

=

= 0.167W

BOOST

V_OUT• I /36 •V

20

(

)

SW

C2

P_DISSBOOST Pin =

V

IN

For an FE package with thermal resistance of 45°C/W,

ambient temperature savings would be, T(ambient) sav-

Typically V (the boost voltage across the capacitor C2)

C2

equals V . This is because diodes D1 and D2 can be

OUT

considered almost equal, where:

D2

D4

V

C2

= V – V – (–V ) = V

OUT FD2 FD1 OUT

Hence the equation used for boost circuitry power dissi-

pation given in the previous Thermal Calculations section

is stated as:

C2

D1

BOOST

L1

V

SW

IN

OUT

IN

V_OUT• I /36

(

)

•V_OUT

SW

C3

P_DISS(BOOST)

=

LT3430/

LT3430-1

V

IN

SHDN

BIAS

Here it can be seen that boost power dissipation increases

as the square of V . It is possible, however, to reduce

R1

+

SYNC

GND

FB

OUT

C1

R2

V

C

V belowV tosavepowerdissipationbyincreasingthe

C2

OUT

voltage drop in the path of D2. Care should be taken that

does not fall below the minimum 3.3V boost voltage

C

V

F

C2

R

C

required for full saturation of the internal power switch.

C

For output voltages of 5V, V is approximately 5V. During

C2

switch turn on, V will fall as the boost capacitor C2 is

C2

3430 F09

dicharged by the BOOST pin. In the previous BOOST Pin

Figure 9. BOOST Pin, Diode Selection

34301fa

20

LT3430/LT3430-1

APPLICATIONS INFORMATION

ings = 0.233W • 45°C/W = 11°C. The 7V zener should be

sized for excess of 0.233W operaton. The tolerances of

In summary:

1. Be aware that the simultaneous requirements of high

V , high I and high f may not be achievable in

the zener should be considered to ensure minimum V

C2

IN

OUT

OSC

exceeds 3.3V + V

.

DROOP

practice due to internal dissipation. The Thermal Con-

siderations section offers a basis to estimate internal

power.Inquestionablecasesaprototypesupplyshould

be built and exercised to verify acceptable operation.

Input Voltage vs Operating Frequency Considerations

TheabsolutemaximuminputsupplyvoltagefortheLT3430/

LT3430-1isspeciﬁedat60V.Thisisbasedsolelyoninternal

semiconductorjunctionbreakdowneffects.Duetointernal

2. ThesimultaneousrequirementsofhighV ,lowV and

IN

OUT

high f

can result in an unacceptably short minimum

OSC

power dissipation, the actual maximum V achievable in

IN

switch on time. Cycle skipping and/or odd/even cycle

behavior will result although correct output voltage is

usually maintained. The LT3430-1 100kHz switching

a particular application may be less than this.

A detailed theoretical basis for estimating internal power

loss is given in the section, Thermal Considerations. Note

that AC switching loss is proportional to both operating

frequencyandoutputcurrent.ThemajorityofACswitching

loss is also proportional to the square of input voltage.

frequency will allow higher V /V

ratios without

IN OUT

pulse skipping.

FREQUENCY COMPENSATION

For example, while the combination of V = 40V, V

IN

OUT

Before starting on the theoretical analysis of frequency

response, the following should be remembered—the

worse the board layout, the more difﬁcult the circuit will

be to stabilize. This is true of almost all high frequency

analog circuits, read the Layout Considerations section

ﬁrst. Common layout errors that appear as stability prob-

lems are distant placement of input decoupling capacitor

= 5V at 2A and f

= 200kHz may be easily achievable,

OSC

simultaneously raising V to 60V and f

to 700kHz is

IN

OSC

not possible. Nevertheless, input voltage transients up to

60V can usually be accommodated, assuming the result-

ing increase in internal dissipation is of insufﬁcient time

duration to raise die temperature signiﬁcantly.

Asecondconsiderationiscontrollability.Apotentiallimita-

and/or catch diode, and connecting the V compensation

C

tion occurs with a high step-down ratio of V to V , as

IN

OUT

to a ground track carrying signiﬁcant switch current. In

addition, the theoretical analysis considers only ﬁrst

order non-ideal component behavior. For these reasons,

it is important that a ﬁnal stability check is made with

production layout and components.

this requires a correspondingly narrow minimum switch

on time. An approximate expression for this (assuming

continuous mode operation) is given as follows:

V_OUT+ V

F

min t_ON

=

V

f

(

)

The LT3430/LT3430-1 use current mode control. This al-

leviates many of the phase shift problems associated with

the inductor. The basic regulator loop is shown in Figure

IN OSC

where:

V = input voltage

IN

10. The LT3430/LT3430-1 can be considered as two g

blocks, the error ampliﬁer and the power stage.

m

V

OUT

= output voltage

V = Schottky diode forward drop

F

OSC

Figure 11 shows the overall loop response. At the V

C

f

= switching frequency

pin, the frequency compensation components used are:

R = 3.3k, C = 0.022µF and C = 220pF. The output

A potential controllability problem arises if the LT3430/

LT3430-1 are called upon to produce an on time shorter

than it is able to produce. Feedback loop action will lower

C

F

capacitor used is a 100µF, 10V tantalum capacitor with

typical ESR of 100mΩ. LT3430-1 uses two of these

capacitors in parallel.

then reduce the V control voltage to the point where

C

some sort of cycle-skipping or odd/even cycle behavior

The ESR of the tantalum output capacitor provides a use-

is exhibited.

ful zero in the loop frequency response for maintaining

34301fa

21

LT3430/LT3430-1

APPLICATIONS INFORMATION

stability. This ESR, however, contributes signiﬁcantly to

the ripple voltage at the output (see Output Ripple Voltage

in the Applications Information section). It is possible to

reduce capacitor size and output ripple voltage by replac-

ing the tantalum output capacitor with a ceramic output

capacitor because of its very low ESR. The zero provided

by the tantalum output capacitor must now be reinserted

backintotheloop.Alternatively,theremaybecaseswhere,

even with the tantalum output capacitor, an additional

zero is required in the loop to increase phase margin for

improved transient response.

loop over the entire V range (to allow for stable pulse

IN

skippingforhighV -to-V ratios≥10).Aceramicoutput

IN

OUT

capacitor can still be used with a simple adjustment to the

resistor R for stable operation (see Ceramic Capacitors

C

section for stabilizing LT3430). If additional phase margin

is required, a capacitor (C ) can be inserted between the

FB

output and FB pin but care must be taken for high output

voltageapplications.Suddenshortstotheoutputcancreate

unacceptably large negative transients on the FB pin.

For V -to-V

ratios < 10, higher loop bandwidths are

OUT

IN

possible by readjusting the frequency compensation

Azerocanbeaddedintotheloopbyplacingaresistor(R )

components at the V pin.

C

at the V pin in series with the compensation capacitor,

C

Whencheckingloopstability,thecircuitshouldbeoperated

over the application’s full voltage, current and tempera-

ture range. Proper loop compensation may be obtained

by empirical methods as described in Application Notes

19 and 76.

C , or by placing a capacitor (C ) between the output

C

FB

and the FB pin.

When using R , the maximum value has two limitations.

C

First, the combination of output capacitor ESR and R

C

may stop the loop rolling off altogether. Second, if the

loop gain is not rolled off sufﬁciently at the switching

CONVERTER WITH BACKUP OUTPUT REGULATOR

frequency, output ripple will perturb the V pin enough to

C

Insystemswithaprimaryandbackupsupply,forexample,

a battery powered device with a wall adapter input, the

output of the LT3430/LT3430-1 can be held up by the

backup supply with the LT3430/LT3430-1 input discon-

nected. In this condition, the SW pin will source current

causeunstabledutycycleswitchingsimilartosubharmonic

oscillations. If needed, an additional capacitor (C ) can be

F

addedacrosstheR /C networkfromtheV pintoground

C

to further suppress V ripple voltage.

C

With a tantalum output capacitor, the LT3430/LT3430-1

into the V pin. If the SHDN pin is held at ground, only the

IN

already includes a resistor (R ) and ﬁlter capacitor (C )

C

F

shut down current of 30µA will be pulled via the SW pin

at the V pin (see Figures 10 and 11) to compensate the

C

from the second supply. With the SHDN pin ﬂoating, the

80

60

180

150

120

90

LT3430/LTC3430-1

GAIN

CURRENT MODE

POWER STAGE

V

SW

OUTPUT

40

ERROR

g

m

= 2mho

AMPLIFIER

C

R1

R2

FB

20

–

TANTALUM CERAMIC

g

=

m

PHASE

2000µmho

ESR

C1

ESL

C1

0

60

+

R

1.22V

O

R

LOAD

200k

+

–20

–40

30

GND

V

C

0

10

100

1k

10k

100k

1M

R

C

F

FREQUENCY (Hz)

3430 F11

V

= 42V

R

C

= 3.3k

= 22nF

= 220pF

IN

C

F

C

V

= 5V

OUT

LOAD

I

= 1A

C

= 100µF, 10V, 0.1Ω

3430 F10

OUT

Figure 10. Model for Loop Response

Figure 11. Overall Loop Response

34301fa

22

LT3430/LT3430-1

APPLICATIONS INFORMATION

LT3430/LT3430-1 will consume their quiescent operating

output.Outputrisetimeiscontrolledbythecurrentthrough

SS BE

current of 1.5mA. The V pin will also source current to

C

deﬁned by R4 and Q1’s V . Once the output is in

IN

any other components connected to the input line. If this

load is greater than 10mA or the input could be shorted to

ground, a series Schottky diode must be added, as shown

inFigure12. Withthesesafeguards, theoutputcanbeheld

regulation, Q1 turns off and the circuit operates normally.

R3 is transient protection for the base of Q1.

R4 C

V

OUT

( )( _SS)(

)

Rise Time =

V_BE

at voltages up to the V absolute maximum rating.

IN

Using the values shown in Figure 10,

47 •10³15•10^–9

5

BUCK CONVERTER WITH ADJUSTABLE SOFT-START

( )

(

)(

)

Rise Time =

= 5ms

0.7

Large capacitive loads or high input voltages can cause

high input currents at start-up. Figure 13 shows a circuit

that limits the dv/dt of the output at start-up, controlling

the capacitor charge rate. The buck converter is a typical

The ramp is linear and rise times in the order of 100ms are

possible. Since the circuit is voltage controlled, the ramp

rate is unaffected by load characteristics and maximum

output current is unchanged. Variants of this circuit can

be used for sequencing multiple regulator outputs.

conﬁguration with the addition of R3, R4, C and Q1. As

SS

the output starts to rise, Q1 turns on, regulating switch

current via the V pin to maintain a constant dv/dt at the

C

D2

MMSD914TI

C2

0.68µF

33µH

D3

30BQ060

BOOST

REMOVABLE

INPUT

V

LT3430 SW

IN

5V, 2A

ALTERNATE

SUPPLY

54k

BIAS

R1

SHDN

SYNC

15.4k

FB

+

C1

100µF

10V

R2

4.99k

GND

V

C

D1

30BQ060

25k

R

C

C3

4.7µF

C

F

3.3k

C

220pF

C

0.022µF

3430 F12

Figure 12. Dual Source Supply with 25µA Reverse Leakage

D2

MMSD914TI

C2

0.68µF

L1

33µH

BOOST

BIAS

SW

OUTPUT

5V

2A

INPUT

40V

V

IN

C3

D1

^C1+

R1

4.7µF

50V

CER

30BQ060

100µF

LT3430

15.4k

OR B250A

10V

SHDN

SYNC GND

FB

C

R2

4.99k

V

C

SS

15nF

C

F

R3

2k

Q1

220pF

R

C

3.3k

3430 F13

C

R4

47k

0.022µF

L1: CDRH104R-220M

Figure 13. Buck Converter with Adjustable Soft-Start

34301fa

23

LT3430/LT3430-1

APPLICATIONS INFORMATION

DUAL OUTPUT SEPIC CONVERTER

POSITIVE-TO-NEGATIVE CONVERTER

ThecircuitinFigure14generatesbothpositiveandnegative

5Voutputswithasinglepieceofmagnetics.Thetwoinduc-

tors shown are actually just two windings on a standard

Coiltronics inductor. The topology for the 5V output is a

standard buck converter. The –5V topology would be a

simple ﬂyback winding coupled to the buck converter if

C4 were not present. C4 creates a SEPIC (single-ended

primary inductance converter) topology which improves

regulation and reduces ripple current in L1. Without C4,

the voltage swing on L1B compared to L1A would vary

due to relative loading and coupling losses. C4 provides a

low impedance path to maintain an equal voltage swing in

L1B, improving regulation. In a ﬂyback converter, during

switch on time, all the converter’s energy is stored in L1A

only, since no current ﬂows in L1B. At switch off, energy

is transferred by magnetic coupling into L1B, powering

the –5V rail. C4 pulls L1B positive during switch on time,

causing current to ﬂow, and energy to build in L1B and

C4. At switch off, the energy stored in both L1B and C4

supply the –5V rail. This reduces the current in L1A and

changes L1B current waveform from square to triangular.

For details on this circuit, including maximum output cur-

rents, see Design Note 100.

The circuit in Figure 15 is a positive-to-negative topology

using a grounded inductor. It differs from the standard

approach in the way the IC chip derives its feedback

signal because the LT3430/LT3430-1 accepts only posi-

tive feedback signals. The ground pin must be tied to the

regulated negative output. A resistor divider to the FB pin

then provides the proper feedback voltage for the chip.

Thefollowingequationcanbeusedtocalculatemaximum

load current for the positive-to-negative converter:

⎡

⎤

(V )(V_OUT

)

IN

I_P–

(V_OUT)(V – 0.15)

IN

⎢

⎥

2(V_OUT+ V )(f)(L)

IN

⎣

⎦

I_MAX

=

(V_OUT+ V – 0.15)(V_OUT+ V_F)

IN

I = Maximum rated switch current

P

V = Minimum input voltage

IN

V

OUT

= Output voltage

V = Catch diode forward voltage

F

0.15 = Switch voltage drop at 3A

Example: with V

= 5.5V, V

MAX

= 12V, L = 10µH,

OUT

IN(MIN)

V = 0.52V, I = 3A: I

= 0.6A.

F

P

D2

MMSD914TI

C2

0.68µF

L1A*

25µH

BOOST

V

OUT

5V

IN

V

SW

IN

7.5V TO 60V

LT3430

R1

SHDN

SYNC

GND

15.4k

C3

4.7µF

100V

+

C1

100µF

10V TANT

FB

C

R2

4.99k

V

CERAMIC

D1

C

F

R

C

220pF

3.3k

C

0.022µF

GND

C4

+

C5

100µF

10V TANT

* L1 IS A SINGLE CORE WITH TWO WINDINGS

COILTRONICS #CTX25-4A

100µF

10V

TANT

L1B*

†

IF LOAD CAN GO TO ZERO, AN OPTIONAL

V

OUT

PRELOAD OF 1k TO 5k MAY BE USED TO

IMPROVE LOAD REGULATION

D1, D3: 30BQ060

–5V^†

3430 F14

D3

Figure 14. Dual Output SEPIC Converter

34301fa

24

LT3430/LT3430-1

APPLICATIONS INFORMATION

†

D4

7V

Minimum inductor continuous mode:

(V )(V_OUT

D2

MMSD914TI

)

IN

L_MIN

=

C2

0.68µF

L1*

10µH

⎡

⎤

⎛

⎝

(V_OUT+ V_F)⎞

2(f)(V + V_OUT) I_P– I_OUT1+

INPUT

5.5V TO

44V

BOOST

LT3430

⎜

⎟

IN

⎢

⎥

V

IN

⎠

V

SW

FB

IN

⎣

⎦

R1

36.5k

D3

For a 40V to –12V converter using the LT3430/LT3430-

1 with peak switch current of 3A and a catch diode of

0.52V:

30BQ015

GND

V

C

C3

+

C1

100µF

16V TANT

D1

30BQ060

4.7µF

100V

CER

C

R2

4.12k

(40)²(3)²

4(40 + 12)(40 + 12 + 0.52)

C

R

F

OUTPUT**

–12V, 0.5A

I_CONT

=

= 1.148A

3430 F15

* INCREASE L1 FOR HIGHER CURRENT APPLICATIONS.

SEE APPLICATIONS INFORMATION

For a load current of 0.5A, this says that discontinuous

mode can be used and the minimum inductor needed is

found from:

** MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE

AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION

Figure 15. Positive-to-Negative Converter

2(12)(0.5)

INDUCTOR VALUE

L_MIN

=

= 6.7µH

(200•10³)(3)²

The criteria for choosing the inductor is typically based on

ensuring that peak switch current rating is not exceeded.

This gives the lowest value of inductance that can be

used, but in some cases (lower output load currents) it

may give a value that creates unnecessarily high output

ripple voltage.

In practice, the inductor should be increased by about

30% over the calculated minimum to handle losses and

variations in value. This suggests a minimum inductor of

10µH for this application.

Ripple Current in the Input and Output Capacitors

The difﬁculty in calculating the minimum inductor size

needed is that you must ﬁrst decide whether the switcher

will be in continuous or discontinuous mode at the critical

point where switch current reaches 3A. The ﬁrst step is to

usethefollowingformulatocalculatetheloadcurrentabove

which the switcher must use continuous mode. If your

load current is less than this, use the discontinuous mode

formula to calculate minimum inductor needed. If load

current is higher, use the continuous mode formula.

Positive-to-negativeconvertershavehighripplecurrentin

the input capacitor. For long capacitor lifetime, the RMS

value of this current must be less than the high frequency

ripplecurrentratingofthecapacitor.Thefollowingformula

willgiveanapproximatevalueforRMSripplecurrent. This

formula assumes continuous mode and large inductor

value. Small inductors will give somewhat higher ripple

current, especially in discontinuous mode. The exact for-

mulas are very complex and appear in Application Note

44, pages 29 and 30. For our purposes here I have simply

added a fudge factor (ff). The value for ff is about 1.2 for

higher load currents and L ≥15µH. It increases to about

2.0 for smaller inductors at lower load currents.

Output current where continuous mode is needed:

(V )²(I_P)²

IN

I_CONT

>

4(V + V_OUT)(V + V_OUT+ V_F)

IN

Minimum inductor discontinuous mode:

V_OUT

Capacitor I_RMS= (ff)(I_OUT

)

2(V_OUT)(I_OUT

(f)(I_P)²

)

V

IN

L_MIN

=

ff = 1.2 to 2.0

The output capacitor ripple current for the positive-to-

negative converter is similar to that for a typical buck

regulator—it is a triangular waveform with peak-to-peak

34301fa

25

LT3430/LT3430-1

APPLICATIONS INFORMATION

valueequaltothepeak-to-peaktriangularwaveformofthe

ESR of the chosen capacitor (see Output Ripple Voltage

in Applications Information).

inductor. The low output ripple design in Figure 15 places

theinputcapacitorbetweenV andtheregulatednegative

IN

Diode Current

output. This placement of the input capacitor signiﬁcantly

reduces the size required for the output capacitor (versus

Average diodecurrentisequaltoloadcurrent. Peak diode

current will be considerably higher.

placing the input capacitor between V and ground).

IN

The peak-to-peak ripple current in both the inductor and

output capacitor (assuming continuous mode) is:

Peak diode current:

Continuous Mode =

DC •V

(V + V_OUT

)

(V )(V_OUT)

IN

2(L)(f)(V + V_OUT)

IN

I_P-P

=

I_OUT

+

f •L

V

IN

V_OUT+ V_F

V_OUT+ V + V_F

2(I_OUT)(V_OUT

(L)(f)

)

DC = Duty Cycle =

Discontinuous Mode =

IN

I_P-P

12

I_COUT(RMS) =

Keep in mind that during start-up and output overloads,

average diode current may be much higher than with nor-

mal loads. Care should be used if diodes rated less than

1A are used, especially if continuous overload conditions

must be tolerated.

The output ripple voltage for this conﬁguration is as low

as the typical buck regulator based predominantly on the

inductor’s triangular peak-to-peak ripple current and the

TYPICAL APPLICATION

3.3V, 2A Buck Converter

MMSD914TI

6

1.5µF

BOOST

68µH

V

3.3V

2A

IN

OUT

3, 4

2, 5

5.5V*

V

SW

IN

TO 60V

30BQ060

4.7µF

LT3430-1

100V

+

100µF 10V

SOLID

TANTALUM

2 IN PARALLEL

15

14

10

12

OFF ON

SHDN

BIAS

20.5k

12.1k

SYNC

GND

FB

V

C

1, 8, 9, 16

11

220pF

3.3k

0.022µF

3430 F16

*FOR INPUT VOLTAGES BELOW 7.5V, SOME RESTRICTIONS MAY APPLY

34301fa

26

LT3430/LT3430-1

PACKAGE DESCRIPTION

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation BB

4.90 – 5.10*

(.193 – .201)

3.58

(.141)

3.58

(.141)

16 1514 13 12 1110

9

6.60 0.10

2.94

(.116)

4.50 0.10

SEE NOTE 4

6.40

2.94

(.252)

(.116)

0.45 0.05

BSC

1.05 0.10

0.65 BSC

5

7

8

1

2

3

4

6

RECOMMENDED SOLDER PAD LAYOUT

1.10

(.0433)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

FE16 (BB) TSSOP 0204

0.195 – 0.30

(.0077 – .0118)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

MILLIMETERS

(INCHES)

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

34301fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

27

LT3430/LT3430-1

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LT1074/LT1074HV

4.4A (I ), 100kHz, High Efﬁciency Step-Down DC/DC V : 7.3V to 45V/64V, V

: 2.21V, I : 8.5mA, I : 10µA DD-5/7,

OUT(MIN) Q SD

OUT

IN

Converters

TO220-5/7

LT1076/LT1076HV

LT1676

1.6A (I ), 100kHz, High Efﬁciency Step-Down DC/DC V : 7.3V to 45V/64V, V

: 2.21V, I : 8.5mA, I : 10µA DD-5/7,

Q SD

OUT

IN

OUT(MIN)

Converters

TO220-5/7

60V, 440mA (I ), 100kHz, High Efﬁciency Step-Down V : 7.4V to 60V, V

: 1.24V, I : 3.2mA, I : 2.5µA, S8

Q SD

OUT

IN

OUT(MIN)

DC/DC Converter

LT1765

25V, 2.75A (I ), 1.25MHz, High Efﬁciency Step-Down V : 3V to 25V, V

: 1.20V, I : 1mA, I : 15µA, S8, TSSOP16E

OUT(MIN) Q SD

OUT

IN

DC/DC Converter

LT1766

60V, 1.2A (I ), 200kHz, High Efﬁciency Step-Down

V : 5.5V to 60V, V

: 1.20V, I : 2.5mA, I : 25µA, TSSOP16/E

OUT(MIN) Q SD

OUT

IN

DC/DC Converter

LT1767

25V, 1.2A (I ), 1.25MHz, High Efﬁciency Step-Down

V : 3V to 25V, V

IN

: 1.20V, I : 1mA, I : 6µA, MS8/E

OUT(MIN) Q SD

OUT

DC/DC Converter

LT1776

40V, 550mA (I ), 200kHz, High Efﬁciency Step-Down V : 7.4V to 40V, V

: 1.24V, I : 3.2mA, I : 30µA, N8, S8

OUT(MIN) Q SD

OUT

IN

DC/DC Converter

LT1940

25V, Dual 1.2A (I ), 1.1MHz, High Efﬁciency

V : 3V to 25V, V

IN

: 1.2V, I : 3.8mA, I : <1µA, TSSOP16E

OUT(MIN) Q SD

OUT

Step-Down DC/DC Converter

LT1956

60V, 1.2A (I ), 500kHz, High Efﬁciency Step-Down

V : 5.5V to 60V, V

: 1.20V, I : 2.5mA, I : 25µA, TSSOP16/E

Q SD

OUT

IN

OUT(MIN)

DC/DC Converter

LT1976

60V, 1.2A (I ), 200kHz, High Efﬁciency Step-Down

V : 3.3V to 60V, V

IN

: 1.20V, I : 100µA, I : <1µA, TSSOP16/E

Q SD

OUT

DC/DC Converter with Burst Mode^®Operation

80V, 50mA Low Noise Linear Regulator

LT3010

V : 1.5V to 80V, V

IN

: 1.28V, I : 30µA, I : <1µA, MSE8

Q SD

LTC3407

Dual 600mA (I ), 1.5MHz, Synchronous Step-Down

V : 2.5V to 5.5V, V

: 0.6V, I : 40µA, I : <1µA, MS10E

Q SD

OUT

IN

OUT(MIN)

DC/DC Converter

LTC3412

2.5A (I ), 4MHz, Synchronous Step-Down DC/DC

V : 2.5V to 5.5V, V

IN

: 0.8V, I : 60µA, I : <1µA, TSSOP16E

Q SD

OUT

Converter

LTC3414

4A (I ), 4MHz, Synchronous Step-Down DC/DC

V : 2.3V to 5.5V, V

IN

: 0.8V, I : 64µA, I : <1µA, TSSOP20E

Q SD

OUT

Converter

LT3430/LT3431

LT3433

60V, 2.75A (I ), 200kHz/500kHz, High Efﬁciency

V : 5.5V to 60V, V

: 1.20V, I : 2.5mA, I : 30µA, TSSOP16E

OUT

IN

OUT(MIN) Q SD

Step-Down DC/DC Converters

60V, 400mA (I ), 200kHz, High Efﬁciency

V : 4V to 60V, V

: 3.3V to 20V, I : 100µA, I : <1µA, TSSOP16E

Q SD

OUT

IN

OUT(MIN)

Step-Up Step-Down DC/DC Converter with Burst Mode

Operation

LTC3727/LTC3727-1 36V, 500kHz, High Efﬁciency Step-Down DC/DC

Controllers

V : 4V to 36V, V

IN

: 0.8V, I : 670µA, I : 20µA, QFN-32, SSOP-28

OUT(MIN) Q SD

Burst Mode is a registered trademark of Linear Technology Corporation.

34301fa

LT 0107 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

28

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT3430-1_15
厂家：	Linear
描述：	High Voltage, 3A, 200kHz/100kHz Step-Down Switching Regulators
文件：	总28页 (文件大小：332K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT3430-1_15 [Linear]

相关型号：

LT3430EFE

LT3430EFE#TR

LT3430EFE-1

LT3430EFE-1#PBF

LT3430EFE-1#TR

LT3430IFE

LT3430IFE#TRMPBF

LT3430IFE-1

LT3430IFE-1#PBF

LT3430IFE-1#TR

LT3430IFE-1#TRPBF

LT3430_15