LT3505IDD#TRPBF [Linear]
LT3505 - 1.2A, Step-Down Switching Regulator in 3mm x 3mm DFN; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C;
| 型号： | LT3505IDD#TRPBF |
| 厂家： | 
Linear |
| 描述： | LT3505 - 1.2A, Step-Down Switching Regulator in 3mm x 3mm DFN; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C 开关 |
| 文件： | 总30页 (文件大小：342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3510
Monolithic Dual Tracking
2A Step-Down Switching
Regulator
FEATURES
DESCRIPTION
n
Wide Input Range: 3.1V to 25V
The LT®3510 is a dual current mode PWM step-down
DC/DC converter with two internal 2.5A switches. Inde-
pendent input voltage, feedback, soft-start and power
good pins for each channel simplify complex power
supply tracking/sequencing requirements.
n
Two Switching Regulators with 2A Output Capability
n
Independent Supply to Each Regulator
n
Adjustable/Synchronizable Fixed Frequency
Operation from 250kHz to 1.5MHz
n
Antiphase Switching
Outputs Can be Paralleled
Both converters are synchronized to either a common
external clock input or a resistor programmable fixed
250kHz to 1.5MHz internal oscillator. At all frequencies, a
180° phase relationship between channels is maintained,
reducingvoltagerippleandcomponentsize.Programmable
frequency allows for optimization between efficiency and
external component size.
n
n
Independent, Sequential, Ratiometric or Absolute
Tracking Between Outputs
n
Independent Soft-Start and Power Good Pins
n
Enhanced Short-Circuit Protection
n
Low Dropout: 95% Maximum Duty Cycle
n
Low Shutdown Current: <10μA
n
Minimum input-to-output voltage ratios are improved
by allowing the switch to stay on through multiple clock
cycles, only switching off when the boost capacitor needs
recharging, resulting in ~95% maximum duty cycle.
20-Lead TSSOP Package with Exposed Leadframe
APPLICATIONS
n
DSP Power Supplies
Each output can be independently disabled using its own
soft-start pin, or by using the SHDN pin the entire part can
be placed in a low quiescent current shutdown mode.
n
Disc Drives
n
DSL/Cable Modems
n
Wall Transformer Regulation
n
The LT3510 is available in a 20-lead TSSOP package with
exposed leadframe for low thermal resistance.
Distributed Power Regulation
n
PCI Cards
L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks
and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
TYPICAL APPLICATION
3.3V and 1.8V Dual 2A Step-Down Converter with Output Tracking
V
IN
12V
Efficiency
4.7μF
V
V
100
90
80
70
60
50
40
30
20
10
0
IN1
IN2
61.9k
V
= 3.3V
= 2.5V
OUT
SHDN
R /SYNC
T
V
= 5V
OUT
BST1
SW1
BST2
SW2
3.3μH
4.7μH
0.47μF
B360A
0.47μF
V
V
= 1.8V
OUT
OUT
PMEG4005
47μF
B360A
PMEG4005
LT3510
IND1
IND2
V
OUT2
V
V
1.8V
2A
OUT1
3.3V
OUT2
V
OUT1
2A
100μF
10k
24.9k
PG1
FB1
V
PG2
FB2
V
I
= 12V
= 0A
IN
V
C2
OUT2
C1
FREQUENCY = 500kHz
470pF
40.2k
470pF
40.2k
SS/TRACK1 SS/TRACK2
GND
0
0.5
LOAD CURRENT (A)
1.5
2
1
8.06k
10pF
47pF
8.06k
0.1μF
3510 TA01b
3510 TA01a
3510fe
1
LT3510
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(Note 1)
TOP VIEW
V
, SHDN, PG1/2...................................... 25V/–0.3V
IN1/2
V
1
2
20
19
18
17
16
15
14
13
12
11
BST1
IN1
SW1/2....................................................................V
IN1/2
SW1
IND1
SS/TRACK1
BST1/2........................................................... 35V/–0.3V
BST1/2 Pins Above SW1/2........................................25V
IND1/2 ..................................................................... 4A
3
V
C1
V
4
FB1
OUT1
PG1
5
R /SYNC
T
21
V
........................................................ V
/–0.3V
OUT1/2
IN1/2
PG2
6
SHDN
FB2
FB1/2, SS1/2, R /SYNC............................................5.5V
C1/2
T
V
7
OUT2
V
...................................................................... 1mA
IND2
SW2
8
V
C2
Operating Junction Temperature Range
9
SS/TRACK2
BST2
LT3510EFE (Notes 2, 8) ..................... –40°C to 125°C
LT3510IFE (Notes 2, 8) ...................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
V
10
IN2
FE PACKAGE
20-LEAD PLASTIC TSSOP
T
= 125°C, θ = 45°C/W, θ = 10°C/W
JC(PAD)
JMAX
JA
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LT3510EFE#PBF
LT3510IFE#PBF
LEAD BASED FINISH
LT3510EFE
TAPE AND REEL
LT3510EFE#TRPBF
LT3510IFE#TRPBF
TAPE AND REEL
LT3510EFE#TR
PART MARKING*
LT3510FE
PACKAGE DESCRIPTION
TEMPERATURE RANGE
20-Lead TSSOP
–40°C to 125°C
–40°C to 125°C
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
LT3510FE
20-Lead TSSOP
PART MARKING*
LT3510FE
PACKAGE DESCRIPTION
20-Lead TSSOP
LT3510IFE
LT3510IFE#TR
LT3510FE
20-Lead TSSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TJ = 25°C. VVIN1/2 = 15V, VBST1/2 = open, VRT/SYNC = 2V, VVOUT1/2 = open,
unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
SHDN Threshold
SHDN Input Current
V
= 0V, R /SYNC = 133k
1.23
1.28
1.37
V
OUT1/2
T
V
SHDN
V
SHDN
= 1.375V
= 1.225V
7
2
10
3
13
5
μA
μA
Minimum Input Voltage Ch 1 (Note 3)
Minimum Input Voltage Ch 2
Supply Shutdown Current Ch 1
Supply Shutdown Current Ch 2
Supply Quiescent Current Ch 1
Supply Quiescent Current Ch 2
Feedback Voltage Ch 1/2
V
FB1/2
V
FB1/2
V
SHDN
V
SHDN
V
FB1/2
V
FB1/2
V
VC1/2
= 0V, V
= 0V, V
= 0V
= 0V, V
= 0V, V
= 0V, R /SYNC = 133k
2.8
2.8
9
3
3
V
V
VOUT1/2
VOUT1/2
IND1/2
T
= 0V
IND1/2
l
30
5
μA
μA
mA
μA
V
= 0V
0
= 0.9V
= 0.9V
= 1V
3.5
200
0.8
5
500
0.816
l
0.784
3510fe
2
LT3510
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VVIN1/2 = 15V, VBST1/2 = open, VRT/SYNC = 2V, VVOUT1/2 = open,
unless otherwise specified.
PARAMETER
CONDITIONS
MIN
–1
TYP
0
MAX
1
UNITS
%
l
l
l
l
Feedback Voltage Line Regulation
Feedback Voltage Offset Ch 1 to Ch 2
Feedback Bias Current Ch 1/Ch 2
V
VIN1/2
V
VC1/2
V
FB1/2
V
VC1/2
= 3V to 25V
= 1V
–16
–200
150
0
16
mV
nA
= 0.8V, V
= 1V
5μA
75
200
450
VC1/2
Error Amplifier g Ch 1/Ch 2
= 1V, I
=
275
1000
2.2
15
μmho
V/V
A/V
μA
m
VC1/2
Error Amplifier Gain Ch 1/Ch 2
Error Amplifier to Switch Gain Ch 1/Ch 2
Error Amplifier Source Current Ch 1/Ch 2
Error Amplifier Sink Current Ch 1/Ch 2
Error Amplifier High Clamp Ch 1/Ch 2
Error Amplifier Switching Threshold Ch 1/Ch 2
Soft-Start Source Current Ch 1/Ch 2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 0.6V, V
= 1V
10
15
25
30
FB1/2
FB1/2
FB1/2
OUT1/2
VC1/2
= 1V, V
= 0.7V
= 1V
20
μA
VC1/2
1.75
0.5
2
2.0
0.7
3
2.25
1.0
4.2
2.4
1000
125
16
V
= 5V, R /SYNC = 133k
V
T
l
= 0.6V, V
= 0.4V
μA
FB1/2
FB1/2
FB1/2
FB1/2
VC1/2
SS1/2
FB1/2
FB1/2
FB1/2
FB1/2
FB1/2
FB1/2
VIN1/2
FB1/2
SS1/2
Soft-Start V Ch 1/Ch 2
= 0.9V
= 0.6V, V
= 0V
1.9
200
50
2
V
OH
Soft-Start Sink Current Ch 1/Ch 2
= 1V
600
80
μA
SS1/2
Soft-Start V Ch 1/Ch 2
mV
mV
mA
mV
mV
μA
OL
l
Soft-Start to Feedback Offset Ch 1/Ch 2
Soft-Start Sink Current Ch 1/Ch 2 POR
Soft-Start POR Threshold Ch 1/Ch 2
Soft-Start Switching Threshold Ch 1/Ch 2
Power Good Leakage Ch 1/Ch 2
= 1V, V
= 0.4V
–16
0.5
55
0
SS1/2
= 0.4V (Note 4), V = 1V
1.5
80
2
VC
= 0V (Note 4)
= 0V
105
70
30
50
= 0.9V, V
= 25V, V
= 25V, V = 5V
OUT
0
1
PG1/2
VIN1/2
l
Power Good Threshold Ch 1/Ch 2
Rising, PG1/2 = 20k to 5V
Falling, PG1/2 = 20k to 5V
87
20
90
93
%
Power Good Hysteresis Ch 1/Ch 2
30
50
mV
μA
Power Good Sink Current Ch 1/Ch 2
Power Good Shutdown Sink Current Ch 1/Ch 2
= 0.65V, V
= 0.4V
400
10
800
50
1200
100
1
PG1/2
= 2V, V
= 0V, V
= 0.4V
μA
FB1/2
PG1/2
R /SYNC Reference Voltage
T
= 0.9V, I
= –40μA
0.93
0.975
V
RT/SYNC
Switching Frequency
R /SYNC = 133k, V
T
= 0.6V, V
FB1/2
= V + 3V
200
1.2
250
1.5
300
1.8
kHz
MHz
T
FB1/2
BST1/2
SW
R /SYNC = 15.4k, V
= 0.6V, V
= V + 3V
BST1/2
SW
Switching Phase Angle Ch A to Ch B
Minimum Boost for 100% Duty Cycle Ch 1/Ch 2
SYNC Frequency Range
R /SYNC = 133k, V
= 0.6V, V
= V + 3V
120
180
1.7
210
2
Deg
V
T
FB1/2
BST1/2
SW
V
V
= 0.7V, I
= –35μA (Note 5), V
= 0V
FB1/2
RT/SYNC
OUT
= V + 3V
250
120
40
1500
210
kHz
Deg
BST1/2
SW
SYNC Switching Phase Angle Ch A to Ch B
SYNC = 250kHz, V
= V + 3V
180
BST1/2
SW
IND + V
Current Ch 1/Ch 2
V
V
= 0V, V
= 0.9V
FB1/2
70
0
100
1
μA
μA
OUT
VOUT1/2
VOUT1/2
= 5V
IND to V
Maximum Current Ch 1/Ch 2
V
V
= 0.5V (Note 6), V
= 0.7V, V
= 20V
BST1/2
2.25
2.5
2.8
2.8
4
4
A
A
OUT
VOUT1/2
VOUT1/2
FB1/2
BST1/2
= 5V (Note 6), R /SYNC = 133k, V
= 20V
T
l
l
Switch Leakage Current Ch 1/Ch 2
Switch Saturation Voltage Ch 1/Ch 2
Boost Current Ch 1/Ch 2
V
= 0V, V
0
50
400
100
2.5
μA
mV
mA
V
SW1/2
SW1/2
SW1/2
SW1/2
VIN1/2 = 25V
I
I
I
= 2A, V
= 2A, V
= 2A, V
= 20V, V
= 20V, V
= 20V, V
= 0.7V
= 0.7V
250
50
BST1/2
BST1/2
BST1/2
FB1/2
FB1/2
FB1/2
25
Minimum Boost Voltage Ch 1/Ch 2
= 0.7V (Note 7)
1.4
Note 2: The LT3510EFE is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
3510fe
3
LT3510
ELECTRICAL CHARACTERISTICS
LT3510IFE is guaranteed and tested over the full –40°C to 125°C operating
junction temperature range.
Note 5: To enhance dropout operation, the output switch will be turned off
for the minimum off time only when the voltage across the boost capacitor
drops below the minimum boost for 100% duty cycle threshold.
Note 3: Minimum input voltage is defined as the voltage where internal
bias lines are regulated so that the reference voltage and oscillator remain
constant. Actual minimum input voltage to maintain a regulated output
will depend upon output voltage and load current. See Applications
Information.
Note 6: The IND to V
current flowing from the IND pin to the V
maximum current is defined as the value of
OUT
pin which resets the switch
OUT
latch when the V pin is at its high clamp.
C
Note 7: This is the minimum voltage across the boost capacitor needed to
Note 4: An internal power-on reset (POR) latch is set on the positive
transition of the SHDN pin through its threshold. The output of the latch
activates current sources on each SS pin which typically sink 1.5mA,
discharging the SS capacitor. The latch is reset when both SS pins are
driven below the soft-start POR threshold or the SHDN pin is taken below
its threshold.
guarantee full saturation of the internal power switch.
Note 8: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown Threshold and Minimum
Input Voltage vs Temperature
Feedback Voltage vs Temperature
RT/SYNC Voltage vs Temperature
3.0
2.5
2.0
1.5
0.816
0.811
0.806
0.801
1.05
1.03
1.01
0.99
0.97
0.95
MINIMUM INPUT
VOLTAGE
SHUTDOWN
THRESHOLD
VOLTAGE
1.0
0.5
0
0.796
0.791
0.786
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
3510 G04
3510 G02
3510 G03
Shutdown Quiescent Current
vs Temperature
Soft-Start Source Current
vs Temperature
IND to VOUT Maximum Current vs
Temperature
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
16
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
14
12
V
VIN1
10
8
V
V
= 5V
= 0V
OUT
OUT
6
4
2
V
VIN2
0
–25
0
50
75 100 125
–50
25
–50 –30 –10 10 30 50 70 90 110
TEMPERATURE (°C)
–50
0
25
50
75 100 125
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
3510 G05
3510 G30
3510 G07
3510fe
4
LT3510
TYPICAL PERFORMANCE CHARACTERISTICS
Soft-Start to Feedback Offset
Voltage vs Temperature
VC Switching Threshold Voltage
vs Temperature
Power Good Threshold Voltage
vs Temperature
4
1000
900
800
700
800
780
760
740
720
700
680
660
640
620
600
3
2
RISING
FALLING
1
0
V
= 5V
OUT
V
0
= 0V
OUT
–1
–2
–3
600
500
400
–4
–25
0
50
75 100 125
–50
–25
25
50
75
100 125
–50
25
–50
0
25
50
75 100 125
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3510 G08
3510 G09
3510 G10
Switching Frequency and Channel
Phase vs Temperature
Power Good Sink Current
vs Temperature
Minimum Switching Times
vs Temperature
1000
950
900
850
800
750
700
650
600
550
500
250
230
210
190
170
150
130
110
90
300
290
280
270
260
250
240
230
220
210
200
200
190
180
170
160
150
140
130
120
110
100
R /SYNC = 133k
T
MINIMUM ON TIME
PHASE
FREQUENCY
MINIMUM OFF TIME
70
50
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–25
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3510 G11
3510 G12
3510 G13
Switching Frequency and Channel
Phase vs Temperature
Synchronization Clock Frequency
Range vs Temperature
Channel Phase vs Temperature
with External Synchronization
188
1650
1600
1550
1500
200
195
190
185
180
175
170
165
160
155
150
2500
R
RT
/SYNC = 15.4k
186
164
182
180
178
176
174
172
170
168
2000
1500
1000
500
0
PHASE
MAXIMUM
SYNCHRONIZATION
FREQUENCY
SYNCHRONIZATION
FREQUENCY = 250kHz
FREQUENCY
1450
1400
1350
MINIMUM
SYNCHRONIZATION
FREQUENCY
SYNCHRONIZATION
FREQUENCY = 1500kHz
–50 –25
0
25
50
75 100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
3510 G16
3510 G14
3510 G15
3510fe
5
LT3510
TYPICAL PERFORMANCE CHARACTERISTICS
Frequency and Phase vs RT/SYNC
Pin Resistance
Switch Saturation Voltage
vs Switch Current
External Sync Duty Cycle Range
vs External Sync Frequency
1600
1400
1200
1000
800
190
185
180
175
170
165
160
155
150
100
90
80
70
60
50
40
30
20
10
0
250
125°C
25°C
FREQUENCY
MAXIMUM CLOCK
DUTY CYCLE
200
150
–50°C
PHASE
100
50
0
600
MINIMUM CLOCK
DUTY CYCLE
400
200
100
0
20
40
60
80 100 120 140
250
500
750
1000
1250
1500
1.3
0.5 0.7 0.9 1.1
1.5 1.7 1.9
RESISTANCE (kΩ)
FREQUENCY (kHz)
CURRENT (A)
3510 G18
3510 G17
3510 G19
Minimum Boost Voltage
vs Temperature
V
OUT + IND Current
VOUT + IND Current
vs VOUT Voltage
vs Temperature
2.5
2.0
1.5
1.0
0.5
0
100
95
90
85
80
75
70
65
60
55
50
100
90
80
70
60
50
40
30
20
10
0
50
75 100 125
–50
0
25
50
75 100 125
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4
VOLTAGE (V)
1.6
1.8 2.0
–50 –25
0
25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
3510 G21
3510 G22
3510 G23
Minimum Input Voltage
vs Load Current
Minimum Input Voltage
vs Load Current
Minimum Input Voltage
vs Load Current
6.0
5.5
5.0
4.5
7.5
7.0
V
= 3.3V
V
= 2.5V
V
= 5V
OUT
OUT
OUT
5.0
4.5
4.0
3.5
6.5
6.0
4.0
3.5
3.0
3.0
2.5
2.0
5.5
5.0
4.5
RUNNING
RUNNING
RUNNING
1000
1
10
100
1000
10000
1
10
100
10000
1
10
100
1000
10000
CURRENT (mA)
CURRENT (mA)
CURRENT (mA)
3510 G25
3510 G24
3510 G26
3510fe
6
LT3510
TYPICAL PERFORMANCE CHARACTERISTICS
Inductor Value vs Frequency for
2A Maximum Load Current
Inductor Value vs Frequency for
2A Maximum Load Current
Dropout Operation
1500
1250
1000
750
6
5
4
3
2
1
0
1500
1250
V
I
= 3.3V
= 1A
LOAD = 1A
V
= 5V
OUT
RIPPLE
OUT
I
= 1A
L = 2.2μH
RIPPLE
V
= 5V
L = 2.2μH
L = 3.3μH
OUT
L = 3.3μH
1000
L = 4.7μH
V
= 3.3V
OUT
750
500
250
L = 4.7μH
L = 6.8μH
500
250
FREQUENCY
1.5MHz
L = 6.8μH
L = 10μH
22.5
250kHz
4.5
3.5
INPUT VOLTAGE (V)
5
2
2.5
3
4
5.5
6
10
15
17.5
20
25
12.5
7
9
11 13 15 17 19 21 23 25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
3510 G27
3510 G29
3510 G28
3510fe
7
LT3510
PIN FUNCTIONS
SS1/SS2 (Pins 19, 12): The SS1/2 pins control the soft-
start and sequence of their respective outputs. A single
capacitor from the SS pin to ground determines the outpt
ramp rate. For soft-start and output tracking/sequencing
details, see the Applications Information section.
V
(Pin 1): The V pin powers the internal control
IN1
IN1
circuitry for both channels and is monitored by the
undervoltage lockout comparator. The V pin is also
IN1
connected to the collector of channel 1’s on-chip power
NPN switch. The V pin has high dI/dt edges and must
IN1
be decoupled to ground close to the pin of the device.
V /V (Pins 18, 13): The V pin is the output of the
C1 C2
C
error amplifier and the input to the peak switch current
comparator. It is normally used for frequency compensa-
tion, but can also be used as a current clamp or control
SW1/SW2 (Pins 2, 9): The SW pin is the emitter of the on-
chip power NPN. At switch off, the inductor will drive this
pin below ground with a high dV/dt. An external Schottky
catch diode to ground, close to the SW pin and respective
loop override. If the error amplifier drives V above the
C
maximum switch current level, a voltage clamp activates.
This indicates that the output is overloaded and current is
pulled from the SS pin, reducing the regulation point.
V decouplingcapacitor’sground,mustbeusedtoprevent
IN
this pin from excessive negative voltages.
IND1/IND2 (Pins 3, 8): The IND pin is the input to the
on-chip sense resistor that measures current flowing in
the inductor. When the current in the resistor exceeds
FB1/FB2 (Pins 17, 14): The FB pin is the negative input
to the error amplifier. The output switches regulate this
pin to 0.8V, with respect to the exposed ground pad. Bias
current flows out of the FB pin.
the current dictated by the V pin, the SW latch is held in
C
reset, disabling the output switch. Bias current flows out
of the IND pin when IND is less than 1.6V.
SHDN (Pin 15): The shutdown pin is used to turn off both
channels and control circuitry to reduce quiescent current
toatypicalvalueof9μA. Theaccurate1.28Vthresholdand
input current hysteresis can be used as an undervoltage
lockout, preventing the regulator from operating until the
input voltage has reached a predetermined level. Force
the SHDN pin above its threshold or let it float for normal
operation.
V
/V
(Pins 4, 7): The V
pin is the output to
OUT1 OUT2
OUT
the on-chip sense resistor that measures current flowing
in the inductor. When the current in the resistor exceeds
the current dictated by the V pin, the SW latch is held in
C
reset, disabling the output switch. Bias current flows out
of the V
pin when V
is less than 1.6V.
OUT
OUT
PG1/PG2 (Pins 5, 6): The power good pin is an open-col-
lector output that sinks current when the feedback falls
R /SYNC (Pin 16): This R /SYNC pin provides two modes
T
T
of setting the constant switch frequency.
below 90% of its nominal regulating voltage. For V
IN1
above 1V, its output state remains true, although during
Connecting a resistor from the R /SYNC pin to ground
T
shutdown,V undervoltagelockoutorthermalshutdown,
IN1
will set the R /SYNC pin to a typical value of 0.975V. The
T
its current sink capability is reduced. The PG pins can be
left open circuit or tied together to form a single power
good signal.
resultant switching frequency will be set by the resistor
value. Theminimumvalueof15.4kandmaximumvalueof
133k sets the switching frequency to 1.5MHz and 250kHz
respectively.
V
(Pin 10): The V pin is the collector of channel 2’s
IN2
IN2
on-chippowerNPNswitch. ThispinisindependentofV
IN1
Driving the R /SYNC pin with an external clock signal will
T
and may be connected to the same or a separate supply. In
either case, high dI/dt edges are present and decoupling
to ground must be used close to this pin.
synchronize the switch to the applied frequency. Synchro-
nization occurs on the rising edge of the clock signal after
3510fe
8
LT3510
PIN FUNCTIONS
the clock signal is detected, with switch 1 in phase with
thesynchronizationsignal. Eachrisingclockedgeinitiates
an oscillator ramp reset. A gain control loop servos the
oscillatorchargingcurrenttomaintainaconstantoscillator
amplitude. Hence, the slope compensation and channel
phase relationship remain unchanged. If the clock signal
is removed, the oscillator reverts to resistor mode and
BST1/BST2 (Pins 20, 11): The BST pin provides a higher
than V base drive to the power NPN to ensure a low
IN
switch drop. A comparator to V imposes a minimum
IN
off time on the SW pin if the BST pin voltage drops too
low. Forcing a SW off time allows the boost capacitor to
recharge.
Exposed Pad (Pin 21): GND. The Exposed Pad GND pin is
the only ground connection for the device. The Exposed
Pad should be soldered to a large copper area to reduce
thermal resistance. The GND pin is common to both chan-
nels and also serves as small-signal ground. For ideal
operation all small-signal ground paths should connect
to the GND pin at a single point, avoiding any high current
ground returns.
reapplies the 0.975V bias to the R /SYNC pin after the
T
synchronization detection circuitry times out. The clock
source impedance should be set such that the current out
oftheR /SYNCpininresistormodegeneratesafrequency
T
roughly equivalent to the synchronization frequency.
3510fe
9
LT3510
BLOCK DIAGRAM
R /SYNC
T
V
IN
ONE CHANNEL
CLK1
CLK2
OSCILLATOR
AND
R3
C
V
IN1
INTERNAL
REGULATOR
AND
AGC
BST
DROPOUT
ENHANCEMENT
REFERENCE
3μA
SLOPE
COMPENSATION
C3
7μA
PRE
S
R
–
+
DRIVER
Q
3
CIRCUITRY
SW
IND
SHDN
+
–
D
L1
+
SHUTDOWN
COMPARATOR
1.28V
+
–
POR
UNDERVOLTAGE
TSD
D
V
OUT
FB
+
0.8V
C
+
–
R1
R2
LOWEST
VOLTAGE
V
CLAMP
C
S
R
Q
POWER GOOD
COMPARATOR
3.25A
PGOOD
–
+
–
+
SS CLAMP
+
+
SOFT-START
RESET
COMPARATOR
80mV
0.72V
GND
3510 BD
SS
V
C
C
Figure 1. Block Diagram (One of Two Switching Regulators Shown)
APPLICATIONS INFORMATION
The LT3510 is dual channel, constant frequency, current
mode buck converter with internal 2A switches. Each
channelisidenticalwithacommonshutdownpin, internal
regulator,oscillator,undervoltagedetect,thermalshutdown
and power-on reset.
When the SHDN pin is opened or driven above 1.28V,
the internal bias circuits turn on generating an internal
regulated voltage, 0.8V , 0.975V R /SYNC references,
FB
T
and a POR signal which sets the soft-start latch.
As the R /SYNC pin reaches its 0.975V regulation point,
T
If the SHDN pin is taken below its 1.28V threshold the
LT3510 will be placed in a low quiescent current mode.
the internal oscillator will start generating two clock sig-
nals 180° out of phase for each regulator at a frequency
In this mode the LT3510 typically draws 9μA from V
determinedbytheresistorfromtheR /SYNCpintoground.
IN1
T
and <1μA from V . In shutdown mode the PG is active
Alternatively, if a synchronization signal is detected by the
IN2
with a typical sink capability of 50μA for V
greater than 2V.
voltage
LT3510attheR /SYNCpin,clocksignals180°outofphase
IN1
T
3510fe
10
LT3510
APPLICATIONS INFORMATION
is turned off. Once the switch is turned off the inductor
will drive the voltage at the SW pin low until the external
Schottky diode starts to conduct, decreasing the current
in the inductor. The cycle is repeated with the start of each
clock cycle. However, if the internal sense resistor voltage
exceedsthepredeterminedlevelatthestartofaclockcycle,
theflip-flopwillnotbesetresultinginafurtherdecreasein
inductor current. Since the output current is controlled by
will be generated at the incoming frequency on the rising
edge of the synchronization pulse with switch 1 in phase
with the synchronization signal. In addition, the internal
slope compensation will be automatically adjusted to pre-
vent subharmonic oscillation during synchronization.
The two regulators are constant frequency, current mode
step-down converters. Current mode regulators are con-
trolled by an internal clock and two feedback loops that
control the duty cycle of the power switch. In addition to
thenormalerroramplifier,thereisacurrentsenseamplifier
that monitors switch current on a cycle-by-cycle basis.
This technique means that the error amplifier commands
current to be delivered to the output rather than voltage.
A voltage fed system will have low phase shift up to the
resonant frequency of the inductor and output capacitor,
then an abrupt 180°, shift will occur. The current fed sys-
tem will have 90° phase shift at a much lower frequency,
but will not have the additional 90° shift until well beyond
the LC resonant frequency. This makes it much easier to
frequency compensate the feedback loop and also gives
much quicker transient response.
the V voltage, output regulation is achieved by the error
C
amplifier continually adjusting the V pin voltage.
C
The error amplifier is a transconductance amplifier that
compares the FB voltage to the lowest voltage present at
either the SS pin or an internal 0.8V reference. Compensa-
tion of the loop is easily achieved with a simple capacitor
or series resistor/capacitor from the V pin to ground.
C
Since the SS pin is driven by a constant current source, a
singlecapacitoronthesoft-startpinwillgeneratecontrolled
linear ramp on the output voltage.
If the current demanded by the output exceeds the maxi-
mum current dictated by the V pin clamp, the SS pin
C
will be discharged, lowering the regulation point until the
outputvoltagecanbesupportedbythemaximumcurrent.
When overload is removed, the output will soft-start from
the overload regulation point.
The Block Diagram in Figure 1 shows only one of the
switching regulators whose operation will be discussed
below. The additional regulator will operate in a similar
manner with the exception that its clock will be 180° out
of phase with the other regulator.
V
undervoltage detection or thermal shutdown will
IN1
set the soft-start latch, resulting in a complete soft-start
When, during power up, the POR signal sets the soft-start
latch, both SS pins will be discharged to ground to ensure
proper start-up operation. When the SS pin voltage drops
sequence.
The switch driver operates from either the V or BST volt-
IN
age. An external diode and capacitor are used to generate
below 80mV, the V pin is driven low disabling switching
C
a drive voltage higher than V to saturate the output NPN
IN
and the soft-start latch is reset. Once the latch is reset the
soft-start capacitor starts to charge with a typical value
of 3.25μA.
and maintain high efficiency. If the BST capacitor voltage
is sufficient, the switch is allowed to operate to 100% duty
cycle. If the boost capacitor discharges towards a level
insufficient to drive the output NPN, a BST pin compara-
tor forces a minimum cycle off time, allowing the boost
capacitor to recharge.
As the voltage rises above 80mV on the SS pin, the V pin
C
will be driven high by the error amplifier. When the voltage
on the V pin exceeds 0.7V, the clock set pulse sets the
C
driver flip-flop which turns on the internal power NPN
A power good comparator with 30mV of hysteresis trips
at 90% of regulated output voltage. The PG output is an
open-collector NPN that is off when the output is in regu-
lation allowing a resistor to pull the PG pin to a desired
voltage.
switch. This causes current from V , through the NPN
IN
switch, inductor and internal sense resistor, to increase.
When the voltage drop across the internal sense resistor
exceeds a predetermined level set by the voltage on the
V pin, the flip-flop is reset and the internal NPN switch
C
3510fe
11
LT3510
APPLICATIONS INFORMATION
Choosing the Output Voltage
1600
1400
1200
1000
800
190
185
180
175
170
165
160
155
150
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the 1% resis-
tors according to:
FREQUENCY
PHASE
V
0.8V
⎛
⎞
OUT
R1= R2 •
– 1
600
⎜
⎝
⎟
⎠
400
R2shouldbe10korlesstoavoidbiascurrenterrors.Refer-
ence designators refer to the Block Diagram in Figure 1.
200
100
0
20
40
60
80 100 120 140
RESISTANCE (kΩ)
Choosing the Switching Frequency
3510 F02
The LT3510 switching frequency is set by resistor R3 in
Figure 2. Frequency and Phase vs RT/SYNC Resistance
Figure1.TheR /SYNCpinisinternallyregulatedat0.975V.
T
The following example along with the data in Table 1
illustrates the tradeoffs of switch frequency selection.
Setting resistor R3 sets the current in the R /SYNC pin
T
which determines the oscillator frequency as illustrated
in Figure 2.
Example.
V = 25V, V
= 3.3V, I
= 2.5A,
The switching frequency is typically set as high as pos-
sible to reduce overall solution size. The LT3510 employs
techniques to enhance dropout at high frequencies but
efficiency and maximum input voltage decrease due to
switching losses and minimum switch on times. The
maximum recommended frequency can be approximated
by the equation:
IN
OUT
OUT
Temperature = 0°C to 85°C
t
= 200ns (85°C from the Typical Performance
ON(MIN)
Characteristics graph), V = 0.6V, V = 0.4V (85°C)
D
SW
3.3 + 0.6
25 – 0.4 + 0.6 200e-9
1
Max Frequency =
•
~ 750kHz
R /SYNC ~ 42k (Figure 2)
T
VOUT + VD
1
Frequency (Hz) =
•
V – V + VD tON(MIN)
IN
SW
Input Voltage Range
Once the switching frequency has been determined, the
input voltage range of the regulator can be determined.
The minimum input voltage is determined by either the
LT3510’s minimum operating voltage of ~2.8V, or by its
whereV istheforwardvoltagedropofthecatchdiode(D1
D
Figure 2), V is the voltage drop of the internal switch,
SW
and t
in the minimum on time of the switch, all at
ON(MIN)
maximum load current.
Table 1. Efficiency and Size Comparisons for Different RRT/SYNC Values. 3.3V
Output
EFFICIENCY
VIN1/2
79.0%
80.9%
81.2%
82.0%
83.9%
†
FREQUENCY
R /SYNC
V
= 12V
V
L*
C*
L + C AREA
T
IN(MAX)
16
18
22
24
24
2
1.2MHz
1.0MHz
750kHz
500kHz
250kHz
20.5k
26.7k
38.3k
61.9k
133k
1.5μH
2.2μH
3.3μH
4.7μH
10μH
22μF
47μF
47μF
47μF
100μF
63mm
66mm
66mm
66mm
2
2
2
2
172mm
†
V
is defined as the highest input voltage that maintains constant output voltage ripple.
IN(MAX)
*Inductor and capacitor values chosen for stability and constant ripple current.
3510fe
12
LT3510
APPLICATIONS INFORMATION
6.0
5.5
maximum duty cycle. The duty cycle is the fraction of time
that the internal switch is on during a clock cycle. Unlike
mostfixedfrequencyregulators,theLT3510willnotswitch
off at the end of each clock cycle if there is sufficient volt-
age across the boost capacitor (C3 in Figure 1) to fully
saturatetheoutputswitch.Forcedswitchoffforaminimum
time will only occur at the end of a clock cycle when the
boost capacitor needs to be recharged. This operation
has the same effect as lowering the clock frequency for a
fixed off time, resulting in a higher duty cycle and lower
minimum input voltage. The resultant duty cycle depends
on the charging times of the boost capacitor and can be
approximated by the following equation:
V
= 3.3V
OUT
5.0
4.5
START-UP
RUNNING
4.0
3.5
3.0
1
10
100
1000
10000
CURRENT (mA)
3510 F03
Figure 3. Minimum Input Voltage vs Load Current
1
Example:
= 3.3V, I
DCMAX
=
1
B
1+
V
= 1A, Frequency = 1MHz, Temperature
OUT
OUT
= 25°C
where B is 2A divided by the typical boost current from
the Electrical Characteristics.
V
SW
= 0.1V, B = 40 (from boost characteristics specifica-
tion), V = 0.4V, t
= 200ns
D
ON(MIN)
This leads to a minimum input voltage of:
1
VOUT + V
DCMAX
DCMAX
=
= 98%
V
=
D – VD + VSW
1
IN(MIN)
1+
40
where V is the voltage drop of the internal switch.
SW
3.3+ 0.4
0.98
V
=
– 0.4+ 0.1= 3.48V
IN(MIN)
Figure 3 shows a typical graph of minimum input voltage
vs load current for the 3.3V and 1.8V application on the
first page of this data sheet. The maximum input voltage
DCMIN = tMIN(ON) • f = 0.200
3.3+ 0.4
is determined by the absolute maximum ratings of the V
IN
and BST pins and by the frequency and minimum duty
V
=
– 0.4+ 0.1= 18.2V
IN(MAX)
0.200
cycle. The minimum duty cycle is defined as :
DC
= t
• Frequency
ON(MIN)
MIN
Inductor Selection and Maximum Output Current
Maximum input voltage as:
A good first choice for the inductor value is:
VOUT + VD
V
=
– VD + VSW
IN(MAX)
V – V
• V
(
)
IN
OUT OUT
DCMIN
L =
V • f
IN
Note that the LT3510 will regulate if the input voltage is
taken above the calculated maximum voltage as long as
where f is frequency in MHz and L is in μH.
maximum ratings of the V and BST pins are not violated.
IN
With this value the maximum load current will be ~2A,
independent of input voltage. The inductor’s RMS current
Howeveroperationinthisregionofinputvoltagewillexhibit
pulse skipping behavior.
3510fe
13
LT3510
APPLICATIONS INFORMATION
rating must be greater than your maximum load current
and its saturation current should be about 30% higher. To
keep efficiency high, the series resistance (DCR) should
be less than 0.05Ω.
less than the LT3510’s switch current limit I . I
2.5Aovertheentiredutycyclerange.Themaximumoutput
current is a function of the chosen inductor value:
is
LIM LIM
ΔIL
2
ΔIL
2
IOUT(MAX) = ILIM
–
= 2.5 –
Forapplicationswithadutycycleofabout50%, theinduc-
tor value should be chosen to obtain an inductor ripple
current less than 40% of peak switch current.
If the inductor value is chosen so that the ripple current
is small, then the available output current will be near the
switch current limit.
Of course, such a simple design guide will not always
result in the optimum inductor for your application. A
larger value provides a slightly higher maximum load
current, and will reduce the output voltage ripple. If your
load is lower than 2A, then you can decrease the value of
the inductor and operate with higher ripple current. This
allows you to use a physically smaller inductor, or one
with a lower DCR resulting in higher efficiency.
One approach to choosing the inductor is to start with the
simple rule given above, look at the available inductors
and choose one to meet cost or space goals. Then use
these equations to check that the LT3510 will be able to
deliver the required output current. Note again that these
equations assume that the inductor current is continuous.
Discontinuous operation occurs when I
L
is less than
OUT
The current in the inductor is a triangle wave with an
average value equal to the load current. The peak switch
current is equal to the output current plus half the peak-to-
peak inductor ripple current. The LT3510 limits its switch
current in order to protect itself and the system from
overload faults. Therefore, the maximum output current
that the LT3510 will deliver depends on the current limit,
the inductor value, switch frequency, and the input and
output voltages. The inductor is chosen based on output
currentrequirements, outputvoltageripplerequirements,
size restrictions and efficiency goals.
I /2 as calculated above.
Figure 4 illustrates the inductance value needed for a 3.3V
output with a maximum load capability of 2A. Referring
to Figure 4, an inductor value between 3.3μH and 4.7μH
will be sufficient for a 15V input voltage and a switch
frequency of 750kHz. There are several graphs in the
Typical Performance Characteristics section of this data
sheet that show inductor selection as a function of input
voltage and switch frequency for several popular output
1500
V
I
= 5V
RIPPLE
OUT
When the switch is off, the inductor sees the output volt-
age plus the catch diode drop. This gives the peak-to-peak
ripple current in the inductor:
= 1A
L = 2.2μH
1250
1000
750
L = 3.3μH
L = 4.7μH
1–DC V
)(
+ VD
(
)
OUT
ΔIL =
L • f
L = 6.8μH
where f is the switching frequency of the LT3510 and L
is the value of the inductor. The peak inductor and switch
current is:
500
250
L = 10μH
22.5
10
15
17.5
20
25
12.5
ΔIL
2
INPUT VOLTAGE (V)
ISW PK =ILPK =IOUT
+
(
)
3510 F04
Figure 4. Inductor Values for 2A Maximum Load Current
vs Frequency and Input Voltage
To maintain output regulation, this peak current must be
3510fe
14
LT3510
APPLICATIONS INFORMATION
voltages and output ripple currents. Also, low inductance
may result in discontinuous mode operation, which is
okay, but further reduces maximum load current. For
details of maximum output current and discontinuous
mode operation, see Linear Technology Application Note
source impedance, determine the energy storage require-
ments of the input capacitor. Determine the worst-case
condition for input ripple current and then size the input
capacitor such that it reduces input voltage ripple to an
acceptable level. Typical values for input capacitors run
from10μFatlowfrequenciesto2.2μFathigherfrequencies.
The combination of small size and low impedance (low
equivalentseriesresistanceorESR)ofceramiccapacitors
make them the preferred choice. The low ESR results in
verylowvoltagerippleandthecapacitorscanhandleplenty
of ripple current. They are also comparatively robust and
can be used in this application at their rated voltage. X5R
and X7R types are stable over temperature and applied
voltage,andgivedependableservice.Othertypes(Y5Vand
Z5U) have very large temperature and voltage coefficients
of capacitance, so they may have only a small fraction of
their nominal capacitance in your application. While they
will still handle the RMS ripple current, the input voltage
ripple may become fairly large, and the ripple current may
end up flowing from your input supply or from other by-
pass capacitors in your system, as opposed to being fully
sourced from the local input capacitor. An alternative to a
high value ceramic capacitor is a lower value along with
a larger electrolytic capacitor, for example a 1μF ceramic
capacitor in parallel with a low ESR tantalum capacitor.
For the electrolytic capacitor, a value larger than 10μF will
be required to meet the ESR and ripple current require-
ments. Because the input capacitor is likely to see high
surge currents when the input source is applied, tantalum
capacitors should be surge rated. The manufacturer may
also recommend operation below the rated voltage of the
capacitor. Be sure to place the 1μF ceramic as close as
44. Finally, for duty cycles greater than 50% (V /V
OUT IN
> 0.5), there is a minimum inductance required to avoid
subharmonic oscillations. See Application Note 19 for
more information.
Input Capacitor Selection
Bypass the inputs of the LT3510 circuit with a 4.7μF or
higher ceramic capacitor of X7R or X5R type. A lower
value or a less expensive Y5V type can be used if there
is additional bypassing provided by bulk electrolytic or
tantalum capacitors. The following paragraphs describe
the input capacitor considerations in more detail.
Step-downregulatorsdrawcurrentfromtheinputsupplyin
pulses with very fast rise and fall times. The input capaci-
tor is required to reduce the resulting voltage ripple at the
LT3510 and to force this very high frequency switching
current into a tight local loop, minimizing EMI. The input
capacitor must have low impedance at the switching fre-
quency to do this effectively, and it must have an adequate
ripple current rating. With two switchers operating at the
same frequency but with different phases and duty cycles,
calculating the input capacitor RMS current is not simple.
However, aconservativevalueistheRMSinputcurrentfor
the channel that is delivering most power (V
This is given by:
• I ).
OUT OUT
IOUT VOUT • V – V
(
)
<
IOUT
2
IN
OUT
ICIN(RMS)
=
possible to the V and GND pins on the IC for optimal
IN
V
IN
noise immunity.
and is largest when V = 2V
(50% duty cycle). As
WhentheLT3510’sinputsuppliesareoperatedatdifferent
input voltages, an input capacitor sized for that channel
should be placed as close as possible to the respective
IN
OUT
the second, lower power channel draws input current,
the input capacitor’s RMS current actually decreases as
the out-of-phase current cancels the current drawn by the
higherpowerchannel.Consideringthatthemaximumload
current from a single channel is ~2A, RMS ripple current
will always be less than 1A.
V pins.
IN
A final caution regarding the use of ceramic capacitors
at the input. A ceramic input capacitor can combine with
stray inductance to form a resonant tank circuit. If power
is applied quickly (for example by plugging the circuit
into a live power source) this tank can ring, doubling the
The frequency, V to V
ratio, and maximum load cur-
OUT
IN
rentrequirementoftheLT3510alongwiththeinputsupply
3510fe
15
LT3510
APPLICATIONS INFORMATION
input voltage and damaging the LT3510. The solution is to
either clamp the input voltage or dampen the tank circuit
by adding a lossy capacitor in parallel with the ceramic
capacitor. For details, see Application Note 88.
The RMS content of this ripple is very low, and the RMS
current rating of the output capacitor is usually not of
concern.
Another constraint on the output capacitor is that it must
havegreaterenergystoragethantheinductor;ifthestored
energy in the inductor is transferred to the output, you
would like the resulting voltage step to be small compared
totheregulationvoltage. Fora5%overshoot, thisrequire-
ment becomes:
Output Capacitor Selection
Typicallystep-downregulatorsareeasilycompensatedwith
an output crossover frequency that is 1/10 of the switch-
ing frequency. This means that the time that the output
capacitor must supply the output load during a transient
step is ~2 or 3 switching periods. With an allowable 5%
drop in output voltage during the step, a good starting
value for the output capacitor can be expressed by:
2
⎛
⎞
ILIM
V
OUT
COUT > 10 L
⎜
⎝
⎟
⎠
Finally,theremustbeenoughcapacitanceforgoodtransient
performance.Thelastequationgivesagoodstartingpoint.
Alternatively, you can start with one of the designs in this
datasheetandexperimenttogetthedesiredperformance.
This topic is covered more thoroughly in the section on
loop compensation.
Max Load Step
Frequency • 0.05 • VOUT
CVOUT
=
Example:
V
= 3.3V, Frequency = 1MHz, Max Load Step = 2A
OUT
Thehighperformance(lowESR),smallsizeandrobustness
of ceramic capacitors make them the preferred type for
LT3510 applications. However, all ceramic capacitors are
not the same. As mentioned above, many of the high value
capacitors use poor dielectrics with high temperature and
voltage coefficients. In particular, Y5V and Z5U types lose
a large fraction of their capacitance with applied voltage
and temperature extremes. Because the loop stability and
2
CVOUT
=
= 12μF
1e6 • 0.05 • 3.3V
The calculated value is only a suggested starting value.
Increasethevalueiftransientresponseneedsimprovement
or reduce the capacitance if size is a priority.
Theoutputcapacitorfilterstheinductorcurrenttogenerate
an output with low voltage ripple. It also stores energy in
ordertosatisfytransientloadsandtostabilizetheLT3510’s
controlloop. TheswitchingfrequencyoftheLT3510deter-
mines the value of output capacitance required. Also, the
current mode control loop doesn’t require the presence
of output capacitor series resistance (ESR). For these
reasons, you are free to use ceramic capacitors to achieve
very low output ripple and small circuit size.
transient response depend on the value of C , you may
OUT
not be able to tolerate this loss. Use X7R and X5R types.
Youcanalsouseelectrolyticcapacitors. TheESRsofmost
aluminum electrolytics are too large to deliver low output
ripple. Tantalum and newer, lower ESR organic electrolytic
capacitors intended for power supply use, are suitable
and the manufacturers will specify the ESR. The choice of
capacitor value will be based on the ESR required for low
ripple. Because the volume of the capacitor determines
its ESR, both the size and the value will be larger than a
ceramic capacitor that would give you similar ripple per-
formance. One benefit is that the larger capacitance may
give better transient response for large changes in load
current. Table 2 lists several capacitor vendors.
Estimate output ripple with the following equations:
V
= ∆I /(8f C ) for ceramic capacitors,
L OUT
RIPPLE
and
V
= ∆I ESR for electrolytic capacitors (tantalum
L
RIPPLE
and aluminum)
where ∆I is the peak-to-peak ripple current in the
L
inductor.
3510fe
16
LT3510
APPLICATIONS INFORMATION
where I
BST(MIN)
the switch.
is the maximum load current, and
Table 2
OUT(MAX)
V is the minimum boost voltage to fully saturate
VENDOR
Taiyo Yuden
AVX
TYPE
SERIES
Ceramic X5R, X7R
Ceramic X5R, X7R
Tantalum
Figure 5 shows four ways to arrange the boost circuit. The
BST pin must be more than 1.4V above the SW pin for
full efficiency. Generally, for outputs of 3.3V and higher
the standard circuit (Figure 5a) is the best. For outputs
between2.8Vand3.3V,replacetheD2withasmallSchottky
diode such as the PMEG4005. For lower output voltages
the boost diode can be tied to the input (Figure 5b). The
circuit in Figure 5a is more efficient because the BST
pin current comes from a lower voltage source. Figure
5c shows the boost voltage source from available DC
sources that are greater than 3V. The highest efficiency is
attained by choosing the lowest boost voltage above 3V.
For example, if you are generating 3.3V and 1.8V and the
3.3V is on whenever the 1.8V is on, the 1.8V boost diode
can be connected to the 3.3V output. In any case, you
must also be sure that the maximum voltage at the BST
pin is less than the maximum specified in the Absolute
Maximum Ratings section.
Kemet
Tantalum
TA Organic
AL Organic
T491, T494, T495
T520
A700
Sanyo
Panasonic
TDK
TA/AL Organic
AL Organic
POSCAP
SP CAP
Ceramic X5R, X7R
Catch Diode
The diode D1 conducts current only during switch off
time. Use a Schottky diode to limit forward voltage drop to
increase efficiency. The Schottky diode must have a peak
reverse voltage that is equal to regulator input voltage and
sized for average forward current in normal operation.
Average forward current can be calculated from:
IOUT
V
IN
ID(AVG)
=
• V – V
(
)
IN
OUT
The boost circuit can also run directly from a DC voltage
that is higher than the input voltage by more than 3V, as
in Figure 5d. The diode is used to prevent damage to the
The only reason to consider a larger diode is the worst-
case condition of a high input voltage and shorted output.
With a shorted condition, diode current will increase to a
typical value of 3A, determined by the peak switch current
limit of the LT3510. This is safe for short periods of time,
but it would be prudent to check with the diode manu-
facturer if continuous operation under these conditions
can be tolerated.
LT3510 in case V is held low while V is present. The
X
IN
circuit saves several components (both BST pins can be
tied to D2). However, efficiency may be lower and dissipa-
tion in the LT3510 may be higher. Also, if V is absent, the
X
LT3510 will still attempt to regulate the output, but will do
so with very low efficiency and high dissipation because
the switch will not be able to saturate, dropping 1.5V to
2V in conduction.
BST Pin Considerations
The capacitor and diode tied to the BST pin generate
a voltage that is higher than the input voltage. In most
cases a 0.47μF capacitor and fast switching diode (such
as the CMDSH-3 or FMMD914) will work well. Almost
any type of film or ceramic capacitor is suitable, but the
ESR should be <1Ω to ensure it can be fully recharged
during the off time of the switch. The capacitor value can
be approximated by:
The minimum input voltage of an LT3510 application is
limited by the minimum operating voltage (<3V) and by
the maximum duty cycle as outlined above. For proper
start-up, the minimum input voltage is also limited by
the boost circuit. If the input voltage is ramped slowly, or
the LT3510 is turned on with its SS pin when the output
is already in regulation, then the boost capacitor may not
be fully charged. Because the boost capacitor is charged
with the energy stored in the inductor, the circuit will rely
on some minimum load current to get the boost circuit
running properly. This minimum load will depend on
3510fe
IOUT(MAX) •DC
CBST
=
B • V
– V
• f
(
)
OUT
BST(MIN)
17
LT3510
APPLICATIONS INFORMATION
D2
C3
C3
D2
V
BST
BST
V
V
V
SW
V
IN
SW
IN
IN
IN
LT3510
LT3510
IND
OUT
IND
OUT
V
< 3V
OUT
V
V
OUT
GND
GND
V
V
– V = V
V
V
– V = V
SW IN
BST
SW
OUT
BST
BST(MAX)
= V + V
= 2 • V
IN
BST(MAX)
IN
OUT
D2
(5a)
(5b)
D2
V
= LOWEST V
IN
OR V
X
V
> V + 3V
IN
X
> 3V
OUT
C3
BST
BST
V
V
SW
V
V
IN
SW
IN
IN
IN
LT3510
LT3510
IND
OUT
IND
OUT
V
< 3V
V
< 3V
OUT
V
V
OUT
GND
GND
V
V
V
– V = V
V
V
V
– V = V
SW X
BST
SW
X
BST
BST(MAX)
3510 F05
= V + V
= V
X
BST(MAX)
IN
X
= 3V
= V + 3V
IN
X(MIN)
X(MIN)
(5c)
(5d)
Figure 5. BST Pin Considerations
input and output voltages, and on the arrangement of the
boost circuit. The Typical Performance Characteristics
section shows plots of the minimum load current to start
and to run as a function of input voltage for 3.3V and 5V
outputs. In many cases the discharged output capacitor
will present a load to the switcher which will allow it to
part of the loop compensation but is used to filter noise
at the switching frequency.
Loop compensation determines the stability and transient
performance.Designingthecompensationnetworkisabit
complicatedandthebestvaluesdependontheapplication
and in particular the type of output capacitor. A practical
approach is to start with one of the circuits in this data
sheet that is similar to your application and tune the com-
pensation network to optimize the performance. Stability
should then be checked across all operating conditions,
including load current, input voltage and temperature.
start. Theplotsshowtheworst-casesituationwhereV is
IN
ramping very slowly. Use a Schottky diode for the lowest
start-up voltage.
Frequency Compensation
The LT3510 uses current mode control to regulate the
output.Thissimplifiesloopcompensation.Inparticular,the
LT3510 does not require the ESR of the output capacitor
for stability so you are free to use ceramic capacitors to
achieve low output ripple and small circuit size.
The LT1375 data sheet contains a more thorough discus-
sion of loop compensation and describes how to test the
stability using a transient load.
Figure6showsanequivalentcircuitfortheLT3510control
loop. The error amp is a transconductance amplifier with
finite output impedance. The power section, consisting of
the modulator, power switch and inductor, is modeled as
a transconductance amplifier generating an output cur-
Frequency compensation is provided by the components
tied to the V pin. Generally a capacitor and a resistor in
C
series to ground determine loop gain. In addition, there
is a lower value capacitor in parallel. This capacitor is not
rent proportional to the voltage at the V pin. Note that
C
3510fe
18
LT3510
APPLICATIONS INFORMATION
LT3510
CURRENT MODE
POWER STAGE
m
SW
OUTPUT
ESR
g
= 2.2mho
C
R1
R2
PL
g
= 275μmho
m
FB
–
+
+
V
C
C1
C1
CERAMIC
3.6M
R
C
ERROR
AMP
TANTALUM
OR
POLYMER
0.8V
C
F
C
C
3510 F06
Figure 6. Model for Loop Response
the output capacitor integrates this current, and that the
capacitor on the V pin (C ) integrates the error ampli-
V
V
CC
OUT1
C
C
LT3510
R /SYNC
SYNCHRONIZATION
CIRCUITRY
fier output current, resulting in two poles in the loop. In
PG1
T
CLK
most cases a zero is required and comes from either the
3510 F07
output capacitor ESR or from a resistor in series with C .
C
This simple model works well as long as the value of the
inductor is not too high and the loop crossover frequency
is much lower than the switching frequency. A phase lead
Figure 7. Synchronous Signal Powered from Regulator’s Output
capacitor (C ) across the feedback divider may improve
PL
time the LT3510 reverts to the free-running frequency
the transient response.
based on the current through R /SYNC. If the R /SYNC
T
T
resistor is held above 2V at any time, switching will be
Synchronization
disabled.
TheR /SYNCpincanbeusedtosynchronizetheregulators
T
If the synchronization signal is not present during regula-
tor start-up (for example, the synchronization circuitry is
to an external clock source. Driving the R /SYNC resistor
T
with a clock source triggers the synchronization detection
circuitry.Oncesynchronizationisdetected,therisingedge
of SW1 will be synchronized to the rising edge of the
poweredfromtheregulatoroutput)theR /SYNCpinmust
T
see an equivalent resistance to ground between 15.4k and
133kuntilthesynchronizationcircuitryisactiveforproper
start-up operation.
R /SYNC pin signal. An AGC loop will adjust the internal
T
oscillators to maintain a 180 degree phase between SW1
and SW2, and also adjust slope compensation to avoid
subharmonic oscillation.
Ifthesynchronizationsignalpowersupinanundetermined
state (V , V , Hi-Z), connect the synchronization clock
OL OH
to the LT3510 as shown in Figure 7. The circuit as shown
will isolate the synchronization signal when the output
voltage is below 90% of the regulated output. The LT3510
will start-up with a switching frequency determined by the
The synchronizing clock signal input to the LT3510 must
have a frequency between 250kHz and 1.5MHz, a duty
cycle between 20% and 80%, a low state below 0.5V and
a high state above 1.6V. Synchronization signals outside
of these parameters will cause erratic switching behavior.
resistor from the R /SYNC pin to ground.
T
The R /SYNC resistor should be set such that the free
Ifthesynchronizationsignalpowersupinalowimpedance
state (V ), connect a resistor between the R /SYNC pin
T
running frequency ((V
– V )/R
SYNCLO
) is
RT/SYNC
RT/SYNC
OL
T
approximately equal to the synchronization frequency. If
the synchronization signal is halted, the synchronization
detection circuitry will timeout in typically 10μs at which
and the synchronizing clock. The equivalent resistance
seen from the R /SYNC pin to ground will set the start-up
T
frequency.
3510fe
19
LT3510
APPLICATIONS INFORMATION
Ifthesynchronizationsignalpowersupinahighimpedance
defaultstheopen-pinconditiontobeoperating(seeTypical
PerformanceCharacteristics).Currenthysteresisisadded
above the SHDN threshold. This can be used to set voltage
hysteresis of the UVLO using the following:
state (Hi-Z), connect a resistor from the R /SYNC pin to
T
ground. The equivalent resistance seen from the R /SYNC
T
pin to ground will set the start-up frequency.
If the synchronization signal changes between high and
VH – V
L
R1=
7μA
lowimpedancestatesduringpowerup(V ,Hi-Z),connect
OL
the synchronization circuitry to the LT3510 as shown in
theTypicalApplicationssection. ThiswillallowtheLT3510
to start-up with a switching frequency determined by the
1.28
R2 =
VH – 1.28
+ 3μA
equivalent resistance from the R /SYNC pin to ground.
T
R1
V = Turn-on threshold
H
Shutdown and Undervoltage Lockout
V = Turn-off threshold
Figure 8 shows how to add undervoltage lockout (UVLO)
to the LT3510. Typically, UVLO is used in situations where
the input supply is current limited, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
loadtothesourceandcancausethesourcetocurrentlimit
or latch low under low source voltage conditions. UVLO
prevents the regulator from operating at source voltages
where these problems might occur.
L
Example:switchingshouldnotstartuntiltheinputisabove
4.75V and is to stop if the input falls below 3.75V.
V = 4.75V
H
V = 3.75V
L
4.75 – 3.75
R1=
R2 =
≅ 143k
+ 3μA
7μA
1.28
4.75 – 1.28
143k
≅ 47k
An internal comparator will force the part into shutdown
below the minimum V
of 2.8V. This feature can be
IN1
used to prevent excessive discharge of battery-operated
systems.
Keep the connections from the resistors to the SHDN
pin short and make sure that the interplane or surface
capacitance to switching nodes is minimized. If high re-
sistor values are used, the SHDN pin should be bypassed
with a 1nF capacitor to prevent coupling problems from
the switch node.
Since V supplies the output stage of channel 2 and is
IN2
not monitored, care must be taken to insure that V is
IN2
present before channel 2 is allowed to switch.
If an adjustable UVLO threshold is required, the SHDN
pin can be used. The threshold voltage of the SHDN
pin comparator is 1.28V. A 3μA internal current source
Soft-Start
The output of the LT3510 regulates to the lowest voltage
present at either the SS pin or an internal 0.8V reference.
A capacitor from the SS pin to ground is charged by an
internal 3.25μA current source resulting in a linear output
ramp from 0V to the regulated output whose duration is
given by:
LT3510
V
IN1
V
> 2.8V
IN1
–
+
+
V
OR V
IN2
IN1
3μA
7μA
1.28V
R1
INTERNAL
REGULATOR
SHDN
3510 F08
C1 R2
C
SS • 0.8V
3.25μA
tRAMP
=
Figure 8. Undervoltage Lockout
3510fe
20
LT3510
APPLICATIONS INFORMATION
At power-up, a reset signal sets the soft-start latch and
discharges both SS pins to approximately 0V to ensure
proper start-up. When both SS pins are fully discharged
the latch is reset and the internal 3.25μA current source
starts to charge the SS pin.
threshold is exceeded. The PG pin is active (sink capability
is reduced in shutdown and undervoltage lockout mode)
as long as the V pin voltage exceeds 1V.
IN1
Output Tracking/Sequencing
Complex output tracking and sequencing between chan-
nels can be implemented using the LT3510’s SS and PG
pins. Figure 9 shows several configurations for output
tracking/sequencing for a 3.3V and 1.8V application.
WhentheSSpinvoltageisbelow50mV,theV pinispulled
low which disables switching. This allows the SS pin to be
used as an individual shutdown for each channel.
C
As the SS pin voltage rises above 50mV, the V pin is re-
C
Independent soft-start for each channel is shown in
Figure 9a. The output ramp time for each channel is set
by the soft-start capacitor as described in the soft-start
section.
leased and the output is regulated to the SS voltage. When
the SS pin voltage exceeds the internal 0.8V reference, the
output is regulated to the reference. The SS pin voltage
will continue to rise until it is clamped at 2V.
RatiometrictrackingisachievedinFigure9bbyconnecting
both SS pins together. In this configuration, the SS pin
source current is doubled (6.5μA) which must be taken
into account when calculating the output rise time.
In the event of a V undervoltage lockout, the SHDN
IN1
pin driven below 1.28V, or the internal die temperature
exceedingitsmaximumratingduringnormaloperation,the
soft-start latch is set, triggering a start-up sequence.
By connecting a feedback network from V
to the SS2
OUT1
voltage, absolute
Inaddition,iftheloadexceedsthemaximumoutputswitch
pin with the same ratio that sets V
OUT2
current, the output will start to drop causing the V pin
C
trackingshowninFigure9cisimplemented.Theminimum
value of the top feedback resistor (R1) should be set such
that the SS pin can be driven all the way to ground with
clamp to be activated. As long as the V pin is clamped,
C
the SS pin will be discharged. As a result, the output will
be regulated to the highest voltage that the maximum
output current can support. For example, if a 6V output
is loaded by 1Ω the SS pin will drop to 0.4V, regulating
the output at 3V ( 3A • 1Ω ). Once the overload condition
is removed, the output will soft-start from the temporary
voltage level to the normal regulation point.
700μAofsinkcurrentwhenV
isatitsregulatedvoltage.
OUT1
In addition, a small V
voltage offset will be present
OUT2
due to the SS2 3.25μA source current. This offset can be
corrected for by slightly reducing the value of R2.
Figure 9d illustrates output sequencing. When V
is
OUT1
within 10% of its regulated voltage, PG1 releases the SS2
soft-start pin allowing V to soft-start. In this case PG1
Since the SS pin is clamped at 2V and has to discharge
to 0.8V before taking control of regulation, momentary
overload conditions will be tolerated without a soft-start
recovery. The typical time before the SS pin takes control
is:
OUT2
will be pulled up to 2V by the SS pin. If a greater voltage
is needed for PG1 logic, a pull-up resistor to V can
OUT1
be used. This will decrease the soft-start ramp time and
increase tolerance to momentary shorts.
C
SS •1.2V
700μA
tSS(CONTROL)
=
If precise output ramp up and down is required, drive the
SS pins as shown in Figure 9e. The minimum value of
resistor (R3) should be set such that the SS pin can be
driven all the way to ground with 700μA of sink current
during power-up and fault conditions.
Power Good Indicators
The PG pin is the open-collector output of an internal
comparator. The comparator compares the FB pin voltage
to 90% of the reference voltage with 30mV of hysteresis.
The PG pin has a sink capability of 800μA when the FB pin
is below the threshold and can withstand 25V when the
Multiple Input Voltages
For applications requiring large inductors due to high V
IN
to V
ratios, a 2-stage step-down approach may reduce
OUT
3510fe
21
LT3510
APPLICATIONS INFORMATION
Independent Start-Up
Ratiometric Start-Up
Absolute Start-Up
V
V
V
OUT1
0.5V/DIV
OUT1
OUT1
0.5V/DIV
0.5V/DIV
PG1
PG1
PG2
PG1
V
V
V
OUT2
0.5V/DIV
OUT2
OUT2
0.5V/DIV
0.5V/DIV
PG2
PG2
5ms/DIV
10ms/DIV
10ms/DIV
3.3V
3.3V
3.3V
1.8V
SS1
SS2
V
SS1
SS2
V
SS1
SS2
V
OUT1
PG1
OUT2
OUT1
PG1
OUT2
OUT1
PG1
OUT2
0.1μF
0.1μF
0.22μF
LT3510
LT3510
LT3510
1.8V
1.8V
V
V
V
0.22μF
PG2
PG2
PG2
R1
13.7k
R2
8.08k
(9a)
(9b)
(9c)
Output Sequencing
Controlled Power Up and Down
V
V
OUT1
0.5V/DIV
OUT1
0.5V/DIV
PG1
V
V
OUT2
0.5V/DIV
OUT2
0.5V/DIV
PG1
PG2
SS1/2
10ms/DIV
10ms/DIV
R3
25k
3.3V
1.8V
3.3V
1.8V
SS1
SS2
V
SS1
SS2
V
OUT1
PG1
OUT2
OUT1
PG1
OUT2
0.1μF
0.1μF
EXTERNAL
SOURCE
LT3510
+
–
LT3510
V
V
PG2
PG2
3510 F09
(9d)
(9e)
Figure 9
3510fe
22
LT3510
APPLICATIONS INFORMATION
V
IN
6V TO 24V
4.7μF
PMEG4005
26.7k
V
V
IN2
IN1
SHDN
BST1
FSET
BST2
SW2
1μH
3.3μH
0.47μF
B360A
0.47μF
B360A
SW1
PMEG4005
LT3510
IND1
IND2
V
OUT2
V
V
OUT2
1.2V
OUT1
5V
V
OUT1
47μF
s2
47μF
42.3k
100k
4k
PG1
FB1
PG2
FB2
V
V
8.06k
C1
C2
8.06k
SS/TRACK1 SS/TRACK2
GND
470pF
470pF
32.4k
10pF
40.2k
0.1μF
0.1μF
10pF
3510 F10
Figure 10. 5V and 1.2V 2-Stage Step-Down Converter with Output Sequencing
inductor size by allowing an increase in frequency. A dual
step down application (Figure 10) steps down the input
Single Step Down:
1.2+ 0.6
voltage (V ) to the highest output voltage then uses that
24 – 0.4+ 0.6
IN1
Frequency (Hz) ≤
= 392kHz
voltage to power the second output (V ). V
must be
190ns
IN2
OUT1
able to provide enough current for its output plus V
OUT2
24 – 5 • 5
24 • 392kHz
(
)
maximum load. Note that the V
must be above V
OUT1
IN2
L1=
L2 =
≥ 10μH
minimum input voltage (2V) when the second channel
starts to switch. Delaying channel 2 can be accomplished
by either independent soft-start capacitors or sequencing
with the PG1 output.
24 – 1.2 •1.2
(
)
≥ 2.7μH
24 • 392kHz
For example, assume a maximum input of 24V:
2-Stage Step-Down:
5+ 0.6
V = 24V, V
IN
= 5V at 1.5A and V
= 1.2V at 1.5A
OUT1
OUT2
24 – 0.4+ 0.6
V
+ V
D
Frequency ≤
= 1.2MHz
OUT
190ns
V – V + V
IN
D
SW
Frequency (Hz) ≤
Max Frequency = 1.2MHz
t
MIN(ON)
24 – 5 • 5
24 •1.2MHz
(
)
V – V
• V
OUT
(
)
IN
OUT
L1=
L2 =
≥ 3.3μH
L ≥
V • f
IN
5 – 1.2 •1.2
(
)
≥ 0.76μH
5 •1.2MHz
3510fe
23
LT3510
APPLICATIONS INFORMATION
LT3510
LT3510
GND
LT3510
GND
V
V
V
IN
SW
SW
SW
IN
IN
GND
3510 F11
(11a)
(11b)
(11c)
Figure 11. Subtracting the Current when the Switch is On (11a) from the Current when the Switch is Off (11b) Reveals the Path of the
High Frequency Switching Current (11c). Keep this Loop Small. The Voltage on the SW and BST Traces will Also Be Switched; Keep
These Traces as Short as Possible. Finally, Make Sure the Circuit is Shielded with a Local Ground Plane
PCB Layout
capacitor C2. Additionally, the SW and BST traces should
be kept as short as possible. The topside metal from the
DC964AdemonstrationboardinFigure12illustratesproper
component placement and trace routing.
ForproperoperationandminimumEMI,caremustbetaken
duringprintedcircuitboard(PCB)layout. Figure11shows
the high di/dt paths in the buck regulator circuit.
Notethatlargeswitchedcurrentsflowinthepowerswitch,
the catch diode and the input capacitor. The loop formed
by these components should be as small as possible.
These components, along with the inductor and output
capacitor, should be placed on the same side of the circuit
board and their connections should be made on that layer.
Place a local, unbroken ground plane below these com-
ponents, and tie this ground plane to system ground at
one location, ideally at the ground terminal of the output
Thermal Considerations
ThePCBmustalsoprovideheatsinkingtokeeptheLT3510
cool. The exposed metal on the bottom of the package
must be soldered to a ground plane. This ground should
be tied to other copper layers below with thermal vias;
theselayerswillspreadtheheatdissipatedbytheLT3510.
Place additional vias near the catch diodes. Adding more
copper to the top and bottom layers and tying this copper
Figure 12. Topside PCB Layout
3510fe
24
LT3510
APPLICATIONS INFORMATION
to the internal planes with vias can further reduce ther-
There is one special consideration regarding the 2-phase
circuit. When the difference between the input voltage and
outputvoltageislessthan2.5V,thentheboostcircuitsmay
prevent the two channels from properly sharing current.
If, for example, channel 1 gets started first, it can supply
the load current, while channel 2 never switches enough
current to get its boost capacitor charged.
mal resistance. With these steps, the thermal resistance
from die (or junction) to ambient can be reduced to θ
JA
= 45°C/W.
The power dissipation in the other power components
such as catch diodes, boost diodes and inductors, cause
additional copper heating and can further increase what
the IC sees as ambient temperature. See the LT1767 data
sheet’s Thermal Considerations section.
In this case, channel 1 will supply the load until it reaches
current limit, the output voltage drops, and channel 2 gets
started. Two solutions to this problem are shown in the
Typical Applications section.
Single, Low Ripple 4A Output
The LT3510 can generate a single, low ripple 4A output
if the outputs of the two switching regulators are tied
together and share a single output capacitor. By tying the
Thesingle3.3V/4Aoutputconvertergeneratesaboostsup-
ply from either SW that will service both switch pins.
The synchronized 3.3V/8A output converter utilizes
undervoltage lockout to prevent the start-up condition.
two FB pins together and the two V pins together, the
C
two channels will share the load current. There are several
advantagestothis2-phasebuckregulator.Ripplecurrents
attheinputandoutputarereduced,reducingvoltageripple
and allowing the use of smaller, less expensive capacitors.
Although two inductors are required, each will be smaller
thantheinductorrequiredforasingle-phaseregulator.This
may be important when there are tight height restrictions
on the circuit.
Other Linear Technology Publications
Application notes AN19, AN35 and AN44 contain more
detailed descriptions and design information for buck
regulators and other switching regulators. The LT1376
data sheet has a more extensive discussion of output
ripple, loop compensation and stability testing. Design
Note DN100 shows how to generate a dual (+ and –)
output supply using a buck regulator.
3510fe
25
LT3510
TYPICAL APPLICATIONS
5V and 2.5V with Absolute Tracking
V
IN
12V
4.7μF
V
V
IN2
R /SYNC
T
IN1
26.7k
SHDN
BST1
SW1
BST2
SW2
2.2μH
3.3μH
0.47μF
B360A
0.47μF
PMEG4005
B360A
PMEG4005
LT3510
IND1
IND2
V
OUT2
V
OUT1
5V
V
OUT2
V
OUT1
2.5V
47μF
47μF
100k
100k
16.9k
42.3k
PG1
FB1
PG2
FB2
V
V
C2
C1
470pF
40.2k
470pF
40.2k
SS/TRACK1 SS/TRACK2
GND
8.06k
10pF
10pF
8.06k
0.1μF
16.9k
7.68k
3510 TA02
1.25MHz Single 3.3V/4A Low Ripple Output
V
6V TO 25V
IN
4.7μF
V
V
IN2
IN1
20.5k
SHDN
R /SYNC
T
BST1
SW1
BST2
SW2
1.5μH
1.5μH
0.47μF
B360A
0.47μF
B360A
PMEG4005
PMEG4005
LT3510
IND1
IND2
V
OUT2
V
OUT1
3.3V
4A
V
OUT1
47μF
s2
24.9k
100k
PG1
FB1
PG2
FB2
V
V
C2
8.06k
C1
SS/TRACK1 SS/TRACK2
GND
1000pF
17.8k
22pF
0.1μF
3510 TA03
3510fe
26
LT3510
TYPICAL APPLICATIONS
1.25MHz Single 3.3V/4A Low Ripple Output
V
IN
4.5V TO 6V
4.7μF
1μF*
V
V
IN2
IN1
20.5k
SHDN
R /SYNC
T
PMEG4005*
PMEG4005*
BST1
SW1
BST2
SW2
1.5μH
1.5μH
0.47μF
B360A
0.47μF
B360A
PMEG4005
PMEG4005
LT3510
IND1
IND2
V
OUT2
V
OUT1
3.3V
4A
V
OUT1
47μF
s2
24.9k
100k
PG1
FB1
PG2
FB2
V
C1
V
C2
8.06k
SS/TRACK1 SS/TRACK2
GND
1000pF
17.8k
22pF
0.1μF
3510 TA04
*ADDITIONAL COMPONENTS ADDED TO SHARE THE BOOST VOLTAGE WHEN V <6V.
IN
THIS IS REQUIRED TO ENSURE LOAD SHARING BETWEEN THE TWO CHANNELS.
Dual LT3510 Synchronized 3.3V/8A Output, 3MHz Effective Switch Frequency
V
IN
5.5V TO 24V
10μF
143k
V
V
IN2
R /SYNC
T
IN1
36.5k
SHDN
BST1
SW1
BST2
SW2
3.3μH
3.3μH
0.47μF
0.47μF
PMEG4005
B360A
B360A
PMEG4005
47μF
LT3510
IND1
IND2
V
OUT2
V
OUT1
3.3V
V
OUT1
49.9k
24.9k
s4
PG1
FB1
PG2
FB2
49.9k
V
V
C2
C1
8.06k
V+ OUT1
LTC6908-1
SET
SS/TRACK1 SS/TRACK2
GND
3300pF
47pF 5.3k
133k
MOD
0.1MF
GND OUT2
49.9k
PMEG4005
PMEG4005
V
V
IN2
IN1
SHDN
R /SYNC
T
BST1
SW1
BST2
SW2
3.3μH
3.3μH
0.47μF
B360A
0.47μF
B360A
LT3510
IND1
IND2
V
V
OUT1
OUT2
PG2
FB2
49.9k
PG1
FB1
V
C1
V
C2
SS/TRACK1 SS/TRACK2
GND
3510 TA05
3510fe
27
LT3510
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev I)
Exposed Pad Variation CB
6.40 – 6.60*
3.86
(.152)
(.252 – .260)
3.86
(.152)
20 1918 17 16 15 14 1312 11
6.60 0.10
2.74
(.108)
4.50 0.10
6.40
(.252)
BSC
2.74
(.108)
SEE NOTE 4
0.45 0.05
1.05 0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE20 (CB) TSSOP REV I 0211
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3510fe
28
LT3510
REVISION HISTORY (Revision history begins at Rev E)
REV
DATE
DESCRIPTION
PAGE NUMBER
E
6/12
Solder pad clarification
28
3510fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
29
LT3510
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
V : 5.5V to 60V, V
LT1766
60V, 1.2A (I ), 200kHz High Efficiency Step-Down DC/DC
= 1.20V, I = 2.5mA, I = 25μA,
OUT(MIN) Q SD
OUT
IN
Converter
16-Lead TSSOPE Package
V : 3.6V to 36V, V = 1.2V, I = 1.6mA, I <1μA,
OUT(MIN) Q SD
LT1933
LT1936
LT1940
500mA (I ), 500kHz Step-Down Switching Regulator in
OUT
IN
SOT-23
ThinSOT™ Package
36V, 1.4A (I ), 500kHz High Efficiency Step-Down DC/DC
V : 3.6V to 36V, V
= 1.2V, I = 1.9mA, I <1μA,
Q SD
OUT
IN
OUT(MIN)
Converter
8-Lead MS8E Package
Dual 25V, 1.4A (I ), 1.1MHz High Efficiency Step-Down
DC/DC Converter
V : 3.6V to 25V, V
= 1.20V, I = 3.8mA, I <30μA,
Q SD
OUT
IN
OUT(MIN)
16-Lead TSSOPE Package
LT1976/LT1977
60V, 1.2A (I ), 200kHz/500kHz High Efficiency Step-Down V : 3.3V to 60V, V
= 1.20V, I = 100μA, I <1μA,
OUT(MIN) Q SD
OUT
IN
DC/DC Converters with Burst Mode® Operation
16-Lead TSSOPE Package
®
LTC 3407/LTC3407-2 Dual 600mA/800mA, 1.5MHz/2.25MHz Synchronous
Step-Down DC/DC Converters
V : 2.5V to 5.5V, V
= 0.6V, I = 40μA, I <1μA,
Q SD
IN
OUT(MIN)
3mm × 3mm DFN and 10-Lead MSE Packages
60V, 2.4A (I ), 200kHz/500kHz High Efficiency Step-Down V : 3.3V to 60V, V = 1.20V, I = 100μA, I <1μA,
OUT IN OUT(MIN)
LT3434/LT3435
Q
SD
DC/DC Converters with Burst Mode Operation
16-Lead TSSOPE Package
LT3437
60V, 400mA (I ), Micropower Step-Down DC/DC Converter V : 3.3V to 60V, V
= 1.25V, I = 100μA, I <1μA,
Q SD
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
with Burst Mode Operation
DFN Package
LT3493
36V, 1.4A (I ), 750kHz High Efficiency Step-Down DC/DC
V : 3.6V to 36V, V
= 0.8V, I = 1.9mA, I <1μA,
Q SD
OUT
IN
Converter
DFN Package
LT3501
Dual 25V, 2A (I ), 1.5MHz High Efficiency Step-Down
V : 3.3V to 25V, V
= 0.8V, I = 3.5mA, I <1μA,
Q SD
OUT
IN
DC/DC Converter
20-Lead TSSOPE Package
V : 3.6V to 36V, V = 0.78V, I = 2mA, I <2μA,
OUT(MIN) Q SD
LT3505
36V, 1.2A (I ), 3MHz High Efficiency Step-Down DC/DC
OUT
IN
Converter
3mm × 3mm DFN and 8-Lead MSE Packages
LT3506/LT3506A
LTC3548
Dual 25V, 1.6A (I ), 575kHz/1.1MHz High Efficiency
V : 3.6V to 25V, V = 0.8V, I = 3.8mA, I <30μA,
OUT
IN
OUT(MIN)
Q
SD
Step-Down DC/DC Converters
4mm × 5mm DFN Package
Dual 400mA/800mA, 2.25MHz Synchronous Step-Down
DC/DC Converters
V : 2.5V to 5.5V, V
= 0.6V, I = 40μA, I <1μA,
Q SD
IN
OUT(MIN)
3mm × 3mm DFN and 10-Lead MSE Packages
3510fe
LT 0612 REV E • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
30
●
●
© LINEAR TECHNOLOGY CORPORATION 2006
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
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LT3506AEDHD#TR
LT3506 - Dual Monolithic 1.6A Step-Down Switching Regulator; Package: DFN; Pins: 16; Temperature Range: -40°C to 85°C
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