LT3507HUHF-TRPBF [Linear]
Triple Monolithic Step-Down Regulator with LDO; 三重单片式降压型稳压器， LDO
| 型号： | LT3507HUHF-TRPBF |
| 厂家： | 
Linear |
| 描述： | Triple Monolithic Step-Down Regulator with LDO |
| 文件： | 总28页 (文件大小：338K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3507
Triple Monolithic Step-Down
Regulator with LDO
DESCRIPTION
FEATURES
The LT®3507 is a triple, current mode, DC/DC converter
with internal power switches and a low dropout regulator.
Theswitchingconvertersarestep-downconverterscapable
of generating one 2.4A output and two 1.5A outputs. All
three converters are synchronized to a single oscillator.
The 2.4A output runs with opposite phase to the other two
converters, reducing input ripple current. Each regulator
has independent shutdown and soft-start circuits, and
generates a power good signal when its output is in regu-
lation, easing power supply sequencing and interfacing
with microcontrollers and DSPs.
n
Wide Input Range: 4V to 36V
n
One 2.4A and Two 1.5A Output Switching
Regulators with Internal Power Switches
n
Low Dropout Linear Regulator with External
Transistor
n
Antiphase Switching Reduces Ripple
n
Independent Run, Tracking/Soft-Start, and Power
Good Indicators Ease Supply Sequencing
n
Uses Small Inductors and Ceramic Capacitors
n
Adjustable, 250kHz to 2.5MHz Switching Frequency,
Synchronizable Over the Full Range
n
User Programmable Overvoltage and Undervoltage
Theswitchingfrequencyissetwithasingleresistoryielding
arangeof250kHzto2.5MHz.Thehighswitchingfrequency
allows the use of small inductors and capacitors resulting
inaverysmalltripleoutputsupply.Theconstantswitching
frequency, combinedwithlowimpedanceceramiccapaci-
tors, results in low, predictable output ripple. With its wide
input voltage range of 4V to 36V, the LT3507 regulates a
broad array of power sources including 5V logic rails,
unregulated wall transformers, lead acid batteries and
distributed power supplies.
Lockouts
n
Thermally Enhanced, 38-Lead 5mm × 7mm QFN
Package
APPLICATIONS
n
DSL and Cable Modems
n
Distributed Power Regulation
n
DSP Power
Automotive
n
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
5V, 3.3V, 2.5V and 1.8V Step-Down Regulator
Start-Up Waveforms—Coincident Tracking
V
IN
6V TO 36V
22μF
V
V
V
IN3
IN1
IN2
BOOST1
BOOST2
V
V
OUT3
0.22μF
V
4.7μH
OUT1
1.8V
2.4A
SW1
0.22μF
10μH
OUT2
1V/DIV
18.7k
V
OUT4
V
OUT1
V
3.3V
1.3A
OUT2
100μF
SW2
FB2
FB1
680pF
15k
18.7k
V
C1
22μF
35.7k
11.5k
LT3507
V
OUT2
BOOST3
SW3
0.22μF
3507 TA01b
V
15μH
OUT3
5V
1.5A
1ms/DIV
1000pF
16.2k
V
C2
53.6k
10.2k
22μF
FB3
BIAS
680pF
24.3k
DRIVE
FB4
V
C3
V
2.5V
0.2A
24.3k
11.5k
OUT4
R /SYNC
T
107k
2.2μF
GND
f
= 450kHz
SW
3507 TA01a
3507f
1
LT3507
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
V Pins...................................................... –0.3V to 36V
IN
TOP VIEW
BOOST Pins ..............................................................55V
BOOST Above SW.....................................................25V
PGOOD Pins..............................................................36V
BIAS Pin....................................................................16V
TRK/SS, V , FB, R /SYNC Pins ...................................6V
38 37 36 35 34 33 32
BOOST1
1
2
3
4
5
6
7
8
9
31
30
29
28
V
V
IN2
IN2
V
IN1
V
IN1
SW2
SW2
C
T
RUN, OVLO, UVLO Pins........................................... V
V
INSW
IN1
OVLO
UVLO
27 BOOST2
TRK/SS4
DRIVE Pin ...................................................................5V
Operating Junction Temperature Range (Notes 2, 5)
LT3507E, LT3507I .............................. –40°C to 125°C
LT3507H ............................................ –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
26
39
V
C1
25 FB4
TRK/SS1
FB1
24 DRIVE
23
V
C2
PGOOD1 10
PGOOD2 11
PGOOD3 12
22 FB2
21 TRK/SS2
20
FB3
13 14 15 16 17 18 19
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
θ
= 34°C/W
JA
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
38-Lead (5mm × 7mm) Plastic QFN
38-Lead (5mm × 7mm) Plastic QFN
38-Lead (5mm × 7mm) Plastic QFN
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
LT3507EUHF#PBF
LT3507IUHF#PBF
LT3507HUHF#PBF
LT3507EUHF#TRPBF
LT3507IUHF#TRPBF
LT3507HUHF#TRPBF
3507
3507
3507
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN1, VIN2, VIN3 = 12V, VBOOST1, VBOOST2, VBOOST3 = 17V, unless
otherwise noted. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
3.8
2
MAX
4
UNITS
V
l
Minimum Operating Voltage
Input Quiescent Current
Bias Quiescent Current
Shutdown Current
Internal UVLO on V
IN1
Not Switching, V
Not Switching, V
= 3.3V
3.5
7.5
1
mA
mA
μA
BIAS
BIAS
= 3.3V
5
V
= 0V
RUN1,2,3
Reference Voltage Line Regulation
5V < V < 36V
0.01
%/V
IN1
3507f
2
LT3507
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN1, VIN2, VIN3 = 12V, VBOOST1, VBOOST2, VBOOST3 = 17V, unless
otherwise noted. (Note 2)
PARAMETER
V Source Current
CONDITIONS
V = 0.6V
MIN
TYP
100
100
1.7
MAX
UNITS
μA
μA
V
C
C
V Sink Current
C
V = 0.6V
C
V Clamp Voltage
C
l
Switching Frequency
R = 40.2k
0.9
1.1
MHz
Deg
kHz
V
T
Switching Phase
SW1 to SW2,3, R = 40.2k
180
120
0.4
1
T
Foldback Frequency
V
FB
= 0V, R = 40.2k
T
Frequency Shift Threshold on FB
RUN Threshold
1.5
0.4
V
PGOOD Output Voltage Low
PGOOD Pin Leakage
I
= 200μA
= 2V
0.2
10
V
PGOOD
V
400
105
812
–500
nA
mV
mV
nA
μS
V/V
V
PGOOD
PGOOD Threshold Offset
Feedback Pin Voltage
V
FB
Rising
58
80
l
l
788
800
–50
330
500
0.9
0.01
1.8
Feedback Pin Bias Current
Error Amplifier Transconductance
Error Amplifier Voltage Gain
V Switching Threshold
C
Switch Leakage Current
10
μA
V
Minimum Boost Voltage Above Switch (Note 4)
Converter 1
2.5
V
to Switch Current Gain
5
A/V
A
C1
l
Switch 1 Current Limit (Note 3)
Switch 1 V
Duty Cycle = 15%
3
2
4.3
400
40
6
I
= 2A
= 2A
600
60
mV
mA
CESAT
SW1
SW1
BOOST1 Operating Current
I
Converter 2
V
to Switch Current Gain
3.6
2.9
350
40
A/V
A
C2
l
Switch 2 Current Limit (Note 3)
Switch 2 V
Duty Cycle = 15%
4
I
= 1.5A
= 1.5A
500
60
mV
mA
CESAT
SW2
SW2
BOOST2 Operating Current
I
Converter 3
V
to Switch Current Gain
3.6
2.9
350
40
A/V
A
C3
l
Switch 3 Current Limit (Note 3)
Switch 3 V
Duty Cycle = 15%
2
4
I
= 1.5A
= 1.5A
500
60
mV
mA
CESAT
SW3
SW3
BOOST3 Operating Current
LDO Regulator
I
l
Feedback Pin Voltage
Feedback Pin Bias Current
Error Amplifier Voltage Gain
Line Regulation
788
800
–150
1100
0.05
812
mV
nA
–500
V/V
%/V
V
IN
from 5V to 36V
3507f
3
LT3507
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN1, VIN2, VIN3 = 12V, VBOOST1, VBOOST2, VBOOST3 = 17V, unless
otherwise noted (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
0.005
15
MAX
UNITS
%/mA
mA
Load Regulation
I
from 0.1mA to 10mA
DRIVE
l
DRIVE Output Current Limit
10
22.5
2.0
Dropout Voltage, V to DRIVE
I
I
= 10mA
= 10mA
1.7
V
IN1
DRIVE
DRIVE
Dropout Voltage, BIAS to DRIVE
Over/Undervoltage Lockout
0.5
0.8
V
Undervoltage Lockout Threshold
Overvoltage Lockout Threhold
1.15
1.15
7
1.20
1.20
10
1.25
1.25
13
V
V
Undervoltage Lockout Hysteresis Current
Overvoltage Lockout Hysteresis Current
Input Bias Current (OVLO and UVLO)
V(UVLO) < 1.2V
V(OVLO) > 1.2V
μA
μA
nA
–7
–10
–100
–13
–200
Note 3: Current limit is guaranteed by design and/or correlation to static
test. Slope compensation reduces current limit at higher duty cycles.
Note 4: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3507E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3507I is guaranteed to meet performance specifications from –40°C
to 125°C junction temperature. The LT3507H is guaranteed over the full
–40°C to 150°C operating junction temperature range. High junction
temperatures degrade operating lifetimes. Operating lifetime is derated at
junction temperatures greater than 125°C.
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions.
Junction temperature will exceed the maximum operating range when
overtemperature protection is active. Continuous operation above the
specified maximum operating junction temperature may impair device
reliability.
3507f
4
LT3507
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current,
Channel 1, VOUT = 1.8V
Efficiency vs Load Current,
Switch VCESAT vs Switch Current,
Channels 1, 2 and 3
Channels 2 and 3, VOUT = 3.3V
100
90
80
70
60
50
40
90
80
70
60
50
40
0.6
0.5
0.4
0.3
0.2
0.1
0
T
f
= 25°C
SW
T
f
= 25°C
SW
A
T = 25°C
A
A
= 450kHz
= 450kHz
V = 6V
IN
V
= 6V
IN
CHANNELS 2 & 3
V
= 12V
IN
V
= 12V
= 36V
IN
V
= 36V
CHANNEL 1
IN
V
IN
0
0.3
0.6
I
0.9
(A)
1.2
1.5
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
(A)
2
2.5
3
I
(A)
I
OUT
OUT
SW
3507 G02
3507 G01
3507 G03
BOOST Pin Current vs Switch
Current, Channels 1, 2 and 3
VFB vs Temperature
Frequency vs RT
100
90
80
70
60
50
40
30
20
10
0
805
804
803
802
801
800
799
798
797
796
795
2.5
T
= 25°C
T
= 25°C
A
A
CHANNELS 2 & 3
CHANNEL 1
0.25
0
0.5
1
1.5
(A)
2
2.5
3
–50 –30 –10 30 50 70 90 110 130 150
10
100
I
TEMPERATURE (°C)
R
T
(kΩ)
SW
3507 G04
3507 G05
3507 G06
Frequency vs Temperature
Frequency vs VFB (Foldback)
ITRK/SS vs Temperature
0.5
0.0
1200
1000
800
600
400
200
0
1.30
1.28
1.26
1.24
1.22
1.20
R
A
= 40.2k
= 25°C
T
T
–0.5
–1.0
–1.5
–2.0
–50 –30 –10 30 50 70 90 110 130 150
0
0.2
0.4
V
0.6
(V)
0.8
1
–50 –30 –10 30 50 70 90 110 130 150
TEMPERATURE (°C)
TEMPERATURE (°C)
FB
3507 G07
3507 G08
3507 G09
3507f
5
LT3507
TYPICAL PERFORMANCE CHARACTERISTICS
RUN Threshold vs Temperature
VIN1-VINSW Voltage Drop vs IVINSW
Current Limit vs Duty Cycle
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
T
= 25°C
T
= 25°C
A
A
CHANNEL 1
CHANNELS 2 & 3
0
0.2
0.4
I
0.6
(mA)
0.8
1.0
0
20
40
60
80
100
–50 –30 –10 30 50 70 90 110 130 150
TEMPERATURE (°C)
DUTY CYCLE (%)
VINSW
3507 G12
3507 G13
3507 G10
Minimum Off-Time vs ISW
Minimum On-Time vs ISW
250
200
150
100
50
200
–40°C
25°C
150
100
50
150°C
150°C
25°C
–40°C
2
0
0
0
1
3
0
0.5
1
1.5
(A)
2
2.5
3
I
(A)
I
SW
SW
3507 G14
3507 G15
3507f
6
LT3507
PIN FUNCTIONS
BOOST1, BOOST2, BOOST3 (Pins 1, 27, 32): The BOOST
pins are used to provide drive voltages, higher than the
input voltage, to the internal bipolar NPN power switches.
PGOOD1, PGOOD2, PGOOD3 (Pins 10, 11, 12): The
PGOOD pins are the open-collector outputs of an internal
comparator. PGOOD remains low until the FB pin is within
10% of the final regulation voltage. As well as indicating
output regulation, the PGOOD pins can sequence the
switchingregulators.Thesepinsmustbeleftunconnected
These pins must be tied through a diode from V , V
OUT IN
or another supply greater than 2.5V.
V
IN1
(Pins2, 3):TheV pinssupplypowertotheinternal
IN1
ifunused.ThePGOODoutputsarevalidwhenV isgreater
IN
switch of the 2.4A regulator and to the LT3507’s internal
referenceandstart-upcircuitry.Thesepinsmustbelocally
bypassed (Note 6).
than 3.5V and any of the RUN pins are high. They are not
valid when all RUN pins are low.
R /SYNC (Pin 13): The R /SYNC pin requires a resistor
T
T
V
(Pin 4): The V
pin is a switched V for the
INSW
INSW IN1
to ground or a clock signal to set the operating frequency
user programmable undervoltage and overvoltage detec-
of the LT3507.
tion. It is connected to V when any of the RUN pins
IN1
are pulled high, and high impedance when all RUN pins
RUN1, RUN2, RUN3 (Pins 14, 15, 16): The RUN pins are
used to shut down the individual switching regulators.
When all three RUN pins are low, the LT3507 shuts down
are low or open.
OVLO(Pin5):TheLT3507goesintoovervoltageshutdown
when this pin goes above 1.2V. If unused, the OVLO pin
should be tied to GND.
and draws less than 1μA from V
.
IN1
BIAS (Pin 17): The BIAS pin supplies the current to the
LT3507’s internal regulator. This pin should be tied to the
UVLO(Pin6):TheLT3507goesintoundervoltageshutdown
lowest available voltage source above 3V (either V , V
IN OUT
when this pin drops below 1.2V. If unused, the UVLO pin
or any other available supply). The LDO pass transistor’s
base current is supplied from the BIAS pin if it is at least
0.8V above the LDO DRIVE output.
should be tied to V
.
INSW
V , V , V (Pins7, 23, 19):TheV pinsaretheoutputs
C1 C2 C3
C
of the internal error amps. The voltages on these pins
control the peak switch currents. These pins are normally
used to compensate the control loops. Each switching
DRIVE (Pin 24): The DRIVE pin provides the base drive for
an external NPN transistor used for the LDO regulator.
regulator can be shut down by pulling its respective V
pin to ground with an NMOS or NPN transistor.
FB4 (Pin 25): The FB4 pin is the negative input to the LDO
error amplifier. It is regulated to 0.8V through the LDO
feedback resistor divider.
C
TRK/SS1, TRK/SS2, TRK/SS3, TRK/SS4 (Pins 8, 21, 18,
26): The TRK/SS pins allow a regulator to track the output
of another regulator. When the TRK/SS pin is below 0.8V,
the FB pin regulates to the TRK/SS voltage. This pin can
also be used as a soft-start by connecting a capacitor from
TRK/SS to ground. The TRK/SS pins should be left open
if neither feature is used.
V
(Pins 30, 31)/V (Pins 35, 36 ): The V and V
IN3 IN2 IN3
IN2
pinssupplypowertotheinternalswitchesofthe1.5Acon-
verters. These pins must be locally bypassed (Note 6).
SW1 (Pins 37, 38)/SW2 (Pins 28, 29)/SW3 (Pins 33,
34): The SW pins are the outputs of the internal power
switches. Connect these pins to the inductors and switch-
ing diodes.
FB1, FB2, FB3 (Pins 9, 22, 20): The FB pins are the nega-
tive inputs of the error amplifiers. The LT3507 regulates
each feedback pin to the lesser of 0.8V or the TRK/SS
pin voltage. Connect the feedback resistor divider taps
to these pins.
Exposed Pad (Pin 39): Ground. The underside Exposed
Pad metal of the package provides both electrical contact
to ground and good thermal contact to the printed circuit
board. The Exposed Pad must be soldered to a grounded
pad on the circuit board for proper operation.
Note 6: V pins that are connected together may share a bypass capacitor.
INX
3507f
7
LT3507
BLOCK DIAGRAM
V
INSW
V
IN1
OVLO
+
–
BIAS
RUN1
RUN2
RUN3
CLK1
CLK2
CLK3
INT REG
AND REF
MASTER
OSC
1.2V
+
–
R /SYNC
T
UVLO
V
IN4
DRIVE
V
OUT4
TRK/SS4
+
+
–
SHDN
0.8V
FB4
THERMAL
SHUTDOWN
V
IN
UNDERVOLTAGE
DETECTION
V
INX
CHANNEL
SHUTDOWN
C
IN
+
–
0.9V
+
C1
D2
BOOST
+
–
SLOPE
R
S
Q
C3
SLAVE
OSC
CLK
L1
D1
SW
V
OUTX
C1
+
–
0.4V
R1
FB
–
–
+
V
C
ERROR
AMP
R2
1.25μA
C
F
R
C
0.8V
–
C
C
I
+
LIMIT
80mV
CLAMP
+
TRK/SS
+
PGOOD
GND
1.7V
+
–
ONE OF THREE STEP-DOWN REGULATORS
3507 F01
Figure 1. LT3507 Block Diagram with Typical External Components
3507f
8
LT3507
OPERATION
The LT3507 contains three independent, constant fre-
quency, current mode, switching regulators with internal
power switches plus a low dropout linear regulator. The
three regulators share common circuitry including input
source, voltage reference and oscillator, but are otherwise
independent. Operation can be best understood by refer-
ring to the Block Diagram (Figure 1).
Each switcher contains an extra, independent oscillator to
perform frequency foldback during overload conditions.
Thisslaveoscillatorisnormallysynchronizedtothemaster
oscillator. AcomparatorsenseswhenV islessthan50%
FB
of its regulated value and switches the regulator from the
masteroscillatortoaslowerslaveoscillator.V islessthan
FB
50% of its regulated value during start-up, short-circuit
and overload conditions. Frequency foldback helps limit
switch current under these conditions.
If the RUN pins are tied to ground, the LT3507 is shut
down and draws <1μA from the input source tied to V
.
IN1
IfanyoftheRUNpinsaredrivenabove1V, theinternalbias
circuitsturnon, includingtheinternalregulator, reference,
and master oscillator. Each switching regulator will only
begin to operate when its corresponding RUN pin reaches
>1.25V.Themasteroscillatorgeneratesthreeclocksignals,
with the signal for Channel 1 out of phase by 180°.
The TRK/SS pins override the 0.8V reference for the FB
pins when the TRK/SS pins are below 0.8V. This allows
eithercoincidentorratiometricsupplytrackingonstart-up
as well as a soft-start capability.
The switch drivers operate either from V or from the
IN
BOOST pin. An external capacitor and diode are used to
generate a voltage at the BOOST pin that is higher than the
input supply. This allows the driver to saturate the internal
bipolar NPN power switch for efficient operation.
The three switchers are current mode regulators. Instead
of directly modulating the duty cycle of the power switch,
the feedback loop controls the peak current in the switch
duringeachcycle.Comparedtovoltagemodecontrol,cur-
rent mode control improves loop dynamics and provides
cycle-by-cycle current limit.
TheBIASpinallowstheinternalcircuitrytodrawitscurrent
from a lower voltage supply than the input, also reducing
power dissipation and increasing efficiency. If the voltage
on the BIAS pin falls below 3V, then its quiescent current
TheBlockDiagramshowsonlyoneofthethreestep-down
switching regulators. A pulse from the slave oscillator
sets the RS flip-flop and turns on the internal NPN bipo-
lar power switch. Current in the switch and the external
inductor begins to increase. When this current exceeds a
will flow from V .
IN
A power good comparator trips when the FB pin is at
90% of its regulated value. The PGOOD output is an
open-collector transistor that is off when the output is in
regulation, allowinganexternalresistortopullthePGOOD
pin high. Power good is valid when the LT3507 is enabled
level determined by the voltage at V , current comparator
C
C1 resets the flip-flop, turning off the switch. The current
in the inductor flows through the external Schottky diode
and begins to decrease. The cycle begins again at the next
pulse from the oscillator. In this way, the voltage on the
and V > 3.5V.
IN
TheLDOregulatorusesanexternalNPNpasstransistorto
form a linear regulator. The loop is internally compensated
to be stable with a load capacitance of 2.2μF or greater.
V pin controls the current through the inductor to the
C
output. The internal error amplifier regulates the output
voltage by continually adjusting the V pin voltage. The
C
The LDO is disabled when all three of the RUN pins are
low.
threshold for switching on the V pin is >1V and an active
C
clamp of 1.8V limits the output current.
The overvoltage and undervoltage detection shuts down
the LT3507 if the input voltage goes above or below re-
sistor programmable thresholds. The hysteresis of these
detectors is also resistor programmable.
3507f
9
LT3507
APPLICATIONS INFORMATION
STEP-DOWN CONSIDERATIONS
1
DCMAX
=
1
B
1+
FB Resistor Network
The output voltage is programmed with a resistor divider
(refer to the Block Diagram) between the output and the
FB pin. Choose the resistors according to:
whereBistheoutputcurrentcapacitydividedbythetypical
boostcurrentfromtheBOOSTpincurrentvsswitchcurrent
in the Typical Performance Characteristics section.
VOUT
ꢀ
ꢂ
ꢃ
The maximum operating voltage without pulse skipping
R1=R2
–1
ꢅ
ꢁ
ꢄ
800mV
is determined by the minimum duty cycle DC
:
MIN
V
OUT + V
DCMIN
The parallel combination of R1 and R2 should be 10k or
less to avoid bias current errors.
F
V
=
– V + VSW
F
IN(PS)
Input Voltage Range
with DC
= t
• f
.
MIN
ON(MIN) SW
The minimum operating voltage is determined either by
Thus both the maximum and minimum input voltages are
a function of the switching frequency and output voltages.
Therefore the maximum switching frequency must be set
to a value that accommodates all the input and output
voltage parameters and must meet both of the following
criteria for each channel:
theLT3507’sinternalundervoltagelockout(4VonV ,3V
IN1
on V and V ) or by its maximum duty cycle. The duty
IN2
IN3
cycle is the fraction of time that the internal switch is on
and is determined by the input and output voltages:
V
OUT + V
F
DC =
ꢀ
ꢃ
ꢅ
V – VSW + V
V
OUT + VF
1
IN
F
fMAX1
=
•
ꢂ
V
IN(PS) – VSW + VF tON(MIN)
ꢁ
ꢄ
where V is the forward voltage drop of the catch diode
F
(~0.4V) and V is the voltage drop of the internal switch
ꢀ
ꢃ
ꢅ
SW
V
OUT + VF
1
fMAX2 = 1–
•
(~0.3V at maximum load). This leads to a minimum input
ꢂ
V
IN(MIN) – VSW + VF tOFF(MIN)
ꢁ
ꢄ
voltage of:
V
OUT + V
F
The values of t
and t
are functions of I
V
=
– V + VSW
F
ON(MIN)
OFF(MIN) SW
IN(MIN)
DCMAX
and temperature (see chart in the Typical Performance
Characteristics section). Worst-case values for switch
The duty cycle is the fraction of time that the internal
switchisonduringaclockcycle. Themaximumdutycycle
is generally given by DC
currents greater than 0.5A are t
= 130ns (for T >
ON(MIN)
= 170ns.
OFF(MIN)
J
125°C t
= 155ns) and t
ON(MIN)
= 1– t
• f . However,
MAX
OFF(MIN) SW
f
is the frequency at which the minimum duty cycle
unlikemostfixedfrequencyregulators,theLT3507willnot
switchoffattheendofeachclockcycleifthereissufficient
voltage across the boost capacitor (C3 in Figure 1) to fully
saturatetheoutputswitch.Forcedswitchoffforaminimum
time will only occur at the end of a clock cycle when the
boost capacitor needs to be recharged. This operation
has the same effect as lowering the clock frequency for a
fixed off time, resulting in a higher duty cycle and lower
minimum input voltage. The resultant duty cycle depends
on the charging times of the boost capacitor and can be
approximated by the following equation:
MAX1
is exceeded. The regulator will skip ON pulses in order to
reduce the overall duty cycle at frequencies above f
.
MAX1
It will continue to regulate but with increased inductor
current and greatly increased output ripple. The increased
peak inductor current in pulse skipping will also stress
the switch transistor at high voltages and high switch-
ing frequency. If the LT3507 is allowed to pulse skip and
the input voltage is greater than 20V, then the switching
frequency must be kept below 1.1MHz to prevent damage
to the LT3507.
3507f
10
LT3507
APPLICATIONS INFORMATION
f
is the frequency at which the maximum duty cycle
MAX2
V
CC
is exceeded. If there is sufficient charge on the BOOST
capacitor, the regulator will skip OFF periods to increase
CLOCK
SYNC
LT3507
R /SYNC SW1
470pF
1k
CLK
V
OUT1
T
the overall duty cycle at frequencies about f
. It will
MAX2
BAS70
R
T
continue to regulate but with increased inductor current
and greatly increased output ripple.
3507 F02
Figure 2. Clock Powered from LT3507 Output
Note that the restriction on the operating input voltage
refers to steady-state limits to keep the output in regula-
tion; the circuit will tolerate input voltage transients up to
the absolute maximum rating.
Inductor Selection and Maximum Output Current
Thecurrentintheinductorisatrianglewavewithanaverage
value equal to the load current. The peak switch current
is equal to the output current plus half the peak-to-peak
inductorripplecurrent.TheLT3507limitsitsswitchcurrent
in order to protect itself and the system from overload
faults. Therefore, the maximum output current that the
LT3507 will deliver depends on the switch current limit,
the inductor value and the input and output voltages.
Switching Frequency
Once the upper and lower bounds for the switching
frequency are found from the duty cycle requirements,
the frequency may be set within those bounds. Lower
frequencies result in lower switching losses, but require
larger inductors and capacitors. The user must decide
the best trade-off.
When the switch is off, the potential across the inductor
is the output voltage plus the catch diode drop. This gives
the peak-to-peak ripple current in the inductor:
The switching frequency is set by a resistor connected
from the R /SYNC pin to ground, or by forcing a clock
T
V
OUT + V
L • f
F
signal into R /SYNC. The LT3507 applies a voltage of
T
ΔI = 1–DC
(
)
L
~1.25V across this resistor and uses the current to set
the oscillator speed. The switching frequency is given by
the following formula:
where f is the switching frequency of the LT3507 and L
is the value of the inductor. The peak inductor and switch
current is:
55
RT +12
fSW
=
ΔIL
2
I
SWPK =ILPK =IOUT +
where f is in MHz and R is in kΩ.
SW
T
To maintain output regulation, this peak current must
be less than the LT3507’s switch current limit, I . For
ThefrequencysyncsignalwillsupportV logiclevelsfrom
H
LIM
1.8V to 5V CMOS or TTL. The duty cycle is not important,
but it needs a minimum on time of 100ns and a minimum
off time of 100ns. If the sync circuit is to be powered from
one of the LT3507 outputs there may be start-up problems
if the driving gate is high impedance without a supply or
pulls high or low at some intermediate supply voltage.
The circuit shown in Figure 2 prevents these problems by
isolating the clock sync circuit until the clock is operating.
The Schottky diode should be a low leakage type such as
theBAS70fromOnSemiorCMOD6263fromCentralSemi.
SW1, I is at least 3A at low duty cycles and decreases
LIM
linearly to 2.4A at DC = 0.8. For SW2 and SW3, I is at
LIM
least 2A for at low duty cycles and decreases linearly to
1.6A at DC = 0.8.
The minimum inductance can now be calculated as:
V
OUT + V
1−DCMIN
F
LMIN
=
•
2• f
ILIM –IOUT
However, it’s generally better to use an inductor larger
than the minimum value. The minimum inductor has large
ripple currents which increase core losses and require
R should be set to provide a frequency within 25% of
T
the final sync frequency.
large output capacitors to keep output voltage ripple low.
3507f
11
LT3507
APPLICATIONS INFORMATION
Output Capacitor Selection
Select an inductor greater than L
that keeps the ripple
MIN
current below 30% of I
.
LIM
Theoutputcapacitorfilterstheinductorcurrenttogenerate
an output with low voltage ripple. It also stores energy in
order to satisfy transient loads and stabilize the LT3507’s
control loop. Because the LT3507 operates at a high
frequency, minimal output capacitance is necessary. In
addition, the control loop operates well with or without
the presence of output capacitor series resistance (ESR).
Ceramic capacitors, which achieve very low output ripple
and small circuit size, are therefore an option.
Theinductor’sRMScurrentratingmustbegreaterthanthe
maximum load current and its saturation current should
be greater than I . For highest efficiency, the series
LPK
resistance (DCR) should be less than 0.1Ω. Table 1 lists
several vendors and types that are suitable.
Table 1. Inductors
VALUE
(μH)
I
DCR
(Ω)
HEIGHT
(mm)
SAT
PART NUMBER
Sumida
(A)
You can estimate output ripple with the following
equations:
CDC5D23-2R2
CDRH5D28-2R6
CDRH6D26-5R6
CDH113-100
Coilcraft
2.2
2.6
5.6
10
2.16
2.60
2.00
2.00
0.030
0.013
0.027
0.047
2.5
3.0
2.8
3.7
ΔIL
8 • f •COUT
VRIPPLE
and
=
for ceramic capacitors
V
RIPPLE = ΔIL •ESR for electrolytic capacitors
(tantalum and aluminum)
DO1606T-152
LPS6225-222ML
DO1608C-332
MSS6132-472ML
DO1813P-682HC
Cooper
1.5
2.2
3.3
4.7
6.8
2.10
4.00
2.00
2.60
2.20
0.060
0.045
0.080
0.056
0.080
2.0
2.4
2.9
3.2
5.0
whereΔI isthepeak-to-peakripplecurrentintheinductor.
L
The RMS content of this ripple is very low so the RMS
current rating of the output capacitor is usually not of
concern. It can be estimated with the formula:
SD414-2R2
2.2
6.8
10
2.73
2.96
1.90
0.061
0.041
0.111
1.35
3.55
5.0
ΔIL
IC(RMS)
=
DRA73-6R8-R
UP1B-100
12
Another constraint on the output capacitor is that it must
havegreaterenergystoragethantheinductor;ifthestored
energyintheinductortransferstotheoutput, theresulting
voltage step should be small compared to the regulation
voltage. For a 5% overshoot, this requirement indicates:
Toko
(D62F)847FY-2R4M
(D73LF)817FY-2R2M
2.4
2.2
2.5
2.7
0.037
0.03
2.7
3.0
This analysis is valid for continuous mode operation
(I > I /2). For details of maximum output current in
ꢃ2
ꢅ
OUT
LIM
ꢀ
ILIM
discontinuous mode operation, see Linear Technology’s
COUT >10 •L •
ꢂ
V
OUT ꢄ
Application Note AN44. Finally, for duty cycles greater
ꢁ
than 50% (V /V > 0.5), a minimum inductance is
OUT IN
ThelowESRandsmallsizeofceramiccapacitorsmakethem
the preferred type for LT3507 applications. Not all ceramic
capacitorsarethesame,however.Manyofthehighervalue
capacitors use poor dielectrics with high temperature and
voltage coefficients. In particular, Y5V and Z5U types lose
a large fraction of their capacitance with applied voltage
and at temperature extremes. Because loop stability and
requiredtoavoidsubharmonicoscillations.Thisminimum
inductance is:
0.45
fSW
SW1:LMIN = V + V •
(
)
OUT
F
0.9
fSW
SW2, SW3:LMIN = V + V •
(
)
OUT
F
transient response depend on the value of C , this loss
OUT
may be unacceptable. Use X7R and X5R types.
with L
in μH and f in MHz.
SW
MIN
3507f
12
LT3507
APPLICATIONS INFORMATION
Table 3. Schottky Diodes
Electrolytic capacitors are also an option. The ESRs of
most aluminum electrolytic capacitors are too large to
deliver low output ripple. Tantalum, as well as newer,
lower-ESR organic electrolytic capacitors intended for
power supply use are suitable. Chose a capacitor with a
low enough ESR for the required output ripple. Because
the volume of the capacitor determines its ESR, both the
size and the value will be larger than a ceramic capacitor
that would give similar ripple performance. One benefit
is that the larger capacitance may give better transient
response for large changes in load current. Table 2 lists
several capacitor vendors.
V
I
V AT 1A
V AT 2A
R
AVE
F
F
PART NUMBER
On Semiconductor
MBRM120E
MBRM140
Diodes Inc
B120
(V)
(A)
(mV)
(mV)
20
40
1
1
530
550
595
20
40
20
40
40
40
1
1
2
2
1
2
500
500
B140
B220
500
500
B240
DFLS140L
DFLS240L
550
550
Table 2. Low ESR Surface Mount Capacitors
VENDOR
Taiyo-Yuden
AVX
TYPE
SERIES
Boost Pin Considerations
Ceramic
The capacitor and diode tied to the BOOST pin generate a
voltagethatishigherthantheinputvoltage.Inmostcases,
a small ceramic capacitor and fast switching diode (such
as the CMDSH-3 or MMSD914LT1) will work well. The
capacitor value is a function of the switching frequency,
peak current, duty cycle and boost voltage; in general a
Ceramic
Tantalum
TPS
Kemet
Sanyo
Tantalum
Tantalum Organic
Aluminum Organic
T491,T494,T495
T520
A700
Tantalum or
Aluminum Organic
POSCAP
SP CAP
value of (0.1μF • 1MHz/f ) works well. Figure 3 shows
SW
Panasonic
TDK
Aluminum Organic
Ceramic
three ways to arrange the boost circuit. The BOOST pin
must be more than 2.5V above the SW pin for full ef-
ficiency. For outputs of 3.3V and higher, the standard
circuit (Figure 3a) is best. For outputs between 2.8V and
3.3V, use a small Schottky diode (such as the BAT54).
For lower output voltages, the boost diode can be tied
to the input (Figure 3b). The circuit in Figure 3a is more
efficient because the BOOST pin current comes from a
lower voltage source. Finally, as shown in Figure 3c, the
anode of the boost diode can be tied to another source
that is at least 3V. For example, if you are generating 3.3V
and 1.8V and the 3.3V is on whenever the 1.8V is on, the
1.8V boost diode can be connected to the 3.3V output. In
this case, the 3.3V output cannot be set to track the 1.8V
output (see Output Voltage Tracking).
Diode Selection
The catch diode (D1 from Figure 2) conducts current only
during switch off time. Average forward current in normal
operation can be calculated from:
IOUT V – V
(
)
IN
OUT
ID(AVG)
=
VIN
The only reason to consider a diode with a larger current
rating than necessary for nominal operation is for the
worst-case condition of shorted output. The diode current
will then increase to the typical peak switch current. Peak
reverse voltage is equal to the regulator input voltage.
Use a diode with a reverse voltage rating greater than the
input voltage. The programmable OVLO can protect the
diode from excessive reverse voltage by shutting down
the regulator if the input voltage exceeds the maximum
rating of the diode. Table 3 lists several Schottky diodes
and their manufacturers.
In any case, be sure that the maximum voltage at the
BOOST pin is less than 55V and the voltage difference
between the BOOST and SW pins is less than 25V.
The minimum operating voltage of an LT3507 applica-
tion is limited by the internal undervoltage lockout (4V
for Channel 1, 3V for Channels 2 and 3) and by the
3507f
13
LT3507
APPLICATIONS INFORMATION
D2
D2
C3
C3
BOOST
LT3507
BOOST
LT3507
V
IN
V
V
IN
V
OUT
V
SW
V
SW
OUT
IN
IN
GND
GND
V
– V ≅ V
SW
BOOST
V
– V ≅ V
BOOST
MAX V
OUT
BOOST
MAX V ≅ 2V
BOOST
SW
IN
IN
≅ V + V
IN
OUT
(3a)
(3b)
D2
V
INB
> 3V
BOOST
LT3507
C3
V
V
V
SW
IN
OUT
IN
GND
V
– V ≅ V
SW
BOOST
MAX V
INB
3507 F03
≅ V + V
BOOST
INB IN
MINIMUM VALUE FOR V = 3V
INB
(3c)
Figure 3. Generating the Boost Voltage
maximum duty cycle. The boost circuit also limits the
minimum input voltage for proper start-up. If the input
voltage ramps slowly, or the LT3507 turns on when the
output is already in regulation, the boost capacitor may
not be fully charged. Because the boost capacitor charges
with the energy stored in the inductor, the circuit will rely
on some minimum load current to get the boost circuit
running properly. This minimum load will depend on
input and output voltages, and on the arrangement of
the boost circuit. The minimum load current generally
goes to zero once the circuit has started. Figure 4 shows
a plot of minimum load to start and to run as a function
of input voltage. Even without an output load current, in
many cases the discharged output capacitor will present
a load to the switcher that will allow it to start.
Theboostcurrentisgenerallysmallbutcanbecomesignifi-
cant at high duty cycles. The required boost current is:
ꢀ
ꢃ
VOUT
I
OUT ꢃ
ꢄ
40
ꢀ
IBOOST
=
ꢂ
ꢅ
ꢂ
ꢅ
ꢁ
V
ꢁ
ꢄ
IN
Converter with Backup Output Regulator
There is another situation to consider in systems where
the output will be held high when the input to the LT3507
is absent. If the V and one of the RUN pins are allowed
IN
5.5
8.0
T
= 25°C
T
A
= 25°C
A
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
5.0
4.5
4.0
3.5
3.0
2.5
TO START
TO START
TO RUN
TO RUN
0.001
0.010
0.100
1.000
0.001
0.010
0.100
1.000
LOAD CURRENT (A)
LOAD CURRENT (A)
3507 F04b
3507 F04a
Figure 4. The Minimum Input Voltage Depends on Output Voltage, Load Current and Boost Circuit
3507f
14
LT3507
APPLICATIONS INFORMATION
to float, then the LT3507’s internal circuitry will pull its
quiescent current through its SW pin. This is acceptable if
the system can tolerate a few mA of load in this state. With
all three RUN pins grounded, the LT3507 enters shutdown
mode and the SW pin current drops to <50μA. However, if
and is largest when V = 2V
(50% duty cycle). As
OUT
IN
the second, lower power channel draws input current,
the input capacitor’s RMS current actually decreases as
the out-of-phase current cancels the current drawn by the
higherpowerchannel.Consideringthatthemaximumload
current from a single phase (if SW2 and SW3 are both at
maximum current) is ~3A, RMS ripple current will always
be less than 1.5A.
the V pin is grounded while the output is held high, then
IN
parasitic diodes inside the LT3507 can pull large currents
from the output through the SW pin and the V pin. A
IN
Schottky diode in series with the input to the LT3507, as
shown in Figure 5, will protect the LT3507 and the system
from a shorted or reversed input.
The high frequency of the LT3507 reduces the energy
storage requirements of the input capacitor, so that the
capacitance required is often less than 10μF. The combi-
nation of small size and low impedance (low equivalent
series resistance or ESR) of ceramic capacitors makes
them the preferred choice. The low ESR results in very
low voltage ripple. Ceramic capacitors can handle larger
magnitudes of ripple current than other capacitor types
of the same value. Use X5R and X7R types.
PARASITIC DIODE
D4
V
SW
IN
V
V
IN
OUT
LT3507
3507 F05
An alternative to a high value ceramic capacitor is a lower
valuealongwithalargerelectrolyticcapacitor, forexample
a1μFceramiccapacitorinparallelwithalowESRtantalum
capacitor. For the electrolytic capacitor, a value larger than
10μF will be required to meet the ESR and ripple current
requirements. Because the input capacitor is likely to see
high surge currents when the input source is applied, tan-
talumcapacitorsshouldbesurgerated. Themanufacturer
may also recommend operation below the rated voltage
of the capacitor. Be sure to place the 1μF ceramic as close
Figure 5. Diode D4 Prevents a Shorted Input from Discharging a
Backup Battery Tied to the Output
Input Capacitor Selection
Bypass the input of the LT3507 circuit with a 10μF or
higher ceramic capacitor of X7R or X5R type. A lower
value or a less expensive Y5V type will work if there is
additional bypassing provided by bulk electrolytic capaci-
tors, or if the input source impedance is low. The following
paragraphs describe the input capacitor considerations
in more detail.
as possible to the V and GND pins on the IC for optimal
IN
noise immunity.
Step-down regulators draw current from the input supply
in pulses with very fast rise and fall times. The input ca-
pacitor is required to reduce the resulting voltage ripple at
the LT3507 input and to force this switching current into a
tight local loop, minimizing EMI. The input capacitor must
have low impedance at the switching frequency to do this
effectively and it must have an adequate ripple current rat-
ing. With three switchers operating at the same frequency
but with different phases and duty cycles, calculating the
input capacitor RMS current is not simple; however, a
conservative value is the RMS input current for the phase
A final caution is in order regarding the use of ceramic
capacitors at the input. A ceramic input capacitor can
combine with stray inductance to form a resonant tank
circuit.Ifpowerisappliedquickly(forexamplebyplugging
the circuit into a live power source), this tank can ring,
doubling the input voltage and damaging the LT3507. The
solution is to either clamp the input voltage or dampen the
tank circuit by adding a lossy capacitor in parallel with the
ceramic capacitor. For details, see Application Note 88.
delivering the most power (V
• I ):
OUT OUT
VOUT V – V
(
)
IOUT
2
IN
OUT
IIN(RMS) =IOUT
•
<
V
IN
3507f
15
LT3507
APPLICATIONS INFORMATION
Frequency Compensation
LT3507
CURRENT MODE
POWER STAGE
V
SW
The LT3507 uses current mode control to regulate the
output.Thissimplifiesloopcompensation.Inparticular,the
LT3507doesnotdependontheESRoftheoutputcapacitor
for stability so you are free to use ceramic capacitors to
achieve low output ripple and small circuit size.
OUTPUT
ERROR
g
mp
AMPLIFIER
C
R1
PL
FB
–
330μS
ESR
+
V
FB
800mV
500k
C1
+
GND
V
C
C1
The components tied to the V pin provide frequency
C
compensation. Generally, a capacitor and a resistor in
series to ground determine loop gain. In addition, there
is a lower value capacitor in parallel. This capacitor filters
noise at the switching frequency and is not part of the
loop compensation.
POLYMER
OR
TANTALUM
CERAMIC
R2
R
C
C
F
C
C
3507 F06
Figure 6. Loop Response Model
Loop compensation determines the stability and transient
performance.Designingthecompensationnetworkisabit
complicatedandthebestvaluesdependontheapplication
and the type of output capacitor. A practical approach is to
startwithoneofthecircuitsinthisdatasheetthatissimilar
to your application and tune the compensation network
to optimize the performance. Check stability across all
operatingconditions, includingloadcurrent, inputvoltage
and temperature. The LT1375 data sheet contains a more
thorough discussion of loop compensation and describes
how to test the stability using a transient load. Application
Note 76 is an excellent source as well.
SHUTDOWN
The RUN pins are used to place the individual switch-
ing regulators and the internal bias circuits in shutdown
mode. When all three RUN pins are pulled low, the LT3507
is in shutdown mode and draws less than 1μA from the
input supply. When any RUN pin is pulled high (>1.5V)
the internal reference, LDO and selected channel are all
turned on.
The RUN pins draw a small amount of current to power
the reference. The current is less than 3μA at 1.8V, so the
RUN pin can be driven directly from 1.8V logic. The RUN
pins are rated up to 36V and can be connected directly to
the input voltage.
Figure6showsanequivalentcircuitfortheLT3507control
loop. The error amp is a transconductance amplifier with
finite output impedance. The power section, consisting of
the modulator, power switch and inductor is modeled as a
transconductance amplifier generating an output current
A RUN pin cannot be pulled up by logic powered by its
ownoutput, i.e., RUN1can’tbepulledupbylogicpowered
by OUT1.
proportional to the voltage at the V pin. The gain of the
C
power stage (g ) is 5S for Channel 1 and 3.6S for Chan-
mp
nels 2 and 3. Note that the output capacitor integrates this
POWER GOOD INDICATORS
currentand thatthecapacitor ontheV pin (C )integrates
C
C
the error amplifier output current, resulting in two poles
in the loop. In most cases, a zero is required and comes
either from the output capacitor ESR or from a resistor
The PGOOD pin is the open-collector output of an internal
comparator. PGOOD remains low until the FB pin is within
10% of the final regulation voltage. Tie the PGOOD to any
supply with a pull-up resistor that will supply less than
200μA. Note that this pin will be open when the LT3507 is
in shutdown mode (all three RUN pins at ground) regard-
less of the voltage at the FB pin. PGOOD is valid when
in series with C . This model works well as long as the
C
inductor current ripple is not too low (ΔI
> 5% I
)
RIPPLE
OUT
and the loop crossover frequency is less than f /5. A
SW
phase lead capacitor (C ) across the feedback divider
PL
may improve the transient response.
the LT3507 is enabled (any RUN pin is high) and V is
IN
greater than ~3.5V.
3507f
16
LT3507
APPLICATIONS INFORMATION
LT3507
LT3507
LT3507
RUN1
C
RUN1
RUN2
RUN3
RUN1
RUN2
RUN3
RUN
RUN1 TRK/SS1
RUN2 TRK/SS2
RUN3 TRK/SS3
RUN
V
INSW
2C
4C
PG1
RUN2
PG2
(7a)
(7b)
RUN3
LT3507
V
RUN
RUN1 TRK/SS1
(7c)
IN
RUN2
PG1
LT3507
RUN2
RUN3 TRK/SS2
PG2
PG1
TRK/SS3
3507 F07
(7e)
Doesn’t Work!
(7d)
Figure 7. Output Sequencing
remember that the delayed channels will start rising right
away, just at a slower rate than the faster channels.
OUTPUT SEQUENCING
The LT3507 outputs can be sequenced in several ways.
The circuits in Figure 7 show some examples of these. In
eachcasechannel1startsfirst,followedbychannel2,then
channel 3. The sequence shown is not a requirement; the
LT3507 can sequence the channels in any order. Note that
thesecircuitssequencetheoutputsduringstart-up. When
shut down the three channels turn off simultaneously.
The PG pins can be also used to sequence the three out-
puts. In Figure 7c, the PG pins drive the RUN pins directly.
Channel 2 will be held off until channel 1 is in regulation
and channel 3 is held off until channel 2 is in regulation.
The resistors pull up to V
so that there is no current
INSW
draw in shutdown. They should be sized to provide at least
1μAintotheRUNpin.Thecapacitorskeepchannels2and 3
off until the power good comparators are functioning (the
power good comparators are disabled in shutdown). The
FETs are necessary to insure the RUN2 and RUN3 pins
are held low during shutdown.
The most obvious method is to bring the RUN pins up
individually in the sequence desired (Figure 7a). This is
the ideal solution if full independent control of all three
channels is needed. This is also a simple solution, but it
does require three logic inputs.
In Figure 7d, the PG pins pull down the TRK/SS pins of
the delayed channels. This is a simple solution requiring
no extra components. Channel 2 is held off by the PG1
output pulling TRK/SS2 down until channel 1 is at 90% of
its final value. PG1 then goes high impedance and allows
the channel 2 soft-start circuit to charge the soft-start
capacitor bringing channel 2 up. Similarly, channel 3 is
held off by PG2.
Another possibility is to use the soft-start feature to slow
thestart-upofspecificchannels(Figure7b). AllthreeRUN
pins are tied together and the difference in soft-start ca-
pacitance will determine the start-up sequence. The larger
capacitor on channel 2 slows its start-up with respect to
channel 1, and channel 3 is even slower. The capacitor on
the delayed channel should be at least twice the value of
the capacitor on the faster channel. A larger ratio may be
required,dependingontheoutputcapacitanceandloadon
each channel. Make sure to test the circuit in the system
before deciding on final values for these capacitors. Also
The circuits in Figure 7a and 7b leave the power good
indicators free. However, the circuits in Figures 7c and
7d have another advantage. As well as sequencing the
outputs at start-up, they also disable the slaved channels
3507f
17
LT3507
APPLICATIONS INFORMATION
V
V
V
OUT1
OUT1
OUT2
V
OUT2
3507 F08
TIME
TIME
(8a) Coincident Tracking
(8b) Ratiometric Tracking
Figure 8. Two Different Modes of Output Voltage Tracking
V
OUT1
V
OUT2
R5
R6
R1
R2
R3
R4
SELECTING VALUES FOR R5 AND R6
COINCIDENT RATIOMETRIC
TO
TRK/SS2
PIN
TO
FB1
PIN
TO
FB2
PIN
V
V
R5 =
R6 =
R3
R4
R1
R1
V
/1V – 1
OUT1
Tracking Setup
V
VOUT2
0.8
ꢀ R1
ꢁ
R3
R4
ꢃ
=
OUT1 –1,
=
–1
ꢂ
ꢅ
ꢄ
R2 0.8
Figure 9. Setup for Coincident and Ratiometric Tracking
of channel 2’s feedback divider (R5 = R3 and R6 = R4). In
this tracking mode, V must be set higher than V
if the master channel falls out of regulation (due to a short
circuit or a collapsing input voltage).
.
OUT2
OUT1
ToimplementtheratiometrictrackinginFigure8b, change
the extra divider ratio to R5 = R1 and R6 = R2 + ΔR. The
extra resistance on R6 should be set so that the TRK/SS2
Finally, be aware that the circuit in Figure 7e does not
work, because the power good comparators are disabled
in shutdown.
voltage is ≥1V when V
is at its final value.
OUT1
The need for this extra resistance is best understood
with the help of the equivalent input circuit shown in
Figure 10. At the input stage of the error amplifier, two
common anode diodes are used to clamp the equivalent
reference voltage and an additional diode is used to match
the shifted common mode voltage. The top two current
sourcesareofthesameamplitude.Inthecoincidentmode,
OUTPUT VOLTAGE TRACKING
The LT3507 allows the user to program how the output
ramps up by means of the TRK/SS pins. Through these
pins, any channel output can be set up to either coinci-
dently or ratiometrically track any other channel output.
This example will show the channel 2 output tracking the
channel 1 output, as shown in Figure 8. The TRK/SS2 pin
acts as a clamp on channel 2’s reference voltage. V
OUT2
I
I
is referenced to the TRK/SS2 voltage when the TRK/SS2
< 0.8V and to the internal precision reference when TRK/
SS2 > 0.8V.
1μA
D1
+
–
D2
EA2
TRK/SS
0.8V
FB
ToimplementthecoincidenttrackinginFigure8a, connect
an extra resistive divider to the output of channel 1 and
connect its midpoint to the TRK/SS2 pin (Figure 9). The
ratio of this divider should be selected the same as that
D3
3507 F10
Figure 10. Equivalent Input Circuit of Error Amplifier
3507f
18
LT3507
APPLICATIONS INFORMATION
the TRK/SS2 voltage is substantially higher than 0.8V at
steady state and effectively turns off D1. D2 and D3 will
thereforeconductthesamecurrentandoffertightmatching
V
. This can be useful in applications regulating outputs
IN3
from a PCI Express bus, where the 12V input is power
limited and the 3.3V input has power available to drive
between V and the internal precision 0.8V reference. In
other outputs. In this case, tie the 12V input to V and
the 3.3V input to V and V
FB2
IN1
the ratiometric mode with R6 = R2, TRK/SS2 equals 0.8V
.
IN2
IN3
at steady state. D1 will divert part of the bias current and
make V
slightly lower than 0.8V. Although this error
FB2
LOW DROPOUT REGULATOR
is minimized by the exponential I-V characteristic of the
diodes, it does impose a finite amount of output voltage
deviation. Further, when channel 1’s output experiences
dynamic excursions (under load transient, for example),
channel 2 will be affected as well. Setting R6 to a value
that pushes the TRK/SS2 voltage to 1V at steady state will
eliminate these problems while providing near ratiometric
tracking.
The low dropout regulator comprises an error amp, loop
compensation and a base drive amp. It uses the same
0.8V reference as the switching regulators. It requires an
external NPN pass transistor and 2.2μF of output capaci-
tance for stability.
Thedropoutcharacteristicswillbedeterminedbythepass
transistor. The collector-emitter saturation characteristics
will limit the dropout voltage. Table 4 lists some suitable
NPN transistors with their saturation specifications.
Theexampleshowschannel2trackingchannel1,however
any channel may be set up to track any other channel.
The base drive voltage has a maximum voltage of 5V.
This will limit the maximum output of the regulator to
If a capacitor is tied from the TRK/SS pin to ground, then
theinternalpull-upcurrentwillgenerateavoltagerampon
this pin. This results in a ramp at the output, limiting the
inductorcurrentandthereforeinputcurrentduringstart-up.
5V – V
where V
is the base-emitter saturation
BESAT
BESAT
voltage of the pass transistor.
A good value for the soft-start capacitor is C /10,000,
OUT
Table 4. NPN Pass Transistors and Saturation Characteristics
where C
is the value of the output capacitor.
OUT
PART NUMBER
On Semiconductor
NSS30071
V
V
I (mA)
I (mA)
CESAT
BESAT
C
B
MULTIPLE INPUT SUPPLIES
, V and V are independent and can be powered
0.25
0.2
0.85
0.85
500
5
NSS30101
1000
10
V
IN1 IN2
IN3
Fairchild
with different voltages provided V is present when V
IN1
IN2
KSC3265
0.4
500
20
or V is present. Each supply must be bypassed as close
IN3
to the V pins as possible.
IN
The LDO is always on when any of the switcher channels
is on. The LDO may be shut down if it is unused by pull-
ing the FB4 pin up with a 30μA current source. The FB4
pin will clamp at about 1.25V and the LDO will shut off
reducingpowerconsumption.Thispull-upcanbesourced
from one of the LT3507 outputs provided that channel is
always on when the other channels are on.
For applications requiring large inductors due to high V
IN
to V
ratios, a 2-stage step-down approach may reduce
OUT
inductor size by allowing an increase in frequency. A dual
step-downapplicationstepsdowntheinputvoltage(V
)
IN1
to the highest output voltage, then uses that voltage to
power the other outputs (V and V ). V must be
IN2
IN3
OUT1
able to provide enough current for its output plus the
input current at V and V when V and V are
at maximum load. The Typical Applications section shows
a 36V to 15V, 1.8V and 1.2V 2-stage converter using this
approach.
The output stage of the LDO will drive the NPN base from
the BIAS voltage if it is at least 0.8V above the LDO DRIVE
voltage.
IN2
IN3
OUT2
OUT3
FB Resistor Network
For applications with multiple voltages, the LT3507 can
The output voltage of the LDO regulator is programmed
witharesistordivider(RefertoBlockDiagram)betweenthe
3507f
accommodate input voltages as low as 3V on V and
IN2
19
LT3507
APPLICATIONS INFORMATION
emitter of the external NPN pass resistor and the feedback
pin, FB4. Choose the resistors according to
The hysteresis voltages are:
V
V
= 10μA • R3
= 10μA • R1
OVHYST
UVHYST
VOUT4
800mV
ꢁ
ꢄ
R1=R2
ꢀ1
ꢆ
ꢃ
ꢂ
ꢅ
If the overvoltage lockout is not used, the OVLO pin must
be tied to ground. If the undervoltage lockout is not used,
the UVLO pin must be tied to V
The parallel combination of R1 and R2 should be 10k or
less to avoid bias current errors.
.
INSW
V
INSW
PROGRAMMABLE OVERVOLTAGE AND
UNDERVOLTAGE LOCKOUT
10μA
R1 R3
R2
UVLO
–
+
The LT3507 provides two input pins that allow user-pro-
grammableovervoltageandundervoltagelockout.Boththe
trip levels and hysteresis can be set by resistor values.
UVLO
V
provides a switched V to minimize power con-
IN1
INSW
1.2V
sumption in shutdown. V
is connected to V when
INSW
IN1
–
+
the LT3507 is operating, with a saturation voltage of about
0.3V. It is high impedance when the LT3507 is in shutdown
(all three RUN pins low).
OVLO
OVLO
R4
The programmable lockout is a pair of comparators with
the trip level set at 1.2V. The OVLO comparator trips when
the OVLO pin exceeds 1.2V while the UVLO comparator
trips when the UVLO pin drops below 1.2V. These com-
parators shut down all four regulators until the input
voltage recovers.
3507 F11
10μA
Figure 11. Undervoltage and Overvoltage Lockout Circuit
PCB LAYOUT
For proper operation and minimum EMI, care must be
taken during printed circuit board (PCB) layout. Figure 12
shows the high current paths in the step-down regula-
tor circuit. Note that in the step-down regulators large,
switched currents flow in the power switch, the catch
diode and the input capacitor. The loop formed by these
components should be as small as possible. Place these
components,alongwiththeinductorandoutputcapacitor,
on the same side of the circuit board and connect them
on that layer. Place a local, unbroken ground plane below
these components and tie this ground plane to system
ground at one location, ideally at the ground terminal of
the output capacitor C2. Additionally, keep the SW and
BOOST nodes as small as possible. Figure 13 shows an
example of proper PCB layout.
The comparators also activate current sources that gener-
ate hysteresis to eliminate chatter. The UVLO comparator
activates a 10μA current sink on the UVLO pin. The OVLO
comparator activates a 10μA current source on the OVLO
pin. These currents generate hysteresis voltage through
the resistance of the divider string.
Figure 11 shows a typical connection. The threshold
voltages are:
R3
R4
R1
R2
ꢀ
ꢁ
ꢃ
ꢄ
VOVTH = 0.3V +1.2V • 1+
ꢂ
ꢅ
ꢀ
ꢃ
VUVTH = 0.3V +1.2V • 1+
ꢂ
ꢅ
ꢁ
ꢄ
3507f
20
LT3507
APPLICATIONS INFORMATION
V
SW
V
SW
IN
IN
GND
GND
(12a)
(12b)
V
SW
L1
V
SW
IN
I
C1
C1
D1
C2
GND
3507 F12
(12c)
Figure 12. Subtracting the Current when the Switch is ON (12a) from the Current when the Switch is OFF (12b) Reveals the Path of the
High Frequency Switching Current (12c) Keep this Loop Small. The Voltage on the SW and Boost Nodes will also be Switched; Keep
These Nodes as Small as Possible. Finally, Make Sure the Circuit is Shielded with a Local Ground Plane
Figure 13. Power Path Components and Topside Layout
dissipated by the LT3507. Place additional vias near the
catch diodes. Adding more copper to the top and bottom
layers and tying this copper to the internal planes with vias
canreducethermalresistancefurther.Withthesesteps,the
thermalresistancefromdie(orjunction)toambientcanbe
THERMAL CONSIDERATIONS
ThehighoutputcurrentcapabilityoftheLT3507willrequire
carefulattentiontopowerdissipationofallthecomponents
to insure a safe thermal design. The PCB must provide
heat sinking to keep the LT3507 cool. The Exposed Pad on
the bottom of the package must be soldered to a ground
plane. This ground should be tied to other copper layers
below with thermal vias; these layers will spread the heat
reduced to θ = 34°C/W or less. With 100 LFPM airflow,
JA
this resistance can fall by another 25%. Further increases
in airflow will lead to lower thermal resistance.
3507f
21
LT3507
APPLICATIONS INFORMATION
The maximum allowed power dissipation by the LT3507
can be determined by:
where R is the equivalent switch resistance (0.18Ω for
channel 1 and 0.22Ω for channels 2 and 3) and f is the
operating frequency.
SWi
TJ(MAX) – TA
PDISS(MAX)
=
The boost loss in channel i is:
θJA
I
ꢀ
ꢃ
VOUTi
V
OUTi + 0.02A
(
)
where T
is the maximum die temperature of 125°C
BOOSTi
ꢂ
ꢅ
JMAX
ꢁ
ꢄ
50
(150°C for H grade).
PBSTi =
V
INi
However, take care in determining T since the catch
A
diodes also dissipate power and must be located close
to the LT3507. Another potential heat source is the LDO
pass transistor. In a compact layout the pass transistor
will be located close to the LT3507. The inductors will
also dissipate some power due to their series resistance
and they must be close to the LT3507. All of these heat
sources will increase the effective ambient temperature
seen by the LT3507.
The quiescent loss is:
P = V (I ) + V (I )
BIAS Q(BIAS)
Q
IN1 Q(VIN1)
If the BIAS pin does not have a voltage of at least 3V ap-
plied, then V must replace V in the equation. Also,
IN1
BIAS
I
can be reduced by 0.2mA (typ) if the LDO is shut
off (see the LDO section).
Q(VIN1)
The LDO drive loss is:
A thorough analysis of eight heat sources in a small PCB
area is beyond the scope of this data sheet, however a
number of thermal analysis programs are available to
calculate the temperature rise in each component (such
as PCAnalyze from K&K Associates or BETAsoft from
Mentor). Thepowerdissipationofeachcomponentwillbe
needed to accurately calculate the thermal characteristics
of the system.
I
ꢂ
OUT(LDO) ꢅ
P
LDO =(VBIAS ꢀVLDO(OUT) ꢀ 0.7V)
,
ꢄ
ꢇ
ꢁPASS
ꢃ
ꢆ
if VBIAS ꢈ VLDO(OUT) +1.5V
or
I
ꢂ
OUT(LDO) ꢅ
PLDO =(VIN1 ꢀVLDO(OUT) ꢀ 0.7V)
,
ꢄ
ꢇ
ꢁPASS
ꢃ
ꢆ
if VBIAS <VLDO(OUT) +1.5V
ThecontributorstopowerdissipationinsidetheLT3507are
switch DC loss, switch AC loss, boost current, quiescent
current and LDO drive current. The total dissipation within
the LT3507 can be expressed as:
where β is the current gain of the external pass
PASS
transistor.
Next, the power in the external components must be taken
into account. The diode power is given by:
3
∑
i=1
PDISS
=
PSWDCi +PSWACi +P
(
+P +P
)
BSTi Q LDO
V V – V
– V I
F OUT
(
)
F
IN
OUT
PDIODE
=
The switch DC and AC losses in channel i are:
RSWi
2 VOUTi
V
IN
I
(
)
OUTi
where V is the forward drop of the diode at I
.
PSWDCi
=
F
OUT
V
INi
The inductor power is:
PSWACi =17ns I
V
f
( )
)
(
)
(
OUTi
INi
2
P
= (I ) ESR
IND
OUT
IND
where ESR is the inductor equivalent series resistance.
IND
3507f
22
LT3507
APPLICATIONS INFORMATION
The LDO pass transistor power is:
The total dissipation on the LT3507 is the sum of all these
and is equal to 0.73W. Note that this is less than half of
DISS(MAX)
P
= I
(V – V
)
NPN
OUTLDO
C
OUTLDO
P
. Next, the power dissipation of the external
where V is the collector voltage on the NPN pass tran-
C
components are:
sistor.
0.45V 8V – 2.5V – 0.45 1.6A
(
)
PDIODE1
=
= 0.46W
Example: An LT3507 design requirements are:
8V
V = 8V, f= 500kHz
IN
2
P
= 1.6A 0.05Ω= 0.13W
(
)
IND1
V1 = 2.5V at I1 = 1.6A
V2 = 3.3V at I2 = 0.8A (used for boost, bias and V4)
V3 = 1.2V at I3 = 1A
Similarly, P
= 0.24W, P
= 0.05W, P
=
DIODE3
DIODE2
IND2
0.36W and P
= 0.05W. And finally:
IND3
P
NPN
= 0.2A(3.3V – 3V) = 0.06W
V4 = 3V at I4 = 0.2A (from 3.3V output)
ThusthetotalpowerdissipatedbytheLT3507andexternal
components is 2.08W. The thermal analysis will use these
power dissipations to calculate the internal component
temperatures. Make sure that none of the components
exceed their rated temperature limits.
T = 50°C, T
= 125°C
A
JMAX
θ
= 34°C/W
JA
Schottky V = 0.45V and Inductor ESR = 0.05Ω
F
125°C – 50°C
PDISS(MAX)
=
= 2.2W
34°C/W
RELATED LINEAR TECHNOLOGY PUBLICATIONS
2
0.18ꢀ 1.6A 2.5V
(
)
Application Notes 19, 35, 44, 76 and 88 contain more
detailed descriptions and design information for buck
regulators and other switching regulators. The LT1375
data sheet has a more extensive discussion of output
ripple, loop compensation, and stability testing. Design
Note 318 shows how to generate a dual polarity output
supply using a buck regulator.
PSWDC1
=
= 0.14W
8V
PSWAC1 =17ns 1.6A 8V 500k = 0.11W
(
)( )(
)
1.6A
50
ꢁ
ꢂ
ꢄ
ꢅ
2.5V 3.3V
+ 0.02A
(
)
ꢃ
ꢆ
PBST1
=
= 0.06W
8V
Similarly, P
= 0.09W, P
= 0.07W, P
BST2
=
=
SWDC2
SWAC2
0.06W, P
= 0.03W, P
= 0.07W and P
SWDC3
SWAC3 BST2
0.03W. Remember, the total current from channel 2 is I2
+ I4 since the LDO pass transistor draws from V2. Ignore
bias and boost currents.
P = 8V 3.5mA + 3.3V 7.5mA = 0.05W
(
)
(
)
Q
0.2A
100
ꢀ
ꢁ
ꢃ
ꢄ
P
= 8V
= 0.02W
ꢂ
ꢅ
LDO
3507f
23
LT3507
TYPICAL APPLICATIONS
3.3V, 5V and 12V from a 24V Input with Ratiometric Tracking
100k
4.53k
4.32k
V
IN
OVLO = 29V
UVLO = 16V
21V TO 27V
49.9k
10μF
50V
V
V
IN2
V
V
IN1
IN3 INSW
BAT54
BOOST1
UVLO
OVLO
L1 3.3μH
41.2k
0.1μF
V
OUT1
3.3V
2A
V
OUT1
SW1
FB1
1000pF
1.5nF
100k 100k 100k
D1
22μF
PGOOD1
PGOOD2
PGOOD3
PGOOD1
PGOOD2
PGOOD3
V
C1
13.3k
16.2k
TRK/SS1
TRK/SS2
TRK/SS3
V
BOOST3
OUT1
BAT54
41.2k
BAT54
18.2k
0.1μF
LT3507
L3 10μH
150k
V
12V
1A
OUT3
BOOST2
SW3
FB3
L2 6.8μH
61.9k
0.1μF
V
OUT2
5V
1.2A
SW2
FB2
470pF
D3
10μF
V
C3
470nF
D2
22μF
26.7k
10.7k
V
C2
11.8k
24.3k
BIAS
V
OUT1
NC
68.1k
DRIVE
FB4
RUN1
RUN2
RUN3
SHDN
D1: ON SEMI MBRS230LT3
R /SYNC
TRK/SS4
T
D2, D3: ON SEMI MBRA130LT3
L1: COILCRAFT DO1813H-332ML
L1: COILCRAFT DO1813H-682ML
L1: COILCRAFT DO1813H-103ML
GND
54.9k
3507 TA02
f
= 800kHz
SW
3507f
24
LT3507
TYPICAL APPLICATIONS
5V, 3.3V, 2.5V and 1.8V with Coincident Tracking
49.9k
18.2k
V
IN
6V TO 36V
22μF
V
V
IN2
V
V
IN1
IN3 INSW
V
V
OUT2
BOOST1
UVLO
OVLO
4.7μH
18.7k
0.22μF
680pF
OUT1
1.8V
2.4A
V
OUT1
SW1
FB1
100k 100k 100k
D1
100μF
PGOOD1
PGOOD2
PGOOD3
PGOOD1
PGOOD2
PGOOD3
V
C1
15k
18.7k
LT3507
15k
BOOST2
TRK/SS1
BOOST3
10μH
35.7k
0.22μF
18.7k
V
3.3V
1.3A
OUT2
V
OUT2
SW2
FB2
0.22μF
680pF
15μH
V
OUT3
5V
1.5A
1000pF
SW3
FB3
53.6k
D3
22μF
V
C2
35.7k
11.5k
16.2k
11.5k
D2
22μF
TRK/SS2
V
C3
10.2k
24.3k
0.01μF
TRK/SS2
BIAS
TRK/SS2
TRK/SS3
DRIVE
FB4
Q1
RUN1
RUN2
RUN3
V
2.5V
0.2A
OUT4
2.2nF
SHDN
105k
L1: WÜRTH WE-PD 744 778 9004
L2: WÜRTH WE-PD 744 778 9115
L3: WÜRTH WE-PD 744 778 910
D1, D2, D3: DIODES, INC. B240A
22μF
24.3k
11.5k
R /SYNC
T
TRK/SS4
GND
3507 TA03
Q1: ON SEMICONDUCTOR NSS30101LT1G
f
= 450kHz
SW
3507f
25
LT3507
TYPICAL APPLICATIONS
15V, 1.8V and 1.2V 2-Stage Step Down
V
IN
21V TO 36V
10μF
49.9k
3.4k
UVLO = 19V
22μF
V
V
V
V
IN1
IN2
IN3 INSW
BOOST1
UVLO
OVLO
L1 10μH
187k
0.1μF
V
OUT1
15V
0.4A
SW1
FB1
220pF
0.01μF
D1
TRK/SS2
TRK/SS3
PGOOD1
V
C1
V
OUT2
10.5k
68.1k
100k
TRK/SS1
BIAS
PGOOD2
PGOOD3
PGOOD
BOOST 2
V
BST
0.1μF
LT3507
L2 3.3μH
V
1.8V
1.5A
OUT2
SW2
FB2
Q1
DRIVE
FB4
22.6k
V
BST
3V
1000pF
D2
33μF
31.6k
11.5k
2.2μF
V
C2
TRK/SS4
270pF
13.3k
18.2k
V
BOOST3
BST
0.1μF
L3 2.2μH
15.0k
V
1.2V
1.5A
OUT3
RUN1
RUN2
RUN3
SW3
FB3
SHDN
1000pF
D3
47μF
D1: DIODES, INC. B140A
V
R /SYNC
T
C3
D2, D3: DIODES, INC. B240A
L1: TDK LTF5022T-100M1R4
L2: TDK VLCF5020T-3R3N2R0-1
L3: TDK VLCF5020T-2R2N1R7
Q1: DIODES INC. BC817-16
GND
12.7k
30.1k
54.9k
f
= 800kHz
SW
3507 TA04
3507f
26
LT3507
PACKAGE DESCRIPTION
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701)
0.70 ± 0.05
5.50 ± 0.05
(2 SIDES)
4.10 ± 0.05
(2 SIDES)
3.15 ± 0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
5.15 ± 0.05 (2 SIDES)
6.10 ± 0.05 (2 SIDES)
7.50 ± 0.05 (2 SIDES)
RECOMMENDED SOLDER PAD LAYOUT
PIN 1 NOTCH
R = 0.30 TYP OR
3.15 ± 0.10
(2 SIDES)
0.75 ± 0.05
0.35 × 45° CHAMFER
5.00 ± 0.10
(2 SIDES)
37 38
0.00 – 0.05
0.40 ±0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
5.15 ± 0.10
(2 SIDES)
7.00 ± 0.10
(2 SIDES)
0.40 ± 0.10
0.200 REF 0.25 ± 0.05
R = 0.115
TYP
(UH) QFN 0205
0.50 BSC
0.200 REF
BOTTOM VIEW—EXPOSED PAD
0.75 ± 0.05
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3. ALL DIMENSIONS ARE IN MILLIMETERS
3507f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3507
TYPICAL APPLICATIONS
12V to 5V, 3.3V, 1.8V and 1.6V with 1.5mm Maximum Height
49.9k
49.9k
4.02k
11.3k
V
IN
8V TO 16V
OVLO = 17V
UVLO = 7V
10μF
V
V
IN2
V
V
IN1
IN3 INSW
BOOST1
UVLO
OVLO
L1 2μH
22.6k
V
0.1μF
OUT1
1.8V
2A
V
OUT2
SW1
FB1
V
OUT1
1000pF
1.5nF
100k 100k 100k
D1
33μF
V
PGOOD1
PGOOD2
PGOOD3
PGOOD1
PGOOD2
PGOOD3
C1
18.2k
13.3k
TRK/SS1
BOOST2
V
BOOST3
OUT2
L3 4.5μH
61.9k
0.1μF
1200pF
1.5nF
V
OUT3
SW3
5V
L2 4.5μH
41.2k
0.1μF
V
LT3507
OUT2
3.3V
1.5A
1.4A
FB3
SW2
FB2
D3
11.3k
10μF
V
2000pF
1.5nF
C3
D2
10μF
11.8k
V
C2
13.3k
7.32k
TRK/SS3
BIAS
V
OUT1
TRK/SS2
V
OUT2
DRIVE
FB4
Q1
RUN1
RUN2
RUN3
V
1.6V
0.2A
OUT4
SHDN
D1: DIODES, INC. DFLS220L
D2, D3: DIODES, INC. DFLS120L
L1: COOPER SD14-2R0-R
20.0k
20.0k
R /SYNC
T
TRK/SS4
22μF
GND
31.6k
2.2nF
L2, L3: COOPER SD14-4R5-R
Q1: ON SEMI NSS30071MR6T1G
f
= 1.25MHz
SW
3507 TA03
RELATED PARTS
PART NUMBER DESCRIPTION
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COMMENTS
= 3.6V, V
LT1939
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LT3480
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LT3493
LT3500
LT3501/10
LT3505
LT3506/A
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LT3684
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V
= 25V, V
= 0.8V, I = 2.5mA,
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IN(MAX)
OUT(MIN)
Q
I
< 10μA, 3 × 3 DFN-10 Package
SD
Dual 25V, 1.4A (I ), 1.1MHz, High Efficiency Step-Down DC/DC
V
= 3.3V, V
= 25V, V = 1.20V,
OUT(MIN)
OUT
IN(MIN)
IN(MAX)
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I = 3.8mA, I < 30μA, TSSOP16E Package
Q
SD
36V with Transient Protection to 60V, 2A (I ), 2.4MHz, High Efficiency
Step-Down DC/DC Converter with Burst Mode Operation
V
= 3.6V, V
= 38V, V
= 0.78V, I = 70μA,
OUT
IN(MIN)
IN(MAX)
OUT(MIN) Q
I
< 1μA, 3 × 3 DFN-10, MSOP-10E Package
SD
34V with Transient Protection to 36V, 2A (I ), 2.8MHz, High Efficiency
Step-Down DC/DC Converter with Burst Mode Operation
V
= 3.6V, V
= 34V, V
= 1.26V, I = 50μA,
OUT
IN(MIN)
IN(MAX)
OUT(MIN) Q
I
< 1μA, 3 × 3 DFN-10, MSOP-10E Package
SD
36V, 1.4A (I ), 750kHz High Efficiency Step-Down DC/DC Converter
V
SD
= 3.6V, V
= 36V, V
= 0.8V, I = 1.9mA,
Q
OUT
IN(MIN)
IN(MAX)
OUT(MIN)
I
< 1μA, 2 × 3 DFN-6 Package
36V, 40Vmax, 2A, 2.5MHz High Efficiency DC/DC Converter and LDO
Controller
V
SD
= 3.6V, V
= 36V, V
= 0.8V, I = 2.5mA,
Q
IN(MIN)
IN(MAX)
OUT(MIN)
I
< 10μA, 3 × 3 DFN-10 Package
25V, Dual 3A/2A (I ), 1.5MHz High Efficiency Step-Down DC/DC
Converter
V
= 3.3V, V
= 25V, V
= 0.8V, I = 3.7mA,
Q
OUT
IN(MIN)
IN(MAX)
OUT(MIN)
I
= 10μA, TSSOP-20E Package
SD
36V with Transient Protection to 40V, 1.4A (I ), 3MHz, High Efficiency
Step-Down DC/DC Converter
V
= 3.6V, V
= 34V, V
= 0.78V, I = 2mA,
Q
OUT
IN(MIN)
IN(MAX)
OUT(MIN)
I
= 2μA, 3 × 3 DFN-8, MSOP-8E Package
SD
25V, Dual 1.6A (I ), 575kHz,/1.1MHz High Efficiency Step-Down
V
= 3.6V, V
= 25V, V
= 0.8V, I = 3.8mA,
OUT
IN(MIN)
IN(MAX)
OUT(MIN) Q
DC/DC Converter
I
= 30μA, TSSOP-16E, 5 × 4 DFN-16 Package
SD
36V with Transient Protection to 40V, Dual 1.4A (I ), 3MHz, High
Efficiency Step-Down DC/DC Converter
V
= 3.7V, V
= 37V, V
= 0.8V, I = 4.6mA,
OUT
IN(MIN)
IN(MAX)
OUT(MIN) Q
I
= 1μA, 4 × 4 QFN-24, TSSOP-16E Package
SD
34V with Transient Protection to 36V, 2A (I ), 2.8MHz, High Efficiency
Step-Down DC/DC Converter
V
Q
= 3.6V, V
= 34V, V
= 1.26V,
OUT
IN(MIN)
IN(MAX)
OUT(MIN)
I = 850μA, I < 1μA, 3 × 3 DFN-10, MSOP-10E Package
SD
36V with Transient Protection to 60V, 2A (I ), 2.4MHz, High Efficiency
Step-Down DC/DC Converter
V
= 3.6V, V
= 38V, V
= 0.78V, I = 70μA,
OUT
IN(MIN)
IN(MAX)
OUT(MIN) Q
I
< 1μA, 3 × 3 DFN-10, MSOP-10E Package
SD
ThinSOT is a trademark of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation.
3507f
LT 0408 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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